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ths33d68b52007-03-18 00:30:29 +00001/*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths33d68b52007-03-18 00:30:29 +000019 */
20
ths3953d782007-03-21 11:04:42 +000021/* CPU / CPU family specific config register values. */
22
ths6d355242007-12-25 03:13:56 +000023/* Have config1, uncached coherency */
ths3953d782007-03-21 11:04:42 +000024#define MIPS_CONFIG0 \
ths6d355242007-12-25 03:13:56 +000025 ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
ths3953d782007-03-21 11:04:42 +000026
thsae5d8052007-07-29 22:11:46 +000027/* Have config2, no coprocessor2 attached, no MDMX support attached,
ths3953d782007-03-21 11:04:42 +000028 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30#define MIPS_CONFIG1 \
thsfcb4a412007-04-17 15:26:47 +000031((1 << CP0C1_M) | \
ths3953d782007-03-21 11:04:42 +000032 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36/* Have config3, no tertiary/secondary caches implemented */
37#define MIPS_CONFIG2 \
38((1 << CP0C2_M))
39
ths6d355242007-12-25 03:13:56 +000040/* No config4, no DSP ASE, no large physaddr (PABITS),
ths3953d782007-03-21 11:04:42 +000041 no external interrupt controller, no vectored interupts,
thsead93602007-09-06 00:18:15 +000042 no 1kb pages, no SmartMIPS ASE, no trace logic */
ths3953d782007-03-21 11:04:42 +000043#define MIPS_CONFIG3 \
44((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
thsead93602007-09-06 00:18:15 +000046 (0 << CP0C3_SM) | (0 << CP0C3_TL))
ths3953d782007-03-21 11:04:42 +000047
ths6d355242007-12-25 03:13:56 +000048/* MMU types, the first four entries have the same layout as the
49 CP0C0_MT field. */
50enum mips_mmu_types {
51 MMU_TYPE_NONE,
52 MMU_TYPE_R4000,
53 MMU_TYPE_RESERVED,
54 MMU_TYPE_FMT,
55 MMU_TYPE_R3000,
56 MMU_TYPE_R6000,
57 MMU_TYPE_R8000
58};
59
Anthony Liguoric227f092009-10-01 16:12:16 -050060struct mips_def_t {
ths50366fe2008-07-20 19:13:19 +000061 const char *name;
ths33d68b52007-03-18 00:30:29 +000062 int32_t CP0_PRid;
63 int32_t CP0_Config0;
64 int32_t CP0_Config1;
ths3953d782007-03-21 11:04:42 +000065 int32_t CP0_Config2;
66 int32_t CP0_Config3;
ths34ee2ed2007-03-24 23:36:18 +000067 int32_t CP0_Config6;
68 int32_t CP0_Config7;
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +010069 target_ulong CP0_LLAddr_rw_bitmask;
70 int CP0_LLAddr_shift;
ths2f644542007-04-11 20:34:23 +000071 int32_t SYNCI_Step;
72 int32_t CCRes;
thsead93602007-09-06 00:18:15 +000073 int32_t CP0_Status_rw_bitmask;
74 int32_t CP0_TCStatus_rw_bitmask;
75 int32_t CP0_SRSCtl;
ths3953d782007-03-21 11:04:42 +000076 int32_t CP1_fcr0;
thse034e2c2007-06-23 18:04:12 +000077 int32_t SEGBITS;
ths6d355242007-12-25 03:13:56 +000078 int32_t PABITS;
thsead93602007-09-06 00:18:15 +000079 int32_t CP0_SRSConf0_rw_bitmask;
80 int32_t CP0_SRSConf0;
81 int32_t CP0_SRSConf1_rw_bitmask;
82 int32_t CP0_SRSConf1;
83 int32_t CP0_SRSConf2_rw_bitmask;
84 int32_t CP0_SRSConf2;
85 int32_t CP0_SRSConf3_rw_bitmask;
86 int32_t CP0_SRSConf3;
87 int32_t CP0_SRSConf4_rw_bitmask;
88 int32_t CP0_SRSConf4;
thse189e742007-09-24 12:48:00 +000089 int insn_flags;
ths6d355242007-12-25 03:13:56 +000090 enum mips_mmu_types mmu_type;
ths33d68b52007-03-18 00:30:29 +000091};
92
93/*****************************************************************************/
94/* MIPS CPU definitions */
Anthony Liguoric227f092009-10-01 16:12:16 -050095static const mips_def_t mips_defs[] =
ths33d68b52007-03-18 00:30:29 +000096{
ths33d68b52007-03-18 00:30:29 +000097 {
98 .name = "4Kc",
99 .CP0_PRid = 0x00018000,
ths6d355242007-12-25 03:13:56 +0000100 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000101 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000102 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800103 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100104 (0 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000105 .CP0_Config2 = MIPS_CONFIG2,
106 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100107 .CP0_LLAddr_rw_bitmask = 0,
108 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000109 .SYNCI_Step = 32,
110 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000111 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000112 .SEGBITS = 32,
113 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100114 .insn_flags = CPU_MIPS32,
ths6d355242007-12-25 03:13:56 +0000115 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000116 },
117 {
ths8d162c22007-11-19 16:10:33 +0000118 .name = "4Km",
119 .CP0_PRid = 0x00018300,
120 /* Config1 implemented, fixed mapping MMU,
121 no virtual icache, uncached coherency. */
ths6d355242007-12-25 03:13:56 +0000122 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
ths8d162c22007-11-19 16:10:33 +0000123 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000124 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800125 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
126 (1 << CP0C1_CA),
ths8d162c22007-11-19 16:10:33 +0000127 .CP0_Config2 = MIPS_CONFIG2,
128 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100129 .CP0_LLAddr_rw_bitmask = 0,
130 .CP0_LLAddr_shift = 4,
ths8d162c22007-11-19 16:10:33 +0000131 .SYNCI_Step = 32,
132 .CCRes = 2,
133 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000134 .SEGBITS = 32,
135 .PABITS = 32,
ths8d162c22007-11-19 16:10:33 +0000136 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000137 .mmu_type = MMU_TYPE_FMT,
ths8d162c22007-11-19 16:10:33 +0000138 },
139 {
ths34ee2ed2007-03-24 23:36:18 +0000140 .name = "4KEcR1",
ths33d68b52007-03-18 00:30:29 +0000141 .CP0_PRid = 0x00018400,
ths6d355242007-12-25 03:13:56 +0000142 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000143 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000144 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800145 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100146 (0 << CP0C1_CA),
ths34ee2ed2007-03-24 23:36:18 +0000147 .CP0_Config2 = MIPS_CONFIG2,
148 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100149 .CP0_LLAddr_rw_bitmask = 0,
150 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000151 .SYNCI_Step = 32,
152 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000153 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000154 .SEGBITS = 32,
155 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100156 .insn_flags = CPU_MIPS32,
ths6d355242007-12-25 03:13:56 +0000157 .mmu_type = MMU_TYPE_R4000,
ths34ee2ed2007-03-24 23:36:18 +0000158 },
159 {
ths8d162c22007-11-19 16:10:33 +0000160 .name = "4KEmR1",
161 .CP0_PRid = 0x00018500,
ths6d355242007-12-25 03:13:56 +0000162 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
ths8d162c22007-11-19 16:10:33 +0000163 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000164 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800165 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
166 (1 << CP0C1_CA),
ths8d162c22007-11-19 16:10:33 +0000167 .CP0_Config2 = MIPS_CONFIG2,
168 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100169 .CP0_LLAddr_rw_bitmask = 0,
170 .CP0_LLAddr_shift = 4,
ths8d162c22007-11-19 16:10:33 +0000171 .SYNCI_Step = 32,
172 .CCRes = 2,
173 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000174 .SEGBITS = 32,
175 .PABITS = 32,
ths8d162c22007-11-19 16:10:33 +0000176 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000177 .mmu_type = MMU_TYPE_FMT,
ths8d162c22007-11-19 16:10:33 +0000178 },
179 {
ths34ee2ed2007-03-24 23:36:18 +0000180 .name = "4KEc",
181 .CP0_PRid = 0x00019000,
ths6d355242007-12-25 03:13:56 +0000182 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
183 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000184 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000185 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800186 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100187 (0 << CP0C1_CA),
ths34ee2ed2007-03-24 23:36:18 +0000188 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000189 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100190 .CP0_LLAddr_rw_bitmask = 0,
191 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000192 .SYNCI_Step = 32,
193 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000194 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000195 .SEGBITS = 32,
196 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100197 .insn_flags = CPU_MIPS32R2,
ths6d355242007-12-25 03:13:56 +0000198 .mmu_type = MMU_TYPE_R4000,
ths34ee2ed2007-03-24 23:36:18 +0000199 },
200 {
ths3e4587d2007-11-14 03:11:17 +0000201 .name = "4KEm",
202 .CP0_PRid = 0x00019100,
ths6d355242007-12-25 03:13:56 +0000203 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000204 (MMU_TYPE_FMT << CP0C0_MT),
ths3e4587d2007-11-14 03:11:17 +0000205 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000206 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800207 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
208 (1 << CP0C1_CA),
ths3e4587d2007-11-14 03:11:17 +0000209 .CP0_Config2 = MIPS_CONFIG2,
210 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100211 .CP0_LLAddr_rw_bitmask = 0,
212 .CP0_LLAddr_shift = 4,
ths3e4587d2007-11-14 03:11:17 +0000213 .SYNCI_Step = 32,
214 .CCRes = 2,
215 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000216 .SEGBITS = 32,
217 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000218 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000219 .mmu_type = MMU_TYPE_FMT,
ths3e4587d2007-11-14 03:11:17 +0000220 },
221 {
ths34ee2ed2007-03-24 23:36:18 +0000222 .name = "24Kc",
223 .CP0_PRid = 0x00019300,
ths6d355242007-12-25 03:13:56 +0000224 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000225 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000226 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000227 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800228 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
229 (1 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000230 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000231 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100232 .CP0_LLAddr_rw_bitmask = 0,
233 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000234 .SYNCI_Step = 32,
235 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000236 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000237 .CP0_Status_rw_bitmask = 0x1278FF1F,
ths6d355242007-12-25 03:13:56 +0000238 .SEGBITS = 32,
239 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000240 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000241 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000242 },
243 {
244 .name = "24Kf",
245 .CP0_PRid = 0x00019300,
ths6d355242007-12-25 03:13:56 +0000246 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
247 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000248 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000249 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800250 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
251 (1 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000252 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000253 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100254 .CP0_LLAddr_rw_bitmask = 0,
255 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000256 .SYNCI_Step = 32,
257 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000258 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000259 .CP0_Status_rw_bitmask = 0x3678FF1F,
ths5a5012e2007-05-07 13:55:33 +0000260 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
261 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
ths6d355242007-12-25 03:13:56 +0000262 .SEGBITS = 32,
263 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000264 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000265 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000266 },
thsead93602007-09-06 00:18:15 +0000267 {
268 .name = "34Kf",
269 .CP0_PRid = 0x00019500,
ths6d355242007-12-25 03:13:56 +0000270 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000271 (MMU_TYPE_R4000 << CP0C0_MT),
thsead93602007-09-06 00:18:15 +0000272 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000273 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800274 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
275 (1 << CP0C1_CA),
thsead93602007-09-06 00:18:15 +0000276 .CP0_Config2 = MIPS_CONFIG2,
277 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100278 .CP0_LLAddr_rw_bitmask = 0,
279 .CP0_LLAddr_shift = 0,
thsead93602007-09-06 00:18:15 +0000280 .SYNCI_Step = 32,
281 .CCRes = 2,
282 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000283 .CP0_Status_rw_bitmask = 0x3678FF1F,
thsead93602007-09-06 00:18:15 +0000284 /* No DSP implemented. */
285 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
286 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
287 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
288 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
289 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
290 (0xff << CP0TCSt_TASID),
291 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
292 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
293 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
294 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
295 .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
296 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
297 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
298 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
299 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
300 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
301 .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
302 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
303 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
304 .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
305 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
306 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
308 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
ths6d355242007-12-25 03:13:56 +0000309 .SEGBITS = 32,
310 .PABITS = 32,
ths7385ac02007-10-23 17:04:27 +0000311 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
ths6d355242007-12-25 03:13:56 +0000312 .mmu_type = MMU_TYPE_R4000,
thsead93602007-09-06 00:18:15 +0000313 },
thsd26bc212007-11-08 18:05:37 +0000314#if defined(TARGET_MIPS64)
ths33d68b52007-03-18 00:30:29 +0000315 {
316 .name = "R4000",
317 .CP0_PRid = 0x00000400,
ths6d355242007-12-25 03:13:56 +0000318 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
319 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
aurel3269585492009-01-14 19:40:36 +0000320 /* Note: Config1 is only used internally, the R4000 has only Config0. */
ths6d355242007-12-25 03:13:56 +0000321 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100322 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
323 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000324 .SYNCI_Step = 16,
325 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000326 .CP0_Status_rw_bitmask = 0x3678FFFF,
aurel3269585492009-01-14 19:40:36 +0000327 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000328 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
thse034e2c2007-06-23 18:04:12 +0000329 .SEGBITS = 40,
ths6d355242007-12-25 03:13:56 +0000330 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000331 .insn_flags = CPU_MIPS3,
ths6d355242007-12-25 03:13:56 +0000332 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000333 },
334 {
thse9c71dd2007-12-25 20:46:56 +0000335 .name = "VR5432",
336 .CP0_PRid = 0x00005400,
337 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
338 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
339 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100340 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
341 .CP0_LLAddr_shift = 4,
thse9c71dd2007-12-25 20:46:56 +0000342 .SYNCI_Step = 16,
343 .CCRes = 2,
344 .CP0_Status_rw_bitmask = 0x3678FFFF,
345 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
346 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
347 .SEGBITS = 40,
348 .PABITS = 32,
349 .insn_flags = CPU_VR54XX,
350 .mmu_type = MMU_TYPE_R4000,
351 },
352 {
thsc9c1a062007-06-01 14:58:56 +0000353 .name = "5Kc",
354 .CP0_PRid = 0x00018100,
ths29fe0e32007-12-25 17:32:46 +0000355 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000356 (MMU_TYPE_R4000 << CP0C0_MT),
thsc9c1a062007-06-01 14:58:56 +0000357 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000358 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
359 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
360 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000361 .CP0_Config2 = MIPS_CONFIG2,
362 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100363 .CP0_LLAddr_rw_bitmask = 0,
364 .CP0_LLAddr_shift = 4,
thsc9c1a062007-06-01 14:58:56 +0000365 .SYNCI_Step = 32,
366 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000367 .CP0_Status_rw_bitmask = 0x32F8FFFF,
thse034e2c2007-06-23 18:04:12 +0000368 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000369 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000370 .insn_flags = CPU_MIPS64,
ths6d355242007-12-25 03:13:56 +0000371 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000372 },
373 {
374 .name = "5Kf",
375 .CP0_PRid = 0x00018100,
ths29fe0e32007-12-25 17:32:46 +0000376 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000377 (MMU_TYPE_R4000 << CP0C0_MT),
thsc9c1a062007-06-01 14:58:56 +0000378 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000379 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
380 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
381 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000382 .CP0_Config2 = MIPS_CONFIG2,
383 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100384 .CP0_LLAddr_rw_bitmask = 0,
385 .CP0_LLAddr_shift = 4,
thsc9c1a062007-06-01 14:58:56 +0000386 .SYNCI_Step = 32,
387 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000388 .CP0_Status_rw_bitmask = 0x36F8FFFF,
aurel3269585492009-01-14 19:40:36 +0000389 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000390 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
391 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
thse034e2c2007-06-23 18:04:12 +0000392 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000393 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000394 .insn_flags = CPU_MIPS64,
ths6d355242007-12-25 03:13:56 +0000395 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000396 },
397 {
398 .name = "20Kc",
aurel3269585492009-01-14 19:40:36 +0000399 /* We emulate a later version of the 20Kc, earlier ones had a broken
thsbd04c6f2007-06-12 12:43:47 +0000400 WAIT instruction. */
401 .CP0_PRid = 0x000182a0,
ths29fe0e32007-12-25 17:32:46 +0000402 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
ths6d355242007-12-25 03:13:56 +0000403 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
thsc9c1a062007-06-01 14:58:56 +0000404 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000405 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
406 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
407 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000408 .CP0_Config2 = MIPS_CONFIG2,
409 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100410 .CP0_LLAddr_rw_bitmask = 0,
411 .CP0_LLAddr_shift = 0,
thsc9c1a062007-06-01 14:58:56 +0000412 .SYNCI_Step = 32,
thsa1daafd2007-12-24 14:33:57 +0000413 .CCRes = 1,
thsead93602007-09-06 00:18:15 +0000414 .CP0_Status_rw_bitmask = 0x36FBFFFF,
aurel3269585492009-01-14 19:40:36 +0000415 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000416 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
ths5a5012e2007-05-07 13:55:33 +0000417 (1 << FCR0_D) | (1 << FCR0_S) |
thsc9c1a062007-06-01 14:58:56 +0000418 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
thse034e2c2007-06-23 18:04:12 +0000419 .SEGBITS = 40,
ths6d355242007-12-25 03:13:56 +0000420 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000421 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
ths6d355242007-12-25 03:13:56 +0000422 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000423 },
thsd2123ea2007-10-29 09:38:43 +0000424 {
aurel3269585492009-01-14 19:40:36 +0000425 /* A generic CPU providing MIPS64 Release 2 features.
thsd2123ea2007-10-29 09:38:43 +0000426 FIXME: Eventually this should be replaced by a real CPU model. */
427 .name = "MIPS64R2-generic",
ths8c893952007-11-18 03:19:58 +0000428 .CP0_PRid = 0x00010000,
ths6d355242007-12-25 03:13:56 +0000429 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000430 (MMU_TYPE_R4000 << CP0C0_MT),
thsd2123ea2007-10-29 09:38:43 +0000431 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000432 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
433 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
434 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsd2123ea2007-10-29 09:38:43 +0000435 .CP0_Config2 = MIPS_CONFIG2,
ths6d355242007-12-25 03:13:56 +0000436 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100437 .CP0_LLAddr_rw_bitmask = 0,
438 .CP0_LLAddr_shift = 0,
thsd2123ea2007-10-29 09:38:43 +0000439 .SYNCI_Step = 32,
440 .CCRes = 2,
441 .CP0_Status_rw_bitmask = 0x36FBFFFF,
thsea4b07f2007-12-28 12:35:05 +0000442 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
444 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
ths6d355242007-12-25 03:13:56 +0000445 .SEGBITS = 42,
446 /* The architectural limit is 59, but we have hardcoded 36 bit
447 in some places...
448 .PABITS = 59, */ /* the architectural limit */
449 .PABITS = 36,
thsd2123ea2007-10-29 09:38:43 +0000450 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
ths6d355242007-12-25 03:13:56 +0000451 .mmu_type = MMU_TYPE_R4000,
thsd2123ea2007-10-29 09:38:43 +0000452 },
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800453 {
454 .name = "Loongson-2E",
455 .CP0_PRid = 0x6302,
456 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
457 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
458 (0x1<<4) | (0x1<<1),
459 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
460 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
461 .SYNCI_Step = 16,
462 .CCRes = 2,
463 .CP0_Status_rw_bitmask = 0x35D0FFFF,
464 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
465 .SEGBITS = 40,
466 .PABITS = 40,
467 .insn_flags = CPU_LOONGSON2E,
468 .mmu_type = MMU_TYPE_R4000,
469 },
470 {
471 .name = "Loongson-2F",
472 .CP0_PRid = 0x6303,
473 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
474 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
475 (0x1<<4) | (0x1<<1),
476 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
477 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
478 .SYNCI_Step = 16,
479 .CCRes = 2,
Stefan Weilebabb672011-04-26 10:29:36 +0200480 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800481 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
482 .SEGBITS = 40,
483 .PABITS = 40,
484 .insn_flags = CPU_LOONGSON2F,
485 .mmu_type = MMU_TYPE_R4000,
486 },
487
ths33d68b52007-03-18 00:30:29 +0000488#endif
489};
490
Anthony Liguoric227f092009-10-01 16:12:16 -0500491static const mips_def_t *cpu_mips_find_by_name (const char *name)
ths33d68b52007-03-18 00:30:29 +0000492{
bellardaaed9092007-11-10 15:15:54 +0000493 int i;
ths33d68b52007-03-18 00:30:29 +0000494
malcb1503cd2008-12-22 20:33:55 +0000495 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
ths33d68b52007-03-18 00:30:29 +0000496 if (strcasecmp(name, mips_defs[i].name) == 0) {
bellardaaed9092007-11-10 15:15:54 +0000497 return &mips_defs[i];
ths33d68b52007-03-18 00:30:29 +0000498 }
499 }
bellardaaed9092007-11-10 15:15:54 +0000500 return NULL;
ths33d68b52007-03-18 00:30:29 +0000501}
502
Stefan Weil9a78eea2010-10-22 23:03:33 +0200503void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
ths33d68b52007-03-18 00:30:29 +0000504{
505 int i;
506
malcb1503cd2008-12-22 20:33:55 +0000507 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
ths33d68b52007-03-18 00:30:29 +0000508 (*cpu_fprintf)(f, "MIPS '%s'\n",
509 mips_defs[i].name);
510 }
511}
512
thsf8a6ec52008-09-02 17:39:45 +0000513#ifndef CONFIG_USER_ONLY
Anthony Liguoric227f092009-10-01 16:12:16 -0500514static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
ths29929e32007-05-13 13:49:44 +0000515{
thsead93602007-09-06 00:18:15 +0000516 env->tlb->nb_tlb = 1;
517 env->tlb->map_address = &no_mmu_map_address;
ths29929e32007-05-13 13:49:44 +0000518}
519
Anthony Liguoric227f092009-10-01 16:12:16 -0500520static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
ths29929e32007-05-13 13:49:44 +0000521{
thsead93602007-09-06 00:18:15 +0000522 env->tlb->nb_tlb = 1;
523 env->tlb->map_address = &fixed_mmu_map_address;
ths29929e32007-05-13 13:49:44 +0000524}
525
Anthony Liguoric227f092009-10-01 16:12:16 -0500526static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
ths29929e32007-05-13 13:49:44 +0000527{
thsead93602007-09-06 00:18:15 +0000528 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
529 env->tlb->map_address = &r4k_map_address;
aurel32c01fccd2009-03-08 00:06:01 +0000530 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
531 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
532 env->tlb->helper_tlbp = r4k_helper_tlbp;
533 env->tlb->helper_tlbr = r4k_helper_tlbr;
thsead93602007-09-06 00:18:15 +0000534}
535
Anthony Liguoric227f092009-10-01 16:12:16 -0500536static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000537{
538 env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
539
ths6d355242007-12-25 03:13:56 +0000540 switch (def->mmu_type) {
541 case MMU_TYPE_NONE:
thsead93602007-09-06 00:18:15 +0000542 no_mmu_init(env, def);
543 break;
ths6d355242007-12-25 03:13:56 +0000544 case MMU_TYPE_R4000:
thsead93602007-09-06 00:18:15 +0000545 r4k_mmu_init(env, def);
546 break;
ths6d355242007-12-25 03:13:56 +0000547 case MMU_TYPE_FMT:
thsead93602007-09-06 00:18:15 +0000548 fixed_mmu_init(env, def);
549 break;
ths6d355242007-12-25 03:13:56 +0000550 case MMU_TYPE_R3000:
551 case MMU_TYPE_R6000:
552 case MMU_TYPE_R8000:
thsead93602007-09-06 00:18:15 +0000553 default:
554 cpu_abort(env, "MMU type not supported\n");
555 }
ths29929e32007-05-13 13:49:44 +0000556}
thsf8a6ec52008-09-02 17:39:45 +0000557#endif /* CONFIG_USER_ONLY */
ths29929e32007-05-13 13:49:44 +0000558
Anthony Liguoric227f092009-10-01 16:12:16 -0500559static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000560{
thsf01be152008-09-18 11:57:27 +0000561 int i;
thsead93602007-09-06 00:18:15 +0000562
thsf01be152008-09-18 11:57:27 +0000563 for (i = 0; i < MIPS_FPU_MAX; i++)
564 env->fpus[i].fcr0 = def->CP1_fcr0;
565
566 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
thsead93602007-09-06 00:18:15 +0000567}
568
Anthony Liguoric227f092009-10-01 16:12:16 -0500569static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000570{
571 env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
572
573 /* MVPConf1 implemented, TLB sharable, no gating storage support,
574 programmable cache partitioning implemented, number of allocatable
575 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
576 implemented, 5 TCs implemented. */
577 env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
578 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
thsead93602007-09-06 00:18:15 +0000579// TODO: actually do 2 VPEs.
580// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
581// (0x04 << CP0MVPC0_PTC);
582 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
583 (0x04 << CP0MVPC0_PTC);
aurel32932e71c2009-01-12 21:33:13 +0000584#if !defined(CONFIG_USER_ONLY)
ths0eaef5a2008-07-23 16:14:22 +0000585 /* Usermode has no TLB support */
aurel32932e71c2009-01-12 21:33:13 +0000586 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
587#endif
ths0eaef5a2008-07-23 16:14:22 +0000588
thsead93602007-09-06 00:18:15 +0000589 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
590 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
591 env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
592 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
593 (0x1 << CP0MVPC1_PCP1);
594}