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bellard2c0262a2003-09-30 20:34:21 +00001/*
2 * i386 virtual CPU header
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard2c0262a2003-09-30 20:34:21 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard2c0262a2003-09-30 20:34:21 +000018 */
19#ifndef CPU_I386_H
20#define CPU_I386_H
21
bellard14ce26e2005-01-03 23:50:08 +000022#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020023#include "qemu-common.h"
bellard14ce26e2005-01-03 23:50:08 +000024
25#ifdef TARGET_X86_64
26#define TARGET_LONG_BITS 64
27#else
bellard3cf1e032004-01-24 15:19:09 +000028#define TARGET_LONG_BITS 32
bellard14ce26e2005-01-03 23:50:08 +000029#endif
bellard3cf1e032004-01-24 15:19:09 +000030
bellardd720b932004-04-25 17:57:43 +000031/* target supports implicit self modifying code */
32#define TARGET_HAS_SMC
33/* support for self modifying code even if the modified instruction is
34 close to the modifying instruction */
35#define TARGET_HAS_PRECISE_SMC
36
bellard1fddef42005-04-17 19:16:13 +000037#define TARGET_HAS_ICE 1
38
ths9042c0e2006-12-23 14:18:40 +000039#ifdef TARGET_X86_64
40#define ELF_MACHINE EM_X86_64
41#else
42#define ELF_MACHINE EM_386
43#endif
44
Andreas Färber9349b4f2012-03-14 01:38:32 +010045#define CPUArchState struct CPUX86State
pbrookc2764712009-03-07 15:24:59 +000046
Paolo Bonzini022c62c2012-12-17 18:19:49 +010047#include "exec/cpu-defs.h"
bellard2c0262a2003-09-30 20:34:21 +000048
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020049#include "fpu/softfloat.h"
bellard7a0e1f42005-03-13 17:01:47 +000050
bellard2c0262a2003-09-30 20:34:21 +000051#define R_EAX 0
52#define R_ECX 1
53#define R_EDX 2
54#define R_EBX 3
55#define R_ESP 4
56#define R_EBP 5
57#define R_ESI 6
58#define R_EDI 7
59
60#define R_AL 0
61#define R_CL 1
62#define R_DL 2
63#define R_BL 3
64#define R_AH 4
65#define R_CH 5
66#define R_DH 6
67#define R_BH 7
68
69#define R_ES 0
70#define R_CS 1
71#define R_SS 2
72#define R_DS 3
73#define R_FS 4
74#define R_GS 5
75
76/* segment descriptor fields */
77#define DESC_G_MASK (1 << 23)
78#define DESC_B_SHIFT 22
79#define DESC_B_MASK (1 << DESC_B_SHIFT)
bellard14ce26e2005-01-03 23:50:08 +000080#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
81#define DESC_L_MASK (1 << DESC_L_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +000082#define DESC_AVL_MASK (1 << 20)
83#define DESC_P_MASK (1 << 15)
84#define DESC_DPL_SHIFT 13
aliguoria3867ed2009-04-18 15:36:11 +000085#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +000086#define DESC_S_MASK (1 << 12)
87#define DESC_TYPE_SHIFT 8
aliguoria3867ed2009-04-18 15:36:11 +000088#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +000089#define DESC_A_MASK (1 << 8)
90
bellarde670b892003-11-12 23:23:42 +000091#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
92#define DESC_C_MASK (1 << 10) /* code: conforming */
93#define DESC_R_MASK (1 << 9) /* code: readable */
bellard2c0262a2003-09-30 20:34:21 +000094
bellarde670b892003-11-12 23:23:42 +000095#define DESC_E_MASK (1 << 10) /* data: expansion direction */
96#define DESC_W_MASK (1 << 9) /* data: writable */
97
98#define DESC_TSS_BUSY_MASK (1 << 9)
bellard2c0262a2003-09-30 20:34:21 +000099
100/* eflags masks */
101#define CC_C 0x0001
102#define CC_P 0x0004
103#define CC_A 0x0010
104#define CC_Z 0x0040
105#define CC_S 0x0080
106#define CC_O 0x0800
107
108#define TF_SHIFT 8
109#define IOPL_SHIFT 12
110#define VM_SHIFT 17
111
112#define TF_MASK 0x00000100
113#define IF_MASK 0x00000200
114#define DF_MASK 0x00000400
115#define IOPL_MASK 0x00003000
116#define NT_MASK 0x00004000
117#define RF_MASK 0x00010000
118#define VM_MASK 0x00020000
ths5fafdf22007-09-16 21:08:06 +0000119#define AC_MASK 0x00040000
bellard2c0262a2003-09-30 20:34:21 +0000120#define VIF_MASK 0x00080000
121#define VIP_MASK 0x00100000
122#define ID_MASK 0x00200000
123
thsaa1f17c2007-07-11 22:48:58 +0000124/* hidden flags - used internally by qemu to represent additional cpu
bellard33c263d2008-06-04 17:39:33 +0000125 states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
H. Peter Anvina9321a42012-09-26 13:18:43 -0700126 redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK
127 bit positions to ease oring with eflags. */
bellard2c0262a2003-09-30 20:34:21 +0000128/* current cpl */
129#define HF_CPL_SHIFT 0
130/* true if soft mmu is being used */
131#define HF_SOFTMMU_SHIFT 2
132/* true if hardware interrupts must be disabled for next instruction */
133#define HF_INHIBIT_IRQ_SHIFT 3
134/* 16 or 32 segments */
135#define HF_CS32_SHIFT 4
136#define HF_SS32_SHIFT 5
bellarddc196a52004-06-13 13:26:14 +0000137/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
bellard2c0262a2003-09-30 20:34:21 +0000138#define HF_ADDSEG_SHIFT 6
bellard65262d52004-01-04 17:20:53 +0000139/* copy of CR0.PE (protected mode) */
140#define HF_PE_SHIFT 7
141#define HF_TF_SHIFT 8 /* must be same as eflags */
bellard7eee2a52004-02-25 23:17:58 +0000142#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
143#define HF_EM_SHIFT 10
144#define HF_TS_SHIFT 11
bellard65262d52004-01-04 17:20:53 +0000145#define HF_IOPL_SHIFT 12 /* must be same as eflags */
bellard14ce26e2005-01-03 23:50:08 +0000146#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
147#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
Jan Kiszkaa2397802009-05-10 22:30:53 +0200148#define HF_RF_SHIFT 16 /* must be same as eflags */
bellard65262d52004-01-04 17:20:53 +0000149#define HF_VM_SHIFT 17 /* must be same as eflags */
H. Peter Anvina9321a42012-09-26 13:18:43 -0700150#define HF_AC_SHIFT 18 /* must be same as eflags */
bellard3b21e032006-09-24 18:41:56 +0000151#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
bellarddb620f42008-06-04 17:02:19 +0000152#define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
153#define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
Jan Kiszkaa2397802009-05-10 22:30:53 +0200154#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
H. Peter Anvina9321a42012-09-26 13:18:43 -0700155#define HF_SMAP_SHIFT 23 /* CR4.SMAP */
bellard2c0262a2003-09-30 20:34:21 +0000156
157#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
158#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
159#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
160#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
161#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
162#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
bellard65262d52004-01-04 17:20:53 +0000163#define HF_PE_MASK (1 << HF_PE_SHIFT)
bellard58fe2f12004-02-16 22:11:32 +0000164#define HF_TF_MASK (1 << HF_TF_SHIFT)
bellard7eee2a52004-02-25 23:17:58 +0000165#define HF_MP_MASK (1 << HF_MP_SHIFT)
166#define HF_EM_MASK (1 << HF_EM_SHIFT)
167#define HF_TS_MASK (1 << HF_TS_SHIFT)
aliguori0650f1a2008-11-05 15:28:47 +0000168#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
bellard14ce26e2005-01-03 23:50:08 +0000169#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
170#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
Jan Kiszkaa2397802009-05-10 22:30:53 +0200171#define HF_RF_MASK (1 << HF_RF_SHIFT)
aliguori0650f1a2008-11-05 15:28:47 +0000172#define HF_VM_MASK (1 << HF_VM_SHIFT)
H. Peter Anvina9321a42012-09-26 13:18:43 -0700173#define HF_AC_MASK (1 << HF_AC_SHIFT)
bellard3b21e032006-09-24 18:41:56 +0000174#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
bellard872929a2008-05-28 16:16:54 +0000175#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
176#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
Jan Kiszkaa2397802009-05-10 22:30:53 +0200177#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
H. Peter Anvina9321a42012-09-26 13:18:43 -0700178#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +0000179
bellarddb620f42008-06-04 17:02:19 +0000180/* hflags2 */
181
182#define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
183#define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
184#define HF2_NMI_SHIFT 2 /* CPU serving NMI */
185#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
186
187#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
188#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
189#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
190#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
191
aliguori0650f1a2008-11-05 15:28:47 +0000192#define CR0_PE_SHIFT 0
193#define CR0_MP_SHIFT 1
194
bellard2c0262a2003-09-30 20:34:21 +0000195#define CR0_PE_MASK (1 << 0)
bellard7eee2a52004-02-25 23:17:58 +0000196#define CR0_MP_MASK (1 << 1)
197#define CR0_EM_MASK (1 << 2)
bellard2c0262a2003-09-30 20:34:21 +0000198#define CR0_TS_MASK (1 << 3)
bellard2ee73ac2004-05-08 21:08:41 +0000199#define CR0_ET_MASK (1 << 4)
bellard7eee2a52004-02-25 23:17:58 +0000200#define CR0_NE_MASK (1 << 5)
bellard2c0262a2003-09-30 20:34:21 +0000201#define CR0_WP_MASK (1 << 16)
202#define CR0_AM_MASK (1 << 18)
203#define CR0_PG_MASK (1 << 31)
204
205#define CR4_VME_MASK (1 << 0)
206#define CR4_PVI_MASK (1 << 1)
207#define CR4_TSD_MASK (1 << 2)
208#define CR4_DE_MASK (1 << 3)
209#define CR4_PSE_MASK (1 << 4)
bellard64a595f2004-02-03 23:27:13 +0000210#define CR4_PAE_MASK (1 << 5)
Huang Ying79c4f6b2009-06-23 10:05:14 +0800211#define CR4_MCE_MASK (1 << 6)
bellard64a595f2004-02-03 23:27:13 +0000212#define CR4_PGE_MASK (1 << 7)
bellard14ce26e2005-01-03 23:50:08 +0000213#define CR4_PCE_MASK (1 << 8)
aliguori0650f1a2008-11-05 15:28:47 +0000214#define CR4_OSFXSR_SHIFT 9
215#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
bellard14ce26e2005-01-03 23:50:08 +0000216#define CR4_OSXMMEXCPT_MASK (1 << 10)
H. Peter Anvina9321a42012-09-26 13:18:43 -0700217#define CR4_VMXE_MASK (1 << 13)
218#define CR4_SMXE_MASK (1 << 14)
219#define CR4_FSGSBASE_MASK (1 << 16)
220#define CR4_PCIDE_MASK (1 << 17)
221#define CR4_OSXSAVE_MASK (1 << 18)
222#define CR4_SMEP_MASK (1 << 20)
223#define CR4_SMAP_MASK (1 << 21)
bellard2c0262a2003-09-30 20:34:21 +0000224
aliguori01df0402008-11-18 21:08:15 +0000225#define DR6_BD (1 << 13)
226#define DR6_BS (1 << 14)
227#define DR6_BT (1 << 15)
228#define DR6_FIXED_1 0xffff0ff0
229
230#define DR7_GD (1 << 13)
231#define DR7_TYPE_SHIFT 16
232#define DR7_LEN_SHIFT 18
233#define DR7_FIXED_1 0x00000400
liguang428065c2013-01-15 13:39:55 +0800234#define DR7_LOCAL_BP_MASK 0x55
235#define DR7_MAX_BP 4
236#define DR7_TYPE_BP_INST 0x0
237#define DR7_TYPE_DATA_WR 0x1
238#define DR7_TYPE_IO_RW 0x2
239#define DR7_TYPE_DATA_RW 0x3
aliguori01df0402008-11-18 21:08:15 +0000240
bellard2c0262a2003-09-30 20:34:21 +0000241#define PG_PRESENT_BIT 0
242#define PG_RW_BIT 1
243#define PG_USER_BIT 2
244#define PG_PWT_BIT 3
245#define PG_PCD_BIT 4
246#define PG_ACCESSED_BIT 5
247#define PG_DIRTY_BIT 6
248#define PG_PSE_BIT 7
249#define PG_GLOBAL_BIT 8
bellard5cf38392005-11-28 21:02:43 +0000250#define PG_NX_BIT 63
bellard2c0262a2003-09-30 20:34:21 +0000251
252#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
253#define PG_RW_MASK (1 << PG_RW_BIT)
254#define PG_USER_MASK (1 << PG_USER_BIT)
255#define PG_PWT_MASK (1 << PG_PWT_BIT)
256#define PG_PCD_MASK (1 << PG_PCD_BIT)
257#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
258#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
259#define PG_PSE_MASK (1 << PG_PSE_BIT)
260#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
Jan Kiszka3f2cbf02012-03-06 15:22:02 +0100261#define PG_HI_USER_MASK 0x7ff0000000000000LL
bellard5cf38392005-11-28 21:02:43 +0000262#define PG_NX_MASK (1LL << PG_NX_BIT)
bellard2c0262a2003-09-30 20:34:21 +0000263
264#define PG_ERROR_W_BIT 1
265
266#define PG_ERROR_P_MASK 0x01
267#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
268#define PG_ERROR_U_MASK 0x04
269#define PG_ERROR_RSVD_MASK 0x08
bellard5cf38392005-11-28 21:02:43 +0000270#define PG_ERROR_I_D_MASK 0x10
bellard2c0262a2003-09-30 20:34:21 +0000271
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300272#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
273#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800274
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300275#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
Huang Ying79c4f6b2009-06-23 10:05:14 +0800276#define MCE_BANKS_DEF 10
277
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300278#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
279#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
Anthony Liguorie6a05752009-07-10 13:39:34 -0500280#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800281
Anthony Liguorie6a05752009-07-10 13:39:34 -0500282#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
283#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
284#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300285#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
286#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
287#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
288#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
289#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
290#define MCI_STATUS_AR (1ULL<<55) /* Action required */
291
292/* MISC register defines */
293#define MCM_ADDR_SEGOFF 0 /* segment offset */
294#define MCM_ADDR_LINEAR 1 /* linear address */
295#define MCM_ADDR_PHYS 2 /* physical address */
296#define MCM_ADDR_MEM 3 /* memory address */
297#define MCM_ADDR_GENERIC 7 /* generic */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800298
aliguori0650f1a2008-11-05 15:28:47 +0000299#define MSR_IA32_TSC 0x10
bellard2c0262a2003-09-30 20:34:21 +0000300#define MSR_IA32_APICBASE 0x1b
301#define MSR_IA32_APICBASE_BSP (1<<8)
302#define MSR_IA32_APICBASE_ENABLE (1<<11)
303#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
Will Auldf28558d2012-11-26 21:32:18 -0800304#define MSR_TSC_ADJUST 0x0000003b
Liu, Jinsongaa82ba52011-10-05 16:52:32 -0300305#define MSR_IA32_TSCDEADLINE 0x6e0
bellard2c0262a2003-09-30 20:34:21 +0000306
aliguoridd5e3b12009-01-29 17:02:17 +0000307#define MSR_MTRRcap 0xfe
308#define MSR_MTRRcap_VCNT 8
309#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
310#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
311
bellard2c0262a2003-09-30 20:34:21 +0000312#define MSR_IA32_SYSENTER_CS 0x174
313#define MSR_IA32_SYSENTER_ESP 0x175
314#define MSR_IA32_SYSENTER_EIP 0x176
315
bellard8f091a52005-07-23 17:41:26 +0000316#define MSR_MCG_CAP 0x179
317#define MSR_MCG_STATUS 0x17a
318#define MSR_MCG_CTL 0x17b
319
balroge737b322008-09-25 18:11:30 +0000320#define MSR_IA32_PERF_STATUS 0x198
321
Avi Kivity21e87c42011-10-04 16:26:35 +0200322#define MSR_IA32_MISC_ENABLE 0x1a0
323/* Indicates good rep/movs microcode on some processors: */
324#define MSR_IA32_MISC_ENABLE_DEFAULT 1
325
aliguori165d9b82009-01-26 17:53:04 +0000326#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
327#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
328
329#define MSR_MTRRfix64K_00000 0x250
330#define MSR_MTRRfix16K_80000 0x258
331#define MSR_MTRRfix16K_A0000 0x259
332#define MSR_MTRRfix4K_C0000 0x268
333#define MSR_MTRRfix4K_C8000 0x269
334#define MSR_MTRRfix4K_D0000 0x26a
335#define MSR_MTRRfix4K_D8000 0x26b
336#define MSR_MTRRfix4K_E0000 0x26c
337#define MSR_MTRRfix4K_E8000 0x26d
338#define MSR_MTRRfix4K_F0000 0x26e
339#define MSR_MTRRfix4K_F8000 0x26f
340
bellard8f091a52005-07-23 17:41:26 +0000341#define MSR_PAT 0x277
342
aliguori165d9b82009-01-26 17:53:04 +0000343#define MSR_MTRRdefType 0x2ff
344
Huang Ying79c4f6b2009-06-23 10:05:14 +0800345#define MSR_MC0_CTL 0x400
346#define MSR_MC0_STATUS 0x401
347#define MSR_MC0_ADDR 0x402
348#define MSR_MC0_MISC 0x403
349
bellard14ce26e2005-01-03 23:50:08 +0000350#define MSR_EFER 0xc0000080
351
352#define MSR_EFER_SCE (1 << 0)
353#define MSR_EFER_LME (1 << 8)
354#define MSR_EFER_LMA (1 << 10)
355#define MSR_EFER_NXE (1 << 11)
bellard872929a2008-05-28 16:16:54 +0000356#define MSR_EFER_SVME (1 << 12)
bellard14ce26e2005-01-03 23:50:08 +0000357#define MSR_EFER_FFXSR (1 << 14)
358
359#define MSR_STAR 0xc0000081
360#define MSR_LSTAR 0xc0000082
361#define MSR_CSTAR 0xc0000083
362#define MSR_FMASK 0xc0000084
363#define MSR_FSBASE 0xc0000100
364#define MSR_GSBASE 0xc0000101
365#define MSR_KERNELGSBASE 0xc0000102
Andre Przywara1b050072009-09-19 00:30:49 +0200366#define MSR_TSC_AUX 0xc0000103
bellard14ce26e2005-01-03 23:50:08 +0000367
ths0573fbf2007-09-23 15:28:04 +0000368#define MSR_VM_HSAVE_PA 0xc0010117
369
Eduardo Habkost5ef57872013-01-07 16:20:45 -0200370/* CPUID feature words */
371typedef enum FeatureWord {
372 FEAT_1_EDX, /* CPUID[1].EDX */
373 FEAT_1_ECX, /* CPUID[1].ECX */
374 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
375 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
376 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
377 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
378 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
379 FEAT_SVM, /* CPUID[8000_000A].EDX */
380 FEATURE_WORDS,
381} FeatureWord;
382
383typedef uint32_t FeatureWordArray[FEATURE_WORDS];
384
bellard14ce26e2005-01-03 23:50:08 +0000385/* cpuid_features bits */
386#define CPUID_FP87 (1 << 0)
387#define CPUID_VME (1 << 1)
388#define CPUID_DE (1 << 2)
389#define CPUID_PSE (1 << 3)
390#define CPUID_TSC (1 << 4)
391#define CPUID_MSR (1 << 5)
392#define CPUID_PAE (1 << 6)
393#define CPUID_MCE (1 << 7)
394#define CPUID_CX8 (1 << 8)
395#define CPUID_APIC (1 << 9)
396#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
397#define CPUID_MTRR (1 << 12)
398#define CPUID_PGE (1 << 13)
399#define CPUID_MCA (1 << 14)
400#define CPUID_CMOV (1 << 15)
bellard8f091a52005-07-23 17:41:26 +0000401#define CPUID_PAT (1 << 16)
bellard8988ae82006-09-27 19:54:02 +0000402#define CPUID_PSE36 (1 << 17)
bellarda049de62007-11-08 13:28:47 +0000403#define CPUID_PN (1 << 18)
bellard8f091a52005-07-23 17:41:26 +0000404#define CPUID_CLFLUSH (1 << 19)
bellarda049de62007-11-08 13:28:47 +0000405#define CPUID_DTS (1 << 21)
406#define CPUID_ACPI (1 << 22)
bellard14ce26e2005-01-03 23:50:08 +0000407#define CPUID_MMX (1 << 23)
408#define CPUID_FXSR (1 << 24)
409#define CPUID_SSE (1 << 25)
410#define CPUID_SSE2 (1 << 26)
bellarda049de62007-11-08 13:28:47 +0000411#define CPUID_SS (1 << 27)
412#define CPUID_HT (1 << 28)
413#define CPUID_TM (1 << 29)
414#define CPUID_IA64 (1 << 30)
415#define CPUID_PBE (1 << 31)
bellard14ce26e2005-01-03 23:50:08 +0000416
bellard465e9832006-04-23 21:54:01 +0000417#define CPUID_EXT_SSE3 (1 << 0)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300418#define CPUID_EXT_PCLMULQDQ (1 << 1)
pbrook558fa832008-09-29 13:55:36 +0000419#define CPUID_EXT_DTES64 (1 << 2)
bellard9df217a2005-02-10 22:05:51 +0000420#define CPUID_EXT_MONITOR (1 << 3)
bellarda049de62007-11-08 13:28:47 +0000421#define CPUID_EXT_DSCPL (1 << 4)
422#define CPUID_EXT_VMX (1 << 5)
423#define CPUID_EXT_SMX (1 << 6)
424#define CPUID_EXT_EST (1 << 7)
425#define CPUID_EXT_TM2 (1 << 8)
426#define CPUID_EXT_SSSE3 (1 << 9)
427#define CPUID_EXT_CID (1 << 10)
Andre Przywarac8acc382012-11-14 16:28:52 -0200428#define CPUID_EXT_FMA (1 << 12)
bellard9df217a2005-02-10 22:05:51 +0000429#define CPUID_EXT_CX16 (1 << 13)
bellarda049de62007-11-08 13:28:47 +0000430#define CPUID_EXT_XTPR (1 << 14)
pbrook558fa832008-09-29 13:55:36 +0000431#define CPUID_EXT_PDCM (1 << 15)
Andre Przywarac8acc382012-11-14 16:28:52 -0200432#define CPUID_EXT_PCID (1 << 17)
pbrook558fa832008-09-29 13:55:36 +0000433#define CPUID_EXT_DCA (1 << 18)
434#define CPUID_EXT_SSE41 (1 << 19)
435#define CPUID_EXT_SSE42 (1 << 20)
436#define CPUID_EXT_X2APIC (1 << 21)
437#define CPUID_EXT_MOVBE (1 << 22)
438#define CPUID_EXT_POPCNT (1 << 23)
Liu, Jinsonga75b3e02012-07-03 02:35:10 +0800439#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300440#define CPUID_EXT_AES (1 << 25)
pbrook558fa832008-09-29 13:55:36 +0000441#define CPUID_EXT_XSAVE (1 << 26)
442#define CPUID_EXT_OSXSAVE (1 << 27)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300443#define CPUID_EXT_AVX (1 << 28)
Andre Przywarac8acc382012-11-14 16:28:52 -0200444#define CPUID_EXT_F16C (1 << 29)
445#define CPUID_EXT_RDRAND (1 << 30)
Andre Przywara6c0d7ee2009-06-25 00:08:04 +0200446#define CPUID_EXT_HYPERVISOR (1 << 31)
bellard9df217a2005-02-10 22:05:51 +0000447
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300448#define CPUID_EXT2_FPU (1 << 0)
Eduardo Habkost8fad4b42012-09-06 10:05:36 +0000449#define CPUID_EXT2_VME (1 << 1)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300450#define CPUID_EXT2_DE (1 << 2)
451#define CPUID_EXT2_PSE (1 << 3)
452#define CPUID_EXT2_TSC (1 << 4)
453#define CPUID_EXT2_MSR (1 << 5)
454#define CPUID_EXT2_PAE (1 << 6)
455#define CPUID_EXT2_MCE (1 << 7)
456#define CPUID_EXT2_CX8 (1 << 8)
457#define CPUID_EXT2_APIC (1 << 9)
bellard9df217a2005-02-10 22:05:51 +0000458#define CPUID_EXT2_SYSCALL (1 << 11)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300459#define CPUID_EXT2_MTRR (1 << 12)
460#define CPUID_EXT2_PGE (1 << 13)
461#define CPUID_EXT2_MCA (1 << 14)
462#define CPUID_EXT2_CMOV (1 << 15)
463#define CPUID_EXT2_PAT (1 << 16)
464#define CPUID_EXT2_PSE36 (1 << 17)
bellarda049de62007-11-08 13:28:47 +0000465#define CPUID_EXT2_MP (1 << 19)
bellard9df217a2005-02-10 22:05:51 +0000466#define CPUID_EXT2_NX (1 << 20)
bellarda049de62007-11-08 13:28:47 +0000467#define CPUID_EXT2_MMXEXT (1 << 22)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300468#define CPUID_EXT2_MMX (1 << 23)
469#define CPUID_EXT2_FXSR (1 << 24)
bellard8d9bfc22005-04-23 17:46:55 +0000470#define CPUID_EXT2_FFXSR (1 << 25)
bellarda049de62007-11-08 13:28:47 +0000471#define CPUID_EXT2_PDPE1GB (1 << 26)
472#define CPUID_EXT2_RDTSCP (1 << 27)
bellard9df217a2005-02-10 22:05:51 +0000473#define CPUID_EXT2_LM (1 << 29)
bellarda049de62007-11-08 13:28:47 +0000474#define CPUID_EXT2_3DNOWEXT (1 << 30)
475#define CPUID_EXT2_3DNOW (1 << 31)
bellard9df217a2005-02-10 22:05:51 +0000476
Eduardo Habkost8fad4b42012-09-06 10:05:36 +0000477/* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
478#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
479 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
480 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
481 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
482 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
483 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
484 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
485 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
486 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
487
bellarda049de62007-11-08 13:28:47 +0000488#define CPUID_EXT3_LAHF_LM (1 << 0)
489#define CPUID_EXT3_CMP_LEG (1 << 1)
ths0573fbf2007-09-23 15:28:04 +0000490#define CPUID_EXT3_SVM (1 << 2)
bellarda049de62007-11-08 13:28:47 +0000491#define CPUID_EXT3_EXTAPIC (1 << 3)
492#define CPUID_EXT3_CR8LEG (1 << 4)
493#define CPUID_EXT3_ABM (1 << 5)
494#define CPUID_EXT3_SSE4A (1 << 6)
495#define CPUID_EXT3_MISALIGNSSE (1 << 7)
496#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
497#define CPUID_EXT3_OSVW (1 << 9)
498#define CPUID_EXT3_IBS (1 << 10)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300499#define CPUID_EXT3_XOP (1 << 11)
bellard872929a2008-05-28 16:16:54 +0000500#define CPUID_EXT3_SKINIT (1 << 12)
Andre Przywarac8acc382012-11-14 16:28:52 -0200501#define CPUID_EXT3_WDT (1 << 13)
502#define CPUID_EXT3_LWP (1 << 15)
Eduardo Habkosta75b0812012-09-05 17:41:09 -0300503#define CPUID_EXT3_FMA4 (1 << 16)
Andre Przywarac8acc382012-11-14 16:28:52 -0200504#define CPUID_EXT3_TCE (1 << 17)
505#define CPUID_EXT3_NODEID (1 << 19)
506#define CPUID_EXT3_TBM (1 << 21)
507#define CPUID_EXT3_TOPOEXT (1 << 22)
508#define CPUID_EXT3_PERFCORE (1 << 23)
509#define CPUID_EXT3_PERFNB (1 << 24)
ths0573fbf2007-09-23 15:28:04 +0000510
Joerg Roedel296acb62010-09-27 15:16:17 +0200511#define CPUID_SVM_NPT (1 << 0)
512#define CPUID_SVM_LBRV (1 << 1)
513#define CPUID_SVM_SVMLOCK (1 << 2)
514#define CPUID_SVM_NRIPSAVE (1 << 3)
515#define CPUID_SVM_TSCSCALE (1 << 4)
516#define CPUID_SVM_VMCBCLEAN (1 << 5)
517#define CPUID_SVM_FLUSHASID (1 << 6)
518#define CPUID_SVM_DECODEASSIST (1 << 7)
519#define CPUID_SVM_PAUSEFILTER (1 << 10)
520#define CPUID_SVM_PFTHRESHOLD (1 << 12)
521
Andre Przywarac8acc382012-11-14 16:28:52 -0200522#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
523#define CPUID_7_0_EBX_BMI1 (1 << 3)
524#define CPUID_7_0_EBX_HLE (1 << 4)
525#define CPUID_7_0_EBX_AVX2 (1 << 5)
H. Peter Anvina9321a42012-09-26 13:18:43 -0700526#define CPUID_7_0_EBX_SMEP (1 << 7)
Andre Przywarac8acc382012-11-14 16:28:52 -0200527#define CPUID_7_0_EBX_BMI2 (1 << 8)
528#define CPUID_7_0_EBX_ERMS (1 << 9)
529#define CPUID_7_0_EBX_INVPCID (1 << 10)
530#define CPUID_7_0_EBX_RTM (1 << 11)
531#define CPUID_7_0_EBX_RDSEED (1 << 18)
532#define CPUID_7_0_EBX_ADX (1 << 19)
H. Peter Anvina9321a42012-09-26 13:18:43 -0700533#define CPUID_7_0_EBX_SMAP (1 << 20)
534
Igor Mammedov9df694e2012-10-22 17:03:10 +0200535#define CPUID_VENDOR_SZ 12
536
balrogc5096da2008-09-25 18:08:05 +0000537#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
538#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
539#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
540
541#define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
brillywu@viatech.com.cnb3baa152011-06-01 09:59:52 +0800542#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
balrogc5096da2008-09-25 18:08:05 +0000543#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
544
brillywu@viatech.com.cnb3baa152011-06-01 09:59:52 +0800545#define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */
546#define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */
547#define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */
548
balroge737b322008-09-25 18:11:30 +0000549#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
balroga876e282008-09-26 21:03:37 +0000550#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
balroge737b322008-09-25 18:11:30 +0000551
bellard2c0262a2003-09-30 20:34:21 +0000552#define EXCP00_DIVZ 0
aliguori01df0402008-11-18 21:08:15 +0000553#define EXCP01_DB 1
bellard2c0262a2003-09-30 20:34:21 +0000554#define EXCP02_NMI 2
555#define EXCP03_INT3 3
556#define EXCP04_INTO 4
557#define EXCP05_BOUND 5
558#define EXCP06_ILLOP 6
559#define EXCP07_PREX 7
560#define EXCP08_DBLE 8
561#define EXCP09_XERR 9
562#define EXCP0A_TSS 10
563#define EXCP0B_NOSEG 11
564#define EXCP0C_STACK 12
565#define EXCP0D_GPF 13
566#define EXCP0E_PAGE 14
567#define EXCP10_COPR 16
568#define EXCP11_ALGN 17
569#define EXCP12_MCHK 18
570
bellardd2fd1af2007-11-14 18:08:56 +0000571#define EXCP_SYSCALL 0x100 /* only happens in user only emulation
572 for syscall instruction */
573
Richard Henderson00a152b2011-05-04 13:34:30 -0700574/* i386-specific interrupt pending bits. */
Jan Kiszka5d62c432012-07-09 16:42:32 +0200575#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
Richard Henderson00a152b2011-05-04 13:34:30 -0700576#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
Richard Henderson85097db2011-05-04 13:34:31 -0700577#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
Richard Henderson00a152b2011-05-04 13:34:30 -0700578#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
579#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
580#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
581#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
Jan Kiszkad362e752012-02-17 18:31:17 +0100582#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3
Richard Henderson00a152b2011-05-04 13:34:30 -0700583
584
bellard2c0262a2003-09-30 20:34:21 +0000585enum {
586 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
ths1235fc02008-06-03 19:51:57 +0000587 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
bellardd36cd602003-12-02 22:01:31 +0000588
589 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
590 CC_OP_MULW,
591 CC_OP_MULL,
bellard14ce26e2005-01-03 23:50:08 +0000592 CC_OP_MULQ,
bellard2c0262a2003-09-30 20:34:21 +0000593
594 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
595 CC_OP_ADDW,
596 CC_OP_ADDL,
bellard14ce26e2005-01-03 23:50:08 +0000597 CC_OP_ADDQ,
bellard2c0262a2003-09-30 20:34:21 +0000598
599 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
600 CC_OP_ADCW,
601 CC_OP_ADCL,
bellard14ce26e2005-01-03 23:50:08 +0000602 CC_OP_ADCQ,
bellard2c0262a2003-09-30 20:34:21 +0000603
604 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
605 CC_OP_SUBW,
606 CC_OP_SUBL,
bellard14ce26e2005-01-03 23:50:08 +0000607 CC_OP_SUBQ,
bellard2c0262a2003-09-30 20:34:21 +0000608
609 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
610 CC_OP_SBBW,
611 CC_OP_SBBL,
bellard14ce26e2005-01-03 23:50:08 +0000612 CC_OP_SBBQ,
bellard2c0262a2003-09-30 20:34:21 +0000613
614 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
615 CC_OP_LOGICW,
616 CC_OP_LOGICL,
bellard14ce26e2005-01-03 23:50:08 +0000617 CC_OP_LOGICQ,
bellard2c0262a2003-09-30 20:34:21 +0000618
619 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
620 CC_OP_INCW,
621 CC_OP_INCL,
bellard14ce26e2005-01-03 23:50:08 +0000622 CC_OP_INCQ,
bellard2c0262a2003-09-30 20:34:21 +0000623
624 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
625 CC_OP_DECW,
626 CC_OP_DECL,
bellard14ce26e2005-01-03 23:50:08 +0000627 CC_OP_DECQ,
bellard2c0262a2003-09-30 20:34:21 +0000628
bellard6b652792004-07-12 20:33:47 +0000629 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
bellard2c0262a2003-09-30 20:34:21 +0000630 CC_OP_SHLW,
631 CC_OP_SHLL,
bellard14ce26e2005-01-03 23:50:08 +0000632 CC_OP_SHLQ,
bellard2c0262a2003-09-30 20:34:21 +0000633
634 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
635 CC_OP_SARW,
636 CC_OP_SARL,
bellard14ce26e2005-01-03 23:50:08 +0000637 CC_OP_SARQ,
bellard2c0262a2003-09-30 20:34:21 +0000638
639 CC_OP_NB,
640};
641
bellard2c0262a2003-09-30 20:34:21 +0000642typedef struct SegmentCache {
643 uint32_t selector;
bellard14ce26e2005-01-03 23:50:08 +0000644 target_ulong base;
bellard2c0262a2003-09-30 20:34:21 +0000645 uint32_t limit;
646 uint32_t flags;
647} SegmentCache;
648
bellard826461b2005-01-06 20:44:11 +0000649typedef union {
bellard664e0f12005-01-08 18:58:29 +0000650 uint8_t _b[16];
651 uint16_t _w[8];
652 uint32_t _l[4];
653 uint64_t _q[2];
bellard7a0e1f42005-03-13 17:01:47 +0000654 float32 _s[4];
655 float64 _d[2];
bellard14ce26e2005-01-03 23:50:08 +0000656} XMMReg;
657
bellard826461b2005-01-06 20:44:11 +0000658typedef union {
659 uint8_t _b[8];
aurel32a35f3ec2008-04-08 19:51:29 +0000660 uint16_t _w[4];
661 uint32_t _l[2];
662 float32 _s[2];
bellard826461b2005-01-06 20:44:11 +0000663 uint64_t q;
664} MMXReg;
665
Juan Quintelae2542fe2009-07-27 16:13:06 +0200666#ifdef HOST_WORDS_BIGENDIAN
bellard826461b2005-01-06 20:44:11 +0000667#define XMM_B(n) _b[15 - (n)]
668#define XMM_W(n) _w[7 - (n)]
669#define XMM_L(n) _l[3 - (n)]
bellard664e0f12005-01-08 18:58:29 +0000670#define XMM_S(n) _s[3 - (n)]
bellard826461b2005-01-06 20:44:11 +0000671#define XMM_Q(n) _q[1 - (n)]
bellard664e0f12005-01-08 18:58:29 +0000672#define XMM_D(n) _d[1 - (n)]
bellard826461b2005-01-06 20:44:11 +0000673
674#define MMX_B(n) _b[7 - (n)]
675#define MMX_W(n) _w[3 - (n)]
676#define MMX_L(n) _l[1 - (n)]
aurel32a35f3ec2008-04-08 19:51:29 +0000677#define MMX_S(n) _s[1 - (n)]
bellard826461b2005-01-06 20:44:11 +0000678#else
679#define XMM_B(n) _b[n]
680#define XMM_W(n) _w[n]
681#define XMM_L(n) _l[n]
bellard664e0f12005-01-08 18:58:29 +0000682#define XMM_S(n) _s[n]
bellard826461b2005-01-06 20:44:11 +0000683#define XMM_Q(n) _q[n]
bellard664e0f12005-01-08 18:58:29 +0000684#define XMM_D(n) _d[n]
bellard826461b2005-01-06 20:44:11 +0000685
686#define MMX_B(n) _b[n]
687#define MMX_W(n) _w[n]
688#define MMX_L(n) _l[n]
aurel32a35f3ec2008-04-08 19:51:29 +0000689#define MMX_S(n) _s[n]
bellard826461b2005-01-06 20:44:11 +0000690#endif
bellard664e0f12005-01-08 18:58:29 +0000691#define MMX_Q(n) q
bellard826461b2005-01-06 20:44:11 +0000692
Juan Quintelaacc68832009-09-29 22:48:58 +0200693typedef union {
Aurelien Jarnoc31da132011-05-15 14:09:18 +0200694 floatx80 d __attribute__((aligned(16)));
Juan Quintelaacc68832009-09-29 22:48:58 +0200695 MMXReg mmx;
696} FPReg;
697
Juan Quintelac1a54d52009-09-29 22:48:59 +0200698typedef struct {
699 uint64_t base;
700 uint64_t mask;
701} MTRRVar;
702
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200703#define CPU_NB_REGS64 16
704#define CPU_NB_REGS32 8
705
bellard14ce26e2005-01-03 23:50:08 +0000706#ifdef TARGET_X86_64
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200707#define CPU_NB_REGS CPU_NB_REGS64
bellard14ce26e2005-01-03 23:50:08 +0000708#else
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200709#define CPU_NB_REGS CPU_NB_REGS32
bellard14ce26e2005-01-03 23:50:08 +0000710#endif
711
H. Peter Anvina9321a42012-09-26 13:18:43 -0700712#define NB_MMU_MODES 3
j_mayer6ebbf392007-10-14 07:07:08 +0000713
Jan Kiszkad362e752012-02-17 18:31:17 +0100714typedef enum TPRAccess {
715 TPR_ACCESS_READ,
716 TPR_ACCESS_WRITE,
717} TPRAccess;
718
bellard2c0262a2003-09-30 20:34:21 +0000719typedef struct CPUX86State {
720 /* standard registers */
bellard14ce26e2005-01-03 23:50:08 +0000721 target_ulong regs[CPU_NB_REGS];
722 target_ulong eip;
723 target_ulong eflags; /* eflags register. During CPU emulation, CC
bellard2c0262a2003-09-30 20:34:21 +0000724 flags and DF are set to zero because they are
725 stored elsewhere */
726
727 /* emulator internal eflags handling */
bellard14ce26e2005-01-03 23:50:08 +0000728 target_ulong cc_src;
729 target_ulong cc_dst;
bellard2c0262a2003-09-30 20:34:21 +0000730 uint32_t cc_op;
731 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
bellarddb620f42008-06-04 17:02:19 +0000732 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
733 are known at translation time. */
734 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
bellard2c0262a2003-09-30 20:34:21 +0000735
bellard9df217a2005-02-10 22:05:51 +0000736 /* segments */
737 SegmentCache segs[6]; /* selector values */
738 SegmentCache ldt;
739 SegmentCache tr;
740 SegmentCache gdt; /* only base and limit are used */
741 SegmentCache idt; /* only base and limit are used */
742
bellarddb620f42008-06-04 17:02:19 +0000743 target_ulong cr[5]; /* NOTE: cr1 is unused */
Juan Quintela5ee0ffa2009-09-29 22:48:49 +0200744 int32_t a20_mask;
bellard9df217a2005-02-10 22:05:51 +0000745
bellard2c0262a2003-09-30 20:34:21 +0000746 /* FPU state */
747 unsigned int fpstt; /* top of stack index */
Juan Quintela67b8f412009-09-29 22:48:51 +0200748 uint16_t fpus;
Juan Quintelaeb831622009-09-29 22:48:50 +0200749 uint16_t fpuc;
bellard2c0262a2003-09-30 20:34:21 +0000750 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
Juan Quintelaacc68832009-09-29 22:48:58 +0200751 FPReg fpregs[8];
Jan Kiszka42cc8fa2011-06-15 15:17:26 +0200752 /* KVM-only so far */
753 uint16_t fpop;
754 uint64_t fpip;
755 uint64_t fpdp;
bellard2c0262a2003-09-30 20:34:21 +0000756
757 /* emulator internal variables */
bellard7a0e1f42005-03-13 17:01:47 +0000758 float_status fp_status;
Aurelien Jarnoc31da132011-05-15 14:09:18 +0200759 floatx80 ft0;
ths3b46e622007-09-17 08:09:54 +0000760
aurel32a35f3ec2008-04-08 19:51:29 +0000761 float_status mmx_status; /* for 3DNow! float ops */
bellard7a0e1f42005-03-13 17:01:47 +0000762 float_status sse_status;
bellard664e0f12005-01-08 18:58:29 +0000763 uint32_t mxcsr;
bellard14ce26e2005-01-03 23:50:08 +0000764 XMMReg xmm_regs[CPU_NB_REGS];
765 XMMReg xmm_t0;
bellard664e0f12005-01-08 18:58:29 +0000766 MMXReg mmx_t0;
bellard1e4840b2008-05-25 17:26:41 +0000767 target_ulong cc_tmp; /* temporary for rcr/rcl */
bellard14ce26e2005-01-03 23:50:08 +0000768
bellard2c0262a2003-09-30 20:34:21 +0000769 /* sysenter registers */
770 uint32_t sysenter_cs;
balrog2436b612008-09-25 18:16:18 +0000771 target_ulong sysenter_esp;
772 target_ulong sysenter_eip;
bellard8d9bfc22005-04-23 17:46:55 +0000773 uint64_t efer;
774 uint64_t star;
ths0573fbf2007-09-23 15:28:04 +0000775
bellard5cc1d1e2008-06-04 18:29:25 +0000776 uint64_t vm_hsave;
777 uint64_t vm_vmcb;
bellard33c263d2008-06-04 17:39:33 +0000778 uint64_t tsc_offset;
ths0573fbf2007-09-23 15:28:04 +0000779 uint64_t intercept;
780 uint16_t intercept_cr_read;
781 uint16_t intercept_cr_write;
782 uint16_t intercept_dr_read;
783 uint16_t intercept_dr_write;
784 uint32_t intercept_exceptions;
bellarddb620f42008-06-04 17:02:19 +0000785 uint8_t v_tpr;
ths0573fbf2007-09-23 15:28:04 +0000786
bellard14ce26e2005-01-03 23:50:08 +0000787#ifdef TARGET_X86_64
bellard14ce26e2005-01-03 23:50:08 +0000788 target_ulong lstar;
789 target_ulong cstar;
790 target_ulong fmask;
791 target_ulong kernelgsbase;
792#endif
Glauber Costa1a036752009-10-22 10:26:56 -0200793 uint64_t system_time_msr;
794 uint64_t wall_clock_msr;
Gleb Natapovf6584ee2010-10-24 14:27:55 +0200795 uint64_t async_pf_en_msr;
Michael S. Tsirkinbc9a8392012-08-28 20:43:56 +0300796 uint64_t pv_eoi_en_msr;
bellard58fe2f12004-02-16 22:11:32 +0000797
aliguori7ba1e612008-11-05 16:04:33 +0000798 uint64_t tsc;
Will Auldf28558d2012-11-26 21:32:18 -0800799 uint64_t tsc_adjust;
Liu, Jinsongaa82ba52011-10-05 16:52:32 -0300800 uint64_t tsc_deadline;
aliguori7ba1e612008-11-05 16:04:33 +0000801
Jan Kiszka18559232011-03-02 08:56:07 +0100802 uint64_t mcg_status;
Avi Kivity21e87c42011-10-04 16:26:35 +0200803 uint64_t msr_ia32_misc_enable;
Jan Kiszka18559232011-03-02 08:56:07 +0100804
bellard2c0262a2003-09-30 20:34:21 +0000805 /* exception/interrupt handling */
bellard2c0262a2003-09-30 20:34:21 +0000806 int error_code;
807 int exception_is_int;
bellard826461b2005-01-06 20:44:11 +0000808 target_ulong exception_next_eip;
bellard14ce26e2005-01-03 23:50:08 +0000809 target_ulong dr[8]; /* debug registers */
aliguori01df0402008-11-18 21:08:15 +0000810 union {
811 CPUBreakpoint *cpu_breakpoint[4];
812 CPUWatchpoint *cpu_watchpoint[4];
813 }; /* break/watchpoints for dr[0..3] */
bellard3b21e032006-09-24 18:41:56 +0000814 uint32_t smbase;
ths678dde12007-03-31 20:28:52 +0000815 int old_exception; /* exception in flight */
bellard2c0262a2003-09-30 20:34:21 +0000816
Jan Kiszkad8f771d2011-01-21 21:48:21 +0100817 /* KVM states, automatically cleared on reset */
818 uint8_t nmi_injected;
819 uint8_t nmi_pending;
820
bellarda316d332005-11-20 10:32:34 +0000821 CPU_COMMON
bellard2c0262a2003-09-30 20:34:21 +0000822
Jan Kiszkaebda3772011-03-15 12:26:21 +0100823 uint64_t pat;
824
bellard14ce26e2005-01-03 23:50:08 +0000825 /* processor features (e.g. for CPUID insn) */
bellard8d9bfc22005-04-23 17:46:55 +0000826 uint32_t cpuid_level;
bellard14ce26e2005-01-03 23:50:08 +0000827 uint32_t cpuid_vendor1;
828 uint32_t cpuid_vendor2;
829 uint32_t cpuid_vendor3;
830 uint32_t cpuid_version;
831 uint32_t cpuid_features;
bellard9df217a2005-02-10 22:05:51 +0000832 uint32_t cpuid_ext_features;
bellard8d9bfc22005-04-23 17:46:55 +0000833 uint32_t cpuid_xlevel;
834 uint32_t cpuid_model[12];
835 uint32_t cpuid_ext2_features;
ths0573fbf2007-09-23 15:28:04 +0000836 uint32_t cpuid_ext3_features;
thseae76292007-04-03 16:38:34 +0000837 uint32_t cpuid_apic_id;
Andre Przywaraef768132009-06-06 01:03:29 +0200838 int cpuid_vendor_override;
brillywu@viatech.com.cnb3baa152011-06-01 09:59:52 +0800839 /* Store the results of Centaur's CPUID instructions */
840 uint32_t cpuid_xlevel2;
841 uint32_t cpuid_ext4_features;
Eduardo Habkost13526722012-05-21 11:27:02 -0300842 /* Flags from CPUID[EAX=7,ECX=0].EBX */
H. Peter Anvina9321a42012-09-26 13:18:43 -0700843 uint32_t cpuid_7_0_ebx_features;
ths3b46e622007-09-17 08:09:54 +0000844
aliguori165d9b82009-01-26 17:53:04 +0000845 /* MTRRs */
846 uint64_t mtrr_fixed[11];
847 uint64_t mtrr_deftype;
Juan Quintelac1a54d52009-09-29 22:48:59 +0200848 MTRRVar mtrr_var[8];
aliguori165d9b82009-01-26 17:53:04 +0000849
aliguori7ba1e612008-11-05 16:04:33 +0000850 /* For KVM */
Jan Kiszkaf8d926e2009-05-02 02:18:38 +0200851 uint32_t mp_state;
Jan Kiszka31827372009-12-14 12:26:17 +0100852 int32_t exception_injected;
Jan Kiszka0e607a82009-11-06 19:39:24 +0100853 int32_t interrupt_injected;
Jan Kiszkaa0fb0022009-11-25 00:33:03 +0100854 uint8_t soft_interrupt;
Jan Kiszkaa0fb0022009-11-25 00:33:03 +0100855 uint8_t has_error_code;
856 uint32_t sipi_vector;
Gleb Natapovbb0300d2010-01-13 15:25:06 +0200857 uint32_t cpuid_kvm_features;
Joerg Roedel296acb62010-09-27 15:16:17 +0200858 uint32_t cpuid_svm_features;
Glauber Costab8cc45d2011-02-03 14:19:53 -0500859 bool tsc_valid;
Joerg Roedelb862d1f2011-07-07 16:13:12 +0200860 int tsc_khz;
Jan Kiszkafabacc02011-10-27 19:25:58 +0200861 void *kvm_xsave_buf;
862
bellard14ce26e2005-01-03 23:50:08 +0000863 /* in order to simplify APIC support, we leave this pointer to the
864 user */
Blue Swirl92a16d72010-06-19 07:47:42 +0000865 struct DeviceState *apic_state;
Huang Ying79c4f6b2009-06-23 10:05:14 +0800866
Andreas Färberac6c4122010-12-19 17:22:41 +0100867 uint64_t mcg_cap;
Andreas Färberac6c4122010-12-19 17:22:41 +0100868 uint64_t mcg_ctl;
869 uint64_t mce_banks[MCE_BANKS_DEF*4];
Andre Przywara1b050072009-09-19 00:30:49 +0200870
871 uint64_t tsc_aux;
Aurelien Jarno5a2d0e52009-10-05 22:41:04 +0200872
873 /* vmstate */
874 uint16_t fpus_vmstate;
875 uint16_t fptag_vmstate;
876 uint16_t fpregs_format_vmstate;
Sheng Yangf1665b22010-06-17 17:53:07 +0800877
878 uint64_t xstate_bv;
879 XMMReg ymmh_regs[CPU_NB_REGS];
880
881 uint64_t xcr0;
Jan Kiszkad362e752012-02-17 18:31:17 +0100882
883 TPRAccess tpr_access_type;
bellard2c0262a2003-09-30 20:34:21 +0000884} CPUX86State;
885
Andreas Färber5fd20872012-04-02 23:20:08 +0200886#include "cpu-qom.h"
887
Andreas Färberb47ed992012-05-02 18:42:46 +0200888X86CPU *cpu_x86_init(const char *cpu_model);
bellard2c0262a2003-09-30 20:34:21 +0000889int cpu_x86_exec(CPUX86State *s);
Peter Maydelle916cbf2012-09-05 17:41:08 -0300890void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
john cooperb5ec5ce2010-02-20 11:14:59 -0600891void x86_cpudef_setup(void);
Andreas Färber317ac622012-03-14 01:38:21 +0100892int cpu_x86_support_mca_broadcast(CPUX86State *env);
john cooperb5ec5ce2010-02-20 11:14:59 -0600893
bellardd720b932004-04-25 17:57:43 +0000894int cpu_get_pic_interrupt(CPUX86State *s);
bellard2ee73ac2004-05-08 21:08:41 +0000895/* MSDOS compatibility mode FPU exception support */
896void cpu_set_ferr(CPUX86State *s);
bellard2c0262a2003-09-30 20:34:21 +0000897
898/* this function must always be used to load data in the segment
899 cache: it synchronizes the hflags with the segment cache values */
ths5fafdf22007-09-16 21:08:06 +0000900static inline void cpu_x86_load_seg_cache(CPUX86State *env,
bellard2c0262a2003-09-30 20:34:21 +0000901 int seg_reg, unsigned int selector,
bellard8988ae82006-09-27 19:54:02 +0000902 target_ulong base,
ths5fafdf22007-09-16 21:08:06 +0000903 unsigned int limit,
bellard2c0262a2003-09-30 20:34:21 +0000904 unsigned int flags)
905{
906 SegmentCache *sc;
907 unsigned int new_hflags;
ths3b46e622007-09-17 08:09:54 +0000908
bellard2c0262a2003-09-30 20:34:21 +0000909 sc = &env->segs[seg_reg];
910 sc->selector = selector;
911 sc->base = base;
912 sc->limit = limit;
913 sc->flags = flags;
914
915 /* update the hidden flags */
bellard14ce26e2005-01-03 23:50:08 +0000916 {
917 if (seg_reg == R_CS) {
918#ifdef TARGET_X86_64
919 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
920 /* long mode */
921 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
922 env->hflags &= ~(HF_ADDSEG_MASK);
ths5fafdf22007-09-16 21:08:06 +0000923 } else
bellard14ce26e2005-01-03 23:50:08 +0000924#endif
925 {
926 /* legacy / compatibility case */
927 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
928 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
929 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
930 new_hflags;
931 }
932 }
933 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
934 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
935 if (env->hflags & HF_CS64_MASK) {
936 /* zero base assumed for DS, ES and SS in long mode */
ths5fafdf22007-09-16 21:08:06 +0000937 } else if (!(env->cr[0] & CR0_PE_MASK) ||
bellard735a8fd2005-01-12 22:36:43 +0000938 (env->eflags & VM_MASK) ||
939 !(env->hflags & HF_CS32_MASK)) {
bellard14ce26e2005-01-03 23:50:08 +0000940 /* XXX: try to avoid this test. The problem comes from the
941 fact that is real mode or vm86 mode we only modify the
942 'base' and 'selector' fields of the segment cache to go
943 faster. A solution may be to force addseg to one in
944 translate-i386.c. */
945 new_hflags |= HF_ADDSEG_MASK;
946 } else {
ths5fafdf22007-09-16 21:08:06 +0000947 new_hflags |= ((env->segs[R_DS].base |
bellard735a8fd2005-01-12 22:36:43 +0000948 env->segs[R_ES].base |
ths5fafdf22007-09-16 21:08:06 +0000949 env->segs[R_SS].base) != 0) <<
bellard14ce26e2005-01-03 23:50:08 +0000950 HF_ADDSEG_SHIFT;
951 }
ths5fafdf22007-09-16 21:08:06 +0000952 env->hflags = (env->hflags &
bellard14ce26e2005-01-03 23:50:08 +0000953 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
bellard2c0262a2003-09-30 20:34:21 +0000954 }
bellard2c0262a2003-09-30 20:34:21 +0000955}
956
Andreas Färbere9f9d6b2012-05-03 15:37:01 +0200957static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300958 int sipi_vector)
959{
Andreas Färbere9f9d6b2012-05-03 15:37:01 +0200960 CPUX86State *env = &cpu->env;
961
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300962 env->eip = 0;
963 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
964 sipi_vector << 12,
965 env->segs[R_CS].limit,
966 env->segs[R_CS].flags);
967 env->halted = 0;
968}
969
Jan Kiszka84273172009-06-27 09:53:51 +0200970int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
971 target_ulong *base, unsigned int *limit,
972 unsigned int *flags);
973
bellard2c0262a2003-09-30 20:34:21 +0000974/* wrapper, just in case memory mappings must be changed */
975static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
976{
977#if HF_CPL_MASK == 3
978 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
979#else
980#error HF_CPL_MASK is hardcoded
981#endif
982}
983
blueswir1d9957a82008-12-13 11:49:17 +0000984/* op_helper.c */
bellard1f1af9f2004-03-31 18:56:43 +0000985/* used for debug or cpu save/restore */
Aurelien Jarnoc31da132011-05-15 14:09:18 +0200986void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
987floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
bellard1f1af9f2004-03-31 18:56:43 +0000988
blueswir1d9957a82008-12-13 11:49:17 +0000989/* cpu-exec.c */
bellard2c0262a2003-09-30 20:34:21 +0000990/* the following helpers are only usable in user mode simulation as
991 they can trigger unexpected exceptions */
992void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
bellard6f12a2a2007-11-11 22:16:56 +0000993void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
994void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
bellard2c0262a2003-09-30 20:34:21 +0000995
996/* you can call this signal handler from your SIGBUS and SIGSEGV
997 signal handlers to inform the virtual CPU of exceptions. non zero
998 is returned if the signal was handled by the virtual CPU. */
ths5fafdf22007-09-16 21:08:06 +0000999int cpu_x86_signal_handler(int host_signum, void *pinfo,
bellard2c0262a2003-09-30 20:34:21 +00001000 void *puc);
blueswir1d9957a82008-12-13 11:49:17 +00001001
Andre Przywarac6dc6f62010-03-11 14:38:55 +01001002/* cpuid.c */
1003void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1004 uint32_t *eax, uint32_t *ebx,
1005 uint32_t *ecx, uint32_t *edx);
Andreas Färber61dcd772012-04-17 12:00:51 +02001006int cpu_x86_register(X86CPU *cpu, const char *cpu_model);
Blue Swirl0e26b7b2010-06-19 10:42:34 +03001007void cpu_clear_apic_feature(CPUX86State *env);
Jan Kiszkabb44e0d2011-01-21 21:48:07 +01001008void host_cpuid(uint32_t function, uint32_t count,
1009 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
Andre Przywarac6dc6f62010-03-11 14:38:55 +01001010
blueswir1d9957a82008-12-13 11:49:17 +00001011/* helper.c */
1012int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
Blue Swirl97b348e2011-08-01 16:12:17 +00001013 int is_write, int mmu_idx);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -07001014#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
bellard461c0472003-11-04 23:34:23 +00001015void cpu_x86_set_a20(CPUX86State *env, int a20_state);
bellard2c0262a2003-09-30 20:34:21 +00001016
liguang59025642013-01-15 08:01:07 +01001017static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
blueswir1d9957a82008-12-13 11:49:17 +00001018{
liguang59025642013-01-15 08:01:07 +01001019 return (dr7 >> (index * 2)) & 1;
1020}
1021
1022static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
1023{
1024 return (dr7 >> (index * 2)) & 2;
1025
1026}
1027static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
1028{
1029 return hw_global_breakpoint_enabled(dr7, index) ||
1030 hw_local_breakpoint_enabled(dr7, index);
blueswir1d9957a82008-12-13 11:49:17 +00001031}
bellard28ab0e22004-05-20 14:02:14 +00001032
blueswir1d9957a82008-12-13 11:49:17 +00001033static inline int hw_breakpoint_type(unsigned long dr7, int index)
1034{
Jan Kiszkad46272c2009-12-14 12:26:27 +01001035 return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
blueswir1d9957a82008-12-13 11:49:17 +00001036}
1037
1038static inline int hw_breakpoint_len(unsigned long dr7, int index)
1039{
Jan Kiszkad46272c2009-12-14 12:26:27 +01001040 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
blueswir1d9957a82008-12-13 11:49:17 +00001041 return (len == 2) ? 8 : len + 1;
1042}
1043
1044void hw_breakpoint_insert(CPUX86State *env, int index);
1045void hw_breakpoint_remove(CPUX86State *env, int index);
liguange175bce2013-01-15 13:39:56 +08001046bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
Igor Mammedovd65e9812012-06-19 15:39:46 +02001047void breakpoint_handler(CPUX86State *env);
blueswir1d9957a82008-12-13 11:49:17 +00001048
1049/* will be suppressed */
1050void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1051void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1052void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1053
blueswir1d9957a82008-12-13 11:49:17 +00001054/* hw/pc.c */
bellard3b21e032006-09-24 18:41:56 +00001055void cpu_smm_update(CPUX86State *env);
blueswir1d9957a82008-12-13 11:49:17 +00001056uint64_t cpu_get_tsc(CPUX86State *env);
aliguori6fd805e2008-11-05 15:34:06 +00001057
bellard2c0262a2003-09-30 20:34:21 +00001058#define TARGET_PAGE_BITS 12
ths9467d442007-06-03 21:02:38 +00001059
Richard Henderson52705892010-03-10 14:33:23 -08001060#ifdef TARGET_X86_64
1061#define TARGET_PHYS_ADDR_SPACE_BITS 52
1062/* ??? This is really 48 bits, sign-extended, but the only thing
1063 accessible to userland with bit 48 set is the VSYSCALL, and that
1064 is handled via other mechanisms. */
1065#define TARGET_VIRT_ADDR_SPACE_BITS 47
1066#else
1067#define TARGET_PHYS_ADDR_SPACE_BITS 36
1068#define TARGET_VIRT_ADDR_SPACE_BITS 32
1069#endif
1070
Andreas Färberb47ed992012-05-02 18:42:46 +02001071static inline CPUX86State *cpu_init(const char *cpu_model)
1072{
1073 X86CPU *cpu = cpu_x86_init(cpu_model);
1074 if (cpu == NULL) {
1075 return NULL;
1076 }
1077 return &cpu->env;
1078}
1079
ths9467d442007-06-03 21:02:38 +00001080#define cpu_exec cpu_x86_exec
1081#define cpu_gen_code cpu_x86_gen_code
1082#define cpu_signal_handler cpu_x86_signal_handler
Peter Maydelle916cbf2012-09-05 17:41:08 -03001083#define cpu_list x86_cpu_list
john cooperb5ec5ce2010-02-20 11:14:59 -06001084#define cpudef_setup x86_cpudef_setup
ths9467d442007-06-03 21:02:38 +00001085
Marcelo Tosatti38d2c272011-10-24 21:27:16 -02001086#define CPU_SAVE_VERSION 12
pbrookb3c77242008-06-30 16:31:04 +00001087
j_mayer6ebbf392007-10-14 07:07:08 +00001088/* MMU modes definitions */
1089#define MMU_MODE0_SUFFIX _kernel
1090#define MMU_MODE1_SUFFIX _user
H. Peter Anvina9321a42012-09-26 13:18:43 -07001091#define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */
1092#define MMU_KERNEL_IDX 0
1093#define MMU_USER_IDX 1
1094#define MMU_KSMAP_IDX 2
Andreas Färber317ac622012-03-14 01:38:21 +01001095static inline int cpu_mmu_index (CPUX86State *env)
j_mayer6ebbf392007-10-14 07:07:08 +00001096{
H. Peter Anvina9321a42012-09-26 13:18:43 -07001097 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1098 ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
1099 ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
j_mayer6ebbf392007-10-14 07:07:08 +00001100}
1101
Blue Swirlf081c762011-05-21 07:10:23 +00001102#undef EAX
1103#define EAX (env->regs[R_EAX])
1104#undef ECX
1105#define ECX (env->regs[R_ECX])
1106#undef EDX
1107#define EDX (env->regs[R_EDX])
1108#undef EBX
1109#define EBX (env->regs[R_EBX])
1110#undef ESP
1111#define ESP (env->regs[R_ESP])
1112#undef EBP
1113#define EBP (env->regs[R_EBP])
1114#undef ESI
1115#define ESI (env->regs[R_ESI])
1116#undef EDI
1117#define EDI (env->regs[R_EDI])
1118#undef EIP
1119#define EIP (env->eip)
1120#define DF (env->df)
1121
1122#define CC_SRC (env->cc_src)
1123#define CC_DST (env->cc_dst)
1124#define CC_OP (env->cc_op)
1125
Blue Swirl5918fff2012-04-29 12:21:21 +00001126/* n must be a constant to be efficient */
1127static inline target_long lshift(target_long x, int n)
1128{
1129 if (n >= 0) {
1130 return x << n;
1131 } else {
1132 return x >> (-n);
1133 }
1134}
1135
Blue Swirlf081c762011-05-21 07:10:23 +00001136/* float macros */
1137#define FT0 (env->ft0)
1138#define ST0 (env->fpregs[env->fpstt].d)
1139#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1140#define ST1 ST(1)
1141
blueswir1d9957a82008-12-13 11:49:17 +00001142/* translate.c */
bellard26a5f132008-05-28 12:30:31 +00001143void optimize_flags_init(void);
1144
pbrook6e68e072008-05-30 17:22:15 +00001145#if defined(CONFIG_USER_ONLY)
Andreas Färber317ac622012-03-14 01:38:21 +01001146static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp)
pbrook6e68e072008-05-30 17:22:15 +00001147{
pbrookf8ed7072008-05-30 17:54:15 +00001148 if (newsp)
pbrook6e68e072008-05-30 17:22:15 +00001149 env->regs[R_ESP] = newsp;
1150 env->regs[R_EAX] = 0;
1151}
1152#endif
1153
Paolo Bonzini022c62c2012-12-17 18:19:49 +01001154#include "exec/cpu-all.h"
ths0573fbf2007-09-23 15:28:04 +00001155#include "svm.h"
1156
Blue Swirl0e26b7b2010-06-19 10:42:34 +03001157#if !defined(CONFIG_USER_ONLY)
1158#include "hw/apic.h"
1159#endif
1160
Andreas Färber3993c6b2012-05-03 06:43:49 +02001161static inline bool cpu_has_work(CPUState *cpu)
Blue Swirlf081c762011-05-21 07:10:23 +00001162{
Andreas Färber3993c6b2012-05-03 06:43:49 +02001163 CPUX86State *env = &X86_CPU(cpu)->env;
1164
Jan Kiszka5d62c432012-07-09 16:42:32 +02001165 return ((env->interrupt_request & (CPU_INTERRUPT_HARD |
1166 CPU_INTERRUPT_POLL)) &&
Blue Swirlf081c762011-05-21 07:10:23 +00001167 (env->eflags & IF_MASK)) ||
1168 (env->interrupt_request & (CPU_INTERRUPT_NMI |
1169 CPU_INTERRUPT_INIT |
1170 CPU_INTERRUPT_SIPI |
1171 CPU_INTERRUPT_MCE));
1172}
1173
Paolo Bonzini022c62c2012-12-17 18:19:49 +01001174#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +00001175
Andreas Färber317ac622012-03-14 01:38:21 +01001176static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb)
Blue Swirlf081c762011-05-21 07:10:23 +00001177{
1178 env->eip = tb->pc - tb->cs_base;
1179}
1180
Andreas Färber317ac622012-03-14 01:38:21 +01001181static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
aliguori6b917542008-11-18 19:46:41 +00001182 target_ulong *cs_base, int *flags)
1183{
1184 *cs_base = env->segs[R_CS].base;
1185 *pc = *cs_base + env->eip;
Jan Kiszkaa2397802009-05-10 22:30:53 +02001186 *flags = env->hflags |
H. Peter Anvina9321a42012-09-26 13:18:43 -07001187 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
aliguori6b917542008-11-18 19:46:41 +00001188}
1189
Andreas Färber232fc232012-05-05 01:14:41 +02001190void do_cpu_init(X86CPU *cpu);
1191void do_cpu_sipi(X86CPU *cpu);
Jan Kiszka2fa11da2011-03-02 08:56:08 +01001192
Jan Kiszka747461c2011-03-02 08:56:10 +01001193#define MCE_INJECT_BROADCAST 1
1194#define MCE_INJECT_UNCOND_AO 2
1195
Andreas Färber8c5cf3b2012-05-03 15:22:54 +02001196void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
Jan Kiszka316378e2011-03-02 08:56:09 +01001197 uint64_t status, uint64_t mcg_status, uint64_t addr,
Jan Kiszka747461c2011-03-02 08:56:10 +01001198 uint64_t misc, int flags);
Jan Kiszka2fa11da2011-03-02 08:56:08 +01001199
Blue Swirl599b9a52012-04-28 19:53:52 +00001200/* excp_helper.c */
Blue Swirl77b2bc22012-04-28 19:35:10 +00001201void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1202void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1203 int error_code);
Blue Swirl599b9a52012-04-28 19:53:52 +00001204void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1205 int error_code, int next_eip_addend);
1206
Blue Swirl5918fff2012-04-29 12:21:21 +00001207/* cc_helper.c */
1208extern const uint8_t parity_table[256];
1209uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1210
1211static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1212{
1213 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK);
1214}
1215
1216/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
1217static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1218 int update_mask)
1219{
1220 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1221 DF = 1 - (2 * ((eflags >> 10) & 1));
1222 env->eflags = (env->eflags & ~update_mask) |
1223 (eflags & update_mask) | 0x2;
1224}
1225
1226/* load efer and update the corresponding hflags. XXX: do consistency
1227 checks with cpuid bits? */
1228static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1229{
1230 env->efer = val;
1231 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1232 if (env->efer & MSR_EFER_LMA) {
1233 env->hflags |= HF_LMA_MASK;
1234 }
1235 if (env->efer & MSR_EFER_SVME) {
1236 env->hflags |= HF_SVME_MASK;
1237 }
1238}
1239
Blue Swirl6bada5e2012-04-29 14:42:35 +00001240/* svm_helper.c */
1241void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1242 uint64_t param);
1243void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1244
Blue Swirl599b9a52012-04-28 19:53:52 +00001245/* op_helper.c */
1246void do_interrupt(CPUX86State *env);
1247void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
Blue Swirle694d4e2011-05-16 19:38:48 +00001248
Andreas Färber317ac622012-03-14 01:38:21 +01001249void do_smm_enter(CPUX86State *env1);
Blue Swirle694d4e2011-05-16 19:38:48 +00001250
Andreas Färber317ac622012-03-14 01:38:21 +01001251void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
Jan Kiszkad362e752012-02-17 18:31:17 +01001252
Eduardo Habkost29694752013-01-17 18:59:29 -02001253void disable_kvm_pv_eoi(void);
Michael S. Tsirkindc599442012-10-18 00:15:48 +02001254
Eduardo Habkost8b4bedd2013-01-04 20:01:06 -02001255/* Return name of 32-bit register, from a R_* constant */
1256const char *get_register_name_32(unsigned int reg);
1257
Eduardo Habkostcb41bad2013-01-22 18:25:04 -02001258uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index);
1259
bellard2c0262a2003-09-30 20:34:21 +00001260#endif /* CPU_I386_H */