bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 virtual CPU header |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 18 | */ |
| 19 | #ifndef CPU_I386_H |
| 20 | #define CPU_I386_H |
| 21 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 22 | #include "config.h" |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 23 | #include "qemu-common.h" |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 24 | |
| 25 | #ifdef TARGET_X86_64 |
| 26 | #define TARGET_LONG_BITS 64 |
| 27 | #else |
bellard | 3cf1e03 | 2004-01-24 15:19:09 +0000 | [diff] [blame] | 28 | #define TARGET_LONG_BITS 32 |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 29 | #endif |
bellard | 3cf1e03 | 2004-01-24 15:19:09 +0000 | [diff] [blame] | 30 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 31 | /* target supports implicit self modifying code */ |
| 32 | #define TARGET_HAS_SMC |
| 33 | /* support for self modifying code even if the modified instruction is |
| 34 | close to the modifying instruction */ |
| 35 | #define TARGET_HAS_PRECISE_SMC |
| 36 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 37 | #define TARGET_HAS_ICE 1 |
| 38 | |
ths | 9042c0e | 2006-12-23 14:18:40 +0000 | [diff] [blame] | 39 | #ifdef TARGET_X86_64 |
| 40 | #define ELF_MACHINE EM_X86_64 |
| 41 | #else |
| 42 | #define ELF_MACHINE EM_386 |
| 43 | #endif |
| 44 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 45 | #define CPUArchState struct CPUX86State |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 46 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 47 | #include "exec/cpu-defs.h" |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 48 | |
Paolo Bonzini | 6b4c305 | 2012-10-24 13:12:00 +0200 | [diff] [blame] | 49 | #include "fpu/softfloat.h" |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 50 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 51 | #define R_EAX 0 |
| 52 | #define R_ECX 1 |
| 53 | #define R_EDX 2 |
| 54 | #define R_EBX 3 |
| 55 | #define R_ESP 4 |
| 56 | #define R_EBP 5 |
| 57 | #define R_ESI 6 |
| 58 | #define R_EDI 7 |
| 59 | |
| 60 | #define R_AL 0 |
| 61 | #define R_CL 1 |
| 62 | #define R_DL 2 |
| 63 | #define R_BL 3 |
| 64 | #define R_AH 4 |
| 65 | #define R_CH 5 |
| 66 | #define R_DH 6 |
| 67 | #define R_BH 7 |
| 68 | |
| 69 | #define R_ES 0 |
| 70 | #define R_CS 1 |
| 71 | #define R_SS 2 |
| 72 | #define R_DS 3 |
| 73 | #define R_FS 4 |
| 74 | #define R_GS 5 |
| 75 | |
| 76 | /* segment descriptor fields */ |
| 77 | #define DESC_G_MASK (1 << 23) |
| 78 | #define DESC_B_SHIFT 22 |
| 79 | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 80 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
| 81 | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 82 | #define DESC_AVL_MASK (1 << 20) |
| 83 | #define DESC_P_MASK (1 << 15) |
| 84 | #define DESC_DPL_SHIFT 13 |
aliguori | a3867ed | 2009-04-18 15:36:11 +0000 | [diff] [blame] | 85 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 86 | #define DESC_S_MASK (1 << 12) |
| 87 | #define DESC_TYPE_SHIFT 8 |
aliguori | a3867ed | 2009-04-18 15:36:11 +0000 | [diff] [blame] | 88 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 89 | #define DESC_A_MASK (1 << 8) |
| 90 | |
bellard | e670b89 | 2003-11-12 23:23:42 +0000 | [diff] [blame] | 91 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
| 92 | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
| 93 | #define DESC_R_MASK (1 << 9) /* code: readable */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 94 | |
bellard | e670b89 | 2003-11-12 23:23:42 +0000 | [diff] [blame] | 95 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
| 96 | #define DESC_W_MASK (1 << 9) /* data: writable */ |
| 97 | |
| 98 | #define DESC_TSS_BUSY_MASK (1 << 9) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 99 | |
| 100 | /* eflags masks */ |
| 101 | #define CC_C 0x0001 |
| 102 | #define CC_P 0x0004 |
| 103 | #define CC_A 0x0010 |
| 104 | #define CC_Z 0x0040 |
| 105 | #define CC_S 0x0080 |
| 106 | #define CC_O 0x0800 |
| 107 | |
| 108 | #define TF_SHIFT 8 |
| 109 | #define IOPL_SHIFT 12 |
| 110 | #define VM_SHIFT 17 |
| 111 | |
| 112 | #define TF_MASK 0x00000100 |
| 113 | #define IF_MASK 0x00000200 |
| 114 | #define DF_MASK 0x00000400 |
| 115 | #define IOPL_MASK 0x00003000 |
| 116 | #define NT_MASK 0x00004000 |
| 117 | #define RF_MASK 0x00010000 |
| 118 | #define VM_MASK 0x00020000 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 119 | #define AC_MASK 0x00040000 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 120 | #define VIF_MASK 0x00080000 |
| 121 | #define VIP_MASK 0x00100000 |
| 122 | #define ID_MASK 0x00200000 |
| 123 | |
ths | aa1f17c | 2007-07-11 22:48:58 +0000 | [diff] [blame] | 124 | /* hidden flags - used internally by qemu to represent additional cpu |
bellard | 33c263d | 2008-06-04 17:39:33 +0000 | [diff] [blame] | 125 | states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 126 | redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK |
| 127 | bit positions to ease oring with eflags. */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 128 | /* current cpl */ |
| 129 | #define HF_CPL_SHIFT 0 |
| 130 | /* true if soft mmu is being used */ |
| 131 | #define HF_SOFTMMU_SHIFT 2 |
| 132 | /* true if hardware interrupts must be disabled for next instruction */ |
| 133 | #define HF_INHIBIT_IRQ_SHIFT 3 |
| 134 | /* 16 or 32 segments */ |
| 135 | #define HF_CS32_SHIFT 4 |
| 136 | #define HF_SS32_SHIFT 5 |
bellard | dc196a5 | 2004-06-13 13:26:14 +0000 | [diff] [blame] | 137 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 138 | #define HF_ADDSEG_SHIFT 6 |
bellard | 65262d5 | 2004-01-04 17:20:53 +0000 | [diff] [blame] | 139 | /* copy of CR0.PE (protected mode) */ |
| 140 | #define HF_PE_SHIFT 7 |
| 141 | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
bellard | 7eee2a5 | 2004-02-25 23:17:58 +0000 | [diff] [blame] | 142 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
| 143 | #define HF_EM_SHIFT 10 |
| 144 | #define HF_TS_SHIFT 11 |
bellard | 65262d5 | 2004-01-04 17:20:53 +0000 | [diff] [blame] | 145 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 146 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
| 147 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
Jan Kiszka | a239780 | 2009-05-10 22:30:53 +0200 | [diff] [blame] | 148 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
bellard | 65262d5 | 2004-01-04 17:20:53 +0000 | [diff] [blame] | 149 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 150 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 151 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 152 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
| 153 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ |
Jan Kiszka | a239780 | 2009-05-10 22:30:53 +0200 | [diff] [blame] | 154 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 155 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 156 | |
| 157 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
| 158 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
| 159 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
| 160 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
| 161 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
| 162 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
bellard | 65262d5 | 2004-01-04 17:20:53 +0000 | [diff] [blame] | 163 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 164 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
bellard | 7eee2a5 | 2004-02-25 23:17:58 +0000 | [diff] [blame] | 165 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
| 166 | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
| 167 | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
aliguori | 0650f1a | 2008-11-05 15:28:47 +0000 | [diff] [blame] | 168 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 169 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
| 170 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
Jan Kiszka | a239780 | 2009-05-10 22:30:53 +0200 | [diff] [blame] | 171 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
aliguori | 0650f1a | 2008-11-05 15:28:47 +0000 | [diff] [blame] | 172 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 173 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 174 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
bellard | 872929a | 2008-05-28 16:16:54 +0000 | [diff] [blame] | 175 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
| 176 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) |
Jan Kiszka | a239780 | 2009-05-10 22:30:53 +0200 | [diff] [blame] | 177 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 178 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 179 | |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 180 | /* hflags2 */ |
| 181 | |
| 182 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
| 183 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ |
| 184 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ |
| 185 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ |
| 186 | |
| 187 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) |
| 188 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) |
| 189 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) |
| 190 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) |
| 191 | |
aliguori | 0650f1a | 2008-11-05 15:28:47 +0000 | [diff] [blame] | 192 | #define CR0_PE_SHIFT 0 |
| 193 | #define CR0_MP_SHIFT 1 |
| 194 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 195 | #define CR0_PE_MASK (1 << 0) |
bellard | 7eee2a5 | 2004-02-25 23:17:58 +0000 | [diff] [blame] | 196 | #define CR0_MP_MASK (1 << 1) |
| 197 | #define CR0_EM_MASK (1 << 2) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 198 | #define CR0_TS_MASK (1 << 3) |
bellard | 2ee73ac | 2004-05-08 21:08:41 +0000 | [diff] [blame] | 199 | #define CR0_ET_MASK (1 << 4) |
bellard | 7eee2a5 | 2004-02-25 23:17:58 +0000 | [diff] [blame] | 200 | #define CR0_NE_MASK (1 << 5) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 201 | #define CR0_WP_MASK (1 << 16) |
| 202 | #define CR0_AM_MASK (1 << 18) |
| 203 | #define CR0_PG_MASK (1 << 31) |
| 204 | |
| 205 | #define CR4_VME_MASK (1 << 0) |
| 206 | #define CR4_PVI_MASK (1 << 1) |
| 207 | #define CR4_TSD_MASK (1 << 2) |
| 208 | #define CR4_DE_MASK (1 << 3) |
| 209 | #define CR4_PSE_MASK (1 << 4) |
bellard | 64a595f | 2004-02-03 23:27:13 +0000 | [diff] [blame] | 210 | #define CR4_PAE_MASK (1 << 5) |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 211 | #define CR4_MCE_MASK (1 << 6) |
bellard | 64a595f | 2004-02-03 23:27:13 +0000 | [diff] [blame] | 212 | #define CR4_PGE_MASK (1 << 7) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 213 | #define CR4_PCE_MASK (1 << 8) |
aliguori | 0650f1a | 2008-11-05 15:28:47 +0000 | [diff] [blame] | 214 | #define CR4_OSFXSR_SHIFT 9 |
| 215 | #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 216 | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 217 | #define CR4_VMXE_MASK (1 << 13) |
| 218 | #define CR4_SMXE_MASK (1 << 14) |
| 219 | #define CR4_FSGSBASE_MASK (1 << 16) |
| 220 | #define CR4_PCIDE_MASK (1 << 17) |
| 221 | #define CR4_OSXSAVE_MASK (1 << 18) |
| 222 | #define CR4_SMEP_MASK (1 << 20) |
| 223 | #define CR4_SMAP_MASK (1 << 21) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 224 | |
aliguori | 01df040 | 2008-11-18 21:08:15 +0000 | [diff] [blame] | 225 | #define DR6_BD (1 << 13) |
| 226 | #define DR6_BS (1 << 14) |
| 227 | #define DR6_BT (1 << 15) |
| 228 | #define DR6_FIXED_1 0xffff0ff0 |
| 229 | |
| 230 | #define DR7_GD (1 << 13) |
| 231 | #define DR7_TYPE_SHIFT 16 |
| 232 | #define DR7_LEN_SHIFT 18 |
| 233 | #define DR7_FIXED_1 0x00000400 |
liguang | 428065c | 2013-01-15 13:39:55 +0800 | [diff] [blame] | 234 | #define DR7_LOCAL_BP_MASK 0x55 |
| 235 | #define DR7_MAX_BP 4 |
| 236 | #define DR7_TYPE_BP_INST 0x0 |
| 237 | #define DR7_TYPE_DATA_WR 0x1 |
| 238 | #define DR7_TYPE_IO_RW 0x2 |
| 239 | #define DR7_TYPE_DATA_RW 0x3 |
aliguori | 01df040 | 2008-11-18 21:08:15 +0000 | [diff] [blame] | 240 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 241 | #define PG_PRESENT_BIT 0 |
| 242 | #define PG_RW_BIT 1 |
| 243 | #define PG_USER_BIT 2 |
| 244 | #define PG_PWT_BIT 3 |
| 245 | #define PG_PCD_BIT 4 |
| 246 | #define PG_ACCESSED_BIT 5 |
| 247 | #define PG_DIRTY_BIT 6 |
| 248 | #define PG_PSE_BIT 7 |
| 249 | #define PG_GLOBAL_BIT 8 |
bellard | 5cf3839 | 2005-11-28 21:02:43 +0000 | [diff] [blame] | 250 | #define PG_NX_BIT 63 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 251 | |
| 252 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
| 253 | #define PG_RW_MASK (1 << PG_RW_BIT) |
| 254 | #define PG_USER_MASK (1 << PG_USER_BIT) |
| 255 | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
| 256 | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
| 257 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
| 258 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
| 259 | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
| 260 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
Jan Kiszka | 3f2cbf0 | 2012-03-06 15:22:02 +0100 | [diff] [blame] | 261 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
bellard | 5cf3839 | 2005-11-28 21:02:43 +0000 | [diff] [blame] | 262 | #define PG_NX_MASK (1LL << PG_NX_BIT) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 263 | |
| 264 | #define PG_ERROR_W_BIT 1 |
| 265 | |
| 266 | #define PG_ERROR_P_MASK 0x01 |
| 267 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
| 268 | #define PG_ERROR_U_MASK 0x04 |
| 269 | #define PG_ERROR_RSVD_MASK 0x08 |
bellard | 5cf3839 | 2005-11-28 21:02:43 +0000 | [diff] [blame] | 270 | #define PG_ERROR_I_D_MASK 0x10 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 271 | |
Marcelo Tosatti | c0532a7 | 2010-10-11 15:31:21 -0300 | [diff] [blame] | 272 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
| 273 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 274 | |
Marcelo Tosatti | c0532a7 | 2010-10-11 15:31:21 -0300 | [diff] [blame] | 275 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 276 | #define MCE_BANKS_DEF 10 |
| 277 | |
Marcelo Tosatti | c0532a7 | 2010-10-11 15:31:21 -0300 | [diff] [blame] | 278 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
| 279 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
Anthony Liguori | e6a0575 | 2009-07-10 13:39:34 -0500 | [diff] [blame] | 280 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 281 | |
Anthony Liguori | e6a0575 | 2009-07-10 13:39:34 -0500 | [diff] [blame] | 282 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| 283 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| 284 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
Marcelo Tosatti | c0532a7 | 2010-10-11 15:31:21 -0300 | [diff] [blame] | 285 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
| 286 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
| 287 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
| 288 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
| 289 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
| 290 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
| 291 | |
| 292 | /* MISC register defines */ |
| 293 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
| 294 | #define MCM_ADDR_LINEAR 1 /* linear address */ |
| 295 | #define MCM_ADDR_PHYS 2 /* physical address */ |
| 296 | #define MCM_ADDR_MEM 3 /* memory address */ |
| 297 | #define MCM_ADDR_GENERIC 7 /* generic */ |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 298 | |
aliguori | 0650f1a | 2008-11-05 15:28:47 +0000 | [diff] [blame] | 299 | #define MSR_IA32_TSC 0x10 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 300 | #define MSR_IA32_APICBASE 0x1b |
| 301 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| 302 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
| 303 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
Will Auld | f28558d | 2012-11-26 21:32:18 -0800 | [diff] [blame] | 304 | #define MSR_TSC_ADJUST 0x0000003b |
Liu, Jinsong | aa82ba5 | 2011-10-05 16:52:32 -0300 | [diff] [blame] | 305 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 306 | |
aliguori | dd5e3b1 | 2009-01-29 17:02:17 +0000 | [diff] [blame] | 307 | #define MSR_MTRRcap 0xfe |
| 308 | #define MSR_MTRRcap_VCNT 8 |
| 309 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) |
| 310 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) |
| 311 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 312 | #define MSR_IA32_SYSENTER_CS 0x174 |
| 313 | #define MSR_IA32_SYSENTER_ESP 0x175 |
| 314 | #define MSR_IA32_SYSENTER_EIP 0x176 |
| 315 | |
bellard | 8f091a5 | 2005-07-23 17:41:26 +0000 | [diff] [blame] | 316 | #define MSR_MCG_CAP 0x179 |
| 317 | #define MSR_MCG_STATUS 0x17a |
| 318 | #define MSR_MCG_CTL 0x17b |
| 319 | |
balrog | e737b32 | 2008-09-25 18:11:30 +0000 | [diff] [blame] | 320 | #define MSR_IA32_PERF_STATUS 0x198 |
| 321 | |
Avi Kivity | 21e87c4 | 2011-10-04 16:26:35 +0200 | [diff] [blame] | 322 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
| 323 | /* Indicates good rep/movs microcode on some processors: */ |
| 324 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 |
| 325 | |
aliguori | 165d9b8 | 2009-01-26 17:53:04 +0000 | [diff] [blame] | 326 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
| 327 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) |
| 328 | |
| 329 | #define MSR_MTRRfix64K_00000 0x250 |
| 330 | #define MSR_MTRRfix16K_80000 0x258 |
| 331 | #define MSR_MTRRfix16K_A0000 0x259 |
| 332 | #define MSR_MTRRfix4K_C0000 0x268 |
| 333 | #define MSR_MTRRfix4K_C8000 0x269 |
| 334 | #define MSR_MTRRfix4K_D0000 0x26a |
| 335 | #define MSR_MTRRfix4K_D8000 0x26b |
| 336 | #define MSR_MTRRfix4K_E0000 0x26c |
| 337 | #define MSR_MTRRfix4K_E8000 0x26d |
| 338 | #define MSR_MTRRfix4K_F0000 0x26e |
| 339 | #define MSR_MTRRfix4K_F8000 0x26f |
| 340 | |
bellard | 8f091a5 | 2005-07-23 17:41:26 +0000 | [diff] [blame] | 341 | #define MSR_PAT 0x277 |
| 342 | |
aliguori | 165d9b8 | 2009-01-26 17:53:04 +0000 | [diff] [blame] | 343 | #define MSR_MTRRdefType 0x2ff |
| 344 | |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 345 | #define MSR_MC0_CTL 0x400 |
| 346 | #define MSR_MC0_STATUS 0x401 |
| 347 | #define MSR_MC0_ADDR 0x402 |
| 348 | #define MSR_MC0_MISC 0x403 |
| 349 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 350 | #define MSR_EFER 0xc0000080 |
| 351 | |
| 352 | #define MSR_EFER_SCE (1 << 0) |
| 353 | #define MSR_EFER_LME (1 << 8) |
| 354 | #define MSR_EFER_LMA (1 << 10) |
| 355 | #define MSR_EFER_NXE (1 << 11) |
bellard | 872929a | 2008-05-28 16:16:54 +0000 | [diff] [blame] | 356 | #define MSR_EFER_SVME (1 << 12) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 357 | #define MSR_EFER_FFXSR (1 << 14) |
| 358 | |
| 359 | #define MSR_STAR 0xc0000081 |
| 360 | #define MSR_LSTAR 0xc0000082 |
| 361 | #define MSR_CSTAR 0xc0000083 |
| 362 | #define MSR_FMASK 0xc0000084 |
| 363 | #define MSR_FSBASE 0xc0000100 |
| 364 | #define MSR_GSBASE 0xc0000101 |
| 365 | #define MSR_KERNELGSBASE 0xc0000102 |
Andre Przywara | 1b05007 | 2009-09-19 00:30:49 +0200 | [diff] [blame] | 366 | #define MSR_TSC_AUX 0xc0000103 |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 367 | |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 368 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 369 | |
Eduardo Habkost | 5ef5787 | 2013-01-07 16:20:45 -0200 | [diff] [blame] | 370 | /* CPUID feature words */ |
| 371 | typedef enum FeatureWord { |
| 372 | FEAT_1_EDX, /* CPUID[1].EDX */ |
| 373 | FEAT_1_ECX, /* CPUID[1].ECX */ |
| 374 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ |
| 375 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
| 376 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ |
| 377 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
| 378 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ |
| 379 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
| 380 | FEATURE_WORDS, |
| 381 | } FeatureWord; |
| 382 | |
| 383 | typedef uint32_t FeatureWordArray[FEATURE_WORDS]; |
| 384 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 385 | /* cpuid_features bits */ |
| 386 | #define CPUID_FP87 (1 << 0) |
| 387 | #define CPUID_VME (1 << 1) |
| 388 | #define CPUID_DE (1 << 2) |
| 389 | #define CPUID_PSE (1 << 3) |
| 390 | #define CPUID_TSC (1 << 4) |
| 391 | #define CPUID_MSR (1 << 5) |
| 392 | #define CPUID_PAE (1 << 6) |
| 393 | #define CPUID_MCE (1 << 7) |
| 394 | #define CPUID_CX8 (1 << 8) |
| 395 | #define CPUID_APIC (1 << 9) |
| 396 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
| 397 | #define CPUID_MTRR (1 << 12) |
| 398 | #define CPUID_PGE (1 << 13) |
| 399 | #define CPUID_MCA (1 << 14) |
| 400 | #define CPUID_CMOV (1 << 15) |
bellard | 8f091a5 | 2005-07-23 17:41:26 +0000 | [diff] [blame] | 401 | #define CPUID_PAT (1 << 16) |
bellard | 8988ae8 | 2006-09-27 19:54:02 +0000 | [diff] [blame] | 402 | #define CPUID_PSE36 (1 << 17) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 403 | #define CPUID_PN (1 << 18) |
bellard | 8f091a5 | 2005-07-23 17:41:26 +0000 | [diff] [blame] | 404 | #define CPUID_CLFLUSH (1 << 19) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 405 | #define CPUID_DTS (1 << 21) |
| 406 | #define CPUID_ACPI (1 << 22) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 407 | #define CPUID_MMX (1 << 23) |
| 408 | #define CPUID_FXSR (1 << 24) |
| 409 | #define CPUID_SSE (1 << 25) |
| 410 | #define CPUID_SSE2 (1 << 26) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 411 | #define CPUID_SS (1 << 27) |
| 412 | #define CPUID_HT (1 << 28) |
| 413 | #define CPUID_TM (1 << 29) |
| 414 | #define CPUID_IA64 (1 << 30) |
| 415 | #define CPUID_PBE (1 << 31) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 416 | |
bellard | 465e983 | 2006-04-23 21:54:01 +0000 | [diff] [blame] | 417 | #define CPUID_EXT_SSE3 (1 << 0) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 418 | #define CPUID_EXT_PCLMULQDQ (1 << 1) |
pbrook | 558fa83 | 2008-09-29 13:55:36 +0000 | [diff] [blame] | 419 | #define CPUID_EXT_DTES64 (1 << 2) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 420 | #define CPUID_EXT_MONITOR (1 << 3) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 421 | #define CPUID_EXT_DSCPL (1 << 4) |
| 422 | #define CPUID_EXT_VMX (1 << 5) |
| 423 | #define CPUID_EXT_SMX (1 << 6) |
| 424 | #define CPUID_EXT_EST (1 << 7) |
| 425 | #define CPUID_EXT_TM2 (1 << 8) |
| 426 | #define CPUID_EXT_SSSE3 (1 << 9) |
| 427 | #define CPUID_EXT_CID (1 << 10) |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 428 | #define CPUID_EXT_FMA (1 << 12) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 429 | #define CPUID_EXT_CX16 (1 << 13) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 430 | #define CPUID_EXT_XTPR (1 << 14) |
pbrook | 558fa83 | 2008-09-29 13:55:36 +0000 | [diff] [blame] | 431 | #define CPUID_EXT_PDCM (1 << 15) |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 432 | #define CPUID_EXT_PCID (1 << 17) |
pbrook | 558fa83 | 2008-09-29 13:55:36 +0000 | [diff] [blame] | 433 | #define CPUID_EXT_DCA (1 << 18) |
| 434 | #define CPUID_EXT_SSE41 (1 << 19) |
| 435 | #define CPUID_EXT_SSE42 (1 << 20) |
| 436 | #define CPUID_EXT_X2APIC (1 << 21) |
| 437 | #define CPUID_EXT_MOVBE (1 << 22) |
| 438 | #define CPUID_EXT_POPCNT (1 << 23) |
Liu, Jinsong | a75b3e0 | 2012-07-03 02:35:10 +0800 | [diff] [blame] | 439 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 440 | #define CPUID_EXT_AES (1 << 25) |
pbrook | 558fa83 | 2008-09-29 13:55:36 +0000 | [diff] [blame] | 441 | #define CPUID_EXT_XSAVE (1 << 26) |
| 442 | #define CPUID_EXT_OSXSAVE (1 << 27) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 443 | #define CPUID_EXT_AVX (1 << 28) |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 444 | #define CPUID_EXT_F16C (1 << 29) |
| 445 | #define CPUID_EXT_RDRAND (1 << 30) |
Andre Przywara | 6c0d7ee | 2009-06-25 00:08:04 +0200 | [diff] [blame] | 446 | #define CPUID_EXT_HYPERVISOR (1 << 31) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 447 | |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 448 | #define CPUID_EXT2_FPU (1 << 0) |
Eduardo Habkost | 8fad4b4 | 2012-09-06 10:05:36 +0000 | [diff] [blame] | 449 | #define CPUID_EXT2_VME (1 << 1) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 450 | #define CPUID_EXT2_DE (1 << 2) |
| 451 | #define CPUID_EXT2_PSE (1 << 3) |
| 452 | #define CPUID_EXT2_TSC (1 << 4) |
| 453 | #define CPUID_EXT2_MSR (1 << 5) |
| 454 | #define CPUID_EXT2_PAE (1 << 6) |
| 455 | #define CPUID_EXT2_MCE (1 << 7) |
| 456 | #define CPUID_EXT2_CX8 (1 << 8) |
| 457 | #define CPUID_EXT2_APIC (1 << 9) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 458 | #define CPUID_EXT2_SYSCALL (1 << 11) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 459 | #define CPUID_EXT2_MTRR (1 << 12) |
| 460 | #define CPUID_EXT2_PGE (1 << 13) |
| 461 | #define CPUID_EXT2_MCA (1 << 14) |
| 462 | #define CPUID_EXT2_CMOV (1 << 15) |
| 463 | #define CPUID_EXT2_PAT (1 << 16) |
| 464 | #define CPUID_EXT2_PSE36 (1 << 17) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 465 | #define CPUID_EXT2_MP (1 << 19) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 466 | #define CPUID_EXT2_NX (1 << 20) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 467 | #define CPUID_EXT2_MMXEXT (1 << 22) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 468 | #define CPUID_EXT2_MMX (1 << 23) |
| 469 | #define CPUID_EXT2_FXSR (1 << 24) |
bellard | 8d9bfc2 | 2005-04-23 17:46:55 +0000 | [diff] [blame] | 470 | #define CPUID_EXT2_FFXSR (1 << 25) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 471 | #define CPUID_EXT2_PDPE1GB (1 << 26) |
| 472 | #define CPUID_EXT2_RDTSCP (1 << 27) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 473 | #define CPUID_EXT2_LM (1 << 29) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 474 | #define CPUID_EXT2_3DNOWEXT (1 << 30) |
| 475 | #define CPUID_EXT2_3DNOW (1 << 31) |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 476 | |
Eduardo Habkost | 8fad4b4 | 2012-09-06 10:05:36 +0000 | [diff] [blame] | 477 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ |
| 478 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ |
| 479 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ |
| 480 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ |
| 481 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ |
| 482 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ |
| 483 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ |
| 484 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ |
| 485 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ |
| 486 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) |
| 487 | |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 488 | #define CPUID_EXT3_LAHF_LM (1 << 0) |
| 489 | #define CPUID_EXT3_CMP_LEG (1 << 1) |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 490 | #define CPUID_EXT3_SVM (1 << 2) |
bellard | a049de6 | 2007-11-08 13:28:47 +0000 | [diff] [blame] | 491 | #define CPUID_EXT3_EXTAPIC (1 << 3) |
| 492 | #define CPUID_EXT3_CR8LEG (1 << 4) |
| 493 | #define CPUID_EXT3_ABM (1 << 5) |
| 494 | #define CPUID_EXT3_SSE4A (1 << 6) |
| 495 | #define CPUID_EXT3_MISALIGNSSE (1 << 7) |
| 496 | #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) |
| 497 | #define CPUID_EXT3_OSVW (1 << 9) |
| 498 | #define CPUID_EXT3_IBS (1 << 10) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 499 | #define CPUID_EXT3_XOP (1 << 11) |
bellard | 872929a | 2008-05-28 16:16:54 +0000 | [diff] [blame] | 500 | #define CPUID_EXT3_SKINIT (1 << 12) |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 501 | #define CPUID_EXT3_WDT (1 << 13) |
| 502 | #define CPUID_EXT3_LWP (1 << 15) |
Eduardo Habkost | a75b081 | 2012-09-05 17:41:09 -0300 | [diff] [blame] | 503 | #define CPUID_EXT3_FMA4 (1 << 16) |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 504 | #define CPUID_EXT3_TCE (1 << 17) |
| 505 | #define CPUID_EXT3_NODEID (1 << 19) |
| 506 | #define CPUID_EXT3_TBM (1 << 21) |
| 507 | #define CPUID_EXT3_TOPOEXT (1 << 22) |
| 508 | #define CPUID_EXT3_PERFCORE (1 << 23) |
| 509 | #define CPUID_EXT3_PERFNB (1 << 24) |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 510 | |
Joerg Roedel | 296acb6 | 2010-09-27 15:16:17 +0200 | [diff] [blame] | 511 | #define CPUID_SVM_NPT (1 << 0) |
| 512 | #define CPUID_SVM_LBRV (1 << 1) |
| 513 | #define CPUID_SVM_SVMLOCK (1 << 2) |
| 514 | #define CPUID_SVM_NRIPSAVE (1 << 3) |
| 515 | #define CPUID_SVM_TSCSCALE (1 << 4) |
| 516 | #define CPUID_SVM_VMCBCLEAN (1 << 5) |
| 517 | #define CPUID_SVM_FLUSHASID (1 << 6) |
| 518 | #define CPUID_SVM_DECODEASSIST (1 << 7) |
| 519 | #define CPUID_SVM_PAUSEFILTER (1 << 10) |
| 520 | #define CPUID_SVM_PFTHRESHOLD (1 << 12) |
| 521 | |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 522 | #define CPUID_7_0_EBX_FSGSBASE (1 << 0) |
| 523 | #define CPUID_7_0_EBX_BMI1 (1 << 3) |
| 524 | #define CPUID_7_0_EBX_HLE (1 << 4) |
| 525 | #define CPUID_7_0_EBX_AVX2 (1 << 5) |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 526 | #define CPUID_7_0_EBX_SMEP (1 << 7) |
Andre Przywara | c8acc38 | 2012-11-14 16:28:52 -0200 | [diff] [blame] | 527 | #define CPUID_7_0_EBX_BMI2 (1 << 8) |
| 528 | #define CPUID_7_0_EBX_ERMS (1 << 9) |
| 529 | #define CPUID_7_0_EBX_INVPCID (1 << 10) |
| 530 | #define CPUID_7_0_EBX_RTM (1 << 11) |
| 531 | #define CPUID_7_0_EBX_RDSEED (1 << 18) |
| 532 | #define CPUID_7_0_EBX_ADX (1 << 19) |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 533 | #define CPUID_7_0_EBX_SMAP (1 << 20) |
| 534 | |
Igor Mammedov | 9df694e | 2012-10-22 17:03:10 +0200 | [diff] [blame] | 535 | #define CPUID_VENDOR_SZ 12 |
| 536 | |
balrog | c5096da | 2008-09-25 18:08:05 +0000 | [diff] [blame] | 537 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
| 538 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ |
| 539 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
| 540 | |
| 541 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
brillywu@viatech.com.cn | b3baa15 | 2011-06-01 09:59:52 +0800 | [diff] [blame] | 542 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
balrog | c5096da | 2008-09-25 18:08:05 +0000 | [diff] [blame] | 543 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
| 544 | |
brillywu@viatech.com.cn | b3baa15 | 2011-06-01 09:59:52 +0800 | [diff] [blame] | 545 | #define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ |
| 546 | #define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ |
| 547 | #define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ |
| 548 | |
balrog | e737b32 | 2008-09-25 18:11:30 +0000 | [diff] [blame] | 549 | #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
balrog | a876e28 | 2008-09-26 21:03:37 +0000 | [diff] [blame] | 550 | #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
balrog | e737b32 | 2008-09-25 18:11:30 +0000 | [diff] [blame] | 551 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 552 | #define EXCP00_DIVZ 0 |
aliguori | 01df040 | 2008-11-18 21:08:15 +0000 | [diff] [blame] | 553 | #define EXCP01_DB 1 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 554 | #define EXCP02_NMI 2 |
| 555 | #define EXCP03_INT3 3 |
| 556 | #define EXCP04_INTO 4 |
| 557 | #define EXCP05_BOUND 5 |
| 558 | #define EXCP06_ILLOP 6 |
| 559 | #define EXCP07_PREX 7 |
| 560 | #define EXCP08_DBLE 8 |
| 561 | #define EXCP09_XERR 9 |
| 562 | #define EXCP0A_TSS 10 |
| 563 | #define EXCP0B_NOSEG 11 |
| 564 | #define EXCP0C_STACK 12 |
| 565 | #define EXCP0D_GPF 13 |
| 566 | #define EXCP0E_PAGE 14 |
| 567 | #define EXCP10_COPR 16 |
| 568 | #define EXCP11_ALGN 17 |
| 569 | #define EXCP12_MCHK 18 |
| 570 | |
bellard | d2fd1af | 2007-11-14 18:08:56 +0000 | [diff] [blame] | 571 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
| 572 | for syscall instruction */ |
| 573 | |
Richard Henderson | 00a152b | 2011-05-04 13:34:30 -0700 | [diff] [blame] | 574 | /* i386-specific interrupt pending bits. */ |
Jan Kiszka | 5d62c43 | 2012-07-09 16:42:32 +0200 | [diff] [blame] | 575 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
Richard Henderson | 00a152b | 2011-05-04 13:34:30 -0700 | [diff] [blame] | 576 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
Richard Henderson | 85097db | 2011-05-04 13:34:31 -0700 | [diff] [blame] | 577 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
Richard Henderson | 00a152b | 2011-05-04 13:34:30 -0700 | [diff] [blame] | 578 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
| 579 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 |
| 580 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 |
| 581 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 |
Jan Kiszka | d362e75 | 2012-02-17 18:31:17 +0100 | [diff] [blame] | 582 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 |
Richard Henderson | 00a152b | 2011-05-04 13:34:30 -0700 | [diff] [blame] | 583 | |
| 584 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 585 | enum { |
| 586 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
ths | 1235fc0 | 2008-06-03 19:51:57 +0000 | [diff] [blame] | 587 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
bellard | d36cd60 | 2003-12-02 22:01:31 +0000 | [diff] [blame] | 588 | |
| 589 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ |
| 590 | CC_OP_MULW, |
| 591 | CC_OP_MULL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 592 | CC_OP_MULQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 593 | |
| 594 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 595 | CC_OP_ADDW, |
| 596 | CC_OP_ADDL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 597 | CC_OP_ADDQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 598 | |
| 599 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 600 | CC_OP_ADCW, |
| 601 | CC_OP_ADCL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 602 | CC_OP_ADCQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 603 | |
| 604 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 605 | CC_OP_SUBW, |
| 606 | CC_OP_SUBL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 607 | CC_OP_SUBQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 608 | |
| 609 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 610 | CC_OP_SBBW, |
| 611 | CC_OP_SBBL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 612 | CC_OP_SBBQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 613 | |
| 614 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ |
| 615 | CC_OP_LOGICW, |
| 616 | CC_OP_LOGICL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 617 | CC_OP_LOGICQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 618 | |
| 619 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
| 620 | CC_OP_INCW, |
| 621 | CC_OP_INCL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 622 | CC_OP_INCQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 623 | |
| 624 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
| 625 | CC_OP_DECW, |
| 626 | CC_OP_DECL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 627 | CC_OP_DECQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 628 | |
bellard | 6b65279 | 2004-07-12 20:33:47 +0000 | [diff] [blame] | 629 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 630 | CC_OP_SHLW, |
| 631 | CC_OP_SHLL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 632 | CC_OP_SHLQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 633 | |
| 634 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ |
| 635 | CC_OP_SARW, |
| 636 | CC_OP_SARL, |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 637 | CC_OP_SARQ, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 638 | |
| 639 | CC_OP_NB, |
| 640 | }; |
| 641 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 642 | typedef struct SegmentCache { |
| 643 | uint32_t selector; |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 644 | target_ulong base; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 645 | uint32_t limit; |
| 646 | uint32_t flags; |
| 647 | } SegmentCache; |
| 648 | |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 649 | typedef union { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 650 | uint8_t _b[16]; |
| 651 | uint16_t _w[8]; |
| 652 | uint32_t _l[4]; |
| 653 | uint64_t _q[2]; |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 654 | float32 _s[4]; |
| 655 | float64 _d[2]; |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 656 | } XMMReg; |
| 657 | |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 658 | typedef union { |
| 659 | uint8_t _b[8]; |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 660 | uint16_t _w[4]; |
| 661 | uint32_t _l[2]; |
| 662 | float32 _s[2]; |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 663 | uint64_t q; |
| 664 | } MMXReg; |
| 665 | |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 666 | #ifdef HOST_WORDS_BIGENDIAN |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 667 | #define XMM_B(n) _b[15 - (n)] |
| 668 | #define XMM_W(n) _w[7 - (n)] |
| 669 | #define XMM_L(n) _l[3 - (n)] |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 670 | #define XMM_S(n) _s[3 - (n)] |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 671 | #define XMM_Q(n) _q[1 - (n)] |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 672 | #define XMM_D(n) _d[1 - (n)] |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 673 | |
| 674 | #define MMX_B(n) _b[7 - (n)] |
| 675 | #define MMX_W(n) _w[3 - (n)] |
| 676 | #define MMX_L(n) _l[1 - (n)] |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 677 | #define MMX_S(n) _s[1 - (n)] |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 678 | #else |
| 679 | #define XMM_B(n) _b[n] |
| 680 | #define XMM_W(n) _w[n] |
| 681 | #define XMM_L(n) _l[n] |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 682 | #define XMM_S(n) _s[n] |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 683 | #define XMM_Q(n) _q[n] |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 684 | #define XMM_D(n) _d[n] |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 685 | |
| 686 | #define MMX_B(n) _b[n] |
| 687 | #define MMX_W(n) _w[n] |
| 688 | #define MMX_L(n) _l[n] |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 689 | #define MMX_S(n) _s[n] |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 690 | #endif |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 691 | #define MMX_Q(n) q |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 692 | |
Juan Quintela | acc6883 | 2009-09-29 22:48:58 +0200 | [diff] [blame] | 693 | typedef union { |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 694 | floatx80 d __attribute__((aligned(16))); |
Juan Quintela | acc6883 | 2009-09-29 22:48:58 +0200 | [diff] [blame] | 695 | MMXReg mmx; |
| 696 | } FPReg; |
| 697 | |
Juan Quintela | c1a54d5 | 2009-09-29 22:48:59 +0200 | [diff] [blame] | 698 | typedef struct { |
| 699 | uint64_t base; |
| 700 | uint64_t mask; |
| 701 | } MTRRVar; |
| 702 | |
Jan Kiszka | 5f30fa1 | 2009-09-17 18:14:13 +0200 | [diff] [blame] | 703 | #define CPU_NB_REGS64 16 |
| 704 | #define CPU_NB_REGS32 8 |
| 705 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 706 | #ifdef TARGET_X86_64 |
Jan Kiszka | 5f30fa1 | 2009-09-17 18:14:13 +0200 | [diff] [blame] | 707 | #define CPU_NB_REGS CPU_NB_REGS64 |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 708 | #else |
Jan Kiszka | 5f30fa1 | 2009-09-17 18:14:13 +0200 | [diff] [blame] | 709 | #define CPU_NB_REGS CPU_NB_REGS32 |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 710 | #endif |
| 711 | |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 712 | #define NB_MMU_MODES 3 |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 713 | |
Jan Kiszka | d362e75 | 2012-02-17 18:31:17 +0100 | [diff] [blame] | 714 | typedef enum TPRAccess { |
| 715 | TPR_ACCESS_READ, |
| 716 | TPR_ACCESS_WRITE, |
| 717 | } TPRAccess; |
| 718 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 719 | typedef struct CPUX86State { |
| 720 | /* standard registers */ |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 721 | target_ulong regs[CPU_NB_REGS]; |
| 722 | target_ulong eip; |
| 723 | target_ulong eflags; /* eflags register. During CPU emulation, CC |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 724 | flags and DF are set to zero because they are |
| 725 | stored elsewhere */ |
| 726 | |
| 727 | /* emulator internal eflags handling */ |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 728 | target_ulong cc_src; |
| 729 | target_ulong cc_dst; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 730 | uint32_t cc_op; |
| 731 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 732 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
| 733 | are known at translation time. */ |
| 734 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 735 | |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 736 | /* segments */ |
| 737 | SegmentCache segs[6]; /* selector values */ |
| 738 | SegmentCache ldt; |
| 739 | SegmentCache tr; |
| 740 | SegmentCache gdt; /* only base and limit are used */ |
| 741 | SegmentCache idt; /* only base and limit are used */ |
| 742 | |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 743 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
Juan Quintela | 5ee0ffa | 2009-09-29 22:48:49 +0200 | [diff] [blame] | 744 | int32_t a20_mask; |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 745 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 746 | /* FPU state */ |
| 747 | unsigned int fpstt; /* top of stack index */ |
Juan Quintela | 67b8f41 | 2009-09-29 22:48:51 +0200 | [diff] [blame] | 748 | uint16_t fpus; |
Juan Quintela | eb83162 | 2009-09-29 22:48:50 +0200 | [diff] [blame] | 749 | uint16_t fpuc; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 750 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
Juan Quintela | acc6883 | 2009-09-29 22:48:58 +0200 | [diff] [blame] | 751 | FPReg fpregs[8]; |
Jan Kiszka | 42cc8fa | 2011-06-15 15:17:26 +0200 | [diff] [blame] | 752 | /* KVM-only so far */ |
| 753 | uint16_t fpop; |
| 754 | uint64_t fpip; |
| 755 | uint64_t fpdp; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 756 | |
| 757 | /* emulator internal variables */ |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 758 | float_status fp_status; |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 759 | floatx80 ft0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 760 | |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 761 | float_status mmx_status; /* for 3DNow! float ops */ |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 762 | float_status sse_status; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 763 | uint32_t mxcsr; |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 764 | XMMReg xmm_regs[CPU_NB_REGS]; |
| 765 | XMMReg xmm_t0; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 766 | MMXReg mmx_t0; |
bellard | 1e4840b | 2008-05-25 17:26:41 +0000 | [diff] [blame] | 767 | target_ulong cc_tmp; /* temporary for rcr/rcl */ |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 768 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 769 | /* sysenter registers */ |
| 770 | uint32_t sysenter_cs; |
balrog | 2436b61 | 2008-09-25 18:16:18 +0000 | [diff] [blame] | 771 | target_ulong sysenter_esp; |
| 772 | target_ulong sysenter_eip; |
bellard | 8d9bfc2 | 2005-04-23 17:46:55 +0000 | [diff] [blame] | 773 | uint64_t efer; |
| 774 | uint64_t star; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 775 | |
bellard | 5cc1d1e | 2008-06-04 18:29:25 +0000 | [diff] [blame] | 776 | uint64_t vm_hsave; |
| 777 | uint64_t vm_vmcb; |
bellard | 33c263d | 2008-06-04 17:39:33 +0000 | [diff] [blame] | 778 | uint64_t tsc_offset; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 779 | uint64_t intercept; |
| 780 | uint16_t intercept_cr_read; |
| 781 | uint16_t intercept_cr_write; |
| 782 | uint16_t intercept_dr_read; |
| 783 | uint16_t intercept_dr_write; |
| 784 | uint32_t intercept_exceptions; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 785 | uint8_t v_tpr; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 786 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 787 | #ifdef TARGET_X86_64 |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 788 | target_ulong lstar; |
| 789 | target_ulong cstar; |
| 790 | target_ulong fmask; |
| 791 | target_ulong kernelgsbase; |
| 792 | #endif |
Glauber Costa | 1a03675 | 2009-10-22 10:26:56 -0200 | [diff] [blame] | 793 | uint64_t system_time_msr; |
| 794 | uint64_t wall_clock_msr; |
Gleb Natapov | f6584ee | 2010-10-24 14:27:55 +0200 | [diff] [blame] | 795 | uint64_t async_pf_en_msr; |
Michael S. Tsirkin | bc9a839 | 2012-08-28 20:43:56 +0300 | [diff] [blame] | 796 | uint64_t pv_eoi_en_msr; |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 797 | |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 798 | uint64_t tsc; |
Will Auld | f28558d | 2012-11-26 21:32:18 -0800 | [diff] [blame] | 799 | uint64_t tsc_adjust; |
Liu, Jinsong | aa82ba5 | 2011-10-05 16:52:32 -0300 | [diff] [blame] | 800 | uint64_t tsc_deadline; |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 801 | |
Jan Kiszka | 1855923 | 2011-03-02 08:56:07 +0100 | [diff] [blame] | 802 | uint64_t mcg_status; |
Avi Kivity | 21e87c4 | 2011-10-04 16:26:35 +0200 | [diff] [blame] | 803 | uint64_t msr_ia32_misc_enable; |
Jan Kiszka | 1855923 | 2011-03-02 08:56:07 +0100 | [diff] [blame] | 804 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 805 | /* exception/interrupt handling */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 806 | int error_code; |
| 807 | int exception_is_int; |
bellard | 826461b | 2005-01-06 20:44:11 +0000 | [diff] [blame] | 808 | target_ulong exception_next_eip; |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 809 | target_ulong dr[8]; /* debug registers */ |
aliguori | 01df040 | 2008-11-18 21:08:15 +0000 | [diff] [blame] | 810 | union { |
| 811 | CPUBreakpoint *cpu_breakpoint[4]; |
| 812 | CPUWatchpoint *cpu_watchpoint[4]; |
| 813 | }; /* break/watchpoints for dr[0..3] */ |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 814 | uint32_t smbase; |
ths | 678dde1 | 2007-03-31 20:28:52 +0000 | [diff] [blame] | 815 | int old_exception; /* exception in flight */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 816 | |
Jan Kiszka | d8f771d | 2011-01-21 21:48:21 +0100 | [diff] [blame] | 817 | /* KVM states, automatically cleared on reset */ |
| 818 | uint8_t nmi_injected; |
| 819 | uint8_t nmi_pending; |
| 820 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 821 | CPU_COMMON |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 822 | |
Jan Kiszka | ebda377 | 2011-03-15 12:26:21 +0100 | [diff] [blame] | 823 | uint64_t pat; |
| 824 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 825 | /* processor features (e.g. for CPUID insn) */ |
bellard | 8d9bfc2 | 2005-04-23 17:46:55 +0000 | [diff] [blame] | 826 | uint32_t cpuid_level; |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 827 | uint32_t cpuid_vendor1; |
| 828 | uint32_t cpuid_vendor2; |
| 829 | uint32_t cpuid_vendor3; |
| 830 | uint32_t cpuid_version; |
| 831 | uint32_t cpuid_features; |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 832 | uint32_t cpuid_ext_features; |
bellard | 8d9bfc2 | 2005-04-23 17:46:55 +0000 | [diff] [blame] | 833 | uint32_t cpuid_xlevel; |
| 834 | uint32_t cpuid_model[12]; |
| 835 | uint32_t cpuid_ext2_features; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 836 | uint32_t cpuid_ext3_features; |
ths | eae7629 | 2007-04-03 16:38:34 +0000 | [diff] [blame] | 837 | uint32_t cpuid_apic_id; |
Andre Przywara | ef76813 | 2009-06-06 01:03:29 +0200 | [diff] [blame] | 838 | int cpuid_vendor_override; |
brillywu@viatech.com.cn | b3baa15 | 2011-06-01 09:59:52 +0800 | [diff] [blame] | 839 | /* Store the results of Centaur's CPUID instructions */ |
| 840 | uint32_t cpuid_xlevel2; |
| 841 | uint32_t cpuid_ext4_features; |
Eduardo Habkost | 1352672 | 2012-05-21 11:27:02 -0300 | [diff] [blame] | 842 | /* Flags from CPUID[EAX=7,ECX=0].EBX */ |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 843 | uint32_t cpuid_7_0_ebx_features; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 844 | |
aliguori | 165d9b8 | 2009-01-26 17:53:04 +0000 | [diff] [blame] | 845 | /* MTRRs */ |
| 846 | uint64_t mtrr_fixed[11]; |
| 847 | uint64_t mtrr_deftype; |
Juan Quintela | c1a54d5 | 2009-09-29 22:48:59 +0200 | [diff] [blame] | 848 | MTRRVar mtrr_var[8]; |
aliguori | 165d9b8 | 2009-01-26 17:53:04 +0000 | [diff] [blame] | 849 | |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 850 | /* For KVM */ |
Jan Kiszka | f8d926e | 2009-05-02 02:18:38 +0200 | [diff] [blame] | 851 | uint32_t mp_state; |
Jan Kiszka | 3182737 | 2009-12-14 12:26:17 +0100 | [diff] [blame] | 852 | int32_t exception_injected; |
Jan Kiszka | 0e607a8 | 2009-11-06 19:39:24 +0100 | [diff] [blame] | 853 | int32_t interrupt_injected; |
Jan Kiszka | a0fb002 | 2009-11-25 00:33:03 +0100 | [diff] [blame] | 854 | uint8_t soft_interrupt; |
Jan Kiszka | a0fb002 | 2009-11-25 00:33:03 +0100 | [diff] [blame] | 855 | uint8_t has_error_code; |
| 856 | uint32_t sipi_vector; |
Gleb Natapov | bb0300d | 2010-01-13 15:25:06 +0200 | [diff] [blame] | 857 | uint32_t cpuid_kvm_features; |
Joerg Roedel | 296acb6 | 2010-09-27 15:16:17 +0200 | [diff] [blame] | 858 | uint32_t cpuid_svm_features; |
Glauber Costa | b8cc45d | 2011-02-03 14:19:53 -0500 | [diff] [blame] | 859 | bool tsc_valid; |
Joerg Roedel | b862d1f | 2011-07-07 16:13:12 +0200 | [diff] [blame] | 860 | int tsc_khz; |
Jan Kiszka | fabacc0 | 2011-10-27 19:25:58 +0200 | [diff] [blame] | 861 | void *kvm_xsave_buf; |
| 862 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 863 | /* in order to simplify APIC support, we leave this pointer to the |
| 864 | user */ |
Blue Swirl | 92a16d7 | 2010-06-19 07:47:42 +0000 | [diff] [blame] | 865 | struct DeviceState *apic_state; |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 866 | |
Andreas Färber | ac6c412 | 2010-12-19 17:22:41 +0100 | [diff] [blame] | 867 | uint64_t mcg_cap; |
Andreas Färber | ac6c412 | 2010-12-19 17:22:41 +0100 | [diff] [blame] | 868 | uint64_t mcg_ctl; |
| 869 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
Andre Przywara | 1b05007 | 2009-09-19 00:30:49 +0200 | [diff] [blame] | 870 | |
| 871 | uint64_t tsc_aux; |
Aurelien Jarno | 5a2d0e5 | 2009-10-05 22:41:04 +0200 | [diff] [blame] | 872 | |
| 873 | /* vmstate */ |
| 874 | uint16_t fpus_vmstate; |
| 875 | uint16_t fptag_vmstate; |
| 876 | uint16_t fpregs_format_vmstate; |
Sheng Yang | f1665b2 | 2010-06-17 17:53:07 +0800 | [diff] [blame] | 877 | |
| 878 | uint64_t xstate_bv; |
| 879 | XMMReg ymmh_regs[CPU_NB_REGS]; |
| 880 | |
| 881 | uint64_t xcr0; |
Jan Kiszka | d362e75 | 2012-02-17 18:31:17 +0100 | [diff] [blame] | 882 | |
| 883 | TPRAccess tpr_access_type; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 884 | } CPUX86State; |
| 885 | |
Andreas Färber | 5fd2087 | 2012-04-02 23:20:08 +0200 | [diff] [blame] | 886 | #include "cpu-qom.h" |
| 887 | |
Andreas Färber | b47ed99 | 2012-05-02 18:42:46 +0200 | [diff] [blame] | 888 | X86CPU *cpu_x86_init(const char *cpu_model); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 889 | int cpu_x86_exec(CPUX86State *s); |
Peter Maydell | e916cbf | 2012-09-05 17:41:08 -0300 | [diff] [blame] | 890 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
john cooper | b5ec5ce | 2010-02-20 11:14:59 -0600 | [diff] [blame] | 891 | void x86_cpudef_setup(void); |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 892 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
john cooper | b5ec5ce | 2010-02-20 11:14:59 -0600 | [diff] [blame] | 893 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 894 | int cpu_get_pic_interrupt(CPUX86State *s); |
bellard | 2ee73ac | 2004-05-08 21:08:41 +0000 | [diff] [blame] | 895 | /* MSDOS compatibility mode FPU exception support */ |
| 896 | void cpu_set_ferr(CPUX86State *s); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 897 | |
| 898 | /* this function must always be used to load data in the segment |
| 899 | cache: it synchronizes the hflags with the segment cache values */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 900 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 901 | int seg_reg, unsigned int selector, |
bellard | 8988ae8 | 2006-09-27 19:54:02 +0000 | [diff] [blame] | 902 | target_ulong base, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 903 | unsigned int limit, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 904 | unsigned int flags) |
| 905 | { |
| 906 | SegmentCache *sc; |
| 907 | unsigned int new_hflags; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 908 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 909 | sc = &env->segs[seg_reg]; |
| 910 | sc->selector = selector; |
| 911 | sc->base = base; |
| 912 | sc->limit = limit; |
| 913 | sc->flags = flags; |
| 914 | |
| 915 | /* update the hidden flags */ |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 916 | { |
| 917 | if (seg_reg == R_CS) { |
| 918 | #ifdef TARGET_X86_64 |
| 919 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { |
| 920 | /* long mode */ |
| 921 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
| 922 | env->hflags &= ~(HF_ADDSEG_MASK); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 923 | } else |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 924 | #endif |
| 925 | { |
| 926 | /* legacy / compatibility case */ |
| 927 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
| 928 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
| 929 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
| 930 | new_hflags; |
| 931 | } |
| 932 | } |
| 933 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
| 934 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
| 935 | if (env->hflags & HF_CS64_MASK) { |
| 936 | /* zero base assumed for DS, ES and SS in long mode */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 937 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
bellard | 735a8fd | 2005-01-12 22:36:43 +0000 | [diff] [blame] | 938 | (env->eflags & VM_MASK) || |
| 939 | !(env->hflags & HF_CS32_MASK)) { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 940 | /* XXX: try to avoid this test. The problem comes from the |
| 941 | fact that is real mode or vm86 mode we only modify the |
| 942 | 'base' and 'selector' fields of the segment cache to go |
| 943 | faster. A solution may be to force addseg to one in |
| 944 | translate-i386.c. */ |
| 945 | new_hflags |= HF_ADDSEG_MASK; |
| 946 | } else { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 947 | new_hflags |= ((env->segs[R_DS].base | |
bellard | 735a8fd | 2005-01-12 22:36:43 +0000 | [diff] [blame] | 948 | env->segs[R_ES].base | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 949 | env->segs[R_SS].base) != 0) << |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 950 | HF_ADDSEG_SHIFT; |
| 951 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 952 | env->hflags = (env->hflags & |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 953 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 954 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 955 | } |
| 956 | |
Andreas Färber | e9f9d6b | 2012-05-03 15:37:01 +0200 | [diff] [blame] | 957 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
Blue Swirl | 0e26b7b | 2010-06-19 10:42:34 +0300 | [diff] [blame] | 958 | int sipi_vector) |
| 959 | { |
Andreas Färber | e9f9d6b | 2012-05-03 15:37:01 +0200 | [diff] [blame] | 960 | CPUX86State *env = &cpu->env; |
| 961 | |
Blue Swirl | 0e26b7b | 2010-06-19 10:42:34 +0300 | [diff] [blame] | 962 | env->eip = 0; |
| 963 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, |
| 964 | sipi_vector << 12, |
| 965 | env->segs[R_CS].limit, |
| 966 | env->segs[R_CS].flags); |
| 967 | env->halted = 0; |
| 968 | } |
| 969 | |
Jan Kiszka | 8427317 | 2009-06-27 09:53:51 +0200 | [diff] [blame] | 970 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
| 971 | target_ulong *base, unsigned int *limit, |
| 972 | unsigned int *flags); |
| 973 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 974 | /* wrapper, just in case memory mappings must be changed */ |
| 975 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
| 976 | { |
| 977 | #if HF_CPL_MASK == 3 |
| 978 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
| 979 | #else |
| 980 | #error HF_CPL_MASK is hardcoded |
| 981 | #endif |
| 982 | } |
| 983 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 984 | /* op_helper.c */ |
bellard | 1f1af9f | 2004-03-31 18:56:43 +0000 | [diff] [blame] | 985 | /* used for debug or cpu save/restore */ |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 986 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); |
| 987 | floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); |
bellard | 1f1af9f | 2004-03-31 18:56:43 +0000 | [diff] [blame] | 988 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 989 | /* cpu-exec.c */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 990 | /* the following helpers are only usable in user mode simulation as |
| 991 | they can trigger unexpected exceptions */ |
| 992 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 993 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
| 994 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 995 | |
| 996 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 997 | signal handlers to inform the virtual CPU of exceptions. non zero |
| 998 | is returned if the signal was handled by the virtual CPU. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 999 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1000 | void *puc); |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1001 | |
Andre Przywara | c6dc6f6 | 2010-03-11 14:38:55 +0100 | [diff] [blame] | 1002 | /* cpuid.c */ |
| 1003 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
| 1004 | uint32_t *eax, uint32_t *ebx, |
| 1005 | uint32_t *ecx, uint32_t *edx); |
Andreas Färber | 61dcd77 | 2012-04-17 12:00:51 +0200 | [diff] [blame] | 1006 | int cpu_x86_register(X86CPU *cpu, const char *cpu_model); |
Blue Swirl | 0e26b7b | 2010-06-19 10:42:34 +0300 | [diff] [blame] | 1007 | void cpu_clear_apic_feature(CPUX86State *env); |
Jan Kiszka | bb44e0d | 2011-01-21 21:48:07 +0100 | [diff] [blame] | 1008 | void host_cpuid(uint32_t function, uint32_t count, |
| 1009 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); |
Andre Przywara | c6dc6f6 | 2010-03-11 14:38:55 +0100 | [diff] [blame] | 1010 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1011 | /* helper.c */ |
| 1012 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, |
Blue Swirl | 97b348e | 2011-08-01 16:12:17 +0000 | [diff] [blame] | 1013 | int is_write, int mmu_idx); |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 1014 | #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault |
bellard | 461c047 | 2003-11-04 23:34:23 +0000 | [diff] [blame] | 1015 | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1016 | |
liguang | 5902564 | 2013-01-15 08:01:07 +0100 | [diff] [blame] | 1017 | static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index) |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1018 | { |
liguang | 5902564 | 2013-01-15 08:01:07 +0100 | [diff] [blame] | 1019 | return (dr7 >> (index * 2)) & 1; |
| 1020 | } |
| 1021 | |
| 1022 | static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index) |
| 1023 | { |
| 1024 | return (dr7 >> (index * 2)) & 2; |
| 1025 | |
| 1026 | } |
| 1027 | static inline bool hw_breakpoint_enabled(unsigned long dr7, int index) |
| 1028 | { |
| 1029 | return hw_global_breakpoint_enabled(dr7, index) || |
| 1030 | hw_local_breakpoint_enabled(dr7, index); |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1031 | } |
bellard | 28ab0e2 | 2004-05-20 14:02:14 +0000 | [diff] [blame] | 1032 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1033 | static inline int hw_breakpoint_type(unsigned long dr7, int index) |
| 1034 | { |
Jan Kiszka | d46272c | 2009-12-14 12:26:27 +0100 | [diff] [blame] | 1035 | return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3; |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1036 | } |
| 1037 | |
| 1038 | static inline int hw_breakpoint_len(unsigned long dr7, int index) |
| 1039 | { |
Jan Kiszka | d46272c | 2009-12-14 12:26:27 +0100 | [diff] [blame] | 1040 | int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3); |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1041 | return (len == 2) ? 8 : len + 1; |
| 1042 | } |
| 1043 | |
| 1044 | void hw_breakpoint_insert(CPUX86State *env, int index); |
| 1045 | void hw_breakpoint_remove(CPUX86State *env, int index); |
liguang | e175bce | 2013-01-15 13:39:56 +0800 | [diff] [blame] | 1046 | bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update); |
Igor Mammedov | d65e981 | 2012-06-19 15:39:46 +0200 | [diff] [blame] | 1047 | void breakpoint_handler(CPUX86State *env); |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1048 | |
| 1049 | /* will be suppressed */ |
| 1050 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); |
| 1051 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); |
| 1052 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); |
| 1053 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1054 | /* hw/pc.c */ |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 1055 | void cpu_smm_update(CPUX86State *env); |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1056 | uint64_t cpu_get_tsc(CPUX86State *env); |
aliguori | 6fd805e | 2008-11-05 15:34:06 +0000 | [diff] [blame] | 1057 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1058 | #define TARGET_PAGE_BITS 12 |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 1059 | |
Richard Henderson | 5270589 | 2010-03-10 14:33:23 -0800 | [diff] [blame] | 1060 | #ifdef TARGET_X86_64 |
| 1061 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 |
| 1062 | /* ??? This is really 48 bits, sign-extended, but the only thing |
| 1063 | accessible to userland with bit 48 set is the VSYSCALL, and that |
| 1064 | is handled via other mechanisms. */ |
| 1065 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 |
| 1066 | #else |
| 1067 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
| 1068 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 1069 | #endif |
| 1070 | |
Andreas Färber | b47ed99 | 2012-05-02 18:42:46 +0200 | [diff] [blame] | 1071 | static inline CPUX86State *cpu_init(const char *cpu_model) |
| 1072 | { |
| 1073 | X86CPU *cpu = cpu_x86_init(cpu_model); |
| 1074 | if (cpu == NULL) { |
| 1075 | return NULL; |
| 1076 | } |
| 1077 | return &cpu->env; |
| 1078 | } |
| 1079 | |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 1080 | #define cpu_exec cpu_x86_exec |
| 1081 | #define cpu_gen_code cpu_x86_gen_code |
| 1082 | #define cpu_signal_handler cpu_x86_signal_handler |
Peter Maydell | e916cbf | 2012-09-05 17:41:08 -0300 | [diff] [blame] | 1083 | #define cpu_list x86_cpu_list |
john cooper | b5ec5ce | 2010-02-20 11:14:59 -0600 | [diff] [blame] | 1084 | #define cpudef_setup x86_cpudef_setup |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 1085 | |
Marcelo Tosatti | 38d2c27 | 2011-10-24 21:27:16 -0200 | [diff] [blame] | 1086 | #define CPU_SAVE_VERSION 12 |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 1087 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1088 | /* MMU modes definitions */ |
| 1089 | #define MMU_MODE0_SUFFIX _kernel |
| 1090 | #define MMU_MODE1_SUFFIX _user |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 1091 | #define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */ |
| 1092 | #define MMU_KERNEL_IDX 0 |
| 1093 | #define MMU_USER_IDX 1 |
| 1094 | #define MMU_KSMAP_IDX 2 |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 1095 | static inline int cpu_mmu_index (CPUX86State *env) |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1096 | { |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 1097 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
| 1098 | ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK)) |
| 1099 | ? MMU_KSMAP_IDX : MMU_KERNEL_IDX; |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1100 | } |
| 1101 | |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 1102 | #undef EAX |
| 1103 | #define EAX (env->regs[R_EAX]) |
| 1104 | #undef ECX |
| 1105 | #define ECX (env->regs[R_ECX]) |
| 1106 | #undef EDX |
| 1107 | #define EDX (env->regs[R_EDX]) |
| 1108 | #undef EBX |
| 1109 | #define EBX (env->regs[R_EBX]) |
| 1110 | #undef ESP |
| 1111 | #define ESP (env->regs[R_ESP]) |
| 1112 | #undef EBP |
| 1113 | #define EBP (env->regs[R_EBP]) |
| 1114 | #undef ESI |
| 1115 | #define ESI (env->regs[R_ESI]) |
| 1116 | #undef EDI |
| 1117 | #define EDI (env->regs[R_EDI]) |
| 1118 | #undef EIP |
| 1119 | #define EIP (env->eip) |
| 1120 | #define DF (env->df) |
| 1121 | |
| 1122 | #define CC_SRC (env->cc_src) |
| 1123 | #define CC_DST (env->cc_dst) |
| 1124 | #define CC_OP (env->cc_op) |
| 1125 | |
Blue Swirl | 5918fff | 2012-04-29 12:21:21 +0000 | [diff] [blame] | 1126 | /* n must be a constant to be efficient */ |
| 1127 | static inline target_long lshift(target_long x, int n) |
| 1128 | { |
| 1129 | if (n >= 0) { |
| 1130 | return x << n; |
| 1131 | } else { |
| 1132 | return x >> (-n); |
| 1133 | } |
| 1134 | } |
| 1135 | |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 1136 | /* float macros */ |
| 1137 | #define FT0 (env->ft0) |
| 1138 | #define ST0 (env->fpregs[env->fpstt].d) |
| 1139 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
| 1140 | #define ST1 ST(1) |
| 1141 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 1142 | /* translate.c */ |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 1143 | void optimize_flags_init(void); |
| 1144 | |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 1145 | #if defined(CONFIG_USER_ONLY) |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 1146 | static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 1147 | { |
pbrook | f8ed707 | 2008-05-30 17:54:15 +0000 | [diff] [blame] | 1148 | if (newsp) |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 1149 | env->regs[R_ESP] = newsp; |
| 1150 | env->regs[R_EAX] = 0; |
| 1151 | } |
| 1152 | #endif |
| 1153 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 1154 | #include "exec/cpu-all.h" |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 1155 | #include "svm.h" |
| 1156 | |
Blue Swirl | 0e26b7b | 2010-06-19 10:42:34 +0300 | [diff] [blame] | 1157 | #if !defined(CONFIG_USER_ONLY) |
| 1158 | #include "hw/apic.h" |
| 1159 | #endif |
| 1160 | |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 1161 | static inline bool cpu_has_work(CPUState *cpu) |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 1162 | { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 1163 | CPUX86State *env = &X86_CPU(cpu)->env; |
| 1164 | |
Jan Kiszka | 5d62c43 | 2012-07-09 16:42:32 +0200 | [diff] [blame] | 1165 | return ((env->interrupt_request & (CPU_INTERRUPT_HARD | |
| 1166 | CPU_INTERRUPT_POLL)) && |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 1167 | (env->eflags & IF_MASK)) || |
| 1168 | (env->interrupt_request & (CPU_INTERRUPT_NMI | |
| 1169 | CPU_INTERRUPT_INIT | |
| 1170 | CPU_INTERRUPT_SIPI | |
| 1171 | CPU_INTERRUPT_MCE)); |
| 1172 | } |
| 1173 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 1174 | #include "exec/exec-all.h" |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 1175 | |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 1176 | static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb) |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 1177 | { |
| 1178 | env->eip = tb->pc - tb->cs_base; |
| 1179 | } |
| 1180 | |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 1181 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1182 | target_ulong *cs_base, int *flags) |
| 1183 | { |
| 1184 | *cs_base = env->segs[R_CS].base; |
| 1185 | *pc = *cs_base + env->eip; |
Jan Kiszka | a239780 | 2009-05-10 22:30:53 +0200 | [diff] [blame] | 1186 | *flags = env->hflags | |
H. Peter Anvin | a9321a4 | 2012-09-26 13:18:43 -0700 | [diff] [blame] | 1187 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1188 | } |
| 1189 | |
Andreas Färber | 232fc23 | 2012-05-05 01:14:41 +0200 | [diff] [blame] | 1190 | void do_cpu_init(X86CPU *cpu); |
| 1191 | void do_cpu_sipi(X86CPU *cpu); |
Jan Kiszka | 2fa11da | 2011-03-02 08:56:08 +0100 | [diff] [blame] | 1192 | |
Jan Kiszka | 747461c | 2011-03-02 08:56:10 +0100 | [diff] [blame] | 1193 | #define MCE_INJECT_BROADCAST 1 |
| 1194 | #define MCE_INJECT_UNCOND_AO 2 |
| 1195 | |
Andreas Färber | 8c5cf3b | 2012-05-03 15:22:54 +0200 | [diff] [blame] | 1196 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
Jan Kiszka | 316378e | 2011-03-02 08:56:09 +0100 | [diff] [blame] | 1197 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
Jan Kiszka | 747461c | 2011-03-02 08:56:10 +0100 | [diff] [blame] | 1198 | uint64_t misc, int flags); |
Jan Kiszka | 2fa11da | 2011-03-02 08:56:08 +0100 | [diff] [blame] | 1199 | |
Blue Swirl | 599b9a5 | 2012-04-28 19:53:52 +0000 | [diff] [blame] | 1200 | /* excp_helper.c */ |
Blue Swirl | 77b2bc2 | 2012-04-28 19:35:10 +0000 | [diff] [blame] | 1201 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
| 1202 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, |
| 1203 | int error_code); |
Blue Swirl | 599b9a5 | 2012-04-28 19:53:52 +0000 | [diff] [blame] | 1204 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
| 1205 | int error_code, int next_eip_addend); |
| 1206 | |
Blue Swirl | 5918fff | 2012-04-29 12:21:21 +0000 | [diff] [blame] | 1207 | /* cc_helper.c */ |
| 1208 | extern const uint8_t parity_table[256]; |
| 1209 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); |
| 1210 | |
| 1211 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) |
| 1212 | { |
| 1213 | return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK); |
| 1214 | } |
| 1215 | |
| 1216 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ |
| 1217 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, |
| 1218 | int update_mask) |
| 1219 | { |
| 1220 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 1221 | DF = 1 - (2 * ((eflags >> 10) & 1)); |
| 1222 | env->eflags = (env->eflags & ~update_mask) | |
| 1223 | (eflags & update_mask) | 0x2; |
| 1224 | } |
| 1225 | |
| 1226 | /* load efer and update the corresponding hflags. XXX: do consistency |
| 1227 | checks with cpuid bits? */ |
| 1228 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) |
| 1229 | { |
| 1230 | env->efer = val; |
| 1231 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); |
| 1232 | if (env->efer & MSR_EFER_LMA) { |
| 1233 | env->hflags |= HF_LMA_MASK; |
| 1234 | } |
| 1235 | if (env->efer & MSR_EFER_SVME) { |
| 1236 | env->hflags |= HF_SVME_MASK; |
| 1237 | } |
| 1238 | } |
| 1239 | |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 1240 | /* svm_helper.c */ |
| 1241 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, |
| 1242 | uint64_t param); |
| 1243 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1); |
| 1244 | |
Blue Swirl | 599b9a5 | 2012-04-28 19:53:52 +0000 | [diff] [blame] | 1245 | /* op_helper.c */ |
| 1246 | void do_interrupt(CPUX86State *env); |
| 1247 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 1248 | |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 1249 | void do_smm_enter(CPUX86State *env1); |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 1250 | |
Andreas Färber | 317ac62 | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 1251 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
Jan Kiszka | d362e75 | 2012-02-17 18:31:17 +0100 | [diff] [blame] | 1252 | |
Eduardo Habkost | 2969475 | 2013-01-17 18:59:29 -0200 | [diff] [blame] | 1253 | void disable_kvm_pv_eoi(void); |
Michael S. Tsirkin | dc59944 | 2012-10-18 00:15:48 +0200 | [diff] [blame] | 1254 | |
Eduardo Habkost | 8b4bedd | 2013-01-04 20:01:06 -0200 | [diff] [blame] | 1255 | /* Return name of 32-bit register, from a R_* constant */ |
| 1256 | const char *get_register_name_32(unsigned int reg); |
| 1257 | |
Eduardo Habkost | cb41bad | 2013-01-22 18:25:04 -0200 | [diff] [blame^] | 1258 | uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index); |
| 1259 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1260 | #endif /* CPU_I386_H */ |