commit 8f091a59605092994c4b52c20b7173c514411e38
author bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Sat Jul 23 17:41:26 2005 +0000
committer bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Sat Jul 23 17:41:26 2005 +0000
tree 15c2bc6210cc181e0b8a58ce3cc8df3d6d90d889
parent 2efbe911d3ea518f5d4648954379f9d5aa02e806

x86_64 fixes (initial patch by Filip Navara)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1517 c046a42c-6fe2-441c-8c8c-71466251a162

target-i386/cpu.h

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 3549511..f8373a1 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -214,6 +214,12 @@
 #define MSR_IA32_SYSENTER_ESP           0x175
 #define MSR_IA32_SYSENTER_EIP           0x176
 
+#define MSR_MCG_CAP                     0x179
+#define MSR_MCG_STATUS                  0x17a
+#define MSR_MCG_CTL                     0x17b
+
+#define MSR_PAT                         0x277
+
 #define MSR_EFER                        0xc0000080
 
 #define MSR_EFER_SCE   (1 << 0)
@@ -246,6 +252,8 @@
 #define CPUID_PGE  (1 << 13)
 #define CPUID_MCA  (1 << 14)
 #define CPUID_CMOV (1 << 15)
+#define CPUID_PAT  (1 << 16)
+#define CPUID_CLFLUSH (1 << 19)
 /* ... */
 #define CPUID_MMX  (1 << 23)
 #define CPUID_FXSR (1 << 24)
@@ -474,6 +482,8 @@
     target_ulong kernelgsbase;
 #endif
 
+    uint64_t pat;
+
     /* temporary data for USE_CODE_COPY mode */
 #ifdef USE_CODE_COPY
     uint32_t tmp0;