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malc810260a2008-07-23 19:17:46 +00001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
Richard Henderson53c89ef2017-07-31 06:03:03 +000025#include "elf.h"
26#include "tcg-pool.inc.c"
27
Richard Hendersonffcfbec2014-03-25 09:13:38 -070028#if defined _CALL_DARWIN || defined __APPLE__
29#define TCG_TARGET_CALL_DARWIN
30#endif
Richard Henderson7f25c462014-03-25 12:11:48 -070031#ifdef _CALL_SYSV
32# define TCG_TARGET_CALL_ALIGN_ARGS 1
33#endif
Richard Hendersonffcfbec2014-03-25 09:13:38 -070034
Richard Hendersondfca1772014-04-30 12:12:16 -070035/* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
39#ifdef _CALL_AIX
40# define TCG_REG_TMP1 TCG_REG_R2
41#else
42# define TCG_REG_TMP1 TCG_REG_R12
43#endif
44
Richard Henderson5964fca2017-07-31 04:16:10 +000045#define TCG_REG_TB TCG_REG_R31
46#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
Richard Hendersona84ac4c2014-03-28 06:53:53 -070047
Richard Hendersonde3d6362014-03-24 15:22:35 -070048/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
49#define SZP ((int)sizeof(void *))
50
Richard Henderson4c3831a2014-03-24 16:03:59 -070051/* Shorthand for size of a register. */
52#define SZR (TCG_TARGET_REG_BITS / 8)
53
Richard Henderson3d582c62013-02-01 16:51:53 -080054#define TCG_CT_CONST_S16 0x100
55#define TCG_CT_CONST_U16 0x200
56#define TCG_CT_CONST_S32 0x400
57#define TCG_CT_CONST_U32 0x800
58#define TCG_CT_CONST_ZERO 0x1000
Richard Henderson6c858762013-03-04 14:26:52 -080059#define TCG_CT_CONST_MONE 0x2000
Richard Hendersond0b07482016-11-16 12:48:55 +010060#define TCG_CT_CONST_WSZ 0x4000
malcfe6f9432008-07-28 23:46:06 +000061
Richard Hendersone083c4a2014-03-28 14:58:38 -070062static tcg_insn_unit *tb_ret_addr;
malc810260a2008-07-23 19:17:46 +000063
Richard Henderson33e75fb2016-11-22 11:43:12 +000064bool have_isa_2_06;
Richard Hendersond0b07482016-11-16 12:48:55 +010065bool have_isa_3_00;
66
Richard Henderson1e6e9ac2013-02-18 09:11:15 -080067#define HAVE_ISA_2_06 have_isa_2_06
68#define HAVE_ISEL have_isa_2_06
Richard Henderson49d98702013-02-02 00:58:14 -080069
Laurent Vivier4cbea592015-08-24 01:42:07 +020070#ifndef CONFIG_SOFTMMU
malcf6548c02009-07-18 10:08:40 +040071#define TCG_GUEST_BASE_REG 30
malcf6548c02009-07-18 10:08:40 +040072#endif
73
Aurelien Jarno8d8fdba2016-04-21 10:48:50 +020074#ifdef CONFIG_DEBUG_TCG
malc810260a2008-07-23 19:17:46 +000075static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
76 "r0",
77 "r1",
malc98926b02010-04-07 02:26:22 +040078 "r2",
malc810260a2008-07-23 19:17:46 +000079 "r3",
80 "r4",
81 "r5",
82 "r6",
83 "r7",
84 "r8",
85 "r9",
86 "r10",
87 "r11",
88 "r12",
89 "r13",
90 "r14",
91 "r15",
92 "r16",
93 "r17",
94 "r18",
95 "r19",
96 "r20",
97 "r21",
98 "r22",
99 "r23",
100 "r24",
101 "r25",
102 "r26",
103 "r27",
104 "r28",
105 "r29",
106 "r30",
107 "r31"
108};
blueswir1d4a9eb12008-10-05 09:59:14 +0000109#endif
malc810260a2008-07-23 19:17:46 +0000110
111static const int tcg_target_reg_alloc_order[] = {
Richard Henderson5e1702b2013-07-31 10:18:49 -0700112 TCG_REG_R14, /* call saved registers */
malc810260a2008-07-23 19:17:46 +0000113 TCG_REG_R15,
114 TCG_REG_R16,
115 TCG_REG_R17,
116 TCG_REG_R18,
117 TCG_REG_R19,
118 TCG_REG_R20,
119 TCG_REG_R21,
120 TCG_REG_R22,
121 TCG_REG_R23,
Richard Henderson5e1702b2013-07-31 10:18:49 -0700122 TCG_REG_R24,
123 TCG_REG_R25,
124 TCG_REG_R26,
125 TCG_REG_R27,
malc810260a2008-07-23 19:17:46 +0000126 TCG_REG_R28,
127 TCG_REG_R29,
128 TCG_REG_R30,
129 TCG_REG_R31,
Richard Henderson5e1702b2013-07-31 10:18:49 -0700130 TCG_REG_R12, /* call clobbered, non-arguments */
malc810260a2008-07-23 19:17:46 +0000131 TCG_REG_R11,
Richard Hendersondfca1772014-04-30 12:12:16 -0700132 TCG_REG_R2,
133 TCG_REG_R13,
Richard Henderson5e1702b2013-07-31 10:18:49 -0700134 TCG_REG_R10, /* call clobbered, arguments */
135 TCG_REG_R9,
136 TCG_REG_R8,
137 TCG_REG_R7,
138 TCG_REG_R6,
139 TCG_REG_R5,
140 TCG_REG_R4,
141 TCG_REG_R3,
malc810260a2008-07-23 19:17:46 +0000142};
143
144static const int tcg_target_call_iarg_regs[] = {
145 TCG_REG_R3,
146 TCG_REG_R4,
147 TCG_REG_R5,
148 TCG_REG_R6,
149 TCG_REG_R7,
150 TCG_REG_R8,
151 TCG_REG_R9,
152 TCG_REG_R10
153};
154
Stefan Weilbe9c4182011-09-05 11:07:02 +0200155static const int tcg_target_call_oarg_regs[] = {
Richard Hendersondfca1772014-04-30 12:12:16 -0700156 TCG_REG_R3,
157 TCG_REG_R4
malc810260a2008-07-23 19:17:46 +0000158};
159
160static const int tcg_target_callee_save_regs[] = {
Richard Hendersondfca1772014-04-30 12:12:16 -0700161#ifdef TCG_TARGET_CALL_DARWIN
Andreas Faerber5d7ff5b2009-12-06 14:00:24 +0100162 TCG_REG_R11,
163#endif
malc810260a2008-07-23 19:17:46 +0000164 TCG_REG_R14,
165 TCG_REG_R15,
166 TCG_REG_R16,
167 TCG_REG_R17,
168 TCG_REG_R18,
169 TCG_REG_R19,
170 TCG_REG_R20,
171 TCG_REG_R21,
172 TCG_REG_R22,
173 TCG_REG_R23,
malc095271d2009-02-11 18:54:02 +0000174 TCG_REG_R24,
175 TCG_REG_R25,
176 TCG_REG_R26,
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000177 TCG_REG_R27, /* currently used for the global env */
malc810260a2008-07-23 19:17:46 +0000178 TCG_REG_R28,
179 TCG_REG_R29,
180 TCG_REG_R30,
181 TCG_REG_R31
182};
183
Richard Hendersonb0940da2013-08-31 06:30:45 -0700184static inline bool in_range_b(tcg_target_long target)
185{
186 return target == sextract64(target, 0, 26);
187}
188
Richard Hendersone083c4a2014-03-28 14:58:38 -0700189static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
malc810260a2008-07-23 19:17:46 +0000190{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700191 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +0200192 tcg_debug_assert(in_range_b(disp));
malc810260a2008-07-23 19:17:46 +0000193 return disp & 0x3fffffc;
194}
195
Richard Hendersone083c4a2014-03-28 14:58:38 -0700196static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
malc810260a2008-07-23 19:17:46 +0000197{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700198 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
malc810260a2008-07-23 19:17:46 +0000199}
200
Richard Hendersone083c4a2014-03-28 14:58:38 -0700201static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
malc810260a2008-07-23 19:17:46 +0000202{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700203 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +0200204 tcg_debug_assert(disp == (int16_t) disp);
malc810260a2008-07-23 19:17:46 +0000205 return disp & 0xfffc;
206}
207
Richard Hendersone083c4a2014-03-28 14:58:38 -0700208static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
malc810260a2008-07-23 19:17:46 +0000209{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700210 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
malc810260a2008-07-23 19:17:46 +0000211}
212
Richard Hendersonc7ca6a22013-08-30 17:58:10 -0700213static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
214{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700215 unsigned retrans = *s->code_ptr & 0x3fffffc;
Richard Hendersonc7ca6a22013-08-30 17:58:10 -0700216 tcg_out32(s, insn | retrans);
217}
218
219static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
220{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700221 unsigned retrans = *s->code_ptr & 0xfffc;
Richard Hendersonc7ca6a22013-08-30 17:58:10 -0700222 tcg_out32(s, insn | retrans);
223}
224
malc810260a2008-07-23 19:17:46 +0000225/* parse target specific constraints */
Richard Henderson069ea732016-11-18 11:50:59 +0100226static const char *target_parse_constraint(TCGArgConstraint *ct,
227 const char *ct_str, TCGType type)
malc810260a2008-07-23 19:17:46 +0000228{
Richard Henderson069ea732016-11-18 11:50:59 +0100229 switch (*ct_str++) {
malc810260a2008-07-23 19:17:46 +0000230 case 'A': case 'B': case 'C': case 'D':
231 ct->ct |= TCG_CT_REG;
Richard Henderson541dd4c2013-08-31 05:14:53 -0700232 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
malc810260a2008-07-23 19:17:46 +0000233 break;
234 case 'r':
235 ct->ct |= TCG_CT_REG;
Richard Hendersonf46934d2017-09-11 12:44:30 -0700236 ct->u.regs = 0xffffffff;
malc810260a2008-07-23 19:17:46 +0000237 break;
238 case 'L': /* qemu_ld constraint */
239 ct->ct |= TCG_CT_REG;
Richard Hendersonf46934d2017-09-11 12:44:30 -0700240 ct->u.regs = 0xffffffff;
Richard Henderson541dd4c2013-08-31 05:14:53 -0700241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
malc735ee402008-08-20 22:39:22 +0000242#ifdef CONFIG_SOFTMMU
Richard Henderson541dd4c2013-08-31 05:14:53 -0700243 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
244 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
Andreas Färberf4f7d012012-05-12 03:16:58 +0200245#endif
malc810260a2008-07-23 19:17:46 +0000246 break;
malcc0703552008-07-26 11:21:03 +0000247 case 'S': /* qemu_st constraint */
malc810260a2008-07-23 19:17:46 +0000248 ct->ct |= TCG_CT_REG;
Richard Hendersonf46934d2017-09-11 12:44:30 -0700249 ct->u.regs = 0xffffffff;
Richard Henderson541dd4c2013-08-31 05:14:53 -0700250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
malc735ee402008-08-20 22:39:22 +0000251#ifdef CONFIG_SOFTMMU
Richard Henderson541dd4c2013-08-31 05:14:53 -0700252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
Andreas Färberf4f7d012012-05-12 03:16:58 +0200255#endif
malc810260a2008-07-23 19:17:46 +0000256 break;
Richard Henderson3d582c62013-02-01 16:51:53 -0800257 case 'I':
258 ct->ct |= TCG_CT_CONST_S16;
259 break;
260 case 'J':
261 ct->ct |= TCG_CT_CONST_U16;
262 break;
Richard Henderson6c858762013-03-04 14:26:52 -0800263 case 'M':
264 ct->ct |= TCG_CT_CONST_MONE;
265 break;
Richard Henderson3d582c62013-02-01 16:51:53 -0800266 case 'T':
267 ct->ct |= TCG_CT_CONST_S32;
268 break;
269 case 'U':
malcfe6f9432008-07-28 23:46:06 +0000270 ct->ct |= TCG_CT_CONST_U32;
271 break;
Richard Hendersond0b07482016-11-16 12:48:55 +0100272 case 'W':
273 ct->ct |= TCG_CT_CONST_WSZ;
274 break;
Richard Henderson3d582c62013-02-01 16:51:53 -0800275 case 'Z':
276 ct->ct |= TCG_CT_CONST_ZERO;
277 break;
malc810260a2008-07-23 19:17:46 +0000278 default:
Richard Henderson069ea732016-11-18 11:50:59 +0100279 return NULL;
malc810260a2008-07-23 19:17:46 +0000280 }
Richard Henderson069ea732016-11-18 11:50:59 +0100281 return ct_str;
malc810260a2008-07-23 19:17:46 +0000282}
283
284/* test if a constant matches the constraint */
Richard Hendersonf6c6afc2014-03-30 21:22:11 -0700285static int tcg_target_const_match(tcg_target_long val, TCGType type,
Richard Henderson541dd4c2013-08-31 05:14:53 -0700286 const TCGArgConstraint *arg_ct)
malc810260a2008-07-23 19:17:46 +0000287{
Richard Henderson3d582c62013-02-01 16:51:53 -0800288 int ct = arg_ct->ct;
289 if (ct & TCG_CT_CONST) {
malc810260a2008-07-23 19:17:46 +0000290 return 1;
Richard Henderson1194dcb2014-03-30 22:07:27 -0700291 }
292
293 /* The only 32-bit constraint we use aside from
294 TCG_CT_CONST is TCG_CT_CONST_S16. */
295 if (type == TCG_TYPE_I32) {
296 val = (int32_t)val;
297 }
298
299 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
malcfe6f9432008-07-28 23:46:06 +0000300 return 1;
Richard Henderson3d582c62013-02-01 16:51:53 -0800301 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
302 return 1;
303 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
304 return 1;
305 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
306 return 1;
307 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
308 return 1;
Richard Henderson6c858762013-03-04 14:26:52 -0800309 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
310 return 1;
Richard Hendersond0b07482016-11-16 12:48:55 +0100311 } else if ((ct & TCG_CT_CONST_WSZ)
312 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
313 return 1;
Richard Henderson3d582c62013-02-01 16:51:53 -0800314 }
malc810260a2008-07-23 19:17:46 +0000315 return 0;
316}
317
318#define OPCD(opc) ((opc)<<26)
319#define XO19(opc) (OPCD(19)|((opc)<<1))
Anton Blanchard8a94cfb2013-06-11 21:19:35 +1000320#define MD30(opc) (OPCD(30)|((opc)<<2))
321#define MDS30(opc) (OPCD(30)|((opc)<<1))
malc810260a2008-07-23 19:17:46 +0000322#define XO31(opc) (OPCD(31)|((opc)<<1))
323#define XO58(opc) (OPCD(58)|(opc))
324#define XO62(opc) (OPCD(62)|(opc))
325
326#define B OPCD( 18)
327#define BC OPCD( 16)
328#define LBZ OPCD( 34)
329#define LHZ OPCD( 40)
330#define LHA OPCD( 42)
331#define LWZ OPCD( 32)
332#define STB OPCD( 38)
333#define STH OPCD( 44)
334#define STW OPCD( 36)
335
336#define STD XO62( 0)
337#define STDU XO62( 1)
338#define STDX XO31(149)
339
340#define LD XO58( 0)
341#define LDX XO31( 21)
342#define LDU XO58( 1)
malc301f6d92008-07-27 10:28:15 +0000343#define LWA XO58( 2)
malc810260a2008-07-23 19:17:46 +0000344#define LWAX XO31(341)
345
malc1cd62ae2010-02-07 02:48:53 +0300346#define ADDIC OPCD( 12)
malc810260a2008-07-23 19:17:46 +0000347#define ADDI OPCD( 14)
348#define ADDIS OPCD( 15)
349#define ORI OPCD( 24)
350#define ORIS OPCD( 25)
351#define XORI OPCD( 26)
352#define XORIS OPCD( 27)
353#define ANDI OPCD( 28)
354#define ANDIS OPCD( 29)
355#define MULLI OPCD( 7)
356#define CMPLI OPCD( 10)
357#define CMPI OPCD( 11)
Richard Henderson148bdd22013-04-04 07:30:20 -0700358#define SUBFIC OPCD( 8)
malc810260a2008-07-23 19:17:46 +0000359
360#define LWZU OPCD( 33)
361#define STWU OPCD( 37)
362
Richard Henderson313d91c2013-01-30 19:24:06 -0800363#define RLWIMI OPCD( 20)
malc810260a2008-07-23 19:17:46 +0000364#define RLWINM OPCD( 21)
Richard Henderson313d91c2013-01-30 19:24:06 -0800365#define RLWNM OPCD( 23)
malc810260a2008-07-23 19:17:46 +0000366
Anton Blanchard8a94cfb2013-06-11 21:19:35 +1000367#define RLDICL MD30( 0)
368#define RLDICR MD30( 1)
369#define RLDIMI MD30( 3)
370#define RLDCL MDS30( 8)
malc810260a2008-07-23 19:17:46 +0000371
372#define BCLR XO19( 16)
373#define BCCTR XO19(528)
374#define CRAND XO19(257)
375#define CRANDC XO19(129)
376#define CRNAND XO19(225)
377#define CROR XO19(449)
malc1cd62ae2010-02-07 02:48:53 +0300378#define CRNOR XO19( 33)
malc810260a2008-07-23 19:17:46 +0000379
380#define EXTSB XO31(954)
381#define EXTSH XO31(922)
382#define EXTSW XO31(986)
383#define ADD XO31(266)
384#define ADDE XO31(138)
Richard Henderson6c858762013-03-04 14:26:52 -0800385#define ADDME XO31(234)
386#define ADDZE XO31(202)
malc810260a2008-07-23 19:17:46 +0000387#define ADDC XO31( 10)
388#define AND XO31( 28)
389#define SUBF XO31( 40)
390#define SUBFC XO31( 8)
391#define SUBFE XO31(136)
Richard Henderson6c858762013-03-04 14:26:52 -0800392#define SUBFME XO31(232)
393#define SUBFZE XO31(200)
malc810260a2008-07-23 19:17:46 +0000394#define OR XO31(444)
395#define XOR XO31(316)
396#define MULLW XO31(235)
Richard Henderson8fa391a2014-03-26 11:37:06 -0700397#define MULHW XO31( 75)
malc810260a2008-07-23 19:17:46 +0000398#define MULHWU XO31( 11)
399#define DIVW XO31(491)
400#define DIVWU XO31(459)
401#define CMP XO31( 0)
402#define CMPL XO31( 32)
403#define LHBRX XO31(790)
404#define LWBRX XO31(534)
Richard Henderson49d98702013-02-02 00:58:14 -0800405#define LDBRX XO31(532)
malc810260a2008-07-23 19:17:46 +0000406#define STHBRX XO31(918)
407#define STWBRX XO31(662)
Richard Henderson49d98702013-02-02 00:58:14 -0800408#define STDBRX XO31(660)
malc810260a2008-07-23 19:17:46 +0000409#define MFSPR XO31(339)
410#define MTSPR XO31(467)
411#define SRAWI XO31(824)
412#define NEG XO31(104)
malc1cd62ae2010-02-07 02:48:53 +0300413#define MFCR XO31( 19)
Richard Henderson6995a4a2013-04-02 15:09:52 -0700414#define MFOCRF (MFCR | (1u << 20))
malc157f2662011-08-22 14:40:00 +0400415#define NOR XO31(124)
malc1cd62ae2010-02-07 02:48:53 +0300416#define CNTLZW XO31( 26)
417#define CNTLZD XO31( 58)
Richard Hendersond0b07482016-11-16 12:48:55 +0100418#define CNTTZW XO31(538)
419#define CNTTZD XO31(570)
Richard Henderson33e75fb2016-11-22 11:43:12 +0000420#define CNTPOPW XO31(378)
421#define CNTPOPD XO31(506)
Richard Hendersonce1010d2013-01-31 07:49:13 -0800422#define ANDC XO31( 60)
423#define ORC XO31(412)
424#define EQV XO31(284)
425#define NAND XO31(476)
Richard Henderson70fac592013-04-02 15:16:10 -0700426#define ISEL XO31( 15)
malc810260a2008-07-23 19:17:46 +0000427
428#define MULLD XO31(233)
429#define MULHD XO31( 73)
430#define MULHDU XO31( 9)
431#define DIVD XO31(489)
432#define DIVDU XO31(457)
433
434#define LBZX XO31( 87)
malc4f4a67a2009-07-18 13:15:55 +0400435#define LHZX XO31(279)
malc810260a2008-07-23 19:17:46 +0000436#define LHAX XO31(343)
437#define LWZX XO31( 23)
438#define STBX XO31(215)
439#define STHX XO31(407)
440#define STWX XO31(151)
441
Pranith Kumar7b4af5e2016-07-14 16:20:19 -0400442#define EIEIO XO31(854)
443#define HWSYNC XO31(598)
444#define LWSYNC (HWSYNC | (1u << 21))
445
Richard Henderson541dd4c2013-08-31 05:14:53 -0700446#define SPR(a, b) ((((a)<<5)|(b))<<11)
malc810260a2008-07-23 19:17:46 +0000447#define LR SPR(8, 0)
448#define CTR SPR(9, 0)
449
450#define SLW XO31( 24)
451#define SRW XO31(536)
452#define SRAW XO31(792)
453
454#define SLD XO31( 27)
455#define SRD XO31(539)
456#define SRAD XO31(794)
malcfe6f9432008-07-28 23:46:06 +0000457#define SRADI XO31(413<<1)
malc810260a2008-07-23 19:17:46 +0000458
malc810260a2008-07-23 19:17:46 +0000459#define TW XO31( 4)
Richard Henderson541dd4c2013-08-31 05:14:53 -0700460#define TRAP (TW | TO(31))
malc810260a2008-07-23 19:17:46 +0000461
Richard Hendersona84ac4c2014-03-28 06:53:53 -0700462#define NOP ORI /* ori 0,0,0 */
463
malc810260a2008-07-23 19:17:46 +0000464#define RT(r) ((r)<<21)
465#define RS(r) ((r)<<21)
466#define RA(r) ((r)<<16)
467#define RB(r) ((r)<<11)
468#define TO(t) ((t)<<21)
469#define SH(s) ((s)<<11)
470#define MB(b) ((b)<<6)
471#define ME(e) ((e)<<1)
472#define BO(o) ((o)<<21)
473#define MB64(b) ((b)<<5)
Richard Henderson6995a4a2013-04-02 15:09:52 -0700474#define FXM(b) (1 << (19 - (b)))
malc810260a2008-07-23 19:17:46 +0000475
476#define LK 1
477
Richard Henderson2fd8edd2013-02-01 16:08:50 -0800478#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
479#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
480#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
481#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
malc810260a2008-07-23 19:17:46 +0000482
483#define BF(n) ((n)<<23)
484#define BI(n, c) (((c)+((n)*4))<<16)
485#define BT(n, c) (((c)+((n)*4))<<21)
486#define BA(n, c) (((c)+((n)*4))<<16)
487#define BB(n, c) (((c)+((n)*4))<<11)
Richard Henderson70fac592013-04-02 15:16:10 -0700488#define BC_(n, c) (((c)+((n)*4))<<6)
malc810260a2008-07-23 19:17:46 +0000489
Richard Henderson541dd4c2013-08-31 05:14:53 -0700490#define BO_COND_TRUE BO(12)
491#define BO_COND_FALSE BO( 4)
492#define BO_ALWAYS BO(20)
malc810260a2008-07-23 19:17:46 +0000493
494enum {
495 CR_LT,
496 CR_GT,
497 CR_EQ,
498 CR_SO
499};
500
Richard Henderson0aed2572012-09-24 14:21:40 -0700501static const uint32_t tcg_to_bc[] = {
Richard Henderson541dd4c2013-08-31 05:14:53 -0700502 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
503 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
504 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
505 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
506 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
507 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
508 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
509 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
510 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
511 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
malc810260a2008-07-23 19:17:46 +0000512};
513
Richard Henderson70fac592013-04-02 15:16:10 -0700514/* The low bit here is set if the RA and RB fields must be inverted. */
515static const uint32_t tcg_to_isel[] = {
516 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
517 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
518 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
519 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
520 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
521 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
522 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
523 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
524 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
525 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
526};
527
Richard Henderson030ffe32018-01-10 07:31:46 +0000528static void patch_reloc(tcg_insn_unit *code_ptr, int type,
529 intptr_t value, intptr_t addend)
530{
531 tcg_insn_unit *target;
532 tcg_insn_unit old;
533
534 value += addend;
535 target = (tcg_insn_unit *)value;
536
537 switch (type) {
538 case R_PPC_REL14:
539 reloc_pc14(code_ptr, target);
540 break;
541 case R_PPC_REL24:
542 reloc_pc24(code_ptr, target);
543 break;
544 case R_PPC_ADDR16:
545 /* We are abusing this relocation type. This points to a pair
546 of insns, addis + load. If the displacement is small, we
547 can nop out the addis. */
548 if (value == (int16_t)value) {
549 code_ptr[0] = NOP;
550 old = deposit32(code_ptr[1], 0, 16, value);
551 code_ptr[1] = deposit32(old, 16, 5, TCG_REG_TB);
552 } else {
553 int16_t lo = value;
554 int hi = value - lo;
555 assert(hi + lo == value);
556 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
557 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
558 }
559 break;
560 default:
561 g_assert_not_reached();
562 }
563}
564
Richard Hendersona84ac4c2014-03-28 06:53:53 -0700565static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
566 TCGReg base, tcg_target_long offset);
567
Richard Henderson796f1a62014-04-30 11:39:20 -0700568static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
malc810260a2008-07-23 19:17:46 +0000569{
Richard Henderson796f1a62014-04-30 11:39:20 -0700570 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
Richard Hendersonf8b84122013-07-30 18:26:04 -1000571 if (ret != arg) {
572 tcg_out32(s, OR | SAB(arg, ret, arg));
573 }
malc810260a2008-07-23 19:17:46 +0000574}
575
Richard Hendersonaceac8d2013-02-01 14:48:37 -0800576static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
577 int sh, int mb)
malc810260a2008-07-23 19:17:46 +0000578{
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +0200579 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
Richard Henderson541dd4c2013-08-31 05:14:53 -0700580 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
581 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
582 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
malc810260a2008-07-23 19:17:46 +0000583}
584
Richard Henderson9e555b72013-02-01 15:00:45 -0800585static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
586 int sh, int mb, int me)
587{
588 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
589}
590
Richard Henderson6e5e0602013-02-01 15:06:30 -0800591static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
592{
593 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
594}
595
Richard Hendersona757e1e2014-03-26 18:10:43 -0700596static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
597{
598 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
599}
600
Richard Henderson0a9564b2013-02-01 15:12:14 -0800601static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
602{
603 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
604}
605
Richard Hendersona757e1e2014-03-26 18:10:43 -0700606static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
607{
608 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
609}
610
Richard Henderson5e916c22013-02-01 15:19:05 -0800611static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
612{
613 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
614}
615
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000616/* Emit a move into ret of arg, if it can be done in one insn. */
617static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
618{
619 if (arg == (int16_t)arg) {
620 tcg_out32(s, ADDI | TAI(ret, 0, arg));
621 return true;
622 }
623 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
624 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
625 return true;
626 }
627 return false;
628}
629
Richard Henderson5964fca2017-07-31 04:16:10 +0000630static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
631 tcg_target_long arg, bool in_prologue)
malc810260a2008-07-23 19:17:46 +0000632{
Richard Henderson5964fca2017-07-31 04:16:10 +0000633 intptr_t tb_diff;
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000634 tcg_target_long tmp;
635 int shift;
Richard Henderson5964fca2017-07-31 04:16:10 +0000636
637 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
638
639 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
640 arg = (int32_t)arg;
641 }
642
643 /* Load 16-bit immediates with one insn. */
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000644 if (tcg_out_movi_one(s, ret, arg)) {
Richard Henderson5964fca2017-07-31 04:16:10 +0000645 return;
646 }
647
648 /* Load addresses within the TB with one insn. */
649 tb_diff = arg - (intptr_t)s->code_gen_ptr;
650 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
651 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
652 return;
653 }
654
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000655 /* Load 32-bit immediates with two insns. Note that we've already
656 eliminated bare ADDIS, so we know both insns are required. */
Richard Henderson5964fca2017-07-31 04:16:10 +0000657 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
Richard Henderson2fd8edd2013-02-01 16:08:50 -0800658 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000659 tcg_out32(s, ORI | SAI(ret, ret, arg));
Richard Henderson5964fca2017-07-31 04:16:10 +0000660 return;
661 }
662 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
663 tcg_out32(s, ADDI | TAI(ret, 0, arg));
664 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
665 return;
666 }
667
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000668 /* Load masked 16-bit value. */
669 if (arg > 0 && (arg & 0x8000)) {
670 tmp = arg | 0x7fff;
671 if ((tmp & (tmp + 1)) == 0) {
672 int mb = clz64(tmp + 1) + 1;
673 tcg_out32(s, ADDI | TAI(ret, 0, arg));
674 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
675 return;
676 }
677 }
678
679 /* Load common masks with 2 insns. */
680 shift = ctz64(arg);
681 tmp = arg >> shift;
682 if (tmp == (int16_t)tmp) {
683 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
684 tcg_out_shli64(s, ret, ret, shift);
685 return;
686 }
687 shift = clz64(arg);
688 if (tcg_out_movi_one(s, ret, arg << shift)) {
689 tcg_out_shri64(s, ret, ret, shift);
690 return;
691 }
692
Richard Henderson5964fca2017-07-31 04:16:10 +0000693 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
694 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
695 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
696 return;
697 }
698
Richard Henderson53c89ef2017-07-31 06:03:03 +0000699 /* Use the constant pool, if possible. */
700 if (!in_prologue && USE_REG_TB) {
701 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
702 -(intptr_t)s->code_gen_ptr);
Richard Henderson030ffe32018-01-10 07:31:46 +0000703 tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0));
704 tcg_out32(s, LD | TAI(ret, ret, 0));
Richard Henderson53c89ef2017-07-31 06:03:03 +0000705 return;
706 }
707
Richard Henderson77bfc7c2017-07-31 04:54:02 +0000708 tmp = arg >> 31 >> 1;
709 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
710 if (tmp) {
Richard Henderson5964fca2017-07-31 04:16:10 +0000711 tcg_out_shli64(s, ret, ret, 32);
712 }
713 if (arg & 0xffff0000) {
714 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
715 }
716 if (arg & 0xffff) {
717 tcg_out32(s, ORI | SAI(ret, ret, arg));
malc810260a2008-07-23 19:17:46 +0000718 }
719}
720
Richard Henderson5964fca2017-07-31 04:16:10 +0000721static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
722 tcg_target_long arg)
malc810260a2008-07-23 19:17:46 +0000723{
Richard Henderson5964fca2017-07-31 04:16:10 +0000724 tcg_out_movi_int(s, type, ret, arg, false);
malc810260a2008-07-23 19:17:46 +0000725}
726
Richard Henderson637af302013-02-01 23:58:17 -0800727static bool mask_operand(uint32_t c, int *mb, int *me)
Richard Hendersona9249df2013-02-01 23:43:42 -0800728{
729 uint32_t lsb, test;
730
731 /* Accept a bit pattern like:
732 0....01....1
733 1....10....0
734 0..01..10..0
735 Keep track of the transitions. */
736 if (c == 0 || c == -1) {
737 return false;
738 }
739 test = c;
740 lsb = test & -test;
741 test += lsb;
742 if (test & (test - 1)) {
743 return false;
744 }
745
746 *me = clz32(lsb);
747 *mb = test ? clz32(test & -test) + 1 : 0;
748 return true;
749}
750
Richard Henderson637af302013-02-01 23:58:17 -0800751static bool mask64_operand(uint64_t c, int *mb, int *me)
752{
753 uint64_t lsb;
754
755 if (c == 0) {
756 return false;
757 }
758
759 lsb = c & -c;
760 /* Accept 1..10..0. */
761 if (c == -lsb) {
762 *mb = 0;
763 *me = clz64(lsb);
764 return true;
765 }
766 /* Accept 0..01..1. */
767 if (lsb == 1 && (c & (c + 1)) == 0) {
768 *mb = clz64(c + 1) + 1;
769 *me = 63;
770 return true;
771 }
772 return false;
773}
774
Richard Hendersona9249df2013-02-01 23:43:42 -0800775static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
776{
777 int mb, me;
778
Richard Henderson1e1df962015-10-02 22:41:01 +0000779 if (mask_operand(c, &mb, &me)) {
780 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
781 } else if ((c & 0xffff) == c) {
Richard Hendersona9249df2013-02-01 23:43:42 -0800782 tcg_out32(s, ANDI | SAI(src, dst, c));
783 return;
784 } else if ((c & 0xffff0000) == c) {
785 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
786 return;
Richard Hendersona9249df2013-02-01 23:43:42 -0800787 } else {
Richard Henderson8327a472013-08-31 05:41:45 -0700788 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
789 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
Richard Hendersona9249df2013-02-01 23:43:42 -0800790 }
791}
792
Richard Henderson637af302013-02-01 23:58:17 -0800793static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
794{
795 int mb, me;
796
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +0200797 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
Richard Henderson1e1df962015-10-02 22:41:01 +0000798 if (mask64_operand(c, &mb, &me)) {
Richard Henderson637af302013-02-01 23:58:17 -0800799 if (mb == 0) {
800 tcg_out_rld(s, RLDICR, dst, src, 0, me);
801 } else {
802 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
803 }
Richard Henderson1e1df962015-10-02 22:41:01 +0000804 } else if ((c & 0xffff) == c) {
805 tcg_out32(s, ANDI | SAI(src, dst, c));
806 return;
807 } else if ((c & 0xffff0000) == c) {
808 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
809 return;
Richard Henderson637af302013-02-01 23:58:17 -0800810 } else {
Richard Henderson8327a472013-08-31 05:41:45 -0700811 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
812 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
Richard Henderson637af302013-02-01 23:58:17 -0800813 }
814}
815
Richard Hendersondce74c52013-02-01 20:22:05 -0800816static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
817 int op_lo, int op_hi)
818{
819 if (c >> 16) {
820 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
821 src = dst;
822 }
823 if (c & 0xffff) {
824 tcg_out32(s, op_lo | SAI(src, dst, c));
825 src = dst;
826 }
827}
828
829static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
830{
831 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
832}
833
834static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
835{
836 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
837}
838
Richard Hendersone083c4a2014-03-28 14:58:38 -0700839static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
Andreas Faerber5d7ff5b2009-12-06 14:00:24 +0100840{
Richard Hendersone083c4a2014-03-28 14:58:38 -0700841 ptrdiff_t disp = tcg_pcrel_diff(s, target);
Richard Hendersonb0940da2013-08-31 06:30:45 -0700842 if (in_range_b(disp)) {
Richard Henderson541dd4c2013-08-31 05:14:53 -0700843 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
844 } else {
Richard Hendersonde3d6362014-03-24 15:22:35 -0700845 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
Richard Henderson8327a472013-08-31 05:41:45 -0700846 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
Richard Henderson541dd4c2013-08-31 05:14:53 -0700847 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
Andreas Faerber5d7ff5b2009-12-06 14:00:24 +0100848 }
849}
850
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700851static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
852 TCGReg base, tcg_target_long offset)
malc810260a2008-07-23 19:17:46 +0000853{
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700854 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
Richard Hendersonde7761a2014-03-25 12:22:18 -0700855 bool is_store = false;
Richard Hendersondfca1772014-04-30 12:12:16 -0700856 TCGReg rs = TCG_REG_TMP1;
malc810260a2008-07-23 19:17:46 +0000857
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700858 switch (opi) {
859 case LD: case LWA:
860 align = 3;
861 /* FALLTHRU */
862 default:
863 if (rt != TCG_REG_R0) {
864 rs = rt;
Richard Hendersonde7761a2014-03-25 12:22:18 -0700865 break;
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700866 }
867 break;
868 case STD:
869 align = 3;
Richard Hendersonde7761a2014-03-25 12:22:18 -0700870 /* FALLTHRU */
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700871 case STB: case STH: case STW:
Richard Hendersonde7761a2014-03-25 12:22:18 -0700872 is_store = true;
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700873 break;
874 }
875
876 /* For unaligned, or very large offsets, use the indexed form. */
877 if (offset & align || offset != (int32_t)offset) {
Richard Hendersond4cba132014-06-26 21:26:00 -0700878 if (rs == base) {
879 rs = TCG_REG_R0;
880 }
881 tcg_debug_assert(!is_store || rs != rt);
Richard Hendersonde7761a2014-03-25 12:22:18 -0700882 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
883 tcg_out32(s, opx | TAB(rt, base, rs));
Richard Hendersonb18d5d22013-07-31 11:36:42 -0700884 return;
885 }
886
887 l0 = (int16_t)offset;
888 offset = (offset - l0) >> 16;
889 l1 = (int16_t)offset;
890
891 if (l1 < 0 && orig >= 0) {
892 extra = 0x4000;
893 l1 = (int16_t)(offset - 0x4000);
894 }
895 if (l1) {
896 tcg_out32(s, ADDIS | TAI(rs, base, l1));
897 base = rs;
898 }
899 if (extra) {
900 tcg_out32(s, ADDIS | TAI(rs, base, extra));
901 base = rs;
902 }
903 if (opi != ADDI || base != rt || l0 != 0) {
904 tcg_out32(s, opi | TAI(rt, base, l0));
malc828808f2008-11-11 03:04:57 +0000905 }
906}
907
Richard Hendersond604f1a2014-03-24 15:44:09 -0700908static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
909 TCGReg arg1, intptr_t arg2)
910{
911 int opi, opx;
912
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +0200913 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
Richard Hendersond604f1a2014-03-24 15:44:09 -0700914 if (type == TCG_TYPE_I32) {
915 opi = LWZ, opx = LWZX;
916 } else {
917 opi = LD, opx = LDX;
918 }
919 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
920}
921
922static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
923 TCGReg arg1, intptr_t arg2)
924{
925 int opi, opx;
926
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +0200927 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
Richard Hendersond604f1a2014-03-24 15:44:09 -0700928 if (type == TCG_TYPE_I32) {
929 opi = STW, opx = STWX;
930 } else {
931 opi = STD, opx = STDX;
932 }
933 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
934}
935
Richard Henderson59d7c142016-06-19 22:59:13 -0700936static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
937 TCGReg base, intptr_t ofs)
938{
939 return false;
940}
941
Richard Hendersond604f1a2014-03-24 15:44:09 -0700942static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
943 int const_arg2, int cr, TCGType type)
944{
945 int imm;
946 uint32_t op;
947
Richard Hendersonabcf61c2014-04-30 11:55:34 -0700948 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
949
Richard Hendersond604f1a2014-03-24 15:44:09 -0700950 /* Simplify the comparisons below wrt CMPI. */
951 if (type == TCG_TYPE_I32) {
952 arg2 = (int32_t)arg2;
953 }
954
955 switch (cond) {
956 case TCG_COND_EQ:
957 case TCG_COND_NE:
958 if (const_arg2) {
959 if ((int16_t) arg2 == arg2) {
960 op = CMPI;
961 imm = 1;
962 break;
963 } else if ((uint16_t) arg2 == arg2) {
964 op = CMPLI;
965 imm = 1;
966 break;
967 }
968 }
969 op = CMPL;
970 imm = 0;
971 break;
972
973 case TCG_COND_LT:
974 case TCG_COND_GE:
975 case TCG_COND_LE:
976 case TCG_COND_GT:
977 if (const_arg2) {
978 if ((int16_t) arg2 == arg2) {
979 op = CMPI;
980 imm = 1;
981 break;
982 }
983 }
984 op = CMP;
985 imm = 0;
986 break;
987
988 case TCG_COND_LTU:
989 case TCG_COND_GEU:
990 case TCG_COND_LEU:
991 case TCG_COND_GTU:
992 if (const_arg2) {
993 if ((uint16_t) arg2 == arg2) {
994 op = CMPLI;
995 imm = 1;
996 break;
997 }
998 }
999 op = CMPL;
1000 imm = 0;
1001 break;
1002
1003 default:
1004 tcg_abort();
1005 }
1006 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1007
1008 if (imm) {
1009 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1010 } else {
1011 if (const_arg2) {
1012 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1013 arg2 = TCG_REG_R0;
1014 }
1015 tcg_out32(s, op | RA(arg1) | RB(arg2));
1016 }
1017}
1018
1019static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1020 TCGReg dst, TCGReg src)
1021{
Richard Hendersona757e1e2014-03-26 18:10:43 -07001022 if (type == TCG_TYPE_I32) {
1023 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1024 tcg_out_shri32(s, dst, dst, 5);
1025 } else {
1026 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1027 tcg_out_shri64(s, dst, dst, 6);
1028 }
Richard Hendersond604f1a2014-03-24 15:44:09 -07001029}
1030
1031static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1032{
1033 /* X != 0 implies X + -1 generates a carry. Extra addition
1034 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1035 if (dst != src) {
1036 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1037 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1038 } else {
1039 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1040 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1041 }
1042}
1043
1044static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1045 bool const_arg2)
1046{
1047 if (const_arg2) {
1048 if ((uint32_t)arg2 == arg2) {
1049 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1050 } else {
1051 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1052 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1053 }
1054 } else {
1055 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1056 }
1057 return TCG_REG_R0;
1058}
1059
1060static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1061 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1062 int const_arg2)
1063{
1064 int crop, sh;
1065
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +02001066 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
Richard Hendersona757e1e2014-03-26 18:10:43 -07001067
Richard Hendersond604f1a2014-03-24 15:44:09 -07001068 /* Ignore high bits of a potential constant arg2. */
1069 if (type == TCG_TYPE_I32) {
1070 arg2 = (uint32_t)arg2;
1071 }
1072
1073 /* Handle common and trivial cases before handling anything else. */
1074 if (arg2 == 0) {
1075 switch (cond) {
1076 case TCG_COND_EQ:
1077 tcg_out_setcond_eq0(s, type, arg0, arg1);
1078 return;
1079 case TCG_COND_NE:
Richard Hendersona757e1e2014-03-26 18:10:43 -07001080 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
Richard Hendersond604f1a2014-03-24 15:44:09 -07001081 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1082 arg1 = TCG_REG_R0;
1083 }
1084 tcg_out_setcond_ne0(s, arg0, arg1);
1085 return;
1086 case TCG_COND_GE:
1087 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1088 arg1 = arg0;
1089 /* FALLTHRU */
1090 case TCG_COND_LT:
1091 /* Extract the sign bit. */
Richard Hendersona757e1e2014-03-26 18:10:43 -07001092 if (type == TCG_TYPE_I32) {
1093 tcg_out_shri32(s, arg0, arg1, 31);
1094 } else {
1095 tcg_out_shri64(s, arg0, arg1, 63);
1096 }
Richard Hendersond604f1a2014-03-24 15:44:09 -07001097 return;
1098 default:
1099 break;
1100 }
1101 }
1102
1103 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1104 All other cases below are also at least 3 insns, so speed up the
1105 code generator by not considering them and always using ISEL. */
1106 if (HAVE_ISEL) {
1107 int isel, tab;
1108
1109 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1110
1111 isel = tcg_to_isel[cond];
1112
1113 tcg_out_movi(s, type, arg0, 1);
1114 if (isel & 1) {
1115 /* arg0 = (bc ? 0 : 1) */
1116 tab = TAB(arg0, 0, arg0);
1117 isel &= ~1;
1118 } else {
1119 /* arg0 = (bc ? 1 : 0) */
1120 tcg_out_movi(s, type, TCG_REG_R0, 0);
1121 tab = TAB(arg0, arg0, TCG_REG_R0);
1122 }
1123 tcg_out32(s, isel | tab);
1124 return;
1125 }
1126
1127 switch (cond) {
1128 case TCG_COND_EQ:
1129 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1130 tcg_out_setcond_eq0(s, type, arg0, arg1);
1131 return;
1132
1133 case TCG_COND_NE:
1134 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1135 /* Discard the high bits only once, rather than both inputs. */
Richard Hendersona757e1e2014-03-26 18:10:43 -07001136 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
Richard Hendersond604f1a2014-03-24 15:44:09 -07001137 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1138 arg1 = TCG_REG_R0;
1139 }
1140 tcg_out_setcond_ne0(s, arg0, arg1);
1141 return;
1142
1143 case TCG_COND_GT:
1144 case TCG_COND_GTU:
1145 sh = 30;
1146 crop = 0;
1147 goto crtest;
1148
1149 case TCG_COND_LT:
1150 case TCG_COND_LTU:
1151 sh = 29;
1152 crop = 0;
1153 goto crtest;
1154
1155 case TCG_COND_GE:
1156 case TCG_COND_GEU:
1157 sh = 31;
1158 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1159 goto crtest;
1160
1161 case TCG_COND_LE:
1162 case TCG_COND_LEU:
1163 sh = 31;
1164 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1165 crtest:
1166 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1167 if (crop) {
1168 tcg_out32(s, crop);
1169 }
1170 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1171 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1172 break;
1173
1174 default:
1175 tcg_abort();
1176 }
1177}
1178
Richard Hendersonbec16312015-02-13 13:39:54 -08001179static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
Richard Hendersond604f1a2014-03-24 15:44:09 -07001180{
Richard Hendersond604f1a2014-03-24 15:44:09 -07001181 if (l->has_value) {
1182 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1183 } else {
Richard Hendersonbec16312015-02-13 13:39:54 -08001184 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
Richard Hendersond604f1a2014-03-24 15:44:09 -07001185 tcg_out_bc_noaddr(s, bc);
1186 }
1187}
1188
1189static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1190 TCGArg arg1, TCGArg arg2, int const_arg2,
Richard Hendersonbec16312015-02-13 13:39:54 -08001191 TCGLabel *l, TCGType type)
Richard Hendersond604f1a2014-03-24 15:44:09 -07001192{
1193 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
Richard Hendersonbec16312015-02-13 13:39:54 -08001194 tcg_out_bc(s, tcg_to_bc[cond], l);
Richard Hendersond604f1a2014-03-24 15:44:09 -07001195}
1196
1197static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1198 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1199 TCGArg v2, bool const_c2)
1200{
1201 /* If for some reason both inputs are zero, don't produce bad code. */
1202 if (v1 == 0 && v2 == 0) {
1203 tcg_out_movi(s, type, dest, 0);
1204 return;
1205 }
1206
1207 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1208
1209 if (HAVE_ISEL) {
1210 int isel = tcg_to_isel[cond];
1211
1212 /* Swap the V operands if the operation indicates inversion. */
1213 if (isel & 1) {
1214 int t = v1;
1215 v1 = v2;
1216 v2 = t;
1217 isel &= ~1;
1218 }
1219 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1220 if (v2 == 0) {
1221 tcg_out_movi(s, type, TCG_REG_R0, 0);
1222 }
1223 tcg_out32(s, isel | TAB(dest, v1, v2));
1224 } else {
1225 if (dest == v2) {
1226 cond = tcg_invert_cond(cond);
1227 v2 = v1;
1228 } else if (dest != v1) {
1229 if (v1 == 0) {
1230 tcg_out_movi(s, type, dest, 0);
1231 } else {
1232 tcg_out_mov(s, type, dest, v1);
1233 }
1234 }
1235 /* Branch forward over one insn */
1236 tcg_out32(s, tcg_to_bc[cond] | 8);
1237 if (v2 == 0) {
1238 tcg_out_movi(s, type, dest, 0);
1239 } else {
1240 tcg_out_mov(s, type, dest, v2);
1241 }
1242 }
1243}
1244
Richard Hendersond0b07482016-11-16 12:48:55 +01001245static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1246 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1247{
1248 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1249 tcg_out32(s, opc | RA(a0) | RS(a1));
1250 } else {
1251 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1252 /* Note that the only other valid constant for a2 is 0. */
1253 if (HAVE_ISEL) {
1254 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1255 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1256 } else if (!const_a2 && a0 == a2) {
1257 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1258 tcg_out32(s, opc | RA(a0) | RS(a1));
1259 } else {
1260 tcg_out32(s, opc | RA(a0) | RS(a1));
1261 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1262 if (const_a2) {
1263 tcg_out_movi(s, type, a0, 0);
1264 } else {
1265 tcg_out_mov(s, type, a0, a2);
1266 }
1267 }
1268 }
1269}
1270
Richard Hendersonabcf61c2014-04-30 11:55:34 -07001271static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1272 const int *const_args)
1273{
1274 static const struct { uint8_t bit1, bit2; } bits[] = {
1275 [TCG_COND_LT ] = { CR_LT, CR_LT },
1276 [TCG_COND_LE ] = { CR_LT, CR_GT },
1277 [TCG_COND_GT ] = { CR_GT, CR_GT },
1278 [TCG_COND_GE ] = { CR_GT, CR_LT },
1279 [TCG_COND_LTU] = { CR_LT, CR_LT },
1280 [TCG_COND_LEU] = { CR_LT, CR_GT },
1281 [TCG_COND_GTU] = { CR_GT, CR_GT },
1282 [TCG_COND_GEU] = { CR_GT, CR_LT },
1283 };
1284
1285 TCGCond cond = args[4], cond2;
1286 TCGArg al, ah, bl, bh;
1287 int blconst, bhconst;
1288 int op, bit1, bit2;
1289
1290 al = args[0];
1291 ah = args[1];
1292 bl = args[2];
1293 bh = args[3];
1294 blconst = const_args[2];
1295 bhconst = const_args[3];
1296
1297 switch (cond) {
1298 case TCG_COND_EQ:
1299 op = CRAND;
1300 goto do_equality;
1301 case TCG_COND_NE:
1302 op = CRNAND;
1303 do_equality:
1304 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1305 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1306 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1307 break;
1308
1309 case TCG_COND_LT:
1310 case TCG_COND_LE:
1311 case TCG_COND_GT:
1312 case TCG_COND_GE:
1313 case TCG_COND_LTU:
1314 case TCG_COND_LEU:
1315 case TCG_COND_GTU:
1316 case TCG_COND_GEU:
1317 bit1 = bits[cond].bit1;
1318 bit2 = bits[cond].bit2;
1319 op = (bit1 != bit2 ? CRANDC : CRAND);
1320 cond2 = tcg_unsigned_cond(cond);
1321
1322 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1323 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1324 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1325 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1326 break;
1327
1328 default:
1329 tcg_abort();
1330 }
1331}
1332
1333static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1334 const int *const_args)
1335{
1336 tcg_out_cmp2(s, args + 1, const_args + 1);
1337 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1338 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1339}
1340
1341static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1342 const int *const_args)
1343{
1344 tcg_out_cmp2(s, args, const_args);
Richard Hendersonbec16312015-02-13 13:39:54 -08001345 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
Richard Hendersonabcf61c2014-04-30 11:55:34 -07001346}
1347
Pranith Kumar7b4af5e2016-07-14 16:20:19 -04001348static void tcg_out_mb(TCGContext *s, TCGArg a0)
1349{
1350 uint32_t insn = HWSYNC;
1351 a0 &= TCG_MO_ALL;
1352 if (a0 == TCG_MO_LD_LD) {
1353 insn = LWSYNC;
1354 } else if (a0 == TCG_MO_ST_ST) {
1355 insn = EIEIO;
1356 }
1357 tcg_out32(s, insn);
1358}
1359
Richard Hendersona8583392017-07-31 22:02:31 -07001360void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
1361 uintptr_t addr)
Richard Hendersond604f1a2014-03-24 15:44:09 -07001362{
Richard Henderson5964fca2017-07-31 04:16:10 +00001363 if (TCG_TARGET_REG_BITS == 64) {
1364 tcg_insn_unit i1, i2;
1365 intptr_t tb_diff = addr - tc_ptr;
1366 intptr_t br_diff = addr - (jmp_addr + 4);
1367 uint64_t pair;
Richard Hendersond604f1a2014-03-24 15:44:09 -07001368
Richard Henderson5964fca2017-07-31 04:16:10 +00001369 /* This does not exercise the range of the branch, but we do
1370 still need to be able to load the new value of TCG_REG_TB.
1371 But this does still happen quite often. */
1372 if (tb_diff == (int16_t)tb_diff) {
1373 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1374 i2 = B | (br_diff & 0x3fffffc);
1375 } else {
1376 intptr_t lo = (int16_t)tb_diff;
1377 intptr_t hi = (int32_t)(tb_diff - lo);
1378 assert(tb_diff == hi + lo);
1379 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1380 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
1381 }
Richard Henderson5bfd75a2015-10-02 22:25:28 +00001382#ifdef HOST_WORDS_BIGENDIAN
Richard Henderson5964fca2017-07-31 04:16:10 +00001383 pair = (uint64_t)i1 << 32 | i2;
Richard Henderson5bfd75a2015-10-02 22:25:28 +00001384#else
Richard Henderson5964fca2017-07-31 04:16:10 +00001385 pair = (uint64_t)i2 << 32 | i1;
Richard Henderson5bfd75a2015-10-02 22:25:28 +00001386#endif
1387
Philippe Mathieu-Daudéba026602017-09-11 17:49:36 -03001388 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
1389 within atomic_set that would fail to build a ppc32 host. */
1390 atomic_set__nocheck((uint64_t *)jmp_addr, pair);
Richard Henderson5964fca2017-07-31 04:16:10 +00001391 flush_icache_range(jmp_addr, jmp_addr + 8);
1392 } else {
1393 intptr_t diff = addr - jmp_addr;
1394 tcg_debug_assert(in_range_b(diff));
1395 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1396 flush_icache_range(jmp_addr, jmp_addr + 4);
1397 }
Richard Hendersond604f1a2014-03-24 15:44:09 -07001398}
1399
1400static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1401{
Richard Hendersoneaf7d1c2014-04-30 11:57:11 -07001402#ifdef _CALL_AIX
Richard Hendersond604f1a2014-03-24 15:44:09 -07001403 /* Look through the descriptor. If the branch is in range, and we
1404 don't have to spend too much effort on building the toc. */
1405 void *tgt = ((void **)target)[0];
1406 uintptr_t toc = ((uintptr_t *)target)[1];
1407 intptr_t diff = tcg_pcrel_diff(s, tgt);
1408
1409 if (in_range_b(diff) && toc == (uint32_t)toc) {
Richard Hendersondfca1772014-04-30 12:12:16 -07001410 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
Richard Hendersond604f1a2014-03-24 15:44:09 -07001411 tcg_out_b(s, LK, tgt);
1412 } else {
1413 /* Fold the low bits of the constant into the addresses below. */
1414 intptr_t arg = (intptr_t)target;
1415 int ofs = (int16_t)arg;
1416
1417 if (ofs + 8 < 0x8000) {
1418 arg -= ofs;
1419 } else {
1420 ofs = 0;
1421 }
Richard Hendersondfca1772014-04-30 12:12:16 -07001422 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1423 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
Richard Hendersond604f1a2014-03-24 15:44:09 -07001424 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
Richard Hendersondfca1772014-04-30 12:12:16 -07001425 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
Richard Hendersond604f1a2014-03-24 15:44:09 -07001426 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1427 }
Ulrich Weigand77e58d02014-04-30 14:33:05 -07001428#elif defined(_CALL_ELF) && _CALL_ELF == 2
1429 intptr_t diff;
1430
1431 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1432 address, which the callee uses to compute its TOC address. */
1433 /* FIXME: when the branch is in range, we could avoid r12 load if we
1434 knew that the destination uses the same TOC, and what its local
1435 entry point offset is. */
1436 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1437
1438 diff = tcg_pcrel_diff(s, target);
1439 if (in_range_b(diff)) {
1440 tcg_out_b(s, LK, target);
1441 } else {
1442 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1443 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1444 }
Richard Hendersoneaf7d1c2014-04-30 11:57:11 -07001445#else
1446 tcg_out_b(s, LK, target);
Richard Hendersond604f1a2014-03-24 15:44:09 -07001447#endif
1448}
1449
Richard Hendersona0585572013-09-03 17:05:37 -07001450static const uint32_t qemu_ldx_opc[16] = {
1451 [MO_UB] = LBZX,
1452 [MO_UW] = LHZX,
1453 [MO_UL] = LWZX,
1454 [MO_Q] = LDX,
1455 [MO_SW] = LHAX,
1456 [MO_SL] = LWAX,
1457 [MO_BSWAP | MO_UB] = LBZX,
1458 [MO_BSWAP | MO_UW] = LHBRX,
1459 [MO_BSWAP | MO_UL] = LWBRX,
1460 [MO_BSWAP | MO_Q] = LDBRX,
Richard Henderson7f12d642013-07-31 16:15:18 -07001461};
1462
Richard Hendersona0585572013-09-03 17:05:37 -07001463static const uint32_t qemu_stx_opc[16] = {
1464 [MO_UB] = STBX,
1465 [MO_UW] = STHX,
1466 [MO_UL] = STWX,
1467 [MO_Q] = STDX,
1468 [MO_BSWAP | MO_UB] = STBX,
1469 [MO_BSWAP | MO_UW] = STHBRX,
1470 [MO_BSWAP | MO_UL] = STWBRX,
1471 [MO_BSWAP | MO_Q] = STDBRX,
Richard Henderson7f12d642013-07-31 16:15:18 -07001472};
1473
1474static const uint32_t qemu_exts_opc[4] = {
1475 EXTSB, EXTSH, EXTSW, 0
1476};
1477
1478#if defined (CONFIG_SOFTMMU)
Richard Henderson659ef5c2017-07-30 12:30:41 -07001479#include "tcg-ldst.inc.c"
1480
Blue Swirle141ab52011-09-18 14:55:46 +00001481/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
Richard Henderson7f12d642013-07-31 16:15:18 -07001482 * int mmu_idx, uintptr_t ra)
1483 */
Richard Hendersone083c4a2014-03-28 14:58:38 -07001484static void * const qemu_ld_helpers[16] = {
Richard Hendersone349a8d2013-09-10 09:05:15 -07001485 [MO_UB] = helper_ret_ldub_mmu,
1486 [MO_LEUW] = helper_le_lduw_mmu,
1487 [MO_LEUL] = helper_le_ldul_mmu,
1488 [MO_LEQ] = helper_le_ldq_mmu,
1489 [MO_BEUW] = helper_be_lduw_mmu,
1490 [MO_BEUL] = helper_be_ldul_mmu,
1491 [MO_BEQ] = helper_be_ldq_mmu,
Blue Swirle141ab52011-09-18 14:55:46 +00001492};
1493
1494/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
Richard Henderson7f12d642013-07-31 16:15:18 -07001495 * uintxx_t val, int mmu_idx, uintptr_t ra)
1496 */
Richard Hendersone083c4a2014-03-28 14:58:38 -07001497static void * const qemu_st_helpers[16] = {
Richard Hendersone349a8d2013-09-10 09:05:15 -07001498 [MO_UB] = helper_ret_stb_mmu,
1499 [MO_LEUW] = helper_le_stw_mmu,
1500 [MO_LEUL] = helper_le_stl_mmu,
1501 [MO_LEQ] = helper_le_stq_mmu,
1502 [MO_BEUW] = helper_be_stw_mmu,
1503 [MO_BEUL] = helper_be_stl_mmu,
1504 [MO_BEQ] = helper_be_stq_mmu,
Blue Swirle141ab52011-09-18 14:55:46 +00001505};
malc810260a2008-07-23 19:17:46 +00001506
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001507/* Perform the TLB load and compare. Places the result of the comparison
1508 in CR7, loads the addend of the TLB into R3, and returns the register
1509 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1510
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001511static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
Richard Henderson7f25c462014-03-25 12:11:48 -07001512 TCGReg addrlo, TCGReg addrhi,
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001513 int mem_index, bool is_read)
malc810260a2008-07-23 19:17:46 +00001514{
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001515 int cmp_off
1516 = (is_read
1517 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1518 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1519 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1520 TCGReg base = TCG_AREG0;
Richard Henderson85aa8082016-07-14 12:43:06 -07001521 unsigned s_bits = opc & MO_SIZE;
1522 unsigned a_bits = get_alignment_bits(opc);
malc810260a2008-07-23 19:17:46 +00001523
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001524 /* Extract the page index, shifted into place for tlb index. */
Richard Henderson7f25c462014-03-25 12:11:48 -07001525 if (TCG_TARGET_REG_BITS == 64) {
1526 if (TARGET_LONG_BITS == 32) {
1527 /* Zero-extend the address into a place helpful for further use. */
1528 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1529 addrlo = TCG_REG_R4;
1530 } else {
1531 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1532 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1533 }
malc4a40e232008-07-27 11:09:21 +00001534 }
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001535
1536 /* Compensate for very large offsets. */
1537 if (add_off >= 0x8000) {
Richard Henderson4a64e0f2018-01-10 07:47:25 +00001538 int low = (int16_t)cmp_off;
1539 int high = cmp_off - low;
1540 assert((high & 0xffff) == 0);
1541 assert(cmp_off - high == (int16_t)(cmp_off - high));
1542 assert(add_off - high == (int16_t)(add_off - high));
1543 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, base, high >> 16));
Richard Hendersondfca1772014-04-30 12:12:16 -07001544 base = TCG_REG_TMP1;
Richard Henderson4a64e0f2018-01-10 07:47:25 +00001545 cmp_off -= high;
1546 add_off -= high;
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001547 }
1548
1549 /* Extraction and shifting, part 2. */
Richard Henderson7f25c462014-03-25 12:11:48 -07001550 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1551 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001552 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1553 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1554 31 - CPU_TLB_ENTRY_BITS);
1555 } else {
1556 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
1557 }
1558
1559 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1560
1561 /* Load the tlb comparator. */
Richard Henderson7f25c462014-03-25 12:11:48 -07001562 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1563 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
Richard Hendersondfca1772014-04-30 12:12:16 -07001564 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
Richard Henderson7f25c462014-03-25 12:11:48 -07001565 } else {
Richard Hendersondfca1772014-04-30 12:12:16 -07001566 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
Richard Henderson7f25c462014-03-25 12:11:48 -07001567 }
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001568
1569 /* Load the TLB addend for use on the fast path. Do this asap
1570 to minimize any load use delay. */
Richard Henderson4c3831a2014-03-24 16:03:59 -07001571 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001572
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001573 /* Clear the non-page, non-alignment bits from the address */
Richard Henderson85aa8082016-07-14 12:43:06 -07001574 if (TCG_TARGET_REG_BITS == 32) {
1575 /* We don't support unaligned accesses on 32-bits.
1576 * Preserve the bottom bits and thus trigger a comparison
1577 * failure on unaligned accesses.
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001578 */
Richard Henderson85aa8082016-07-14 12:43:06 -07001579 if (a_bits < s_bits) {
Sergey Sorokin1f00b272016-06-23 21:16:46 +03001580 a_bits = s_bits;
1581 }
Richard Henderson7f25c462014-03-25 12:11:48 -07001582 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
Sergey Sorokin1f00b272016-06-23 21:16:46 +03001583 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
Richard Henderson85aa8082016-07-14 12:43:06 -07001584 } else {
1585 TCGReg t = addrlo;
1586
1587 /* If the access is unaligned, we need to make sure we fail if we
1588 * cross a page boundary. The trick is to add the access size-1
1589 * to the address before masking the low bits. That will make the
1590 * address overflow to the next page if we cross a page boundary,
1591 * which will then force a mismatch of the TLB compare.
1592 */
1593 if (a_bits < s_bits) {
1594 unsigned a_mask = (1 << a_bits) - 1;
1595 unsigned s_mask = (1 << s_bits) - 1;
1596 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1597 t = TCG_REG_R0;
1598 }
1599
1600 /* Mask the address for the requested alignment. */
1601 if (TARGET_LONG_BITS == 32) {
1602 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1603 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
1604 } else if (a_bits == 0) {
1605 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1606 } else {
1607 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
Sergey Sorokin1f00b272016-06-23 21:16:46 +03001608 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001609 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001610 }
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001611 }
1612
Richard Henderson7f25c462014-03-25 12:11:48 -07001613 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
Richard Hendersondfca1772014-04-30 12:12:16 -07001614 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1615 0, 7, TCG_TYPE_I32);
Richard Henderson7f25c462014-03-25 12:11:48 -07001616 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1617 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1618 } else {
Richard Hendersondfca1772014-04-30 12:12:16 -07001619 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1620 0, 7, TCG_TYPE_TL);
Richard Henderson7f25c462014-03-25 12:11:48 -07001621 }
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001622
Richard Henderson7f25c462014-03-25 12:11:48 -07001623 return addrlo;
malc810260a2008-07-23 19:17:46 +00001624}
1625
Richard Henderson7f12d642013-07-31 16:15:18 -07001626/* Record the context of a call to the out of line helper code for the slow
1627 path for a load or store, so that we can later generate the correct
1628 helper code. */
Richard Henderson3972ef62015-05-13 09:10:33 -07001629static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
Richard Henderson7f25c462014-03-25 12:11:48 -07001630 TCGReg datalo_reg, TCGReg datahi_reg,
1631 TCGReg addrlo_reg, TCGReg addrhi_reg,
Richard Henderson3972ef62015-05-13 09:10:33 -07001632 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
Richard Henderson7f12d642013-07-31 16:15:18 -07001633{
Richard Henderson9ecefc82013-10-03 14:51:24 -05001634 TCGLabelQemuLdst *label = new_ldst_label(s);
Richard Henderson49d98702013-02-02 00:58:14 -08001635
Richard Henderson7f12d642013-07-31 16:15:18 -07001636 label->is_ld = is_ld;
Richard Henderson3972ef62015-05-13 09:10:33 -07001637 label->oi = oi;
Richard Henderson7f25c462014-03-25 12:11:48 -07001638 label->datalo_reg = datalo_reg;
1639 label->datahi_reg = datahi_reg;
1640 label->addrlo_reg = addrlo_reg;
1641 label->addrhi_reg = addrhi_reg;
Richard Henderson7f12d642013-07-31 16:15:18 -07001642 label->raddr = raddr;
Richard Henderson7f25c462014-03-25 12:11:48 -07001643 label->label_ptr[0] = lptr;
Richard Henderson7f12d642013-07-31 16:15:18 -07001644}
1645
1646static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1647{
Richard Henderson3972ef62015-05-13 09:10:33 -07001648 TCGMemOpIdx oi = lb->oi;
1649 TCGMemOp opc = get_memop(oi);
Richard Henderson7f25c462014-03-25 12:11:48 -07001650 TCGReg hi, lo, arg = TCG_REG_R3;
Richard Henderson7f12d642013-07-31 16:15:18 -07001651
Richard Hendersone083c4a2014-03-28 14:58:38 -07001652 reloc_pc14(lb->label_ptr[0], s->code_ptr);
Richard Henderson7f12d642013-07-31 16:15:18 -07001653
Richard Henderson7f25c462014-03-25 12:11:48 -07001654 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
Richard Henderson7f12d642013-07-31 16:15:18 -07001655
Richard Henderson7f25c462014-03-25 12:11:48 -07001656 lo = lb->addrlo_reg;
1657 hi = lb->addrhi_reg;
1658 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1659#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1660 arg |= 1;
1661#endif
1662 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1663 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1664 } else {
1665 /* If the address needed to be zero-extended, we'll have already
1666 placed it in R4. The only remaining case is 64-bit guest. */
1667 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1668 }
Richard Henderson7f12d642013-07-31 16:15:18 -07001669
Richard Henderson3972ef62015-05-13 09:10:33 -07001670 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
Richard Henderson7f25c462014-03-25 12:11:48 -07001671 tcg_out32(s, MFSPR | RT(arg) | LR);
Richard Henderson7f12d642013-07-31 16:15:18 -07001672
Richard Henderson2b7ec662015-05-29 09:16:51 -07001673 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
Richard Henderson7f12d642013-07-31 16:15:18 -07001674
Richard Henderson7f25c462014-03-25 12:11:48 -07001675 lo = lb->datalo_reg;
1676 hi = lb->datahi_reg;
1677 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1678 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1679 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1680 } else if (opc & MO_SIGN) {
Richard Hendersone349a8d2013-09-10 09:05:15 -07001681 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
Richard Henderson7f25c462014-03-25 12:11:48 -07001682 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
Richard Henderson7f12d642013-07-31 16:15:18 -07001683 } else {
Richard Henderson7f25c462014-03-25 12:11:48 -07001684 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
Richard Henderson7f12d642013-07-31 16:15:18 -07001685 }
1686
Richard Hendersone083c4a2014-03-28 14:58:38 -07001687 tcg_out_b(s, 0, lb->raddr);
Richard Henderson7f12d642013-07-31 16:15:18 -07001688}
1689
1690static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1691{
Richard Henderson3972ef62015-05-13 09:10:33 -07001692 TCGMemOpIdx oi = lb->oi;
1693 TCGMemOp opc = get_memop(oi);
Richard Hendersone349a8d2013-09-10 09:05:15 -07001694 TCGMemOp s_bits = opc & MO_SIZE;
Richard Henderson7f25c462014-03-25 12:11:48 -07001695 TCGReg hi, lo, arg = TCG_REG_R3;
Richard Henderson7f12d642013-07-31 16:15:18 -07001696
Richard Hendersone083c4a2014-03-28 14:58:38 -07001697 reloc_pc14(lb->label_ptr[0], s->code_ptr);
Richard Henderson7f12d642013-07-31 16:15:18 -07001698
Richard Henderson7f25c462014-03-25 12:11:48 -07001699 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
Richard Henderson7f12d642013-07-31 16:15:18 -07001700
Richard Henderson7f25c462014-03-25 12:11:48 -07001701 lo = lb->addrlo_reg;
1702 hi = lb->addrhi_reg;
1703 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1704#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1705 arg |= 1;
1706#endif
1707 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1708 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1709 } else {
1710 /* If the address needed to be zero-extended, we'll have already
1711 placed it in R4. The only remaining case is 64-bit guest. */
1712 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1713 }
Richard Henderson7f12d642013-07-31 16:15:18 -07001714
Richard Henderson7f25c462014-03-25 12:11:48 -07001715 lo = lb->datalo_reg;
1716 hi = lb->datahi_reg;
1717 if (TCG_TARGET_REG_BITS == 32) {
1718 switch (s_bits) {
1719 case MO_64:
1720#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1721 arg |= 1;
1722#endif
1723 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1724 /* FALLTHRU */
1725 case MO_32:
1726 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1727 break;
1728 default:
1729 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1730 break;
1731 }
1732 } else {
1733 if (s_bits == MO_64) {
1734 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1735 } else {
1736 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1737 }
1738 }
1739
Richard Henderson3972ef62015-05-13 09:10:33 -07001740 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
Richard Henderson7f25c462014-03-25 12:11:48 -07001741 tcg_out32(s, MFSPR | RT(arg) | LR);
Richard Henderson7f12d642013-07-31 16:15:18 -07001742
Richard Henderson2b7ec662015-05-29 09:16:51 -07001743 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
Richard Henderson7f12d642013-07-31 16:15:18 -07001744
Richard Hendersone083c4a2014-03-28 14:58:38 -07001745 tcg_out_b(s, 0, lb->raddr);
Richard Henderson7f12d642013-07-31 16:15:18 -07001746}
Richard Henderson7f12d642013-07-31 16:15:18 -07001747#endif /* SOFTMMU */
Richard Henderson49d98702013-02-02 00:58:14 -08001748
Richard Henderson7f25c462014-03-25 12:11:48 -07001749static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
malc810260a2008-07-23 19:17:46 +00001750{
Richard Henderson7f25c462014-03-25 12:11:48 -07001751 TCGReg datalo, datahi, addrlo, rbase;
1752 TCGReg addrhi __attribute__((unused));
Richard Henderson59227d52015-05-12 11:51:44 -07001753 TCGMemOpIdx oi;
Richard Henderson7f25c462014-03-25 12:11:48 -07001754 TCGMemOp opc, s_bits;
malc810260a2008-07-23 19:17:46 +00001755#ifdef CONFIG_SOFTMMU
Richard Henderson7f25c462014-03-25 12:11:48 -07001756 int mem_index;
Richard Hendersone083c4a2014-03-28 14:58:38 -07001757 tcg_insn_unit *label_ptr;
malc810260a2008-07-23 19:17:46 +00001758#endif
1759
Richard Henderson7f25c462014-03-25 12:11:48 -07001760 datalo = *args++;
1761 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1762 addrlo = *args++;
1763 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
Richard Henderson59227d52015-05-12 11:51:44 -07001764 oi = *args++;
1765 opc = get_memop(oi);
Richard Henderson7f25c462014-03-25 12:11:48 -07001766 s_bits = opc & MO_SIZE;
1767
David Gibson9df3b452011-10-30 19:57:33 +00001768#ifdef CONFIG_SOFTMMU
Richard Henderson59227d52015-05-12 11:51:44 -07001769 mem_index = get_mmuidx(oi);
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001770 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
malc810260a2008-07-23 19:17:46 +00001771
Richard Henderson7f12d642013-07-31 16:15:18 -07001772 /* Load a pointer into the current opcode w/conditional branch-link. */
1773 label_ptr = s->code_ptr;
1774 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
malc810260a2008-07-23 19:17:46 +00001775
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001776 rbase = TCG_REG_R3;
malc810260a2008-07-23 19:17:46 +00001777#else /* !CONFIG_SOFTMMU */
Laurent Vivierb76f21a2015-08-24 14:53:54 +02001778 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
Richard Henderson7f25c462014-03-25 12:11:48 -07001779 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
Richard Hendersondfca1772014-04-30 12:12:16 -07001780 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1781 addrlo = TCG_REG_TMP1;
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001782 }
malc810260a2008-07-23 19:17:46 +00001783#endif
1784
Richard Henderson7f25c462014-03-25 12:11:48 -07001785 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1786 if (opc & MO_BSWAP) {
1787 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1788 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1789 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1790 } else if (rbase != 0) {
1791 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1792 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1793 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1794 } else if (addrlo == datahi) {
1795 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1796 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1797 } else {
1798 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1799 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1800 }
Richard Henderson49d98702013-02-02 00:58:14 -08001801 } else {
Richard Henderson2b7ec662015-05-29 09:16:51 -07001802 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
Richard Henderson7f25c462014-03-25 12:11:48 -07001803 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1804 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1805 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1806 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1807 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1808 } else if (insn) {
1809 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1810 } else {
1811 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1812 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1813 insn = qemu_exts_opc[s_bits];
1814 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1815 }
malc810260a2008-07-23 19:17:46 +00001816 }
1817
1818#ifdef CONFIG_SOFTMMU
Richard Henderson3972ef62015-05-13 09:10:33 -07001819 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1820 s->code_ptr, label_ptr);
malc810260a2008-07-23 19:17:46 +00001821#endif
1822}
1823
Richard Henderson7f25c462014-03-25 12:11:48 -07001824static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
malc810260a2008-07-23 19:17:46 +00001825{
Richard Henderson7f25c462014-03-25 12:11:48 -07001826 TCGReg datalo, datahi, addrlo, rbase;
1827 TCGReg addrhi __attribute__((unused));
Richard Henderson59227d52015-05-12 11:51:44 -07001828 TCGMemOpIdx oi;
Richard Henderson7f25c462014-03-25 12:11:48 -07001829 TCGMemOp opc, s_bits;
malc810260a2008-07-23 19:17:46 +00001830#ifdef CONFIG_SOFTMMU
Richard Henderson7f25c462014-03-25 12:11:48 -07001831 int mem_index;
Richard Hendersone083c4a2014-03-28 14:58:38 -07001832 tcg_insn_unit *label_ptr;
malc810260a2008-07-23 19:17:46 +00001833#endif
1834
Richard Henderson7f25c462014-03-25 12:11:48 -07001835 datalo = *args++;
1836 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1837 addrlo = *args++;
1838 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
Richard Henderson59227d52015-05-12 11:51:44 -07001839 oi = *args++;
1840 opc = get_memop(oi);
Richard Henderson7f25c462014-03-25 12:11:48 -07001841 s_bits = opc & MO_SIZE;
1842
malc810260a2008-07-23 19:17:46 +00001843#ifdef CONFIG_SOFTMMU
Richard Henderson59227d52015-05-12 11:51:44 -07001844 mem_index = get_mmuidx(oi);
Benjamin Herrenschmidt68d45bb2015-07-21 15:19:38 +10001845 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
malc810260a2008-07-23 19:17:46 +00001846
Richard Henderson7f12d642013-07-31 16:15:18 -07001847 /* Load a pointer into the current opcode w/conditional branch-link. */
1848 label_ptr = s->code_ptr;
1849 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
malc810260a2008-07-23 19:17:46 +00001850
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001851 rbase = TCG_REG_R3;
malc810260a2008-07-23 19:17:46 +00001852#else /* !CONFIG_SOFTMMU */
Laurent Vivierb76f21a2015-08-24 14:53:54 +02001853 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
Richard Henderson7f25c462014-03-25 12:11:48 -07001854 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
Richard Hendersondfca1772014-04-30 12:12:16 -07001855 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1856 addrlo = TCG_REG_TMP1;
Richard Hendersonfedee3e2013-07-31 15:11:44 -07001857 }
malc810260a2008-07-23 19:17:46 +00001858#endif
1859
Richard Henderson7f25c462014-03-25 12:11:48 -07001860 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1861 if (opc & MO_BSWAP) {
1862 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1863 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1864 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1865 } else if (rbase != 0) {
1866 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1867 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1868 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1869 } else {
1870 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1871 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1872 }
Richard Henderson49d98702013-02-02 00:58:14 -08001873 } else {
Richard Henderson2b7ec662015-05-29 09:16:51 -07001874 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
Richard Henderson7f25c462014-03-25 12:11:48 -07001875 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1876 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
Richard Hendersondfca1772014-04-30 12:12:16 -07001877 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
Richard Henderson7f25c462014-03-25 12:11:48 -07001878 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
Richard Hendersondfca1772014-04-30 12:12:16 -07001879 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
Richard Henderson7f25c462014-03-25 12:11:48 -07001880 } else {
1881 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1882 }
malc810260a2008-07-23 19:17:46 +00001883 }
1884
1885#ifdef CONFIG_SOFTMMU
Richard Henderson3972ef62015-05-13 09:10:33 -07001886 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1887 s->code_ptr, label_ptr);
malc810260a2008-07-23 19:17:46 +00001888#endif
1889}
1890
Richard Henderson53c89ef2017-07-31 06:03:03 +00001891static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
1892{
1893 int i;
1894 for (i = 0; i < count; ++i) {
1895 p[i] = NOP;
1896 }
1897}
1898
Richard Hendersona921fdd2014-03-25 08:11:53 -07001899/* Parameters for function call generation, used in tcg.c. */
1900#define TCG_TARGET_STACK_ALIGN 16
Richard Hendersona921fdd2014-03-25 08:11:53 -07001901#define TCG_TARGET_EXTEND_ARGS 1
1902
Richard Henderson802ca562014-03-25 08:55:12 -07001903#ifdef _CALL_AIX
1904# define LINK_AREA_SIZE (6 * SZR)
1905# define LR_OFFSET (1 * SZR)
1906# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
Peter Maydell1045fc02014-06-26 16:37:17 +01001907#elif defined(TCG_TARGET_CALL_DARWIN)
1908# define LINK_AREA_SIZE (6 * SZR)
1909# define LR_OFFSET (2 * SZR)
Richard Hendersonffcfbec2014-03-25 09:13:38 -07001910#elif TCG_TARGET_REG_BITS == 64
1911# if defined(_CALL_ELF) && _CALL_ELF == 2
1912# define LINK_AREA_SIZE (4 * SZR)
1913# define LR_OFFSET (1 * SZR)
1914# endif
1915#else /* TCG_TARGET_REG_BITS == 32 */
1916# if defined(_CALL_SYSV)
Richard Hendersonffcfbec2014-03-25 09:13:38 -07001917# define LINK_AREA_SIZE (2 * SZR)
1918# define LR_OFFSET (1 * SZR)
Richard Hendersonffcfbec2014-03-25 09:13:38 -07001919# endif
1920#endif
1921#ifndef LR_OFFSET
1922# error "Unhandled abi"
1923#endif
1924#ifndef TCG_TARGET_CALL_STACK_OFFSET
Richard Hendersona2a98f82014-03-25 08:57:23 -07001925# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
Richard Henderson802ca562014-03-25 08:55:12 -07001926#endif
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07001927
Richard Henderson802ca562014-03-25 08:55:12 -07001928#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1929#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1930
1931#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1932 + TCG_STATIC_CALL_ARGS_SIZE \
1933 + CPU_TEMP_BUF_SIZE \
1934 + REG_SAVE_SIZE \
1935 + TCG_TARGET_STACK_ALIGN - 1) \
1936 & -TCG_TARGET_STACK_ALIGN)
1937
1938#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07001939
Richard Henderson541dd4c2013-08-31 05:14:53 -07001940static void tcg_target_qemu_prologue(TCGContext *s)
malc810260a2008-07-23 19:17:46 +00001941{
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07001942 int i;
malc810260a2008-07-23 19:17:46 +00001943
Richard Hendersona84ac4c2014-03-28 06:53:53 -07001944#ifdef _CALL_AIX
1945 void **desc = (void **)s->code_ptr;
1946 desc[0] = desc + 2; /* entry point */
1947 desc[1] = 0; /* environment pointer */
1948 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1949#endif
1950
Richard Henderson802ca562014-03-25 08:55:12 -07001951 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1952 CPU_TEMP_BUF_SIZE);
Blue Swirl136a0b52011-06-26 22:23:54 +03001953
malca69abbe2008-07-24 17:37:09 +00001954 /* Prologue */
Richard Henderson8327a472013-08-31 05:41:45 -07001955 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
Richard Hendersonffcfbec2014-03-25 09:13:38 -07001956 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1957 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
Richard Henderson802ca562014-03-25 08:55:12 -07001958
Richard Henderson29b69192013-08-31 05:23:23 -07001959 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
Richard Henderson4c3831a2014-03-24 16:03:59 -07001960 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1961 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
Richard Henderson29b69192013-08-31 05:23:23 -07001962 }
Richard Henderson802ca562014-03-25 08:55:12 -07001963 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
malc810260a2008-07-23 19:17:46 +00001964
Laurent Vivier4cbea592015-08-24 01:42:07 +02001965#ifndef CONFIG_SOFTMMU
Laurent Vivierb76f21a2015-08-24 14:53:54 +02001966 if (guest_base) {
Richard Henderson5964fca2017-07-31 04:16:10 +00001967 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
Richard Henderson541dd4c2013-08-31 05:14:53 -07001968 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
Richard Hendersonb9e946c2010-05-06 05:50:45 +00001969 }
malcf6548c02009-07-18 10:08:40 +04001970#endif
1971
Richard Henderson541dd4c2013-08-31 05:14:53 -07001972 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1973 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
Richard Henderson5964fca2017-07-31 04:16:10 +00001974 if (USE_REG_TB) {
1975 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
Richard Hendersona84ac4c2014-03-28 06:53:53 -07001976 }
Richard Henderson5964fca2017-07-31 04:16:10 +00001977 tcg_out32(s, BCCTR | BO_ALWAYS);
malca69abbe2008-07-24 17:37:09 +00001978
1979 /* Epilogue */
Richard Henderson5964fca2017-07-31 04:16:10 +00001980 s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
malc810260a2008-07-23 19:17:46 +00001981
Richard Henderson802ca562014-03-25 08:55:12 -07001982 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
Richard Henderson29b69192013-08-31 05:23:23 -07001983 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
Richard Henderson4c3831a2014-03-24 16:03:59 -07001984 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1985 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
Richard Henderson29b69192013-08-31 05:23:23 -07001986 }
Richard Henderson8327a472013-08-31 05:41:45 -07001987 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07001988 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
Richard Henderson2fd8edd2013-02-01 16:08:50 -08001989 tcg_out32(s, BCLR | BO_ALWAYS);
malc810260a2008-07-23 19:17:46 +00001990}
1991
Richard Henderson541dd4c2013-08-31 05:14:53 -07001992static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1993 const int *const_args)
malc810260a2008-07-23 19:17:46 +00001994{
Richard Hendersonee924fa2013-02-01 16:17:17 -08001995 TCGArg a0, a1, a2;
malce46b9682008-07-23 20:01:23 +00001996 int c;
1997
malc810260a2008-07-23 19:17:46 +00001998 switch (opc) {
1999 case INDEX_op_exit_tb:
Richard Hendersonde3d6362014-03-24 15:22:35 -07002000 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
Richard Hendersone083c4a2014-03-28 14:58:38 -07002001 tcg_out_b(s, 0, tb_ret_addr);
malc810260a2008-07-23 19:17:46 +00002002 break;
2003 case INDEX_op_goto_tb:
Richard Henderson5964fca2017-07-31 04:16:10 +00002004 if (s->tb_jmp_insn_offset) {
2005 /* Direct jump. */
2006 if (TCG_TARGET_REG_BITS == 64) {
2007 /* Ensure the next insns are 8-byte aligned. */
2008 if ((uintptr_t)s->code_ptr & 7) {
2009 tcg_out32(s, NOP);
2010 }
2011 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2012 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2013 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2014 } else {
2015 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2016 tcg_out32(s, B);
2017 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
2018 break;
2019 }
2020 } else {
2021 /* Indirect jump. */
2022 tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
2023 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2024 (intptr_t)(s->tb_jmp_insn_offset + args[0]));
malc810260a2008-07-23 19:17:46 +00002025 }
Richard Henderson5964fca2017-07-31 04:16:10 +00002026 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
Richard Henderson5bfd75a2015-10-02 22:25:28 +00002027 tcg_out32(s, BCCTR | BO_ALWAYS);
Richard Henderson5964fca2017-07-31 04:16:10 +00002028 s->tb_jmp_reset_offset[args[0]] = c = tcg_current_code_size(s);
2029 if (USE_REG_TB) {
2030 /* For the unlinked case, need to reset TCG_REG_TB. */
2031 c = -c;
2032 assert(c == (int16_t)c);
2033 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
2034 }
malc810260a2008-07-23 19:17:46 +00002035 break;
Richard Henderson0c240782017-04-26 11:50:31 +00002036 case INDEX_op_goto_ptr:
2037 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
Richard Henderson5964fca2017-07-31 04:16:10 +00002038 if (USE_REG_TB) {
2039 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2040 }
2041 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
Richard Henderson0c240782017-04-26 11:50:31 +00002042 tcg_out32(s, BCCTR | BO_ALWAYS);
2043 break;
malc810260a2008-07-23 19:17:46 +00002044 case INDEX_op_br:
2045 {
Richard Hendersonbec16312015-02-13 13:39:54 -08002046 TCGLabel *l = arg_label(args[0]);
malc810260a2008-07-23 19:17:46 +00002047
2048 if (l->has_value) {
Richard Hendersone083c4a2014-03-28 14:58:38 -07002049 tcg_out_b(s, 0, l->u.value_ptr);
Richard Henderson541dd4c2013-08-31 05:14:53 -07002050 } else {
Richard Hendersonbec16312015-02-13 13:39:54 -08002051 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
Richard Hendersonc7ca6a22013-08-30 17:58:10 -07002052 tcg_out_b_noaddr(s, B);
malc810260a2008-07-23 19:17:46 +00002053 }
2054 }
2055 break;
malc810260a2008-07-23 19:17:46 +00002056 case INDEX_op_ld8u_i32:
2057 case INDEX_op_ld8u_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002058 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002059 break;
2060 case INDEX_op_ld8s_i32:
2061 case INDEX_op_ld8s_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002062 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
Richard Henderson541dd4c2013-08-31 05:14:53 -07002063 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
malc810260a2008-07-23 19:17:46 +00002064 break;
2065 case INDEX_op_ld16u_i32:
2066 case INDEX_op_ld16u_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002067 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002068 break;
2069 case INDEX_op_ld16s_i32:
2070 case INDEX_op_ld16s_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002071 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002072 break;
2073 case INDEX_op_ld_i32:
2074 case INDEX_op_ld32u_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002075 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002076 break;
2077 case INDEX_op_ld32s_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002078 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002079 break;
2080 case INDEX_op_ld_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002081 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002082 break;
2083 case INDEX_op_st8_i32:
2084 case INDEX_op_st8_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002085 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002086 break;
2087 case INDEX_op_st16_i32:
2088 case INDEX_op_st16_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002089 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002090 break;
2091 case INDEX_op_st_i32:
2092 case INDEX_op_st32_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002093 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002094 break;
2095 case INDEX_op_st_i64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002096 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
malc810260a2008-07-23 19:17:46 +00002097 break;
2098
2099 case INDEX_op_add_i32:
Richard Hendersonee924fa2013-02-01 16:17:17 -08002100 a0 = args[0], a1 = args[1], a2 = args[2];
2101 if (const_args[2]) {
Richard Hendersonee924fa2013-02-01 16:17:17 -08002102 do_addi_32:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002103 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
Richard Hendersonee924fa2013-02-01 16:17:17 -08002104 } else {
2105 tcg_out32(s, ADD | TAB(a0, a1, a2));
2106 }
malc810260a2008-07-23 19:17:46 +00002107 break;
2108 case INDEX_op_sub_i32:
Richard Hendersonee924fa2013-02-01 16:17:17 -08002109 a0 = args[0], a1 = args[1], a2 = args[2];
Richard Henderson148bdd22013-04-04 07:30:20 -07002110 if (const_args[1]) {
2111 if (const_args[2]) {
2112 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2113 } else {
2114 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2115 }
2116 } else if (const_args[2]) {
Richard Hendersonee924fa2013-02-01 16:17:17 -08002117 a2 = -a2;
2118 goto do_addi_32;
2119 } else {
2120 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2121 }
malc810260a2008-07-23 19:17:46 +00002122 break;
2123
2124 case INDEX_op_and_i32:
Richard Henderson37251b92013-03-04 13:48:38 -08002125 a0 = args[0], a1 = args[1], a2 = args[2];
malc810260a2008-07-23 19:17:46 +00002126 if (const_args[2]) {
Richard Henderson37251b92013-03-04 13:48:38 -08002127 tcg_out_andi32(s, a0, a1, a2);
Richard Hendersona9249df2013-02-01 23:43:42 -08002128 } else {
Richard Henderson37251b92013-03-04 13:48:38 -08002129 tcg_out32(s, AND | SAB(a1, a0, a2));
Richard Hendersona9249df2013-02-01 23:43:42 -08002130 }
2131 break;
2132 case INDEX_op_and_i64:
Richard Henderson37251b92013-03-04 13:48:38 -08002133 a0 = args[0], a1 = args[1], a2 = args[2];
Richard Hendersona9249df2013-02-01 23:43:42 -08002134 if (const_args[2]) {
Richard Henderson37251b92013-03-04 13:48:38 -08002135 tcg_out_andi64(s, a0, a1, a2);
Richard Henderson637af302013-02-01 23:58:17 -08002136 } else {
Richard Henderson37251b92013-03-04 13:48:38 -08002137 tcg_out32(s, AND | SAB(a1, a0, a2));
malc810260a2008-07-23 19:17:46 +00002138 }
malc810260a2008-07-23 19:17:46 +00002139 break;
malcfe6f9432008-07-28 23:46:06 +00002140 case INDEX_op_or_i64:
malc810260a2008-07-23 19:17:46 +00002141 case INDEX_op_or_i32:
Richard Hendersondce74c52013-02-01 20:22:05 -08002142 a0 = args[0], a1 = args[1], a2 = args[2];
malc810260a2008-07-23 19:17:46 +00002143 if (const_args[2]) {
Richard Hendersondce74c52013-02-01 20:22:05 -08002144 tcg_out_ori32(s, a0, a1, a2);
2145 } else {
2146 tcg_out32(s, OR | SAB(a1, a0, a2));
malc810260a2008-07-23 19:17:46 +00002147 }
malc810260a2008-07-23 19:17:46 +00002148 break;
malcfe6f9432008-07-28 23:46:06 +00002149 case INDEX_op_xor_i64:
malc810260a2008-07-23 19:17:46 +00002150 case INDEX_op_xor_i32:
Richard Hendersondce74c52013-02-01 20:22:05 -08002151 a0 = args[0], a1 = args[1], a2 = args[2];
malc810260a2008-07-23 19:17:46 +00002152 if (const_args[2]) {
Richard Hendersondce74c52013-02-01 20:22:05 -08002153 tcg_out_xori32(s, a0, a1, a2);
2154 } else {
2155 tcg_out32(s, XOR | SAB(a1, a0, a2));
malc810260a2008-07-23 19:17:46 +00002156 }
malc810260a2008-07-23 19:17:46 +00002157 break;
Richard Hendersonce1010d2013-01-31 07:49:13 -08002158 case INDEX_op_andc_i32:
Richard Henderson37251b92013-03-04 13:48:38 -08002159 a0 = args[0], a1 = args[1], a2 = args[2];
2160 if (const_args[2]) {
2161 tcg_out_andi32(s, a0, a1, ~a2);
2162 } else {
2163 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2164 }
2165 break;
Richard Hendersonce1010d2013-01-31 07:49:13 -08002166 case INDEX_op_andc_i64:
Richard Henderson37251b92013-03-04 13:48:38 -08002167 a0 = args[0], a1 = args[1], a2 = args[2];
2168 if (const_args[2]) {
2169 tcg_out_andi64(s, a0, a1, ~a2);
2170 } else {
2171 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2172 }
Richard Hendersonce1010d2013-01-31 07:49:13 -08002173 break;
2174 case INDEX_op_orc_i32:
Richard Henderson37251b92013-03-04 13:48:38 -08002175 if (const_args[2]) {
2176 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2177 break;
2178 }
2179 /* FALLTHRU */
Richard Hendersonce1010d2013-01-31 07:49:13 -08002180 case INDEX_op_orc_i64:
2181 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2182 break;
2183 case INDEX_op_eqv_i32:
Richard Henderson37251b92013-03-04 13:48:38 -08002184 if (const_args[2]) {
2185 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2186 break;
2187 }
2188 /* FALLTHRU */
Richard Hendersonce1010d2013-01-31 07:49:13 -08002189 case INDEX_op_eqv_i64:
2190 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2191 break;
2192 case INDEX_op_nand_i32:
2193 case INDEX_op_nand_i64:
2194 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2195 break;
2196 case INDEX_op_nor_i32:
2197 case INDEX_op_nor_i64:
2198 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2199 break;
malc810260a2008-07-23 19:17:46 +00002200
Richard Hendersond0b07482016-11-16 12:48:55 +01002201 case INDEX_op_clz_i32:
2202 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2203 args[2], const_args[2]);
2204 break;
2205 case INDEX_op_ctz_i32:
2206 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2207 args[2], const_args[2]);
2208 break;
Richard Henderson33e75fb2016-11-22 11:43:12 +00002209 case INDEX_op_ctpop_i32:
2210 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2211 break;
Richard Hendersond0b07482016-11-16 12:48:55 +01002212
2213 case INDEX_op_clz_i64:
2214 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2215 args[2], const_args[2]);
2216 break;
2217 case INDEX_op_ctz_i64:
2218 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2219 args[2], const_args[2]);
2220 break;
Richard Henderson33e75fb2016-11-22 11:43:12 +00002221 case INDEX_op_ctpop_i64:
2222 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2223 break;
Richard Hendersond0b07482016-11-16 12:48:55 +01002224
malc810260a2008-07-23 19:17:46 +00002225 case INDEX_op_mul_i32:
Richard Hendersonef809302013-01-31 09:45:11 -08002226 a0 = args[0], a1 = args[1], a2 = args[2];
malc810260a2008-07-23 19:17:46 +00002227 if (const_args[2]) {
Richard Hendersonef809302013-01-31 09:45:11 -08002228 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2229 } else {
2230 tcg_out32(s, MULLW | TAB(a0, a1, a2));
malc810260a2008-07-23 19:17:46 +00002231 }
malc810260a2008-07-23 19:17:46 +00002232 break;
2233
2234 case INDEX_op_div_i32:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002235 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
malc810260a2008-07-23 19:17:46 +00002236 break;
2237
2238 case INDEX_op_divu_i32:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002239 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
malc810260a2008-07-23 19:17:46 +00002240 break;
2241
malc810260a2008-07-23 19:17:46 +00002242 case INDEX_op_shl_i32:
2243 if (const_args[2]) {
Richard Hendersona757e1e2014-03-26 18:10:43 -07002244 tcg_out_shli32(s, args[0], args[1], args[2]);
Richard Henderson9e555b72013-02-01 15:00:45 -08002245 } else {
Richard Henderson541dd4c2013-08-31 05:14:53 -07002246 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
Richard Henderson9e555b72013-02-01 15:00:45 -08002247 }
malc810260a2008-07-23 19:17:46 +00002248 break;
2249 case INDEX_op_shr_i32:
2250 if (const_args[2]) {
Richard Hendersona757e1e2014-03-26 18:10:43 -07002251 tcg_out_shri32(s, args[0], args[1], args[2]);
Richard Henderson9e555b72013-02-01 15:00:45 -08002252 } else {
Richard Henderson541dd4c2013-08-31 05:14:53 -07002253 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
Richard Henderson9e555b72013-02-01 15:00:45 -08002254 }
malc810260a2008-07-23 19:17:46 +00002255 break;
2256 case INDEX_op_sar_i32:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002257 if (const_args[2]) {
2258 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2259 } else {
2260 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2261 }
malc810260a2008-07-23 19:17:46 +00002262 break;
Richard Henderson313d91c2013-01-30 19:24:06 -08002263 case INDEX_op_rotl_i32:
2264 if (const_args[2]) {
2265 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2266 } else {
2267 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2268 | MB(0) | ME(31));
2269 }
2270 break;
2271 case INDEX_op_rotr_i32:
2272 if (const_args[2]) {
2273 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2274 } else {
Richard Henderson8327a472013-08-31 05:41:45 -07002275 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2276 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
Richard Henderson313d91c2013-01-30 19:24:06 -08002277 | MB(0) | ME(31));
2278 }
2279 break;
malc810260a2008-07-23 19:17:46 +00002280
2281 case INDEX_op_brcond_i32:
Richard Henderson4c314da2013-04-02 14:58:27 -07002282 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
Richard Hendersonbec16312015-02-13 13:39:54 -08002283 arg_label(args[3]), TCG_TYPE_I32);
malce924bbe2008-07-28 19:42:23 +00002284 break;
malc810260a2008-07-23 19:17:46 +00002285 case INDEX_op_brcond_i64:
Richard Henderson4c314da2013-04-02 14:58:27 -07002286 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
Richard Hendersonbec16312015-02-13 13:39:54 -08002287 arg_label(args[3]), TCG_TYPE_I64);
malc810260a2008-07-23 19:17:46 +00002288 break;
Richard Hendersonabcf61c2014-04-30 11:55:34 -07002289 case INDEX_op_brcond2_i32:
2290 tcg_out_brcond2(s, args, const_args);
2291 break;
malc810260a2008-07-23 19:17:46 +00002292
2293 case INDEX_op_neg_i32:
malc810260a2008-07-23 19:17:46 +00002294 case INDEX_op_neg_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002295 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
malc810260a2008-07-23 19:17:46 +00002296 break;
2297
malc157f2662011-08-22 14:40:00 +04002298 case INDEX_op_not_i32:
2299 case INDEX_op_not_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002300 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
malc157f2662011-08-22 14:40:00 +04002301 break;
2302
malc810260a2008-07-23 19:17:46 +00002303 case INDEX_op_add_i64:
Richard Hendersonee924fa2013-02-01 16:17:17 -08002304 a0 = args[0], a1 = args[1], a2 = args[2];
2305 if (const_args[2]) {
Richard Hendersonee924fa2013-02-01 16:17:17 -08002306 do_addi_64:
Richard Hendersonb18d5d22013-07-31 11:36:42 -07002307 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
Richard Hendersonee924fa2013-02-01 16:17:17 -08002308 } else {
2309 tcg_out32(s, ADD | TAB(a0, a1, a2));
2310 }
malc810260a2008-07-23 19:17:46 +00002311 break;
2312 case INDEX_op_sub_i64:
Richard Hendersonee924fa2013-02-01 16:17:17 -08002313 a0 = args[0], a1 = args[1], a2 = args[2];
Richard Henderson148bdd22013-04-04 07:30:20 -07002314 if (const_args[1]) {
2315 if (const_args[2]) {
2316 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2317 } else {
2318 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2319 }
2320 } else if (const_args[2]) {
Richard Hendersonee924fa2013-02-01 16:17:17 -08002321 a2 = -a2;
2322 goto do_addi_64;
2323 } else {
2324 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2325 }
malc810260a2008-07-23 19:17:46 +00002326 break;
2327
2328 case INDEX_op_shl_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002329 if (const_args[2]) {
Richard Henderson0a9564b2013-02-01 15:12:14 -08002330 tcg_out_shli64(s, args[0], args[1], args[2]);
Richard Henderson541dd4c2013-08-31 05:14:53 -07002331 } else {
2332 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2333 }
malc810260a2008-07-23 19:17:46 +00002334 break;
2335 case INDEX_op_shr_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002336 if (const_args[2]) {
Richard Henderson5e916c22013-02-01 15:19:05 -08002337 tcg_out_shri64(s, args[0], args[1], args[2]);
Richard Henderson541dd4c2013-08-31 05:14:53 -07002338 } else {
2339 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2340 }
malc810260a2008-07-23 19:17:46 +00002341 break;
2342 case INDEX_op_sar_i64:
malcfe6f9432008-07-28 23:46:06 +00002343 if (const_args[2]) {
Richard Henderson541dd4c2013-08-31 05:14:53 -07002344 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2345 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2346 } else {
2347 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
malcfe6f9432008-07-28 23:46:06 +00002348 }
malc810260a2008-07-23 19:17:46 +00002349 break;
Richard Henderson313d91c2013-01-30 19:24:06 -08002350 case INDEX_op_rotl_i64:
2351 if (const_args[2]) {
2352 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2353 } else {
2354 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2355 }
2356 break;
2357 case INDEX_op_rotr_i64:
2358 if (const_args[2]) {
2359 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2360 } else {
Richard Henderson8327a472013-08-31 05:41:45 -07002361 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2362 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
Richard Henderson313d91c2013-01-30 19:24:06 -08002363 }
2364 break;
malc810260a2008-07-23 19:17:46 +00002365
2366 case INDEX_op_mul_i64:
Richard Hendersonef809302013-01-31 09:45:11 -08002367 a0 = args[0], a1 = args[1], a2 = args[2];
2368 if (const_args[2]) {
2369 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2370 } else {
2371 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2372 }
malc810260a2008-07-23 19:17:46 +00002373 break;
2374 case INDEX_op_div_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002375 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
malc810260a2008-07-23 19:17:46 +00002376 break;
2377 case INDEX_op_divu_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002378 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
malc810260a2008-07-23 19:17:46 +00002379 break;
malc810260a2008-07-23 19:17:46 +00002380
Richard Henderson1768ec02013-09-10 10:15:25 -07002381 case INDEX_op_qemu_ld_i32:
Richard Henderson7f25c462014-03-25 12:11:48 -07002382 tcg_out_qemu_ld(s, args, false);
2383 break;
Richard Henderson1768ec02013-09-10 10:15:25 -07002384 case INDEX_op_qemu_ld_i64:
Richard Henderson7f25c462014-03-25 12:11:48 -07002385 tcg_out_qemu_ld(s, args, true);
malc810260a2008-07-23 19:17:46 +00002386 break;
Richard Henderson1768ec02013-09-10 10:15:25 -07002387 case INDEX_op_qemu_st_i32:
Richard Henderson7f25c462014-03-25 12:11:48 -07002388 tcg_out_qemu_st(s, args, false);
2389 break;
Richard Henderson1768ec02013-09-10 10:15:25 -07002390 case INDEX_op_qemu_st_i64:
Richard Henderson7f25c462014-03-25 12:11:48 -07002391 tcg_out_qemu_st(s, args, true);
malc810260a2008-07-23 19:17:46 +00002392 break;
2393
malce46b9682008-07-23 20:01:23 +00002394 case INDEX_op_ext8s_i32:
2395 case INDEX_op_ext8s_i64:
2396 c = EXTSB;
2397 goto gen_ext;
2398 case INDEX_op_ext16s_i32:
2399 case INDEX_op_ext16s_i64:
2400 c = EXTSH;
2401 goto gen_ext;
Aurelien Jarno4f2331e2015-07-27 12:41:45 +02002402 case INDEX_op_ext_i32_i64:
malce46b9682008-07-23 20:01:23 +00002403 case INDEX_op_ext32s_i64:
2404 c = EXTSW;
2405 goto gen_ext;
2406 gen_ext:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002407 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
malce46b9682008-07-23 20:01:23 +00002408 break;
Aurelien Jarno4f2331e2015-07-27 12:41:45 +02002409 case INDEX_op_extu_i32_i64:
2410 tcg_out_ext32u(s, args[0], args[1]);
2411 break;
malce46b9682008-07-23 20:01:23 +00002412
malc1cd62ae2010-02-07 02:48:53 +03002413 case INDEX_op_setcond_i32:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002414 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2415 const_args[2]);
malc1cd62ae2010-02-07 02:48:53 +03002416 break;
2417 case INDEX_op_setcond_i64:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002418 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2419 const_args[2]);
malc1cd62ae2010-02-07 02:48:53 +03002420 break;
Richard Hendersonabcf61c2014-04-30 11:55:34 -07002421 case INDEX_op_setcond2_i32:
2422 tcg_out_setcond2(s, args, const_args);
2423 break;
malc1cd62ae2010-02-07 02:48:53 +03002424
Richard Henderson5d221582013-01-30 21:16:38 -08002425 case INDEX_op_bswap16_i32:
2426 case INDEX_op_bswap16_i64:
2427 a0 = args[0], a1 = args[1];
2428 /* a1 = abcd */
2429 if (a0 != a1) {
2430 /* a0 = (a1 r<< 24) & 0xff # 000c */
2431 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2432 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2433 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2434 } else {
2435 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2436 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2437 /* a0 = (a1 r<< 24) & 0xff # 000c */
2438 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2439 /* a0 = a0 | r0 # 00dc */
2440 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2441 }
2442 break;
2443
2444 case INDEX_op_bswap32_i32:
2445 case INDEX_op_bswap32_i64:
2446 /* Stolen from gcc's builtin_bswap32 */
2447 a1 = args[1];
2448 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2449
2450 /* a1 = args[1] # abcd */
2451 /* a0 = rotate_left (a1, 8) # bcda */
2452 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2453 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2454 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2455 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2456 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2457
2458 if (a0 == TCG_REG_R0) {
Richard Hendersonde3d6362014-03-24 15:22:35 -07002459 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
Richard Henderson5d221582013-01-30 21:16:38 -08002460 }
2461 break;
2462
Richard Henderson68aebd42013-01-30 21:41:54 -08002463 case INDEX_op_bswap64_i64:
Richard Henderson8327a472013-08-31 05:41:45 -07002464 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
Richard Henderson68aebd42013-01-30 21:41:54 -08002465 if (a0 == a1) {
Richard Henderson8327a472013-08-31 05:41:45 -07002466 a0 = TCG_REG_R0;
Richard Henderson68aebd42013-01-30 21:41:54 -08002467 a2 = a1;
2468 }
2469
2470 /* a1 = # abcd efgh */
2471 /* a0 = rl32(a1, 8) # 0000 fghe */
2472 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2473 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2474 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2475 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2476 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2477
2478 /* a0 = rl64(a0, 32) # hgfe 0000 */
2479 /* a2 = rl64(a1, 32) # efgh abcd */
2480 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2481 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2482
2483 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2484 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2485 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2486 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2487 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2488 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2489
2490 if (a0 == 0) {
Richard Hendersonde3d6362014-03-24 15:22:35 -07002491 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
Richard Henderson68aebd42013-01-30 21:41:54 -08002492 }
2493 break;
2494
Richard Henderson33de9ed2013-01-31 08:39:30 -08002495 case INDEX_op_deposit_i32:
Richard Henderson39dc85b2013-04-04 12:47:22 -07002496 if (const_args[2]) {
2497 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2498 tcg_out_andi32(s, args[0], args[0], ~mask);
2499 } else {
2500 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2501 32 - args[3] - args[4], 31 - args[3]);
2502 }
Richard Henderson33de9ed2013-01-31 08:39:30 -08002503 break;
2504 case INDEX_op_deposit_i64:
Richard Henderson39dc85b2013-04-04 12:47:22 -07002505 if (const_args[2]) {
2506 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2507 tcg_out_andi64(s, args[0], args[0], ~mask);
2508 } else {
2509 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2510 64 - args[3] - args[4]);
2511 }
Richard Henderson33de9ed2013-01-31 08:39:30 -08002512 break;
2513
Richard Hendersonc05021c2016-10-14 14:18:03 -05002514 case INDEX_op_extract_i32:
2515 tcg_out_rlw(s, RLWINM, args[0], args[1],
2516 32 - args[2], 32 - args[3], 31);
2517 break;
2518 case INDEX_op_extract_i64:
2519 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2520 break;
2521
Richard Henderson027ffea2013-02-01 13:00:05 -08002522 case INDEX_op_movcond_i32:
2523 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2524 args[3], args[4], const_args[2]);
2525 break;
2526 case INDEX_op_movcond_i64:
2527 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2528 args[3], args[4], const_args[2]);
2529 break;
2530
Richard Henderson796f1a62014-04-30 11:39:20 -07002531#if TCG_TARGET_REG_BITS == 64
Richard Henderson6c858762013-03-04 14:26:52 -08002532 case INDEX_op_add2_i64:
Richard Henderson796f1a62014-04-30 11:39:20 -07002533#else
2534 case INDEX_op_add2_i32:
2535#endif
Richard Henderson6c858762013-03-04 14:26:52 -08002536 /* Note that the CA bit is defined based on the word size of the
2537 environment. So in 64-bit mode it's always carry-out of bit 63.
2538 The fallback code using deposit works just as well for 32-bit. */
2539 a0 = args[0], a1 = args[1];
Anton Blanchard84247352013-06-02 22:29:39 +10002540 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
Richard Henderson6c858762013-03-04 14:26:52 -08002541 a0 = TCG_REG_R0;
2542 }
Anton Blanchard84247352013-06-02 22:29:39 +10002543 if (const_args[4]) {
2544 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
Richard Henderson6c858762013-03-04 14:26:52 -08002545 } else {
Anton Blanchard84247352013-06-02 22:29:39 +10002546 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
Richard Henderson6c858762013-03-04 14:26:52 -08002547 }
2548 if (const_args[5]) {
Anton Blanchard84247352013-06-02 22:29:39 +10002549 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
Richard Henderson6c858762013-03-04 14:26:52 -08002550 } else {
Anton Blanchard84247352013-06-02 22:29:39 +10002551 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
Richard Henderson6c858762013-03-04 14:26:52 -08002552 }
2553 if (a0 != args[0]) {
Richard Hendersonde3d6362014-03-24 15:22:35 -07002554 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
Richard Henderson6c858762013-03-04 14:26:52 -08002555 }
2556 break;
2557
Richard Henderson796f1a62014-04-30 11:39:20 -07002558#if TCG_TARGET_REG_BITS == 64
Richard Henderson6c858762013-03-04 14:26:52 -08002559 case INDEX_op_sub2_i64:
Richard Henderson796f1a62014-04-30 11:39:20 -07002560#else
2561 case INDEX_op_sub2_i32:
2562#endif
Richard Henderson6c858762013-03-04 14:26:52 -08002563 a0 = args[0], a1 = args[1];
Richard Hendersonb31284c2014-03-26 18:56:31 -07002564 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
Richard Henderson6c858762013-03-04 14:26:52 -08002565 a0 = TCG_REG_R0;
2566 }
2567 if (const_args[2]) {
Richard Hendersonb31284c2014-03-26 18:56:31 -07002568 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
Richard Henderson6c858762013-03-04 14:26:52 -08002569 } else {
Richard Hendersonb31284c2014-03-26 18:56:31 -07002570 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
Richard Henderson6c858762013-03-04 14:26:52 -08002571 }
Richard Hendersonb31284c2014-03-26 18:56:31 -07002572 if (const_args[3]) {
2573 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
Richard Henderson6c858762013-03-04 14:26:52 -08002574 } else {
Richard Hendersonb31284c2014-03-26 18:56:31 -07002575 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
Richard Henderson6c858762013-03-04 14:26:52 -08002576 }
2577 if (a0 != args[0]) {
Richard Hendersonde3d6362014-03-24 15:22:35 -07002578 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
Richard Henderson6c858762013-03-04 14:26:52 -08002579 }
2580 break;
2581
Richard Hendersonabcf61c2014-04-30 11:55:34 -07002582 case INDEX_op_muluh_i32:
2583 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2584 break;
Richard Henderson8fa391a2014-03-26 11:37:06 -07002585 case INDEX_op_mulsh_i32:
2586 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2587 break;
Richard Henderson32f57172013-08-14 14:46:08 -07002588 case INDEX_op_muluh_i64:
2589 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2590 break;
2591 case INDEX_op_mulsh_i64:
2592 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
Richard Henderson6645c142013-03-04 16:20:51 -08002593 break;
2594
Pranith Kumar7b4af5e2016-07-14 16:20:19 -04002595 case INDEX_op_mb:
2596 tcg_out_mb(s, args[0]);
2597 break;
2598
Richard Henderson96d0ee72014-04-25 15:19:33 -04002599 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2600 case INDEX_op_mov_i64:
2601 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2602 case INDEX_op_movi_i64:
2603 case INDEX_op_call: /* Always emitted via tcg_out_call. */
malc810260a2008-07-23 19:17:46 +00002604 default:
Richard Henderson541dd4c2013-08-31 05:14:53 -07002605 tcg_abort();
malc810260a2008-07-23 19:17:46 +00002606 }
2607}
2608
Richard Hendersonf69d2772016-11-18 09:31:40 +01002609static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2610{
Richard Henderson6cb36582017-09-14 02:29:32 +00002611 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2612 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2613 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2614 static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
2615 static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
2616 static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
2617 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2618 static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
2619 static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
2620 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2621 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2622 static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
2623 static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
2624 static const TCGTargetOpDef r_rI_ri
2625 = { .args_ct_str = { "r", "rI", "ri" } };
2626 static const TCGTargetOpDef r_rI_rT
2627 = { .args_ct_str = { "r", "rI", "rT" } };
2628 static const TCGTargetOpDef r_r_rZW
2629 = { .args_ct_str = { "r", "r", "rZW" } };
2630 static const TCGTargetOpDef L_L_L_L
2631 = { .args_ct_str = { "L", "L", "L", "L" } };
2632 static const TCGTargetOpDef S_S_S_S
2633 = { .args_ct_str = { "S", "S", "S", "S" } };
2634 static const TCGTargetOpDef movc
2635 = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
2636 static const TCGTargetOpDef dep
2637 = { .args_ct_str = { "r", "0", "rZ" } };
2638 static const TCGTargetOpDef br2
2639 = { .args_ct_str = { "r", "r", "ri", "ri" } };
2640 static const TCGTargetOpDef setc2
2641 = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
2642 static const TCGTargetOpDef add2
2643 = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
2644 static const TCGTargetOpDef sub2
2645 = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
Richard Hendersonf69d2772016-11-18 09:31:40 +01002646
Richard Henderson6cb36582017-09-14 02:29:32 +00002647 switch (op) {
2648 case INDEX_op_goto_ptr:
2649 return &r;
2650
2651 case INDEX_op_ld8u_i32:
2652 case INDEX_op_ld8s_i32:
2653 case INDEX_op_ld16u_i32:
2654 case INDEX_op_ld16s_i32:
2655 case INDEX_op_ld_i32:
2656 case INDEX_op_st8_i32:
2657 case INDEX_op_st16_i32:
2658 case INDEX_op_st_i32:
2659 case INDEX_op_ctpop_i32:
2660 case INDEX_op_neg_i32:
2661 case INDEX_op_not_i32:
2662 case INDEX_op_ext8s_i32:
2663 case INDEX_op_ext16s_i32:
2664 case INDEX_op_bswap16_i32:
2665 case INDEX_op_bswap32_i32:
2666 case INDEX_op_extract_i32:
2667 case INDEX_op_ld8u_i64:
2668 case INDEX_op_ld8s_i64:
2669 case INDEX_op_ld16u_i64:
2670 case INDEX_op_ld16s_i64:
2671 case INDEX_op_ld32u_i64:
2672 case INDEX_op_ld32s_i64:
2673 case INDEX_op_ld_i64:
2674 case INDEX_op_st8_i64:
2675 case INDEX_op_st16_i64:
2676 case INDEX_op_st32_i64:
2677 case INDEX_op_st_i64:
2678 case INDEX_op_ctpop_i64:
2679 case INDEX_op_neg_i64:
2680 case INDEX_op_not_i64:
2681 case INDEX_op_ext8s_i64:
2682 case INDEX_op_ext16s_i64:
2683 case INDEX_op_ext32s_i64:
2684 case INDEX_op_ext_i32_i64:
2685 case INDEX_op_extu_i32_i64:
2686 case INDEX_op_bswap16_i64:
2687 case INDEX_op_bswap32_i64:
2688 case INDEX_op_bswap64_i64:
2689 case INDEX_op_extract_i64:
2690 return &r_r;
2691
2692 case INDEX_op_add_i32:
2693 case INDEX_op_and_i32:
2694 case INDEX_op_or_i32:
2695 case INDEX_op_xor_i32:
2696 case INDEX_op_andc_i32:
2697 case INDEX_op_orc_i32:
2698 case INDEX_op_eqv_i32:
2699 case INDEX_op_shl_i32:
2700 case INDEX_op_shr_i32:
2701 case INDEX_op_sar_i32:
2702 case INDEX_op_rotl_i32:
2703 case INDEX_op_rotr_i32:
2704 case INDEX_op_setcond_i32:
2705 case INDEX_op_and_i64:
2706 case INDEX_op_andc_i64:
2707 case INDEX_op_shl_i64:
2708 case INDEX_op_shr_i64:
2709 case INDEX_op_sar_i64:
2710 case INDEX_op_rotl_i64:
2711 case INDEX_op_rotr_i64:
2712 case INDEX_op_setcond_i64:
2713 return &r_r_ri;
2714 case INDEX_op_mul_i32:
2715 case INDEX_op_mul_i64:
2716 return &r_r_rI;
2717 case INDEX_op_div_i32:
2718 case INDEX_op_divu_i32:
2719 case INDEX_op_nand_i32:
2720 case INDEX_op_nor_i32:
2721 case INDEX_op_muluh_i32:
2722 case INDEX_op_mulsh_i32:
2723 case INDEX_op_orc_i64:
2724 case INDEX_op_eqv_i64:
2725 case INDEX_op_nand_i64:
2726 case INDEX_op_nor_i64:
2727 case INDEX_op_div_i64:
2728 case INDEX_op_divu_i64:
2729 case INDEX_op_mulsh_i64:
2730 case INDEX_op_muluh_i64:
2731 return &r_r_r;
2732 case INDEX_op_sub_i32:
2733 return &r_rI_ri;
2734 case INDEX_op_add_i64:
2735 return &r_r_rT;
2736 case INDEX_op_or_i64:
2737 case INDEX_op_xor_i64:
2738 return &r_r_rU;
2739 case INDEX_op_sub_i64:
2740 return &r_rI_rT;
2741 case INDEX_op_clz_i32:
2742 case INDEX_op_ctz_i32:
2743 case INDEX_op_clz_i64:
2744 case INDEX_op_ctz_i64:
2745 return &r_r_rZW;
2746
2747 case INDEX_op_brcond_i32:
2748 case INDEX_op_brcond_i64:
2749 return &r_ri;
2750
2751 case INDEX_op_movcond_i32:
2752 case INDEX_op_movcond_i64:
2753 return &movc;
2754 case INDEX_op_deposit_i32:
2755 case INDEX_op_deposit_i64:
2756 return &dep;
2757 case INDEX_op_brcond2_i32:
2758 return &br2;
2759 case INDEX_op_setcond2_i32:
2760 return &setc2;
2761 case INDEX_op_add2_i64:
2762 case INDEX_op_add2_i32:
2763 return &add2;
2764 case INDEX_op_sub2_i64:
2765 case INDEX_op_sub2_i32:
2766 return &sub2;
2767
2768 case INDEX_op_qemu_ld_i32:
2769 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2770 ? &r_L : &r_L_L);
2771 case INDEX_op_qemu_st_i32:
2772 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2773 ? &S_S : &S_S_S);
2774 case INDEX_op_qemu_ld_i64:
2775 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2776 : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
2777 case INDEX_op_qemu_st_i64:
2778 return (TCG_TARGET_REG_BITS == 64 ? &S_S
2779 : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
2780
2781 default:
2782 return NULL;
Richard Hendersonf69d2772016-11-18 09:31:40 +01002783 }
Richard Hendersonf69d2772016-11-18 09:31:40 +01002784}
2785
Richard Henderson541dd4c2013-08-31 05:14:53 -07002786static void tcg_target_init(TCGContext *s)
malc810260a2008-07-23 19:17:46 +00002787{
Richard Hendersoncd629de2013-06-04 11:37:17 -07002788 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
Richard Hendersond0b07482016-11-16 12:48:55 +01002789 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
2790
Richard Henderson1e6e9ac2013-02-18 09:11:15 -08002791 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2792 have_isa_2_06 = true;
2793 }
Richard Hendersond0b07482016-11-16 12:48:55 +01002794#ifdef PPC_FEATURE2_ARCH_3_00
2795 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
2796 have_isa_3_00 = true;
2797 }
2798#endif
Richard Henderson1e6e9ac2013-02-18 09:11:15 -08002799
Richard Hendersonf46934d2017-09-11 12:44:30 -07002800 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2801 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2802
2803 tcg_target_call_clobber_regs = 0;
2804 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2805 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2806 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2807 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
2808 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
2809 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
2810 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
2811 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2812 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2813 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2814 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2815 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
malc810260a2008-07-23 19:17:46 +00002816
Richard Hendersonccb1bb62017-09-11 11:25:55 -07002817 s->reserved_regs = 0;
Richard Henderson5e1702b2013-07-31 10:18:49 -07002818 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2819 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
Richard Hendersondfca1772014-04-30 12:12:16 -07002820#if defined(_CALL_SYSV)
2821 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
Andreas Faerber5d7ff5b2009-12-06 14:00:24 +01002822#endif
Richard Hendersondfca1772014-04-30 12:12:16 -07002823#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
Richard Henderson5e1702b2013-07-31 10:18:49 -07002824 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
Richard Hendersondfca1772014-04-30 12:12:16 -07002825#endif
2826 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
Richard Henderson5964fca2017-07-31 04:16:10 +00002827 if (USE_REG_TB) {
2828 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
Richard Hendersona84ac4c2014-03-28 06:53:53 -07002829 }
malc810260a2008-07-23 19:17:46 +00002830}
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002831
Richard Hendersonffcfbec2014-03-25 09:13:38 -07002832#ifdef __ELF__
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002833typedef struct {
2834 DebugFrameCIE cie;
2835 DebugFrameFDEHeader fde;
2836 uint8_t fde_def_cfa[4];
2837 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2838} DebugFrame;
2839
2840/* We're expecting a 2 byte uleb128 encoded value. */
2841QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2842
Richard Hendersonffcfbec2014-03-25 09:13:38 -07002843#if TCG_TARGET_REG_BITS == 64
2844# define ELF_HOST_MACHINE EM_PPC64
2845#else
2846# define ELF_HOST_MACHINE EM_PPC
2847#endif
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002848
2849static DebugFrame debug_frame = {
2850 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2851 .cie.id = -1,
2852 .cie.version = 1,
2853 .cie.code_align = 1,
Richard Henderson802ca562014-03-25 08:55:12 -07002854 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002855 .cie.return_column = 65,
2856
2857 /* Total FDE size does not include the "len" member. */
2858 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2859
2860 .fde_def_cfa = {
Richard Henderson802ca562014-03-25 08:55:12 -07002861 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002862 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2863 (FRAME_SIZE >> 7)
2864 },
2865 .fde_reg_ofs = {
Richard Henderson802ca562014-03-25 08:55:12 -07002866 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2867 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002868 }
2869};
2870
2871void tcg_register_jit(void *buf, size_t buf_size)
2872{
2873 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2874 int i;
2875
2876 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2877 p[0] = 0x80 + tcg_target_callee_save_regs[i];
Richard Henderson802ca562014-03-25 08:55:12 -07002878 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002879 }
2880
Richard Henderson802ca562014-03-25 08:55:12 -07002881 debug_frame.fde.func_start = (uintptr_t)buf;
Richard Hendersonfa94c3b2013-08-31 04:44:21 -07002882 debug_frame.fde.func_len = buf_size;
2883
2884 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2885}
Richard Hendersonffcfbec2014-03-25 09:13:38 -07002886#endif /* __ELF__ */
Richard Henderson224f9fd2014-04-30 13:56:50 -07002887
Richard Henderson224f9fd2014-04-30 13:56:50 -07002888void flush_icache_range(uintptr_t start, uintptr_t stop)
2889{
2890 uintptr_t p, start1, stop1;
Emilio G. Cotab255b2c2017-06-06 20:17:04 -04002891 size_t dsize = qemu_dcache_linesize;
2892 size_t isize = qemu_icache_linesize;
Richard Henderson224f9fd2014-04-30 13:56:50 -07002893
2894 start1 = start & ~(dsize - 1);
2895 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2896 for (p = start1; p < stop1; p += dsize) {
2897 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2898 }
2899 asm volatile ("sync" : : : "memory");
2900
2901 start &= start & ~(isize - 1);
2902 stop1 = (stop + isize - 1) & ~(isize - 1);
2903 for (p = start1; p < stop1; p += isize) {
2904 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2905 }
2906 asm volatile ("sync" : : : "memory");
2907 asm volatile ("isync" : : : "memory");
2908}