Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2009, 2011 Stefan Weil |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * This code implements a TCG which does not generate machine code for some |
| 27 | * real target machine but which generates virtual machine code for an |
| 28 | * interpreter. Interpreted pseudo code is slow, but it works on any host. |
| 29 | * |
| 30 | * Some remarks might help in understanding the code: |
| 31 | * |
| 32 | * "target" or "TCG target" is the machine which runs the generated code. |
| 33 | * This is different to the usual meaning in QEMU where "target" is the |
| 34 | * emulated machine. So normally QEMU host is identical to TCG target. |
| 35 | * Here the TCG target is a virtual machine, but this virtual machine must |
| 36 | * use the same word size like the real machine. |
| 37 | * Therefore, we need both 32 and 64 bit virtual machines (interpreter). |
| 38 | */ |
| 39 | |
Markus Armbruster | 175de52 | 2016-06-29 15:29:06 +0200 | [diff] [blame] | 40 | #ifndef TCG_TARGET_H |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 41 | #define TCG_TARGET_H |
| 42 | |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 43 | #define TCG_TARGET_INTERPRETER 1 |
Richard Henderson | 6508988 | 2021-02-01 21:27:41 -1000 | [diff] [blame] | 44 | #define TCG_TARGET_INSN_UNIT_SIZE 4 |
Paolo Bonzini | 006f863 | 2015-05-05 09:18:22 +0200 | [diff] [blame] | 45 | #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 |
Richard Henderson | 26a75d1 | 2021-03-09 23:30:38 -0600 | [diff] [blame] | 46 | #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 47 | |
Richard Henderson | 78cd7b8 | 2013-08-20 14:41:29 -0700 | [diff] [blame] | 48 | #if UINTPTR_MAX == UINT32_MAX |
| 49 | # define TCG_TARGET_REG_BITS 32 |
| 50 | #elif UINTPTR_MAX == UINT64_MAX |
| 51 | # define TCG_TARGET_REG_BITS 64 |
| 52 | #else |
| 53 | # error Unknown pointer size for tci target |
| 54 | #endif |
| 55 | |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 56 | #ifdef CONFIG_DEBUG_TCG |
| 57 | /* Enable debug output. */ |
| 58 | #define CONFIG_DEBUG_TCG_INTERPRETER |
| 59 | #endif |
| 60 | |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 61 | /* Optional instructions. */ |
| 62 | |
| 63 | #define TCG_TARGET_HAS_bswap16_i32 1 |
| 64 | #define TCG_TARGET_HAS_bswap32_i32 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 65 | #define TCG_TARGET_HAS_div_i32 1 |
Richard Henderson | ca675f4 | 2013-03-11 22:41:47 -0700 | [diff] [blame] | 66 | #define TCG_TARGET_HAS_rem_i32 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 67 | #define TCG_TARGET_HAS_ext8s_i32 1 |
| 68 | #define TCG_TARGET_HAS_ext16s_i32 1 |
| 69 | #define TCG_TARGET_HAS_ext8u_i32 1 |
| 70 | #define TCG_TARGET_HAS_ext16u_i32 1 |
Richard Henderson | a81520b | 2021-02-02 16:29:18 -0800 | [diff] [blame] | 71 | #define TCG_TARGET_HAS_andc_i32 1 |
Stefan Weil | e24dc9f | 2012-09-18 22:52:14 +0200 | [diff] [blame] | 72 | #define TCG_TARGET_HAS_deposit_i32 1 |
Richard Henderson | 0f10d7c | 2021-02-02 16:48:48 -0800 | [diff] [blame] | 73 | #define TCG_TARGET_HAS_extract_i32 1 |
| 74 | #define TCG_TARGET_HAS_sextract_i32 1 |
Richard Henderson | fce1296 | 2019-02-25 10:29:25 -0800 | [diff] [blame] | 75 | #define TCG_TARGET_HAS_extract2_i32 0 |
Richard Henderson | a81520b | 2021-02-02 16:29:18 -0800 | [diff] [blame] | 76 | #define TCG_TARGET_HAS_eqv_i32 1 |
| 77 | #define TCG_TARGET_HAS_nand_i32 1 |
| 78 | #define TCG_TARGET_HAS_nor_i32 1 |
Richard Henderson | 5255f48 | 2021-02-02 17:01:57 -0800 | [diff] [blame] | 79 | #define TCG_TARGET_HAS_clz_i32 1 |
| 80 | #define TCG_TARGET_HAS_ctz_i32 1 |
| 81 | #define TCG_TARGET_HAS_ctpop_i32 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 82 | #define TCG_TARGET_HAS_neg_i32 1 |
| 83 | #define TCG_TARGET_HAS_not_i32 1 |
Richard Henderson | a81520b | 2021-02-02 16:29:18 -0800 | [diff] [blame] | 84 | #define TCG_TARGET_HAS_orc_i32 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 85 | #define TCG_TARGET_HAS_rot_i32 1 |
Richard Henderson | df093c1 | 2021-02-02 16:15:45 -0800 | [diff] [blame] | 86 | #define TCG_TARGET_HAS_movcond_i32 1 |
Richard Henderson | f6db0d8 | 2021-02-02 17:21:27 -0800 | [diff] [blame] | 87 | #define TCG_TARGET_HAS_muls2_i32 1 |
Richard Henderson | 0327152 | 2013-08-14 14:35:56 -0700 | [diff] [blame] | 88 | #define TCG_TARGET_HAS_muluh_i32 0 |
| 89 | #define TCG_TARGET_HAS_mulsh_i32 0 |
Richard Henderson | 1670a2b | 2021-01-29 22:11:43 -1000 | [diff] [blame] | 90 | #define TCG_TARGET_HAS_direct_jump 0 |
Richard Henderson | 07ce0b0 | 2020-12-09 13:58:39 -0600 | [diff] [blame] | 91 | #define TCG_TARGET_HAS_qemu_st8_i32 0 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 92 | |
| 93 | #if TCG_TARGET_REG_BITS == 64 |
Richard Henderson | 609ad70 | 2015-07-24 07:16:00 -0700 | [diff] [blame] | 94 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
| 95 | #define TCG_TARGET_HAS_extrh_i64_i32 0 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 96 | #define TCG_TARGET_HAS_bswap16_i64 1 |
| 97 | #define TCG_TARGET_HAS_bswap32_i64 1 |
| 98 | #define TCG_TARGET_HAS_bswap64_i64 1 |
Stefan Weil | e24dc9f | 2012-09-18 22:52:14 +0200 | [diff] [blame] | 99 | #define TCG_TARGET_HAS_deposit_i64 1 |
Richard Henderson | 0f10d7c | 2021-02-02 16:48:48 -0800 | [diff] [blame] | 100 | #define TCG_TARGET_HAS_extract_i64 1 |
| 101 | #define TCG_TARGET_HAS_sextract_i64 1 |
Richard Henderson | fce1296 | 2019-02-25 10:29:25 -0800 | [diff] [blame] | 102 | #define TCG_TARGET_HAS_extract2_i64 0 |
Richard Henderson | ae40c09 | 2021-01-27 20:30:00 -1000 | [diff] [blame] | 103 | #define TCG_TARGET_HAS_div_i64 1 |
| 104 | #define TCG_TARGET_HAS_rem_i64 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 105 | #define TCG_TARGET_HAS_ext8s_i64 1 |
| 106 | #define TCG_TARGET_HAS_ext16s_i64 1 |
| 107 | #define TCG_TARGET_HAS_ext32s_i64 1 |
| 108 | #define TCG_TARGET_HAS_ext8u_i64 1 |
| 109 | #define TCG_TARGET_HAS_ext16u_i64 1 |
| 110 | #define TCG_TARGET_HAS_ext32u_i64 1 |
Richard Henderson | a81520b | 2021-02-02 16:29:18 -0800 | [diff] [blame] | 111 | #define TCG_TARGET_HAS_andc_i64 1 |
| 112 | #define TCG_TARGET_HAS_eqv_i64 1 |
| 113 | #define TCG_TARGET_HAS_nand_i64 1 |
| 114 | #define TCG_TARGET_HAS_nor_i64 1 |
Richard Henderson | 5255f48 | 2021-02-02 17:01:57 -0800 | [diff] [blame] | 115 | #define TCG_TARGET_HAS_clz_i64 1 |
| 116 | #define TCG_TARGET_HAS_ctz_i64 1 |
| 117 | #define TCG_TARGET_HAS_ctpop_i64 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 118 | #define TCG_TARGET_HAS_neg_i64 1 |
| 119 | #define TCG_TARGET_HAS_not_i64 1 |
Richard Henderson | a81520b | 2021-02-02 16:29:18 -0800 | [diff] [blame] | 120 | #define TCG_TARGET_HAS_orc_i64 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 121 | #define TCG_TARGET_HAS_rot_i64 1 |
Richard Henderson | df093c1 | 2021-02-02 16:15:45 -0800 | [diff] [blame] | 122 | #define TCG_TARGET_HAS_movcond_i64 1 |
Richard Henderson | f6db0d8 | 2021-02-02 17:21:27 -0800 | [diff] [blame] | 123 | #define TCG_TARGET_HAS_muls2_i64 1 |
Richard Henderson | 08096b1 | 2021-02-02 17:40:12 -0800 | [diff] [blame] | 124 | #define TCG_TARGET_HAS_add2_i32 1 |
| 125 | #define TCG_TARGET_HAS_sub2_i32 1 |
Richard Henderson | f6db0d8 | 2021-02-02 17:21:27 -0800 | [diff] [blame] | 126 | #define TCG_TARGET_HAS_mulu2_i32 1 |
Richard Henderson | 08096b1 | 2021-02-02 17:40:12 -0800 | [diff] [blame] | 127 | #define TCG_TARGET_HAS_add2_i64 1 |
| 128 | #define TCG_TARGET_HAS_sub2_i64 1 |
Richard Henderson | f6db0d8 | 2021-02-02 17:21:27 -0800 | [diff] [blame] | 129 | #define TCG_TARGET_HAS_mulu2_i64 1 |
Richard Henderson | 0327152 | 2013-08-14 14:35:56 -0700 | [diff] [blame] | 130 | #define TCG_TARGET_HAS_muluh_i64 0 |
| 131 | #define TCG_TARGET_HAS_mulsh_i64 0 |
Richard Henderson | df9ebea | 2014-03-26 10:59:14 -0700 | [diff] [blame] | 132 | #else |
| 133 | #define TCG_TARGET_HAS_mulu2_i32 1 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 134 | #endif /* TCG_TARGET_REG_BITS == 64 */ |
| 135 | |
Richard Henderson | 187f44d | 2021-01-28 14:54:16 -1000 | [diff] [blame] | 136 | /* Number of registers available. */ |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 137 | #define TCG_TARGET_NB_REGS 16 |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 138 | |
| 139 | /* List of registers which are used by TCG. */ |
| 140 | typedef enum { |
| 141 | TCG_REG_R0 = 0, |
| 142 | TCG_REG_R1, |
| 143 | TCG_REG_R2, |
| 144 | TCG_REG_R3, |
| 145 | TCG_REG_R4, |
| 146 | TCG_REG_R5, |
| 147 | TCG_REG_R6, |
| 148 | TCG_REG_R7, |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 149 | TCG_REG_R8, |
| 150 | TCG_REG_R9, |
| 151 | TCG_REG_R10, |
| 152 | TCG_REG_R11, |
| 153 | TCG_REG_R12, |
| 154 | TCG_REG_R13, |
| 155 | TCG_REG_R14, |
| 156 | TCG_REG_R15, |
Richard Henderson | 187f44d | 2021-01-28 14:54:16 -1000 | [diff] [blame] | 157 | |
Richard Henderson | baa94c0 | 2021-01-31 23:26:14 -1000 | [diff] [blame] | 158 | TCG_REG_TMP = TCG_REG_R13, |
Richard Henderson | 187f44d | 2021-01-28 14:54:16 -1000 | [diff] [blame] | 159 | TCG_AREG0 = TCG_REG_R14, |
| 160 | TCG_REG_CALL_STACK = TCG_REG_R15, |
Richard Henderson | 771142c | 2011-11-09 08:03:33 +0000 | [diff] [blame] | 161 | } TCGReg; |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 162 | |
Richard Henderson | ee79c35 | 2013-03-28 05:37:55 +0000 | [diff] [blame] | 163 | /* Used for function call generation. */ |
Richard Henderson | ee79c35 | 2013-03-28 05:37:55 +0000 | [diff] [blame] | 164 | #define TCG_TARGET_CALL_STACK_OFFSET 0 |
Richard Henderson | 7b7d8b2 | 2021-01-30 14:24:25 -0800 | [diff] [blame] | 165 | #define TCG_TARGET_STACK_ALIGN 8 |
Richard Henderson | ee79c35 | 2013-03-28 05:37:55 +0000 | [diff] [blame] | 166 | |
Paolo Bonzini | 5a58e88 | 2015-05-19 09:59:34 +0200 | [diff] [blame] | 167 | #define HAVE_TCG_QEMU_TB_EXEC |
Richard Henderson | 6508988 | 2021-02-01 21:27:41 -1000 | [diff] [blame] | 168 | #define TCG_TARGET_NEED_POOL_LABELS |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 169 | |
Richard Henderson | cda4a33 | 2017-09-07 10:54:30 -0700 | [diff] [blame] | 170 | /* We could notice __i386__ or __s390x__ and reduce the barriers depending |
| 171 | on the host. But if you want performance, you use the normal backend. |
| 172 | We prefer consistency across hosts on this. */ |
| 173 | #define TCG_TARGET_DEFAULT_MO (0) |
| 174 | |
Richard Henderson | e1dcf35 | 2018-11-20 08:37:42 +0100 | [diff] [blame] | 175 | #define TCG_TARGET_HAS_MEMORY_BSWAP 1 |
| 176 | |
Richard Henderson | 1670a2b | 2021-01-29 22:11:43 -1000 | [diff] [blame] | 177 | /* not defined -- call should be eliminated at compile time */ |
| 178 | void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); |
Richard Henderson | a858339 | 2017-07-31 22:02:31 -0700 | [diff] [blame] | 179 | |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 180 | #endif /* TCG_TARGET_H */ |