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bellard7d132992003-03-06 23:23:54 +00001/*
2 * i386 emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
bellard7d132992003-03-06 23:23:54 +000019 */
bellarde4533c72003-06-15 19:51:39 +000020#include "config.h"
bellard93ac68b2003-09-30 20:57:29 +000021#include "exec.h"
bellard956034d2003-04-29 20:40:53 +000022#include "disas.h"
bellard7d132992003-03-06 23:23:54 +000023
bellardfbf9eeb2004-04-25 21:21:33 +000024#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
bellard36bdbe52003-11-19 22:12:02 +000038int tb_invalidated_flag;
39
bellarddc990652003-03-19 00:00:28 +000040//#define DEBUG_EXEC
bellard9de5e442003-03-23 16:49:39 +000041//#define DEBUG_SIGNAL
bellard7d132992003-03-06 23:23:54 +000042
bellarde4533c72003-06-15 19:51:39 +000043void cpu_loop_exit(void)
44{
thsbfed01f2007-06-03 17:44:37 +000045 /* NOTE: the register at this point must be saved by hand because
46 longjmp restore them */
47 regs_to_env();
bellarde4533c72003-06-15 19:51:39 +000048 longjmp(env->jmp_env, 1);
49}
thsbfed01f2007-06-03 17:44:37 +000050
pbrooke6e59062006-10-22 00:18:54 +000051#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
bellard34751872005-07-02 14:31:34 +000052#define reg_T2
53#endif
bellarde4533c72003-06-15 19:51:39 +000054
bellardfbf9eeb2004-04-25 21:21:33 +000055/* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
ths5fafdf22007-09-16 21:08:06 +000058void cpu_resume_from_signal(CPUState *env1, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000059{
60#if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62#endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68#if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73#endif
74 longjmp(env->jmp_env, 1);
75}
76
bellard8a40a182005-11-20 10:35:40 +000077
78static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +000080 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +000081{
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
ths3b46e622007-09-17 08:09:54 +000087
bellard8a40a182005-11-20 10:35:40 +000088 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +000091
bellard8a40a182005-11-20 10:35:40 +000092 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
ths3b46e622007-09-17 08:09:54 +000093
bellard8a40a182005-11-20 10:35:40 +000094 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000104 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000105 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000106 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
ths5fafdf22007-09-16 21:08:06 +0000110 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
bellard15388002005-12-19 01:42:32 +0000130 tb_invalidated_flag = 1;
bellard8a40a182005-11-20 10:35:40 +0000131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
ths3b46e622007-09-17 08:09:54 +0000138
bellard8a40a182005-11-20 10:35:40 +0000139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
ths3b46e622007-09-17 08:09:54 +0000146
bellard8a40a182005-11-20 10:35:40 +0000147 found:
bellard8a40a182005-11-20 10:35:40 +0000148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152}
153
154static inline TranslationBlock *tb_find_fast(void)
155{
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
j_mayerc0686882007-09-20 22:47:42 +0000158 uint64_t flags;
bellard8a40a182005-11-20 10:35:40 +0000159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163#if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
ths0573fbf2007-09-23 15:28:04 +0000166 flags |= env->intercept;
bellard8a40a182005-11-20 10:35:40 +0000167 cs_base = env->segs[R_CS].base;
168 pc = cs_base + env->eip;
169#elif defined(TARGET_ARM)
170 flags = env->thumb | (env->vfp.vec_len << 1)
bellardb5ff1b32005-11-26 10:38:39 +0000171 | (env->vfp.vec_stride << 4);
172 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
173 flags |= (1 << 6);
pbrook40f137e2006-02-20 00:33:36 +0000174 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
175 flags |= (1 << 7);
bellard8a40a182005-11-20 10:35:40 +0000176 cs_base = 0;
177 pc = env->regs[15];
178#elif defined(TARGET_SPARC)
179#ifdef TARGET_SPARC64
bellarda80dde02006-06-26 19:53:29 +0000180 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
181 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
bellard8a40a182005-11-20 10:35:40 +0000183#else
blueswir140ce0a92007-09-24 19:44:09 +0000184 // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
185 flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
186 | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
bellarda80dde02006-06-26 19:53:29 +0000187 | env->psrs;
bellard8a40a182005-11-20 10:35:40 +0000188#endif
189 cs_base = env->npc;
190 pc = env->pc;
191#elif defined(TARGET_PPC)
j_mayer1527c872007-09-19 05:37:56 +0000192 flags = env->hflags;
bellard8a40a182005-11-20 10:35:40 +0000193 cs_base = 0;
194 pc = env->nip;
195#elif defined(TARGET_MIPS)
pbrook56b19402006-03-11 16:23:39 +0000196 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
bellardcc9442b2005-11-26 18:43:28 +0000197 cs_base = 0;
thsead93602007-09-06 00:18:15 +0000198 pc = env->PC[env->current_tc];
pbrooke6e59062006-10-22 00:18:54 +0000199#elif defined(TARGET_M68K)
pbrookacf930a2007-05-29 14:57:59 +0000200 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
201 | (env->sr & SR_S) /* Bit 13 */
202 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
pbrooke6e59062006-10-22 00:18:54 +0000203 cs_base = 0;
204 pc = env->pc;
bellardfdf9b3e2006-04-27 21:07:38 +0000205#elif defined(TARGET_SH4)
206 flags = env->sr & (SR_MD | SR_RB);
207 cs_base = 0; /* XXXXX */
208 pc = env->pc;
j_mayereddf68a2007-04-05 07:22:49 +0000209#elif defined(TARGET_ALPHA)
210 flags = env->ps;
211 cs_base = 0;
212 pc = env->pc;
thsf1ccf902007-10-08 13:16:14 +0000213#elif defined(TARGET_CRIS)
214 flags = 0;
215 cs_base = 0;
216 pc = env->pc;
bellard8a40a182005-11-20 10:35:40 +0000217#else
218#error unsupported CPU
219#endif
220 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
221 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
222 tb->flags != flags, 0)) {
223 tb = tb_find_slow(pc, cs_base, flags);
bellard15388002005-12-19 01:42:32 +0000224 /* Note: we do it here to avoid a gcc bug on Mac OS X when
225 doing it in tb_find_slow */
226 if (tb_invalidated_flag) {
227 /* as some TB could have been invalidated because
228 of memory exceptions while generating the code, we
229 must recompute the hash index here */
230 T0 = 0;
231 }
bellard8a40a182005-11-20 10:35:40 +0000232 }
233 return tb;
234}
235
236
bellard7d132992003-03-06 23:23:54 +0000237/* main execution loop */
238
bellarde4533c72003-06-15 19:51:39 +0000239int cpu_exec(CPUState *env1)
bellard7d132992003-03-06 23:23:54 +0000240{
pbrook1057eaa2007-02-04 13:37:44 +0000241#define DECLARE_HOST_REGS 1
242#include "hostregs_helper.h"
243#if defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000244#if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
246#endif
247#endif
bellardfdbb4692006-06-14 17:32:25 +0000248#if defined(__sparc__) && !defined(HOST_SOLARIS)
thsb49d07b2007-02-02 03:57:09 +0000249 int saved_i7;
250 target_ulong tmp_T0;
bellard8c6939c2003-06-09 15:28:00 +0000251#endif
bellard8a40a182005-11-20 10:35:40 +0000252 int ret, interrupt_request;
bellard7d132992003-03-06 23:23:54 +0000253 void (*gen_func)(void);
bellard8a40a182005-11-20 10:35:40 +0000254 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000255 uint8_t *tc_ptr;
bellard8c6939c2003-06-09 15:28:00 +0000256
thsbfed01f2007-06-03 17:44:37 +0000257 if (cpu_halted(env1) == EXCP_HALTED)
258 return EXCP_HALTED;
bellard5a1e3cf2005-11-23 21:02:53 +0000259
ths5fafdf22007-09-16 21:08:06 +0000260 cpu_single_env = env1;
bellard6a00d602005-11-21 23:25:50 +0000261
bellard7d132992003-03-06 23:23:54 +0000262 /* first we save global registers */
pbrook1057eaa2007-02-04 13:37:44 +0000263#define SAVE_HOST_REGS 1
264#include "hostregs_helper.h"
bellardc27004e2005-01-03 23:35:10 +0000265 env = env1;
bellardfdbb4692006-06-14 17:32:25 +0000266#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellarde4533c72003-06-15 19:51:39 +0000267 /* we also save i7 because longjmp may not restore it */
268 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
269#endif
270
bellard0d1a29f2004-10-12 22:01:28 +0000271 env_to_regs();
thsecb644f2007-06-03 18:45:53 +0000272#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000273 /* put eflags in CPU temporary format */
bellardfc2b4c42003-03-29 16:52:44 +0000274 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
275 DF = 1 - (2 * ((env->eflags >> 10) & 1));
bellard9de5e442003-03-23 16:49:39 +0000276 CC_OP = CC_OP_EFLAGS;
bellardfc2b4c42003-03-29 16:52:44 +0000277 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard93ac68b2003-09-30 20:57:29 +0000278#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000279#if defined(reg_REGWPTR)
280 saved_regwptr = REGWPTR;
281#endif
pbrooke6e59062006-10-22 00:18:54 +0000282#elif defined(TARGET_M68K)
283 env->cc_op = CC_OP_FLAGS;
284 env->cc_dest = env->sr & 0xf;
285 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000286#elif defined(TARGET_ALPHA)
287#elif defined(TARGET_ARM)
288#elif defined(TARGET_PPC)
bellard6af0bf92005-07-02 14:58:51 +0000289#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000290#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000291#elif defined(TARGET_CRIS)
bellardfdf9b3e2006-04-27 21:07:38 +0000292 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000293#else
294#error unsupported target CPU
295#endif
bellard3fb2ded2003-06-24 13:22:59 +0000296 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000297
bellard7d132992003-03-06 23:23:54 +0000298 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000299 for(;;) {
300 if (setjmp(env->jmp_env) == 0) {
bellardee8b7022004-02-03 23:35:10 +0000301 env->current_tb = NULL;
bellard3fb2ded2003-06-24 13:22:59 +0000302 /* if an exception is pending, we execute it here */
303 if (env->exception_index >= 0) {
304 if (env->exception_index >= EXCP_INTERRUPT) {
305 /* exit request from the cpu execution loop */
306 ret = env->exception_index;
307 break;
308 } else if (env->user_mode_only) {
309 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000310 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000311 loop */
bellard83479e72003-06-25 16:12:37 +0000312#if defined(TARGET_I386)
ths5fafdf22007-09-16 21:08:06 +0000313 do_interrupt_user(env->exception_index,
314 env->exception_is_int,
315 env->error_code,
bellard3fb2ded2003-06-24 13:22:59 +0000316 env->exception_next_eip);
bellard83479e72003-06-25 16:12:37 +0000317#endif
bellard3fb2ded2003-06-24 13:22:59 +0000318 ret = env->exception_index;
319 break;
320 } else {
bellard83479e72003-06-25 16:12:37 +0000321#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000322 /* simulate a real cpu exception. On i386, it can
323 trigger new exceptions, but we do not handle
324 double or triple faults yet. */
ths5fafdf22007-09-16 21:08:06 +0000325 do_interrupt(env->exception_index,
326 env->exception_is_int,
327 env->error_code,
bellardd05e66d2003-08-20 21:34:35 +0000328 env->exception_next_eip, 0);
ths678dde12007-03-31 20:28:52 +0000329 /* successfully delivered */
330 env->old_exception = -1;
bellardce097762004-01-04 23:53:18 +0000331#elif defined(TARGET_PPC)
332 do_interrupt(env);
bellard6af0bf92005-07-02 14:58:51 +0000333#elif defined(TARGET_MIPS)
334 do_interrupt(env);
bellarde95c8d52004-09-30 22:22:08 +0000335#elif defined(TARGET_SPARC)
bellard1a0c3292005-02-13 19:02:07 +0000336 do_interrupt(env->exception_index);
bellardb5ff1b32005-11-26 10:38:39 +0000337#elif defined(TARGET_ARM)
338 do_interrupt(env);
bellardfdf9b3e2006-04-27 21:07:38 +0000339#elif defined(TARGET_SH4)
340 do_interrupt(env);
j_mayereddf68a2007-04-05 07:22:49 +0000341#elif defined(TARGET_ALPHA)
342 do_interrupt(env);
thsf1ccf902007-10-08 13:16:14 +0000343#elif defined(TARGET_CRIS)
344 do_interrupt(env);
pbrook06338792007-05-23 19:58:11 +0000345#elif defined(TARGET_M68K)
346 do_interrupt(0);
bellard83479e72003-06-25 16:12:37 +0000347#endif
bellard3fb2ded2003-06-24 13:22:59 +0000348 }
349 env->exception_index = -1;
ths5fafdf22007-09-16 21:08:06 +0000350 }
bellard9df217a2005-02-10 22:05:51 +0000351#ifdef USE_KQEMU
352 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
353 int ret;
354 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
355 ret = kqemu_cpu_exec(env);
356 /* put eflags in CPU temporary format */
357 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
358 DF = 1 - (2 * ((env->eflags >> 10) & 1));
359 CC_OP = CC_OP_EFLAGS;
360 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
361 if (ret == 1) {
362 /* exception */
363 longjmp(env->jmp_env, 1);
364 } else if (ret == 2) {
365 /* softmmu execution needed */
366 } else {
367 if (env->interrupt_request != 0) {
368 /* hardware interrupt will be executed just after */
369 } else {
370 /* otherwise, we restart */
371 longjmp(env->jmp_env, 1);
372 }
373 }
bellard9de5e442003-03-23 16:49:39 +0000374 }
bellard9df217a2005-02-10 22:05:51 +0000375#endif
376
bellard3fb2ded2003-06-24 13:22:59 +0000377 T0 = 0; /* force lookup of first TB */
378 for(;;) {
bellardfdbb4692006-06-14 17:32:25 +0000379#if defined(__sparc__) && !defined(HOST_SOLARIS)
ths5fafdf22007-09-16 21:08:06 +0000380 /* g1 can be modified by some libc? functions */
bellard3fb2ded2003-06-24 13:22:59 +0000381 tmp_T0 = T0;
ths3b46e622007-09-17 08:09:54 +0000382#endif
bellard68a79312003-06-30 13:12:32 +0000383 interrupt_request = env->interrupt_request;
ths0573fbf2007-09-23 15:28:04 +0000384 if (__builtin_expect(interrupt_request, 0)
385#if defined(TARGET_I386)
386 && env->hflags & HF_GIF_MASK
387#endif
388 ) {
pbrook6658ffb2007-03-16 23:58:11 +0000389 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
390 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
391 env->exception_index = EXCP_DEBUG;
392 cpu_loop_exit();
393 }
balroga90b7312007-05-01 01:28:01 +0000394#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
thsf1ccf902007-10-08 13:16:14 +0000395 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
balroga90b7312007-05-01 01:28:01 +0000396 if (interrupt_request & CPU_INTERRUPT_HALT) {
397 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
398 env->halted = 1;
399 env->exception_index = EXCP_HLT;
400 cpu_loop_exit();
401 }
402#endif
bellard68a79312003-06-30 13:12:32 +0000403#if defined(TARGET_I386)
bellard3b21e032006-09-24 18:41:56 +0000404 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
405 !(env->hflags & HF_SMM_MASK)) {
ths0573fbf2007-09-23 15:28:04 +0000406 svm_check_intercept(SVM_EXIT_SMI);
bellard3b21e032006-09-24 18:41:56 +0000407 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
408 do_smm_enter();
409#if defined(__sparc__) && !defined(HOST_SOLARIS)
410 tmp_T0 = 0;
411#else
412 T0 = 0;
413#endif
414 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
ths0573fbf2007-09-23 15:28:04 +0000415 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
bellard3f337312003-08-20 23:02:09 +0000416 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
bellard68a79312003-06-30 13:12:32 +0000417 int intno;
ths0573fbf2007-09-23 15:28:04 +0000418 svm_check_intercept(SVM_EXIT_INTR);
ths52621682007-09-27 01:52:00 +0000419 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
bellarda541f292004-04-12 20:39:29 +0000420 intno = cpu_get_pic_interrupt(env);
bellardf193c792004-03-21 17:06:25 +0000421 if (loglevel & CPU_LOG_TB_IN_ASM) {
bellard68a79312003-06-30 13:12:32 +0000422 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
423 }
bellardd05e66d2003-08-20 21:34:35 +0000424 do_interrupt(intno, 0, 0, 0, 1);
bellard907a5b22003-06-30 23:18:22 +0000425 /* ensure that no TB jump will be modified as
426 the program flow was changed */
bellardfdbb4692006-06-14 17:32:25 +0000427#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard907a5b22003-06-30 23:18:22 +0000428 tmp_T0 = 0;
429#else
430 T0 = 0;
431#endif
ths0573fbf2007-09-23 15:28:04 +0000432#if !defined(CONFIG_USER_ONLY)
433 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
434 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
435 int intno;
436 /* FIXME: this should respect TPR */
437 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
ths52621682007-09-27 01:52:00 +0000438 svm_check_intercept(SVM_EXIT_VINTR);
ths0573fbf2007-09-23 15:28:04 +0000439 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
440 if (loglevel & CPU_LOG_TB_IN_ASM)
441 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
442 do_interrupt(intno, 0, 0, -1, 1);
ths52621682007-09-27 01:52:00 +0000443 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
444 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
ths0573fbf2007-09-23 15:28:04 +0000445#if defined(__sparc__) && !defined(HOST_SOLARIS)
446 tmp_T0 = 0;
447#else
448 T0 = 0;
449#endif
450#endif
bellard68a79312003-06-30 13:12:32 +0000451 }
bellardce097762004-01-04 23:53:18 +0000452#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000453#if 0
454 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
455 cpu_ppc_reset(env);
456 }
457#endif
j_mayer47103572007-03-30 09:38:04 +0000458 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000459 ppc_hw_interrupt(env);
460 if (env->pending_interrupts == 0)
461 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellardfdbb4692006-06-14 17:32:25 +0000462#if defined(__sparc__) && !defined(HOST_SOLARIS)
j_mayere9df0142007-04-09 22:45:36 +0000463 tmp_T0 = 0;
bellard8a40a182005-11-20 10:35:40 +0000464#else
j_mayere9df0142007-04-09 22:45:36 +0000465 T0 = 0;
bellard8a40a182005-11-20 10:35:40 +0000466#endif
bellardce097762004-01-04 23:53:18 +0000467 }
bellard6af0bf92005-07-02 14:58:51 +0000468#elif defined(TARGET_MIPS)
469 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
ths24c7b0e2007-03-30 16:44:54 +0000470 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
bellard6af0bf92005-07-02 14:58:51 +0000471 (env->CP0_Status & (1 << CP0St_IE)) &&
ths24c7b0e2007-03-30 16:44:54 +0000472 !(env->CP0_Status & (1 << CP0St_EXL)) &&
473 !(env->CP0_Status & (1 << CP0St_ERL)) &&
bellard6af0bf92005-07-02 14:58:51 +0000474 !(env->hflags & MIPS_HFLAG_DM)) {
475 /* Raise it */
476 env->exception_index = EXCP_EXT_INTERRUPT;
477 env->error_code = 0;
478 do_interrupt(env);
bellardfdbb4692006-06-14 17:32:25 +0000479#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8a40a182005-11-20 10:35:40 +0000480 tmp_T0 = 0;
481#else
482 T0 = 0;
483#endif
bellard6af0bf92005-07-02 14:58:51 +0000484 }
bellarde95c8d52004-09-30 22:22:08 +0000485#elif defined(TARGET_SPARC)
bellard66321a12005-04-06 20:47:48 +0000486 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
487 (env->psret != 0)) {
488 int pil = env->interrupt_index & 15;
489 int type = env->interrupt_index & 0xf0;
490
491 if (((type == TT_EXTINT) &&
492 (pil == 15 || pil > env->psrpil)) ||
493 type != TT_EXTINT) {
494 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
495 do_interrupt(env->interrupt_index);
496 env->interrupt_index = 0;
blueswir1327ac2e2007-08-04 10:50:30 +0000497#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
498 cpu_check_irqs(env);
499#endif
bellardfdbb4692006-06-14 17:32:25 +0000500#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8a40a182005-11-20 10:35:40 +0000501 tmp_T0 = 0;
502#else
503 T0 = 0;
504#endif
bellard66321a12005-04-06 20:47:48 +0000505 }
bellarde95c8d52004-09-30 22:22:08 +0000506 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
507 //do_interrupt(0, 0, 0, 0, 0);
508 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
balroga90b7312007-05-01 01:28:01 +0000509 }
bellardb5ff1b32005-11-26 10:38:39 +0000510#elif defined(TARGET_ARM)
511 if (interrupt_request & CPU_INTERRUPT_FIQ
512 && !(env->uncached_cpsr & CPSR_F)) {
513 env->exception_index = EXCP_FIQ;
514 do_interrupt(env);
515 }
516 if (interrupt_request & CPU_INTERRUPT_HARD
517 && !(env->uncached_cpsr & CPSR_I)) {
518 env->exception_index = EXCP_IRQ;
519 do_interrupt(env);
520 }
bellardfdf9b3e2006-04-27 21:07:38 +0000521#elif defined(TARGET_SH4)
522 /* XXXXX */
j_mayereddf68a2007-04-05 07:22:49 +0000523#elif defined(TARGET_ALPHA)
524 if (interrupt_request & CPU_INTERRUPT_HARD) {
525 do_interrupt(env);
526 }
thsf1ccf902007-10-08 13:16:14 +0000527#elif defined(TARGET_CRIS)
528 if (interrupt_request & CPU_INTERRUPT_HARD) {
529 do_interrupt(env);
530 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
531 }
pbrook06338792007-05-23 19:58:11 +0000532#elif defined(TARGET_M68K)
533 if (interrupt_request & CPU_INTERRUPT_HARD
534 && ((env->sr & SR_I) >> SR_I_SHIFT)
535 < env->pending_level) {
536 /* Real hardware gets the interrupt vector via an
537 IACK cycle at this point. Current emulated
538 hardware doesn't rely on this, so we
539 provide/save the vector when the interrupt is
540 first signalled. */
541 env->exception_index = env->pending_vector;
542 do_interrupt(1);
543 }
bellard68a79312003-06-30 13:12:32 +0000544#endif
bellard9d050952006-05-22 22:03:52 +0000545 /* Don't use the cached interupt_request value,
546 do_interrupt may have updated the EXITTB flag. */
bellardb5ff1b32005-11-26 10:38:39 +0000547 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bellardbf3e8bf2004-02-16 21:58:54 +0000548 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
549 /* ensure that no TB jump will be modified as
550 the program flow was changed */
bellardfdbb4692006-06-14 17:32:25 +0000551#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellardbf3e8bf2004-02-16 21:58:54 +0000552 tmp_T0 = 0;
553#else
554 T0 = 0;
555#endif
556 }
bellard68a79312003-06-30 13:12:32 +0000557 if (interrupt_request & CPU_INTERRUPT_EXIT) {
558 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
559 env->exception_index = EXCP_INTERRUPT;
560 cpu_loop_exit();
561 }
bellard3fb2ded2003-06-24 13:22:59 +0000562 }
563#ifdef DEBUG_EXEC
bellardb5ff1b32005-11-26 10:38:39 +0000564 if ((loglevel & CPU_LOG_TB_CPU)) {
bellard3fb2ded2003-06-24 13:22:59 +0000565 /* restore flags in standard format */
thsecb644f2007-06-03 18:45:53 +0000566 regs_to_env();
567#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000568 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard7fe48482004-10-09 18:08:01 +0000569 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
bellard3fb2ded2003-06-24 13:22:59 +0000570 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000571#elif defined(TARGET_ARM)
bellard7fe48482004-10-09 18:08:01 +0000572 cpu_dump_state(env, logfile, fprintf, 0);
bellard93ac68b2003-09-30 20:57:29 +0000573#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000574 REGWPTR = env->regbase + (env->cwp * 16);
575 env->regwptr = REGWPTR;
576 cpu_dump_state(env, logfile, fprintf, 0);
bellard67867302003-11-23 17:05:30 +0000577#elif defined(TARGET_PPC)
bellard7fe48482004-10-09 18:08:01 +0000578 cpu_dump_state(env, logfile, fprintf, 0);
pbrooke6e59062006-10-22 00:18:54 +0000579#elif defined(TARGET_M68K)
580 cpu_m68k_flush_flags(env, env->cc_op);
581 env->cc_op = CC_OP_FLAGS;
582 env->sr = (env->sr & 0xffe0)
583 | env->cc_dest | (env->cc_x << 4);
584 cpu_dump_state(env, logfile, fprintf, 0);
bellard6af0bf92005-07-02 14:58:51 +0000585#elif defined(TARGET_MIPS)
586 cpu_dump_state(env, logfile, fprintf, 0);
bellardfdf9b3e2006-04-27 21:07:38 +0000587#elif defined(TARGET_SH4)
588 cpu_dump_state(env, logfile, fprintf, 0);
j_mayereddf68a2007-04-05 07:22:49 +0000589#elif defined(TARGET_ALPHA)
590 cpu_dump_state(env, logfile, fprintf, 0);
thsf1ccf902007-10-08 13:16:14 +0000591#elif defined(TARGET_CRIS)
592 cpu_dump_state(env, logfile, fprintf, 0);
bellarde4533c72003-06-15 19:51:39 +0000593#else
ths5fafdf22007-09-16 21:08:06 +0000594#error unsupported target CPU
bellarde4533c72003-06-15 19:51:39 +0000595#endif
bellard3fb2ded2003-06-24 13:22:59 +0000596 }
bellard7d132992003-03-06 23:23:54 +0000597#endif
bellard8a40a182005-11-20 10:35:40 +0000598 tb = tb_find_fast();
bellard9d27abd2003-05-10 13:13:54 +0000599#ifdef DEBUG_EXEC
bellardc1135f62005-01-30 22:41:54 +0000600 if ((loglevel & CPU_LOG_EXEC)) {
bellardc27004e2005-01-03 23:35:10 +0000601 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
602 (long)tb->tc_ptr, tb->pc,
603 lookup_symbol(tb->pc));
bellard3fb2ded2003-06-24 13:22:59 +0000604 }
bellard9d27abd2003-05-10 13:13:54 +0000605#endif
bellardfdbb4692006-06-14 17:32:25 +0000606#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard3fb2ded2003-06-24 13:22:59 +0000607 T0 = tmp_T0;
ths3b46e622007-09-17 08:09:54 +0000608#endif
bellard8a40a182005-11-20 10:35:40 +0000609 /* see if we can patch the calling TB. When the TB
610 spans two pages, we cannot safely do a direct
611 jump. */
bellardc27004e2005-01-03 23:35:10 +0000612 {
bellard8a40a182005-11-20 10:35:40 +0000613 if (T0 != 0 &&
bellardf32fc642006-02-08 22:43:39 +0000614#if USE_KQEMU
615 (env->kqemu_enabled != 2) &&
616#endif
bellard8a40a182005-11-20 10:35:40 +0000617 tb->page_addr[1] == -1
bellardbf3e8bf2004-02-16 21:58:54 +0000618#if defined(TARGET_I386) && defined(USE_CODE_COPY)
ths5fafdf22007-09-16 21:08:06 +0000619 && (tb->cflags & CF_CODE_COPY) ==
bellardbf3e8bf2004-02-16 21:58:54 +0000620 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
621#endif
622 ) {
bellard3fb2ded2003-06-24 13:22:59 +0000623 spin_lock(&tb_lock);
bellardc27004e2005-01-03 23:35:10 +0000624 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
bellard97eb5b12004-02-25 23:19:55 +0000625#if defined(USE_CODE_COPY)
626 /* propagates the FP use info */
ths5fafdf22007-09-16 21:08:06 +0000627 ((TranslationBlock *)(T0 & ~3))->cflags |=
bellard97eb5b12004-02-25 23:19:55 +0000628 (tb->cflags & CF_FP_USED);
629#endif
bellard3fb2ded2003-06-24 13:22:59 +0000630 spin_unlock(&tb_lock);
631 }
bellardc27004e2005-01-03 23:35:10 +0000632 }
bellard3fb2ded2003-06-24 13:22:59 +0000633 tc_ptr = tb->tc_ptr;
bellard83479e72003-06-25 16:12:37 +0000634 env->current_tb = tb;
bellard3fb2ded2003-06-24 13:22:59 +0000635 /* execute the generated code */
636 gen_func = (void *)tc_ptr;
637#if defined(__sparc__)
638 __asm__ __volatile__("call %0\n\t"
639 "mov %%o7,%%i0"
640 : /* no outputs */
ths5fafdf22007-09-16 21:08:06 +0000641 : "r" (gen_func)
bellardfdbb4692006-06-14 17:32:25 +0000642 : "i0", "i1", "i2", "i3", "i4", "i5",
thsfaab7592007-03-19 20:39:49 +0000643 "o0", "o1", "o2", "o3", "o4", "o5",
bellardfdbb4692006-06-14 17:32:25 +0000644 "l0", "l1", "l2", "l3", "l4", "l5",
645 "l6", "l7");
bellard3fb2ded2003-06-24 13:22:59 +0000646#elif defined(__arm__)
647 asm volatile ("mov pc, %0\n\t"
648 ".global exec_loop\n\t"
649 "exec_loop:\n\t"
650 : /* no outputs */
651 : "r" (gen_func)
652 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bellardbf3e8bf2004-02-16 21:58:54 +0000653#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
654{
655 if (!(tb->cflags & CF_CODE_COPY)) {
bellard97eb5b12004-02-25 23:19:55 +0000656 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
657 save_native_fp_state(env);
658 }
bellardbf3e8bf2004-02-16 21:58:54 +0000659 gen_func();
660 } else {
bellard97eb5b12004-02-25 23:19:55 +0000661 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
662 restore_native_fp_state(env);
663 }
bellardbf3e8bf2004-02-16 21:58:54 +0000664 /* we work with native eflags */
665 CC_SRC = cc_table[CC_OP].compute_all();
666 CC_OP = CC_OP_EFLAGS;
667 asm(".globl exec_loop\n"
668 "\n"
669 "debug1:\n"
670 " pushl %%ebp\n"
671 " fs movl %10, %9\n"
672 " fs movl %11, %%eax\n"
673 " andl $0x400, %%eax\n"
674 " fs orl %8, %%eax\n"
675 " pushl %%eax\n"
676 " popf\n"
677 " fs movl %%esp, %12\n"
678 " fs movl %0, %%eax\n"
679 " fs movl %1, %%ecx\n"
680 " fs movl %2, %%edx\n"
681 " fs movl %3, %%ebx\n"
682 " fs movl %4, %%esp\n"
683 " fs movl %5, %%ebp\n"
684 " fs movl %6, %%esi\n"
685 " fs movl %7, %%edi\n"
686 " fs jmp *%9\n"
687 "exec_loop:\n"
688 " fs movl %%esp, %4\n"
689 " fs movl %12, %%esp\n"
690 " fs movl %%eax, %0\n"
691 " fs movl %%ecx, %1\n"
692 " fs movl %%edx, %2\n"
693 " fs movl %%ebx, %3\n"
694 " fs movl %%ebp, %5\n"
695 " fs movl %%esi, %6\n"
696 " fs movl %%edi, %7\n"
697 " pushf\n"
698 " popl %%eax\n"
699 " movl %%eax, %%ecx\n"
700 " andl $0x400, %%ecx\n"
701 " shrl $9, %%ecx\n"
702 " andl $0x8d5, %%eax\n"
703 " fs movl %%eax, %8\n"
704 " movl $1, %%eax\n"
705 " subl %%ecx, %%eax\n"
706 " fs movl %%eax, %11\n"
707 " fs movl %9, %%ebx\n" /* get T0 value */
708 " popl %%ebp\n"
709 :
710 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
711 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
712 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
713 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
714 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
715 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
716 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
717 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
718 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
719 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
720 "a" (gen_func),
721 "m" (*(uint8_t *)offsetof(CPUState, df)),
722 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
723 : "%ecx", "%edx"
724 );
725 }
726}
bellardb8076a72005-04-07 22:20:31 +0000727#elif defined(__ia64)
728 struct fptr {
729 void *ip;
730 void *gp;
731 } fp;
732
733 fp.ip = tc_ptr;
734 fp.gp = code_gen_buffer + 2 * (1 << 20);
735 (*(void (*)(void)) &fp)();
bellard3fb2ded2003-06-24 13:22:59 +0000736#else
737 gen_func();
738#endif
bellard83479e72003-06-25 16:12:37 +0000739 env->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000740 /* reset soft MMU for next block (it can currently
741 only be set by a memory fault) */
742#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
bellard3f337312003-08-20 23:02:09 +0000743 if (env->hflags & HF_SOFTMMU_MASK) {
744 env->hflags &= ~HF_SOFTMMU_MASK;
bellard4cbf74b2003-08-10 21:48:43 +0000745 /* do not allow linking to another block */
746 T0 = 0;
747 }
748#endif
bellardf32fc642006-02-08 22:43:39 +0000749#if defined(USE_KQEMU)
750#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
751 if (kqemu_is_ok(env) &&
752 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
753 cpu_loop_exit();
754 }
755#endif
ths50a518e2007-06-03 18:52:15 +0000756 } /* for(;;) */
bellard3fb2ded2003-06-24 13:22:59 +0000757 } else {
bellard0d1a29f2004-10-12 22:01:28 +0000758 env_to_regs();
bellard7d132992003-03-06 23:23:54 +0000759 }
bellard3fb2ded2003-06-24 13:22:59 +0000760 } /* for(;;) */
761
bellard7d132992003-03-06 23:23:54 +0000762
bellarde4533c72003-06-15 19:51:39 +0000763#if defined(TARGET_I386)
bellard97eb5b12004-02-25 23:19:55 +0000764#if defined(USE_CODE_COPY)
765 if (env->native_fp_regs) {
766 save_native_fp_state(env);
767 }
768#endif
bellard9de5e442003-03-23 16:49:39 +0000769 /* restore flags in standard format */
bellardfc2b4c42003-03-29 16:52:44 +0000770 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000771#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000772 /* XXX: Save/restore host fpu exception state?. */
bellard93ac68b2003-09-30 20:57:29 +0000773#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000774#if defined(reg_REGWPTR)
775 REGWPTR = saved_regwptr;
776#endif
bellard67867302003-11-23 17:05:30 +0000777#elif defined(TARGET_PPC)
pbrooke6e59062006-10-22 00:18:54 +0000778#elif defined(TARGET_M68K)
779 cpu_m68k_flush_flags(env, env->cc_op);
780 env->cc_op = CC_OP_FLAGS;
781 env->sr = (env->sr & 0xffe0)
782 | env->cc_dest | (env->cc_x << 4);
bellard6af0bf92005-07-02 14:58:51 +0000783#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000784#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000785#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000786#elif defined(TARGET_CRIS)
bellardfdf9b3e2006-04-27 21:07:38 +0000787 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000788#else
789#error unsupported target CPU
790#endif
pbrook1057eaa2007-02-04 13:37:44 +0000791
792 /* restore global registers */
bellardfdbb4692006-06-14 17:32:25 +0000793#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8c6939c2003-06-09 15:28:00 +0000794 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
795#endif
pbrook1057eaa2007-02-04 13:37:44 +0000796#include "hostregs_helper.h"
797
bellard6a00d602005-11-21 23:25:50 +0000798 /* fail safe : never use cpu_single_env outside cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000799 cpu_single_env = NULL;
bellard7d132992003-03-06 23:23:54 +0000800 return ret;
801}
bellard6dbad632003-03-16 18:05:05 +0000802
bellardfbf9eeb2004-04-25 21:21:33 +0000803/* must only be called from the generated code as an exception can be
804 generated */
805void tb_invalidate_page_range(target_ulong start, target_ulong end)
806{
bellarddc5d0b32004-06-22 18:43:30 +0000807 /* XXX: cannot enable it yet because it yields to MMU exception
808 where NIP != read address on PowerPC */
809#if 0
bellardfbf9eeb2004-04-25 21:21:33 +0000810 target_ulong phys_addr;
811 phys_addr = get_phys_addr_code(env, start);
812 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
bellarddc5d0b32004-06-22 18:43:30 +0000813#endif
bellardfbf9eeb2004-04-25 21:21:33 +0000814}
815
bellard1a18c712003-10-30 01:07:51 +0000816#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
bellarde4533c72003-06-15 19:51:39 +0000817
bellard6dbad632003-03-16 18:05:05 +0000818void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
819{
820 CPUX86State *saved_env;
821
822 saved_env = env;
823 env = s;
bellarda412ac52003-07-26 18:01:40 +0000824 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
bellarda513fe12003-05-27 23:29:48 +0000825 selector &= 0xffff;
ths5fafdf22007-09-16 21:08:06 +0000826 cpu_x86_load_seg_cache(env, seg_reg, selector,
bellardc27004e2005-01-03 23:35:10 +0000827 (selector << 4), 0xffff, 0);
bellarda513fe12003-05-27 23:29:48 +0000828 } else {
bellardb453b702004-01-04 15:45:21 +0000829 load_seg(seg_reg, selector);
bellarda513fe12003-05-27 23:29:48 +0000830 }
bellard6dbad632003-03-16 18:05:05 +0000831 env = saved_env;
832}
bellard9de5e442003-03-23 16:49:39 +0000833
bellardd0a1ffc2003-05-29 20:04:28 +0000834void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
835{
836 CPUX86State *saved_env;
837
838 saved_env = env;
839 env = s;
ths3b46e622007-09-17 08:09:54 +0000840
bellardc27004e2005-01-03 23:35:10 +0000841 helper_fsave((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000842
843 env = saved_env;
844}
845
846void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
847{
848 CPUX86State *saved_env;
849
850 saved_env = env;
851 env = s;
ths3b46e622007-09-17 08:09:54 +0000852
bellardc27004e2005-01-03 23:35:10 +0000853 helper_frstor((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000854
855 env = saved_env;
856}
857
bellarde4533c72003-06-15 19:51:39 +0000858#endif /* TARGET_I386 */
859
bellard67b915a2004-03-31 23:37:16 +0000860#if !defined(CONFIG_SOFTMMU)
861
bellard3fb2ded2003-06-24 13:22:59 +0000862#if defined(TARGET_I386)
863
bellardb56dad12003-05-08 15:38:04 +0000864/* 'pc' is the host PC at which the exception was raised. 'address' is
bellardfd6ce8f2003-05-14 19:00:11 +0000865 the effective address of the memory exception. 'is_write' is 1 if a
866 write caused the exception and otherwise 0'. 'old_set' is the
867 signal set which should be restored */
bellard2b413142003-05-14 23:01:10 +0000868static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
ths5fafdf22007-09-16 21:08:06 +0000869 int is_write, sigset_t *old_set,
bellardbf3e8bf2004-02-16 21:58:54 +0000870 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000871{
bellarda513fe12003-05-27 23:29:48 +0000872 TranslationBlock *tb;
873 int ret;
bellard68a79312003-06-30 13:12:32 +0000874
bellard83479e72003-06-25 16:12:37 +0000875 if (cpu_single_env)
876 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellardfd6ce8f2003-05-14 19:00:11 +0000877#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +0000878 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellardbf3e8bf2004-02-16 21:58:54 +0000879 pc, address, is_write, *(unsigned long *)old_set);
bellard9de5e442003-03-23 16:49:39 +0000880#endif
bellard25eb4482003-05-14 21:50:54 +0000881 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000882 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellardfd6ce8f2003-05-14 19:00:11 +0000883 return 1;
884 }
bellardfbf9eeb2004-04-25 21:21:33 +0000885
bellard3fb2ded2003-06-24 13:22:59 +0000886 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +0000887 ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellard3fb2ded2003-06-24 13:22:59 +0000888 if (ret < 0)
889 return 0; /* not an MMU fault */
890 if (ret == 0)
891 return 1; /* the MMU fault was handled without causing real CPU fault */
892 /* now we have a real cpu fault */
bellarda513fe12003-05-27 23:29:48 +0000893 tb = tb_find_pc(pc);
894 if (tb) {
bellard9de5e442003-03-23 16:49:39 +0000895 /* the PC is inside the translated code. It means that we have
896 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +0000897 cpu_restore_state(tb, env, pc, puc);
bellard3fb2ded2003-06-24 13:22:59 +0000898 }
bellard4cbf74b2003-08-10 21:48:43 +0000899 if (ret == 1) {
bellard3fb2ded2003-06-24 13:22:59 +0000900#if 0
ths5fafdf22007-09-16 21:08:06 +0000901 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
bellard4cbf74b2003-08-10 21:48:43 +0000902 env->eip, env->cr[2], env->error_code);
bellard3fb2ded2003-06-24 13:22:59 +0000903#endif
bellard4cbf74b2003-08-10 21:48:43 +0000904 /* we restore the process signal mask as the sigreturn should
905 do it (XXX: use sigsetjmp) */
906 sigprocmask(SIG_SETMASK, old_set, NULL);
bellard54ca9092005-12-04 18:46:06 +0000907 raise_exception_err(env->exception_index, env->error_code);
bellard4cbf74b2003-08-10 21:48:43 +0000908 } else {
909 /* activate soft MMU for this block */
bellard3f337312003-08-20 23:02:09 +0000910 env->hflags |= HF_SOFTMMU_MASK;
bellardfbf9eeb2004-04-25 21:21:33 +0000911 cpu_resume_from_signal(env, puc);
bellard4cbf74b2003-08-10 21:48:43 +0000912 }
bellard3fb2ded2003-06-24 13:22:59 +0000913 /* never comes here */
914 return 1;
915}
916
bellarde4533c72003-06-15 19:51:39 +0000917#elif defined(TARGET_ARM)
bellard3fb2ded2003-06-24 13:22:59 +0000918static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000919 int is_write, sigset_t *old_set,
920 void *puc)
bellard3fb2ded2003-06-24 13:22:59 +0000921{
bellard68016c62005-02-07 23:12:27 +0000922 TranslationBlock *tb;
923 int ret;
924
925 if (cpu_single_env)
926 env = cpu_single_env; /* XXX: find a correct solution for multithread */
927#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +0000928 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellard68016c62005-02-07 23:12:27 +0000929 pc, address, is_write, *(unsigned long *)old_set);
930#endif
bellard9f0777e2005-02-02 20:42:01 +0000931 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000932 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellard9f0777e2005-02-02 20:42:01 +0000933 return 1;
934 }
bellard68016c62005-02-07 23:12:27 +0000935 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +0000936 ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellard68016c62005-02-07 23:12:27 +0000937 if (ret < 0)
938 return 0; /* not an MMU fault */
939 if (ret == 0)
940 return 1; /* the MMU fault was handled without causing real CPU fault */
941 /* now we have a real cpu fault */
942 tb = tb_find_pc(pc);
943 if (tb) {
944 /* the PC is inside the translated code. It means that we have
945 a virtual CPU fault */
946 cpu_restore_state(tb, env, pc, puc);
947 }
948 /* we restore the process signal mask as the sigreturn should
949 do it (XXX: use sigsetjmp) */
950 sigprocmask(SIG_SETMASK, old_set, NULL);
951 cpu_loop_exit();
bellard3fb2ded2003-06-24 13:22:59 +0000952}
bellard93ac68b2003-09-30 20:57:29 +0000953#elif defined(TARGET_SPARC)
954static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000955 int is_write, sigset_t *old_set,
956 void *puc)
bellard93ac68b2003-09-30 20:57:29 +0000957{
bellard68016c62005-02-07 23:12:27 +0000958 TranslationBlock *tb;
959 int ret;
960
961 if (cpu_single_env)
962 env = cpu_single_env; /* XXX: find a correct solution for multithread */
963#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +0000964 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellard68016c62005-02-07 23:12:27 +0000965 pc, address, is_write, *(unsigned long *)old_set);
966#endif
bellardb453b702004-01-04 15:45:21 +0000967 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000968 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellardb453b702004-01-04 15:45:21 +0000969 return 1;
970 }
bellard68016c62005-02-07 23:12:27 +0000971 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +0000972 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellard68016c62005-02-07 23:12:27 +0000973 if (ret < 0)
974 return 0; /* not an MMU fault */
975 if (ret == 0)
976 return 1; /* the MMU fault was handled without causing real CPU fault */
977 /* now we have a real cpu fault */
978 tb = tb_find_pc(pc);
979 if (tb) {
980 /* the PC is inside the translated code. It means that we have
981 a virtual CPU fault */
982 cpu_restore_state(tb, env, pc, puc);
983 }
984 /* we restore the process signal mask as the sigreturn should
985 do it (XXX: use sigsetjmp) */
986 sigprocmask(SIG_SETMASK, old_set, NULL);
987 cpu_loop_exit();
bellard93ac68b2003-09-30 20:57:29 +0000988}
bellard67867302003-11-23 17:05:30 +0000989#elif defined (TARGET_PPC)
990static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000991 int is_write, sigset_t *old_set,
992 void *puc)
bellard67867302003-11-23 17:05:30 +0000993{
994 TranslationBlock *tb;
bellardce097762004-01-04 23:53:18 +0000995 int ret;
ths3b46e622007-09-17 08:09:54 +0000996
bellard67867302003-11-23 17:05:30 +0000997 if (cpu_single_env)
998 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellard67867302003-11-23 17:05:30 +0000999#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +00001000 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellard67867302003-11-23 17:05:30 +00001001 pc, address, is_write, *(unsigned long *)old_set);
1002#endif
1003 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +00001004 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellard67867302003-11-23 17:05:30 +00001005 return 1;
1006 }
1007
bellardce097762004-01-04 23:53:18 +00001008 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +00001009 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellardce097762004-01-04 23:53:18 +00001010 if (ret < 0)
1011 return 0; /* not an MMU fault */
1012 if (ret == 0)
1013 return 1; /* the MMU fault was handled without causing real CPU fault */
1014
bellard67867302003-11-23 17:05:30 +00001015 /* now we have a real cpu fault */
1016 tb = tb_find_pc(pc);
1017 if (tb) {
1018 /* the PC is inside the translated code. It means that we have
1019 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +00001020 cpu_restore_state(tb, env, pc, puc);
bellard67867302003-11-23 17:05:30 +00001021 }
bellardce097762004-01-04 23:53:18 +00001022 if (ret == 1) {
bellard67867302003-11-23 17:05:30 +00001023#if 0
ths5fafdf22007-09-16 21:08:06 +00001024 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
bellardce097762004-01-04 23:53:18 +00001025 env->nip, env->error_code, tb);
bellard67867302003-11-23 17:05:30 +00001026#endif
1027 /* we restore the process signal mask as the sigreturn should
1028 do it (XXX: use sigsetjmp) */
bellardbf3e8bf2004-02-16 21:58:54 +00001029 sigprocmask(SIG_SETMASK, old_set, NULL);
bellard9fddaa02004-05-21 12:59:32 +00001030 do_raise_exception_err(env->exception_index, env->error_code);
bellardce097762004-01-04 23:53:18 +00001031 } else {
1032 /* activate soft MMU for this block */
bellardfbf9eeb2004-04-25 21:21:33 +00001033 cpu_resume_from_signal(env, puc);
bellardce097762004-01-04 23:53:18 +00001034 }
bellard67867302003-11-23 17:05:30 +00001035 /* never comes here */
1036 return 1;
1037}
bellard6af0bf92005-07-02 14:58:51 +00001038
pbrooke6e59062006-10-22 00:18:54 +00001039#elif defined(TARGET_M68K)
1040static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1041 int is_write, sigset_t *old_set,
1042 void *puc)
1043{
1044 TranslationBlock *tb;
1045 int ret;
1046
1047 if (cpu_single_env)
1048 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1049#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +00001050 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
pbrooke6e59062006-10-22 00:18:54 +00001051 pc, address, is_write, *(unsigned long *)old_set);
1052#endif
1053 /* XXX: locking issue */
1054 if (is_write && page_unprotect(address, pc, puc)) {
1055 return 1;
1056 }
1057 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +00001058 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
pbrooke6e59062006-10-22 00:18:54 +00001059 if (ret < 0)
1060 return 0; /* not an MMU fault */
1061 if (ret == 0)
1062 return 1; /* the MMU fault was handled without causing real CPU fault */
1063 /* now we have a real cpu fault */
1064 tb = tb_find_pc(pc);
1065 if (tb) {
1066 /* the PC is inside the translated code. It means that we have
1067 a virtual CPU fault */
1068 cpu_restore_state(tb, env, pc, puc);
1069 }
1070 /* we restore the process signal mask as the sigreturn should
1071 do it (XXX: use sigsetjmp) */
1072 sigprocmask(SIG_SETMASK, old_set, NULL);
1073 cpu_loop_exit();
1074 /* never comes here */
1075 return 1;
1076}
1077
bellard6af0bf92005-07-02 14:58:51 +00001078#elif defined (TARGET_MIPS)
1079static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1080 int is_write, sigset_t *old_set,
1081 void *puc)
1082{
1083 TranslationBlock *tb;
1084 int ret;
ths3b46e622007-09-17 08:09:54 +00001085
bellard6af0bf92005-07-02 14:58:51 +00001086 if (cpu_single_env)
1087 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1088#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +00001089 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellard6af0bf92005-07-02 14:58:51 +00001090 pc, address, is_write, *(unsigned long *)old_set);
1091#endif
1092 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +00001093 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellard6af0bf92005-07-02 14:58:51 +00001094 return 1;
1095 }
1096
1097 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +00001098 ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellard6af0bf92005-07-02 14:58:51 +00001099 if (ret < 0)
1100 return 0; /* not an MMU fault */
1101 if (ret == 0)
1102 return 1; /* the MMU fault was handled without causing real CPU fault */
1103
1104 /* now we have a real cpu fault */
1105 tb = tb_find_pc(pc);
1106 if (tb) {
1107 /* the PC is inside the translated code. It means that we have
1108 a virtual CPU fault */
1109 cpu_restore_state(tb, env, pc, puc);
1110 }
1111 if (ret == 1) {
1112#if 0
ths5fafdf22007-09-16 21:08:06 +00001113 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
ths1eb52072007-05-12 16:57:42 +00001114 env->PC, env->error_code, tb);
bellard6af0bf92005-07-02 14:58:51 +00001115#endif
1116 /* we restore the process signal mask as the sigreturn should
1117 do it (XXX: use sigsetjmp) */
1118 sigprocmask(SIG_SETMASK, old_set, NULL);
1119 do_raise_exception_err(env->exception_index, env->error_code);
1120 } else {
1121 /* activate soft MMU for this block */
1122 cpu_resume_from_signal(env, puc);
1123 }
1124 /* never comes here */
1125 return 1;
1126}
1127
bellardfdf9b3e2006-04-27 21:07:38 +00001128#elif defined (TARGET_SH4)
1129static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1130 int is_write, sigset_t *old_set,
1131 void *puc)
1132{
1133 TranslationBlock *tb;
1134 int ret;
ths3b46e622007-09-17 08:09:54 +00001135
bellardfdf9b3e2006-04-27 21:07:38 +00001136 if (cpu_single_env)
1137 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1138#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +00001139 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellardfdf9b3e2006-04-27 21:07:38 +00001140 pc, address, is_write, *(unsigned long *)old_set);
1141#endif
1142 /* XXX: locking issue */
1143 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1144 return 1;
1145 }
1146
1147 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +00001148 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellardfdf9b3e2006-04-27 21:07:38 +00001149 if (ret < 0)
1150 return 0; /* not an MMU fault */
1151 if (ret == 0)
1152 return 1; /* the MMU fault was handled without causing real CPU fault */
1153
1154 /* now we have a real cpu fault */
1155 tb = tb_find_pc(pc);
1156 if (tb) {
1157 /* the PC is inside the translated code. It means that we have
1158 a virtual CPU fault */
1159 cpu_restore_state(tb, env, pc, puc);
1160 }
bellardfdf9b3e2006-04-27 21:07:38 +00001161#if 0
ths5fafdf22007-09-16 21:08:06 +00001162 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
bellardfdf9b3e2006-04-27 21:07:38 +00001163 env->nip, env->error_code, tb);
1164#endif
1165 /* we restore the process signal mask as the sigreturn should
1166 do it (XXX: use sigsetjmp) */
pbrook355fb232006-06-17 19:58:25 +00001167 sigprocmask(SIG_SETMASK, old_set, NULL);
1168 cpu_loop_exit();
bellardfdf9b3e2006-04-27 21:07:38 +00001169 /* never comes here */
1170 return 1;
1171}
j_mayereddf68a2007-04-05 07:22:49 +00001172
1173#elif defined (TARGET_ALPHA)
1174static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1175 int is_write, sigset_t *old_set,
1176 void *puc)
1177{
1178 TranslationBlock *tb;
1179 int ret;
ths3b46e622007-09-17 08:09:54 +00001180
j_mayereddf68a2007-04-05 07:22:49 +00001181 if (cpu_single_env)
1182 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1183#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +00001184 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
j_mayereddf68a2007-04-05 07:22:49 +00001185 pc, address, is_write, *(unsigned long *)old_set);
1186#endif
1187 /* XXX: locking issue */
1188 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1189 return 1;
1190 }
1191
1192 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +00001193 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
j_mayereddf68a2007-04-05 07:22:49 +00001194 if (ret < 0)
1195 return 0; /* not an MMU fault */
1196 if (ret == 0)
1197 return 1; /* the MMU fault was handled without causing real CPU fault */
1198
1199 /* now we have a real cpu fault */
1200 tb = tb_find_pc(pc);
1201 if (tb) {
1202 /* the PC is inside the translated code. It means that we have
1203 a virtual CPU fault */
1204 cpu_restore_state(tb, env, pc, puc);
1205 }
1206#if 0
ths5fafdf22007-09-16 21:08:06 +00001207 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
j_mayereddf68a2007-04-05 07:22:49 +00001208 env->nip, env->error_code, tb);
1209#endif
1210 /* we restore the process signal mask as the sigreturn should
1211 do it (XXX: use sigsetjmp) */
1212 sigprocmask(SIG_SETMASK, old_set, NULL);
1213 cpu_loop_exit();
1214 /* never comes here */
1215 return 1;
1216}
thsf1ccf902007-10-08 13:16:14 +00001217#elif defined (TARGET_CRIS)
1218static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1219 int is_write, sigset_t *old_set,
1220 void *puc)
1221{
1222 TranslationBlock *tb;
1223 int ret;
1224
1225 if (cpu_single_env)
1226 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1227#if defined(DEBUG_SIGNAL)
1228 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1229 pc, address, is_write, *(unsigned long *)old_set);
1230#endif
1231 /* XXX: locking issue */
1232 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1233 return 1;
1234 }
1235
1236 /* see if it is an MMU fault */
j_mayer6ebbf392007-10-14 07:07:08 +00001237 ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
thsf1ccf902007-10-08 13:16:14 +00001238 if (ret < 0)
1239 return 0; /* not an MMU fault */
1240 if (ret == 0)
1241 return 1; /* the MMU fault was handled without causing real CPU fault */
1242
1243 /* now we have a real cpu fault */
1244 tb = tb_find_pc(pc);
1245 if (tb) {
1246 /* the PC is inside the translated code. It means that we have
1247 a virtual CPU fault */
1248 cpu_restore_state(tb, env, pc, puc);
1249 }
1250#if 0
1251 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1252 env->nip, env->error_code, tb);
1253#endif
1254 /* we restore the process signal mask as the sigreturn should
1255 do it (XXX: use sigsetjmp) */
1256 sigprocmask(SIG_SETMASK, old_set, NULL);
1257 cpu_loop_exit();
1258 /* never comes here */
1259 return 1;
1260}
1261
bellarde4533c72003-06-15 19:51:39 +00001262#else
1263#error unsupported target CPU
1264#endif
bellard9de5e442003-03-23 16:49:39 +00001265
bellard2b413142003-05-14 23:01:10 +00001266#if defined(__i386__)
1267
bellardd8ecc0b2007-02-05 21:41:46 +00001268#if defined(__APPLE__)
1269# include <sys/ucontext.h>
1270
1271# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1272# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1273# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1274#else
1275# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1276# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1277# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1278#endif
1279
bellardbf3e8bf2004-02-16 21:58:54 +00001280#if defined(USE_CODE_COPY)
ths5fafdf22007-09-16 21:08:06 +00001281static void cpu_send_trap(unsigned long pc, int trap,
bellardbf3e8bf2004-02-16 21:58:54 +00001282 struct ucontext *uc)
1283{
1284 TranslationBlock *tb;
1285
1286 if (cpu_single_env)
1287 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1288 /* now we have a real cpu fault */
1289 tb = tb_find_pc(pc);
1290 if (tb) {
1291 /* the PC is inside the translated code. It means that we have
1292 a virtual CPU fault */
1293 cpu_restore_state(tb, env, pc, uc);
1294 }
1295 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1296 raise_exception_err(trap, env->error_code);
1297}
1298#endif
1299
ths5fafdf22007-09-16 21:08:06 +00001300int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001301 void *puc)
bellard9de5e442003-03-23 16:49:39 +00001302{
ths5a7b5422007-01-31 12:16:51 +00001303 siginfo_t *info = pinfo;
bellard9de5e442003-03-23 16:49:39 +00001304 struct ucontext *uc = puc;
1305 unsigned long pc;
bellardbf3e8bf2004-02-16 21:58:54 +00001306 int trapno;
bellard97eb5b12004-02-25 23:19:55 +00001307
bellardd691f662003-03-24 21:58:34 +00001308#ifndef REG_EIP
1309/* for glibc 2.1 */
bellardfd6ce8f2003-05-14 19:00:11 +00001310#define REG_EIP EIP
1311#define REG_ERR ERR
1312#define REG_TRAPNO TRAPNO
bellardd691f662003-03-24 21:58:34 +00001313#endif
bellardd8ecc0b2007-02-05 21:41:46 +00001314 pc = EIP_sig(uc);
1315 trapno = TRAP_sig(uc);
bellardbf3e8bf2004-02-16 21:58:54 +00001316#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1317 if (trapno == 0x00 || trapno == 0x05) {
1318 /* send division by zero or bound exception */
1319 cpu_send_trap(pc, trapno, uc);
1320 return 1;
1321 } else
1322#endif
ths5fafdf22007-09-16 21:08:06 +00001323 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1324 trapno == 0xe ?
bellardd8ecc0b2007-02-05 21:41:46 +00001325 (ERROR_sig(uc) >> 1) & 1 : 0,
bellardbf3e8bf2004-02-16 21:58:54 +00001326 &uc->uc_sigmask, puc);
bellard2b413142003-05-14 23:01:10 +00001327}
1328
bellardbc51c5c2004-03-17 23:46:04 +00001329#elif defined(__x86_64__)
1330
ths5a7b5422007-01-31 12:16:51 +00001331int cpu_signal_handler(int host_signum, void *pinfo,
bellardbc51c5c2004-03-17 23:46:04 +00001332 void *puc)
1333{
ths5a7b5422007-01-31 12:16:51 +00001334 siginfo_t *info = pinfo;
bellardbc51c5c2004-03-17 23:46:04 +00001335 struct ucontext *uc = puc;
1336 unsigned long pc;
1337
1338 pc = uc->uc_mcontext.gregs[REG_RIP];
ths5fafdf22007-09-16 21:08:06 +00001339 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1340 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
bellardbc51c5c2004-03-17 23:46:04 +00001341 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1342 &uc->uc_sigmask, puc);
1343}
1344
bellard83fb7ad2004-07-05 21:25:26 +00001345#elif defined(__powerpc__)
bellard2b413142003-05-14 23:01:10 +00001346
bellard83fb7ad2004-07-05 21:25:26 +00001347/***********************************************************************
1348 * signal context platform-specific definitions
1349 * From Wine
1350 */
1351#ifdef linux
1352/* All Registers access - only for local access */
1353# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1354/* Gpr Registers access */
1355# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1356# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1357# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1358# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1359# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1360# define LR_sig(context) REG_sig(link, context) /* Link register */
1361# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1362/* Float Registers access */
1363# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1364# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1365/* Exception Registers access */
1366# define DAR_sig(context) REG_sig(dar, context)
1367# define DSISR_sig(context) REG_sig(dsisr, context)
1368# define TRAP_sig(context) REG_sig(trap, context)
1369#endif /* linux */
1370
1371#ifdef __APPLE__
1372# include <sys/ucontext.h>
1373typedef struct ucontext SIGCONTEXT;
1374/* All Registers access - only for local access */
1375# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1376# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1377# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1378# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1379/* Gpr Registers access */
1380# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1381# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1382# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1383# define CTR_sig(context) REG_sig(ctr, context)
1384# define XER_sig(context) REG_sig(xer, context) /* Link register */
1385# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1386# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1387/* Float Registers access */
1388# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1389# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1390/* Exception Registers access */
1391# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1392# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1393# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1394#endif /* __APPLE__ */
1395
ths5fafdf22007-09-16 21:08:06 +00001396int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001397 void *puc)
bellard2b413142003-05-14 23:01:10 +00001398{
ths5a7b5422007-01-31 12:16:51 +00001399 siginfo_t *info = pinfo;
bellard25eb4482003-05-14 21:50:54 +00001400 struct ucontext *uc = puc;
bellard25eb4482003-05-14 21:50:54 +00001401 unsigned long pc;
bellard25eb4482003-05-14 21:50:54 +00001402 int is_write;
1403
bellard83fb7ad2004-07-05 21:25:26 +00001404 pc = IAR_sig(uc);
bellard25eb4482003-05-14 21:50:54 +00001405 is_write = 0;
1406#if 0
1407 /* ppc 4xx case */
bellard83fb7ad2004-07-05 21:25:26 +00001408 if (DSISR_sig(uc) & 0x00800000)
bellard25eb4482003-05-14 21:50:54 +00001409 is_write = 1;
bellard9de5e442003-03-23 16:49:39 +00001410#else
bellard83fb7ad2004-07-05 21:25:26 +00001411 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
bellard25eb4482003-05-14 21:50:54 +00001412 is_write = 1;
1413#endif
ths5fafdf22007-09-16 21:08:06 +00001414 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001415 is_write, &uc->uc_sigmask, puc);
bellard9de5e442003-03-23 16:49:39 +00001416}
bellard2b413142003-05-14 23:01:10 +00001417
bellard2f87c602003-06-02 20:38:09 +00001418#elif defined(__alpha__)
1419
ths5fafdf22007-09-16 21:08:06 +00001420int cpu_signal_handler(int host_signum, void *pinfo,
bellard2f87c602003-06-02 20:38:09 +00001421 void *puc)
1422{
ths5a7b5422007-01-31 12:16:51 +00001423 siginfo_t *info = pinfo;
bellard2f87c602003-06-02 20:38:09 +00001424 struct ucontext *uc = puc;
1425 uint32_t *pc = uc->uc_mcontext.sc_pc;
1426 uint32_t insn = *pc;
1427 int is_write = 0;
1428
bellard8c6939c2003-06-09 15:28:00 +00001429 /* XXX: need kernel patch to get write flag faster */
bellard2f87c602003-06-02 20:38:09 +00001430 switch (insn >> 26) {
1431 case 0x0d: // stw
1432 case 0x0e: // stb
1433 case 0x0f: // stq_u
1434 case 0x24: // stf
1435 case 0x25: // stg
1436 case 0x26: // sts
1437 case 0x27: // stt
1438 case 0x2c: // stl
1439 case 0x2d: // stq
1440 case 0x2e: // stl_c
1441 case 0x2f: // stq_c
1442 is_write = 1;
1443 }
1444
ths5fafdf22007-09-16 21:08:06 +00001445 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001446 is_write, &uc->uc_sigmask, puc);
bellard2f87c602003-06-02 20:38:09 +00001447}
bellard8c6939c2003-06-09 15:28:00 +00001448#elif defined(__sparc__)
1449
ths5fafdf22007-09-16 21:08:06 +00001450int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001451 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001452{
ths5a7b5422007-01-31 12:16:51 +00001453 siginfo_t *info = pinfo;
bellard8c6939c2003-06-09 15:28:00 +00001454 uint32_t *regs = (uint32_t *)(info + 1);
1455 void *sigmask = (regs + 20);
1456 unsigned long pc;
1457 int is_write;
1458 uint32_t insn;
ths3b46e622007-09-17 08:09:54 +00001459
bellard8c6939c2003-06-09 15:28:00 +00001460 /* XXX: is there a standard glibc define ? */
1461 pc = regs[1];
1462 /* XXX: need kernel patch to get write flag faster */
1463 is_write = 0;
1464 insn = *(uint32_t *)pc;
1465 if ((insn >> 30) == 3) {
1466 switch((insn >> 19) & 0x3f) {
1467 case 0x05: // stb
1468 case 0x06: // sth
1469 case 0x04: // st
1470 case 0x07: // std
1471 case 0x24: // stf
1472 case 0x27: // stdf
1473 case 0x25: // stfsr
1474 is_write = 1;
1475 break;
1476 }
1477 }
ths5fafdf22007-09-16 21:08:06 +00001478 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001479 is_write, sigmask, NULL);
bellard8c6939c2003-06-09 15:28:00 +00001480}
1481
1482#elif defined(__arm__)
1483
ths5fafdf22007-09-16 21:08:06 +00001484int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001485 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001486{
ths5a7b5422007-01-31 12:16:51 +00001487 siginfo_t *info = pinfo;
bellard8c6939c2003-06-09 15:28:00 +00001488 struct ucontext *uc = puc;
1489 unsigned long pc;
1490 int is_write;
ths3b46e622007-09-17 08:09:54 +00001491
bellard8c6939c2003-06-09 15:28:00 +00001492 pc = uc->uc_mcontext.gregs[R15];
1493 /* XXX: compute is_write */
1494 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001495 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellard8c6939c2003-06-09 15:28:00 +00001496 is_write,
pbrookf3a96762006-07-29 19:09:31 +00001497 &uc->uc_sigmask, puc);
bellard8c6939c2003-06-09 15:28:00 +00001498}
1499
bellard38e584a2003-08-10 22:14:22 +00001500#elif defined(__mc68000)
1501
ths5fafdf22007-09-16 21:08:06 +00001502int cpu_signal_handler(int host_signum, void *pinfo,
bellard38e584a2003-08-10 22:14:22 +00001503 void *puc)
1504{
ths5a7b5422007-01-31 12:16:51 +00001505 siginfo_t *info = pinfo;
bellard38e584a2003-08-10 22:14:22 +00001506 struct ucontext *uc = puc;
1507 unsigned long pc;
1508 int is_write;
ths3b46e622007-09-17 08:09:54 +00001509
bellard38e584a2003-08-10 22:14:22 +00001510 pc = uc->uc_mcontext.gregs[16];
1511 /* XXX: compute is_write */
1512 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001513 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellard38e584a2003-08-10 22:14:22 +00001514 is_write,
bellardbf3e8bf2004-02-16 21:58:54 +00001515 &uc->uc_sigmask, puc);
bellard38e584a2003-08-10 22:14:22 +00001516}
1517
bellardb8076a72005-04-07 22:20:31 +00001518#elif defined(__ia64)
1519
1520#ifndef __ISR_VALID
1521 /* This ought to be in <bits/siginfo.h>... */
1522# define __ISR_VALID 1
bellardb8076a72005-04-07 22:20:31 +00001523#endif
1524
ths5a7b5422007-01-31 12:16:51 +00001525int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
bellardb8076a72005-04-07 22:20:31 +00001526{
ths5a7b5422007-01-31 12:16:51 +00001527 siginfo_t *info = pinfo;
bellardb8076a72005-04-07 22:20:31 +00001528 struct ucontext *uc = puc;
1529 unsigned long ip;
1530 int is_write = 0;
1531
1532 ip = uc->uc_mcontext.sc_ip;
1533 switch (host_signum) {
1534 case SIGILL:
1535 case SIGFPE:
1536 case SIGSEGV:
1537 case SIGBUS:
1538 case SIGTRAP:
bellardfd4a43e2006-04-24 20:32:17 +00001539 if (info->si_code && (info->si_segvflags & __ISR_VALID))
bellardb8076a72005-04-07 22:20:31 +00001540 /* ISR.W (write-access) is bit 33: */
1541 is_write = (info->si_isr >> 33) & 1;
1542 break;
1543
1544 default:
1545 break;
1546 }
1547 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1548 is_write,
1549 &uc->uc_sigmask, puc);
1550}
1551
bellard90cb9492005-07-24 15:11:38 +00001552#elif defined(__s390__)
1553
ths5fafdf22007-09-16 21:08:06 +00001554int cpu_signal_handler(int host_signum, void *pinfo,
bellard90cb9492005-07-24 15:11:38 +00001555 void *puc)
1556{
ths5a7b5422007-01-31 12:16:51 +00001557 siginfo_t *info = pinfo;
bellard90cb9492005-07-24 15:11:38 +00001558 struct ucontext *uc = puc;
1559 unsigned long pc;
1560 int is_write;
ths3b46e622007-09-17 08:09:54 +00001561
bellard90cb9492005-07-24 15:11:38 +00001562 pc = uc->uc_mcontext.psw.addr;
1563 /* XXX: compute is_write */
1564 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001565 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
thsc4b89d12007-05-05 19:23:11 +00001566 is_write, &uc->uc_sigmask, puc);
1567}
1568
1569#elif defined(__mips__)
1570
ths5fafdf22007-09-16 21:08:06 +00001571int cpu_signal_handler(int host_signum, void *pinfo,
thsc4b89d12007-05-05 19:23:11 +00001572 void *puc)
1573{
ths9617efe2007-05-08 21:05:55 +00001574 siginfo_t *info = pinfo;
thsc4b89d12007-05-05 19:23:11 +00001575 struct ucontext *uc = puc;
1576 greg_t pc = uc->uc_mcontext.pc;
1577 int is_write;
ths3b46e622007-09-17 08:09:54 +00001578
thsc4b89d12007-05-05 19:23:11 +00001579 /* XXX: compute is_write */
1580 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001581 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
thsc4b89d12007-05-05 19:23:11 +00001582 is_write, &uc->uc_sigmask, puc);
bellard90cb9492005-07-24 15:11:38 +00001583}
1584
bellard2b413142003-05-14 23:01:10 +00001585#else
1586
bellard3fb2ded2003-06-24 13:22:59 +00001587#error host CPU specific signal handler needed
bellard2b413142003-05-14 23:01:10 +00001588
1589#endif
bellard67b915a2004-03-31 23:37:16 +00001590
1591#endif /* !defined(CONFIG_SOFTMMU) */