bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 19 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 20 | #include "config.h" |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 21 | #include "exec.h" |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 22 | #include "disas.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 23 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 24 | #if !defined(CONFIG_SOFTMMU) |
| 25 | #undef EAX |
| 26 | #undef ECX |
| 27 | #undef EDX |
| 28 | #undef EBX |
| 29 | #undef ESP |
| 30 | #undef EBP |
| 31 | #undef ESI |
| 32 | #undef EDI |
| 33 | #undef EIP |
| 34 | #include <signal.h> |
| 35 | #include <sys/ucontext.h> |
| 36 | #endif |
| 37 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 38 | int tb_invalidated_flag; |
| 39 | |
bellard | dc99065 | 2003-03-19 00:00:28 +0000 | [diff] [blame] | 40 | //#define DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 41 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 42 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 43 | void cpu_loop_exit(void) |
| 44 | { |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 45 | /* NOTE: the register at this point must be saved by hand because |
| 46 | longjmp restore them */ |
| 47 | regs_to_env(); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 48 | longjmp(env->jmp_env, 1); |
| 49 | } |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 50 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 51 | #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K)) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 52 | #define reg_T2 |
| 53 | #endif |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 54 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 55 | /* exit the current TB from a signal handler. The host registers are |
| 56 | restored in a state compatible with the CPU emulator |
| 57 | */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 58 | void cpu_resume_from_signal(CPUState *env1, void *puc) |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 59 | { |
| 60 | #if !defined(CONFIG_SOFTMMU) |
| 61 | struct ucontext *uc = puc; |
| 62 | #endif |
| 63 | |
| 64 | env = env1; |
| 65 | |
| 66 | /* XXX: restore cpu registers saved in host registers */ |
| 67 | |
| 68 | #if !defined(CONFIG_SOFTMMU) |
| 69 | if (puc) { |
| 70 | /* XXX: use siglongjmp ? */ |
| 71 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
| 72 | } |
| 73 | #endif |
| 74 | longjmp(env->jmp_env, 1); |
| 75 | } |
| 76 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 77 | |
| 78 | static TranslationBlock *tb_find_slow(target_ulong pc, |
| 79 | target_ulong cs_base, |
j_mayer | c068688 | 2007-09-20 22:47:42 +0000 | [diff] [blame] | 80 | uint64_t flags) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 81 | { |
| 82 | TranslationBlock *tb, **ptb1; |
| 83 | int code_gen_size; |
| 84 | unsigned int h; |
| 85 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
| 86 | uint8_t *tc_ptr; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 87 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 88 | spin_lock(&tb_lock); |
| 89 | |
| 90 | tb_invalidated_flag = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 91 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 92 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 93 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 94 | /* find translated block using physical mappings */ |
| 95 | phys_pc = get_phys_addr_code(env, pc); |
| 96 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
| 97 | phys_page2 = -1; |
| 98 | h = tb_phys_hash_func(phys_pc); |
| 99 | ptb1 = &tb_phys_hash[h]; |
| 100 | for(;;) { |
| 101 | tb = *ptb1; |
| 102 | if (!tb) |
| 103 | goto not_found; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 104 | if (tb->pc == pc && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 105 | tb->page_addr[0] == phys_page1 && |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 106 | tb->cs_base == cs_base && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 107 | tb->flags == flags) { |
| 108 | /* check next page if needed */ |
| 109 | if (tb->page_addr[1] != -1) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 110 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 111 | TARGET_PAGE_SIZE; |
| 112 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 113 | if (tb->page_addr[1] == phys_page2) |
| 114 | goto found; |
| 115 | } else { |
| 116 | goto found; |
| 117 | } |
| 118 | } |
| 119 | ptb1 = &tb->phys_hash_next; |
| 120 | } |
| 121 | not_found: |
| 122 | /* if no translated code available, then translate it now */ |
| 123 | tb = tb_alloc(pc); |
| 124 | if (!tb) { |
| 125 | /* flush must be done */ |
| 126 | tb_flush(env); |
| 127 | /* cannot fail at this point */ |
| 128 | tb = tb_alloc(pc); |
| 129 | /* don't forget to invalidate previous TB info */ |
bellard | 1538800 | 2005-12-19 01:42:32 +0000 | [diff] [blame] | 130 | tb_invalidated_flag = 1; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 131 | } |
| 132 | tc_ptr = code_gen_ptr; |
| 133 | tb->tc_ptr = tc_ptr; |
| 134 | tb->cs_base = cs_base; |
| 135 | tb->flags = flags; |
| 136 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
| 137 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 138 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 139 | /* check next page if needed */ |
| 140 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
| 141 | phys_page2 = -1; |
| 142 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
| 143 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 144 | } |
| 145 | tb_link_phys(tb, phys_pc, phys_page2); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 146 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 147 | found: |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 148 | /* we add the TB in the virtual pc hash table */ |
| 149 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
| 150 | spin_unlock(&tb_lock); |
| 151 | return tb; |
| 152 | } |
| 153 | |
| 154 | static inline TranslationBlock *tb_find_fast(void) |
| 155 | { |
| 156 | TranslationBlock *tb; |
| 157 | target_ulong cs_base, pc; |
j_mayer | c068688 | 2007-09-20 22:47:42 +0000 | [diff] [blame] | 158 | uint64_t flags; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 159 | |
| 160 | /* we record a subset of the CPU state. It will |
| 161 | always be the same before a given translated block |
| 162 | is executed. */ |
| 163 | #if defined(TARGET_I386) |
| 164 | flags = env->hflags; |
| 165 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 166 | flags |= env->intercept; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 167 | cs_base = env->segs[R_CS].base; |
| 168 | pc = cs_base + env->eip; |
| 169 | #elif defined(TARGET_ARM) |
| 170 | flags = env->thumb | (env->vfp.vec_len << 1) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 171 | | (env->vfp.vec_stride << 4); |
| 172 | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) |
| 173 | flags |= (1 << 6); |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 174 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
| 175 | flags |= (1 << 7); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 176 | cs_base = 0; |
| 177 | pc = env->regs[15]; |
| 178 | #elif defined(TARGET_SPARC) |
| 179 | #ifdef TARGET_SPARC64 |
bellard | a80dde0 | 2006-06-26 19:53:29 +0000 | [diff] [blame] | 180 | // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled |
| 181 | flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
| 182 | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 183 | #else |
blueswir1 | 40ce0a9 | 2007-09-24 19:44:09 +0000 | [diff] [blame] | 184 | // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor |
| 185 | flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3) |
| 186 | | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) |
bellard | a80dde0 | 2006-06-26 19:53:29 +0000 | [diff] [blame] | 187 | | env->psrs; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 188 | #endif |
| 189 | cs_base = env->npc; |
| 190 | pc = env->pc; |
| 191 | #elif defined(TARGET_PPC) |
j_mayer | 1527c87 | 2007-09-19 05:37:56 +0000 | [diff] [blame] | 192 | flags = env->hflags; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 193 | cs_base = 0; |
| 194 | pc = env->nip; |
| 195 | #elif defined(TARGET_MIPS) |
pbrook | 56b1940 | 2006-03-11 16:23:39 +0000 | [diff] [blame] | 196 | flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
bellard | cc9442b | 2005-11-26 18:43:28 +0000 | [diff] [blame] | 197 | cs_base = 0; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 198 | pc = env->PC[env->current_tc]; |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 199 | #elif defined(TARGET_M68K) |
pbrook | acf930a | 2007-05-29 14:57:59 +0000 | [diff] [blame] | 200 | flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */ |
| 201 | | (env->sr & SR_S) /* Bit 13 */ |
| 202 | | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 203 | cs_base = 0; |
| 204 | pc = env->pc; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 205 | #elif defined(TARGET_SH4) |
| 206 | flags = env->sr & (SR_MD | SR_RB); |
| 207 | cs_base = 0; /* XXXXX */ |
| 208 | pc = env->pc; |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 209 | #elif defined(TARGET_ALPHA) |
| 210 | flags = env->ps; |
| 211 | cs_base = 0; |
| 212 | pc = env->pc; |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 213 | #elif defined(TARGET_CRIS) |
| 214 | flags = 0; |
| 215 | cs_base = 0; |
| 216 | pc = env->pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 217 | #else |
| 218 | #error unsupported CPU |
| 219 | #endif |
| 220 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
| 221 | if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base || |
| 222 | tb->flags != flags, 0)) { |
| 223 | tb = tb_find_slow(pc, cs_base, flags); |
bellard | 1538800 | 2005-12-19 01:42:32 +0000 | [diff] [blame] | 224 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
| 225 | doing it in tb_find_slow */ |
| 226 | if (tb_invalidated_flag) { |
| 227 | /* as some TB could have been invalidated because |
| 228 | of memory exceptions while generating the code, we |
| 229 | must recompute the hash index here */ |
| 230 | T0 = 0; |
| 231 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 232 | } |
| 233 | return tb; |
| 234 | } |
| 235 | |
| 236 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 237 | /* main execution loop */ |
| 238 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 239 | int cpu_exec(CPUState *env1) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 240 | { |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 241 | #define DECLARE_HOST_REGS 1 |
| 242 | #include "hostregs_helper.h" |
| 243 | #if defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 244 | #if defined(reg_REGWPTR) |
| 245 | uint32_t *saved_regwptr; |
| 246 | #endif |
| 247 | #endif |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 248 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
ths | b49d07b | 2007-02-02 03:57:09 +0000 | [diff] [blame] | 249 | int saved_i7; |
| 250 | target_ulong tmp_T0; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 251 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 252 | int ret, interrupt_request; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 253 | void (*gen_func)(void); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 254 | TranslationBlock *tb; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 255 | uint8_t *tc_ptr; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 256 | |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 257 | if (cpu_halted(env1) == EXCP_HALTED) |
| 258 | return EXCP_HALTED; |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 259 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 260 | cpu_single_env = env1; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 261 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 262 | /* first we save global registers */ |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 263 | #define SAVE_HOST_REGS 1 |
| 264 | #include "hostregs_helper.h" |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 265 | env = env1; |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 266 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 267 | /* we also save i7 because longjmp may not restore it */ |
| 268 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
| 269 | #endif |
| 270 | |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 271 | env_to_regs(); |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 272 | #if defined(TARGET_I386) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 273 | /* put eflags in CPU temporary format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 274 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 275 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 276 | CC_OP = CC_OP_EFLAGS; |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 277 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 278 | #elif defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 279 | #if defined(reg_REGWPTR) |
| 280 | saved_regwptr = REGWPTR; |
| 281 | #endif |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 282 | #elif defined(TARGET_M68K) |
| 283 | env->cc_op = CC_OP_FLAGS; |
| 284 | env->cc_dest = env->sr & 0xf; |
| 285 | env->cc_x = (env->sr >> 4) & 1; |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 286 | #elif defined(TARGET_ALPHA) |
| 287 | #elif defined(TARGET_ARM) |
| 288 | #elif defined(TARGET_PPC) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 289 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 290 | #elif defined(TARGET_SH4) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 291 | #elif defined(TARGET_CRIS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 292 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 293 | #else |
| 294 | #error unsupported target CPU |
| 295 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 296 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 297 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 298 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 299 | for(;;) { |
| 300 | if (setjmp(env->jmp_env) == 0) { |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 301 | env->current_tb = NULL; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 302 | /* if an exception is pending, we execute it here */ |
| 303 | if (env->exception_index >= 0) { |
| 304 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 305 | /* exit request from the cpu execution loop */ |
| 306 | ret = env->exception_index; |
| 307 | break; |
| 308 | } else if (env->user_mode_only) { |
| 309 | /* if user mode only, we simulate a fake exception |
ths | 9f08349 | 2006-12-07 18:28:42 +0000 | [diff] [blame] | 310 | which will be handled outside the cpu execution |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 311 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 312 | #if defined(TARGET_I386) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 313 | do_interrupt_user(env->exception_index, |
| 314 | env->exception_is_int, |
| 315 | env->error_code, |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 316 | env->exception_next_eip); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 317 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 318 | ret = env->exception_index; |
| 319 | break; |
| 320 | } else { |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 321 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 322 | /* simulate a real cpu exception. On i386, it can |
| 323 | trigger new exceptions, but we do not handle |
| 324 | double or triple faults yet. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 325 | do_interrupt(env->exception_index, |
| 326 | env->exception_is_int, |
| 327 | env->error_code, |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 328 | env->exception_next_eip, 0); |
ths | 678dde1 | 2007-03-31 20:28:52 +0000 | [diff] [blame] | 329 | /* successfully delivered */ |
| 330 | env->old_exception = -1; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 331 | #elif defined(TARGET_PPC) |
| 332 | do_interrupt(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 333 | #elif defined(TARGET_MIPS) |
| 334 | do_interrupt(env); |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 335 | #elif defined(TARGET_SPARC) |
bellard | 1a0c329 | 2005-02-13 19:02:07 +0000 | [diff] [blame] | 336 | do_interrupt(env->exception_index); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 337 | #elif defined(TARGET_ARM) |
| 338 | do_interrupt(env); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 339 | #elif defined(TARGET_SH4) |
| 340 | do_interrupt(env); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 341 | #elif defined(TARGET_ALPHA) |
| 342 | do_interrupt(env); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 343 | #elif defined(TARGET_CRIS) |
| 344 | do_interrupt(env); |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 345 | #elif defined(TARGET_M68K) |
| 346 | do_interrupt(0); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 347 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 348 | } |
| 349 | env->exception_index = -1; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 350 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 351 | #ifdef USE_KQEMU |
| 352 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
| 353 | int ret; |
| 354 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 355 | ret = kqemu_cpu_exec(env); |
| 356 | /* put eflags in CPU temporary format */ |
| 357 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 358 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 359 | CC_OP = CC_OP_EFLAGS; |
| 360 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 361 | if (ret == 1) { |
| 362 | /* exception */ |
| 363 | longjmp(env->jmp_env, 1); |
| 364 | } else if (ret == 2) { |
| 365 | /* softmmu execution needed */ |
| 366 | } else { |
| 367 | if (env->interrupt_request != 0) { |
| 368 | /* hardware interrupt will be executed just after */ |
| 369 | } else { |
| 370 | /* otherwise, we restart */ |
| 371 | longjmp(env->jmp_env, 1); |
| 372 | } |
| 373 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 374 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 375 | #endif |
| 376 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 377 | T0 = 0; /* force lookup of first TB */ |
| 378 | for(;;) { |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 379 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 380 | /* g1 can be modified by some libc? functions */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 381 | tmp_T0 = T0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 382 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 383 | interrupt_request = env->interrupt_request; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 384 | if (__builtin_expect(interrupt_request, 0) |
| 385 | #if defined(TARGET_I386) |
| 386 | && env->hflags & HF_GIF_MASK |
| 387 | #endif |
| 388 | ) { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 389 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
| 390 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; |
| 391 | env->exception_index = EXCP_DEBUG; |
| 392 | cpu_loop_exit(); |
| 393 | } |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 394 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 395 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 396 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
| 397 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
| 398 | env->halted = 1; |
| 399 | env->exception_index = EXCP_HLT; |
| 400 | cpu_loop_exit(); |
| 401 | } |
| 402 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 403 | #if defined(TARGET_I386) |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 404 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
| 405 | !(env->hflags & HF_SMM_MASK)) { |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 406 | svm_check_intercept(SVM_EXIT_SMI); |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 407 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
| 408 | do_smm_enter(); |
| 409 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
| 410 | tmp_T0 = 0; |
| 411 | #else |
| 412 | T0 = 0; |
| 413 | #endif |
| 414 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 415 | (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) && |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 416 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 417 | int intno; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 418 | svm_check_intercept(SVM_EXIT_INTR); |
ths | 5262168 | 2007-09-27 01:52:00 +0000 | [diff] [blame] | 419 | env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 420 | intno = cpu_get_pic_interrupt(env); |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 421 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 422 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
| 423 | } |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 424 | do_interrupt(intno, 0, 0, 0, 1); |
bellard | 907a5b2 | 2003-06-30 23:18:22 +0000 | [diff] [blame] | 425 | /* ensure that no TB jump will be modified as |
| 426 | the program flow was changed */ |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 427 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 907a5b2 | 2003-06-30 23:18:22 +0000 | [diff] [blame] | 428 | tmp_T0 = 0; |
| 429 | #else |
| 430 | T0 = 0; |
| 431 | #endif |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 432 | #if !defined(CONFIG_USER_ONLY) |
| 433 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
| 434 | (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
| 435 | int intno; |
| 436 | /* FIXME: this should respect TPR */ |
| 437 | env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
ths | 5262168 | 2007-09-27 01:52:00 +0000 | [diff] [blame] | 438 | svm_check_intercept(SVM_EXIT_VINTR); |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 439 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
| 440 | if (loglevel & CPU_LOG_TB_IN_ASM) |
| 441 | fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno); |
| 442 | do_interrupt(intno, 0, 0, -1, 1); |
ths | 5262168 | 2007-09-27 01:52:00 +0000 | [diff] [blame] | 443 | stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), |
| 444 | ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK); |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 445 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
| 446 | tmp_T0 = 0; |
| 447 | #else |
| 448 | T0 = 0; |
| 449 | #endif |
| 450 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 451 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 452 | #elif defined(TARGET_PPC) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 453 | #if 0 |
| 454 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
| 455 | cpu_ppc_reset(env); |
| 456 | } |
| 457 | #endif |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 458 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 459 | ppc_hw_interrupt(env); |
| 460 | if (env->pending_interrupts == 0) |
| 461 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 462 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 463 | tmp_T0 = 0; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 464 | #else |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 465 | T0 = 0; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 466 | #endif |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 467 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 468 | #elif defined(TARGET_MIPS) |
| 469 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 470 | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 471 | (env->CP0_Status & (1 << CP0St_IE)) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 472 | !(env->CP0_Status & (1 << CP0St_EXL)) && |
| 473 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 474 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 475 | /* Raise it */ |
| 476 | env->exception_index = EXCP_EXT_INTERRUPT; |
| 477 | env->error_code = 0; |
| 478 | do_interrupt(env); |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 479 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 480 | tmp_T0 = 0; |
| 481 | #else |
| 482 | T0 = 0; |
| 483 | #endif |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 484 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 485 | #elif defined(TARGET_SPARC) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 486 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 487 | (env->psret != 0)) { |
| 488 | int pil = env->interrupt_index & 15; |
| 489 | int type = env->interrupt_index & 0xf0; |
| 490 | |
| 491 | if (((type == TT_EXTINT) && |
| 492 | (pil == 15 || pil > env->psrpil)) || |
| 493 | type != TT_EXTINT) { |
| 494 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 495 | do_interrupt(env->interrupt_index); |
| 496 | env->interrupt_index = 0; |
blueswir1 | 327ac2e | 2007-08-04 10:50:30 +0000 | [diff] [blame] | 497 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) |
| 498 | cpu_check_irqs(env); |
| 499 | #endif |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 500 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 501 | tmp_T0 = 0; |
| 502 | #else |
| 503 | T0 = 0; |
| 504 | #endif |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 505 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 506 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 507 | //do_interrupt(0, 0, 0, 0, 0); |
| 508 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 509 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 510 | #elif defined(TARGET_ARM) |
| 511 | if (interrupt_request & CPU_INTERRUPT_FIQ |
| 512 | && !(env->uncached_cpsr & CPSR_F)) { |
| 513 | env->exception_index = EXCP_FIQ; |
| 514 | do_interrupt(env); |
| 515 | } |
| 516 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 517 | && !(env->uncached_cpsr & CPSR_I)) { |
| 518 | env->exception_index = EXCP_IRQ; |
| 519 | do_interrupt(env); |
| 520 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 521 | #elif defined(TARGET_SH4) |
| 522 | /* XXXXX */ |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 523 | #elif defined(TARGET_ALPHA) |
| 524 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 525 | do_interrupt(env); |
| 526 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 527 | #elif defined(TARGET_CRIS) |
| 528 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 529 | do_interrupt(env); |
| 530 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 531 | } |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 532 | #elif defined(TARGET_M68K) |
| 533 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 534 | && ((env->sr & SR_I) >> SR_I_SHIFT) |
| 535 | < env->pending_level) { |
| 536 | /* Real hardware gets the interrupt vector via an |
| 537 | IACK cycle at this point. Current emulated |
| 538 | hardware doesn't rely on this, so we |
| 539 | provide/save the vector when the interrupt is |
| 540 | first signalled. */ |
| 541 | env->exception_index = env->pending_vector; |
| 542 | do_interrupt(1); |
| 543 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 544 | #endif |
bellard | 9d05095 | 2006-05-22 22:03:52 +0000 | [diff] [blame] | 545 | /* Don't use the cached interupt_request value, |
| 546 | do_interrupt may have updated the EXITTB flag. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 547 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 548 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
| 549 | /* ensure that no TB jump will be modified as |
| 550 | the program flow was changed */ |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 551 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 552 | tmp_T0 = 0; |
| 553 | #else |
| 554 | T0 = 0; |
| 555 | #endif |
| 556 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 557 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
| 558 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
| 559 | env->exception_index = EXCP_INTERRUPT; |
| 560 | cpu_loop_exit(); |
| 561 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 562 | } |
| 563 | #ifdef DEBUG_EXEC |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 564 | if ((loglevel & CPU_LOG_TB_CPU)) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 565 | /* restore flags in standard format */ |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 566 | regs_to_env(); |
| 567 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 568 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 569 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 570 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 571 | #elif defined(TARGET_ARM) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 572 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 573 | #elif defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 574 | REGWPTR = env->regbase + (env->cwp * 16); |
| 575 | env->regwptr = REGWPTR; |
| 576 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 577 | #elif defined(TARGET_PPC) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 578 | cpu_dump_state(env, logfile, fprintf, 0); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 579 | #elif defined(TARGET_M68K) |
| 580 | cpu_m68k_flush_flags(env, env->cc_op); |
| 581 | env->cc_op = CC_OP_FLAGS; |
| 582 | env->sr = (env->sr & 0xffe0) |
| 583 | | env->cc_dest | (env->cc_x << 4); |
| 584 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 585 | #elif defined(TARGET_MIPS) |
| 586 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 587 | #elif defined(TARGET_SH4) |
| 588 | cpu_dump_state(env, logfile, fprintf, 0); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 589 | #elif defined(TARGET_ALPHA) |
| 590 | cpu_dump_state(env, logfile, fprintf, 0); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 591 | #elif defined(TARGET_CRIS) |
| 592 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 593 | #else |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 594 | #error unsupported target CPU |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 595 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 596 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 597 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 598 | tb = tb_find_fast(); |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 599 | #ifdef DEBUG_EXEC |
bellard | c1135f6 | 2005-01-30 22:41:54 +0000 | [diff] [blame] | 600 | if ((loglevel & CPU_LOG_EXEC)) { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 601 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
| 602 | (long)tb->tc_ptr, tb->pc, |
| 603 | lookup_symbol(tb->pc)); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 604 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 605 | #endif |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 606 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 607 | T0 = tmp_T0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 608 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 609 | /* see if we can patch the calling TB. When the TB |
| 610 | spans two pages, we cannot safely do a direct |
| 611 | jump. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 612 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 613 | if (T0 != 0 && |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 614 | #if USE_KQEMU |
| 615 | (env->kqemu_enabled != 2) && |
| 616 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 617 | tb->page_addr[1] == -1 |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 618 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 619 | && (tb->cflags & CF_CODE_COPY) == |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 620 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) |
| 621 | #endif |
| 622 | ) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 623 | spin_lock(&tb_lock); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 624 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 625 | #if defined(USE_CODE_COPY) |
| 626 | /* propagates the FP use info */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 627 | ((TranslationBlock *)(T0 & ~3))->cflags |= |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 628 | (tb->cflags & CF_FP_USED); |
| 629 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 630 | spin_unlock(&tb_lock); |
| 631 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 632 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 633 | tc_ptr = tb->tc_ptr; |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 634 | env->current_tb = tb; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 635 | /* execute the generated code */ |
| 636 | gen_func = (void *)tc_ptr; |
| 637 | #if defined(__sparc__) |
| 638 | __asm__ __volatile__("call %0\n\t" |
| 639 | "mov %%o7,%%i0" |
| 640 | : /* no outputs */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 641 | : "r" (gen_func) |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 642 | : "i0", "i1", "i2", "i3", "i4", "i5", |
ths | faab759 | 2007-03-19 20:39:49 +0000 | [diff] [blame] | 643 | "o0", "o1", "o2", "o3", "o4", "o5", |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 644 | "l0", "l1", "l2", "l3", "l4", "l5", |
| 645 | "l6", "l7"); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 646 | #elif defined(__arm__) |
| 647 | asm volatile ("mov pc, %0\n\t" |
| 648 | ".global exec_loop\n\t" |
| 649 | "exec_loop:\n\t" |
| 650 | : /* no outputs */ |
| 651 | : "r" (gen_func) |
| 652 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 653 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 654 | { |
| 655 | if (!(tb->cflags & CF_CODE_COPY)) { |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 656 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
| 657 | save_native_fp_state(env); |
| 658 | } |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 659 | gen_func(); |
| 660 | } else { |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 661 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
| 662 | restore_native_fp_state(env); |
| 663 | } |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 664 | /* we work with native eflags */ |
| 665 | CC_SRC = cc_table[CC_OP].compute_all(); |
| 666 | CC_OP = CC_OP_EFLAGS; |
| 667 | asm(".globl exec_loop\n" |
| 668 | "\n" |
| 669 | "debug1:\n" |
| 670 | " pushl %%ebp\n" |
| 671 | " fs movl %10, %9\n" |
| 672 | " fs movl %11, %%eax\n" |
| 673 | " andl $0x400, %%eax\n" |
| 674 | " fs orl %8, %%eax\n" |
| 675 | " pushl %%eax\n" |
| 676 | " popf\n" |
| 677 | " fs movl %%esp, %12\n" |
| 678 | " fs movl %0, %%eax\n" |
| 679 | " fs movl %1, %%ecx\n" |
| 680 | " fs movl %2, %%edx\n" |
| 681 | " fs movl %3, %%ebx\n" |
| 682 | " fs movl %4, %%esp\n" |
| 683 | " fs movl %5, %%ebp\n" |
| 684 | " fs movl %6, %%esi\n" |
| 685 | " fs movl %7, %%edi\n" |
| 686 | " fs jmp *%9\n" |
| 687 | "exec_loop:\n" |
| 688 | " fs movl %%esp, %4\n" |
| 689 | " fs movl %12, %%esp\n" |
| 690 | " fs movl %%eax, %0\n" |
| 691 | " fs movl %%ecx, %1\n" |
| 692 | " fs movl %%edx, %2\n" |
| 693 | " fs movl %%ebx, %3\n" |
| 694 | " fs movl %%ebp, %5\n" |
| 695 | " fs movl %%esi, %6\n" |
| 696 | " fs movl %%edi, %7\n" |
| 697 | " pushf\n" |
| 698 | " popl %%eax\n" |
| 699 | " movl %%eax, %%ecx\n" |
| 700 | " andl $0x400, %%ecx\n" |
| 701 | " shrl $9, %%ecx\n" |
| 702 | " andl $0x8d5, %%eax\n" |
| 703 | " fs movl %%eax, %8\n" |
| 704 | " movl $1, %%eax\n" |
| 705 | " subl %%ecx, %%eax\n" |
| 706 | " fs movl %%eax, %11\n" |
| 707 | " fs movl %9, %%ebx\n" /* get T0 value */ |
| 708 | " popl %%ebp\n" |
| 709 | : |
| 710 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
| 711 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
| 712 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
| 713 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
| 714 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
| 715 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
| 716 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
| 717 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
| 718 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), |
| 719 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), |
| 720 | "a" (gen_func), |
| 721 | "m" (*(uint8_t *)offsetof(CPUState, df)), |
| 722 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) |
| 723 | : "%ecx", "%edx" |
| 724 | ); |
| 725 | } |
| 726 | } |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 727 | #elif defined(__ia64) |
| 728 | struct fptr { |
| 729 | void *ip; |
| 730 | void *gp; |
| 731 | } fp; |
| 732 | |
| 733 | fp.ip = tc_ptr; |
| 734 | fp.gp = code_gen_buffer + 2 * (1 << 20); |
| 735 | (*(void (*)(void)) &fp)(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 736 | #else |
| 737 | gen_func(); |
| 738 | #endif |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 739 | env->current_tb = NULL; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 740 | /* reset soft MMU for next block (it can currently |
| 741 | only be set by a memory fault) */ |
| 742 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 743 | if (env->hflags & HF_SOFTMMU_MASK) { |
| 744 | env->hflags &= ~HF_SOFTMMU_MASK; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 745 | /* do not allow linking to another block */ |
| 746 | T0 = 0; |
| 747 | } |
| 748 | #endif |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 749 | #if defined(USE_KQEMU) |
| 750 | #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) |
| 751 | if (kqemu_is_ok(env) && |
| 752 | (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { |
| 753 | cpu_loop_exit(); |
| 754 | } |
| 755 | #endif |
ths | 50a518e | 2007-06-03 18:52:15 +0000 | [diff] [blame] | 756 | } /* for(;;) */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 757 | } else { |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 758 | env_to_regs(); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 759 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 760 | } /* for(;;) */ |
| 761 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 762 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 763 | #if defined(TARGET_I386) |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 764 | #if defined(USE_CODE_COPY) |
| 765 | if (env->native_fp_regs) { |
| 766 | save_native_fp_state(env); |
| 767 | } |
| 768 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 769 | /* restore flags in standard format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 770 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 771 | #elif defined(TARGET_ARM) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 772 | /* XXX: Save/restore host fpu exception state?. */ |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 773 | #elif defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 774 | #if defined(reg_REGWPTR) |
| 775 | REGWPTR = saved_regwptr; |
| 776 | #endif |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 777 | #elif defined(TARGET_PPC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 778 | #elif defined(TARGET_M68K) |
| 779 | cpu_m68k_flush_flags(env, env->cc_op); |
| 780 | env->cc_op = CC_OP_FLAGS; |
| 781 | env->sr = (env->sr & 0xffe0) |
| 782 | | env->cc_dest | (env->cc_x << 4); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 783 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 784 | #elif defined(TARGET_SH4) |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 785 | #elif defined(TARGET_ALPHA) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 786 | #elif defined(TARGET_CRIS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 787 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 788 | #else |
| 789 | #error unsupported target CPU |
| 790 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 791 | |
| 792 | /* restore global registers */ |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 793 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 794 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
| 795 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 796 | #include "hostregs_helper.h" |
| 797 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 798 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 799 | cpu_single_env = NULL; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 800 | return ret; |
| 801 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 802 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 803 | /* must only be called from the generated code as an exception can be |
| 804 | generated */ |
| 805 | void tb_invalidate_page_range(target_ulong start, target_ulong end) |
| 806 | { |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 807 | /* XXX: cannot enable it yet because it yields to MMU exception |
| 808 | where NIP != read address on PowerPC */ |
| 809 | #if 0 |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 810 | target_ulong phys_addr; |
| 811 | phys_addr = get_phys_addr_code(env, start); |
| 812 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 813 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 814 | } |
| 815 | |
bellard | 1a18c71 | 2003-10-30 01:07:51 +0000 | [diff] [blame] | 816 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 817 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 818 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 819 | { |
| 820 | CPUX86State *saved_env; |
| 821 | |
| 822 | saved_env = env; |
| 823 | env = s; |
bellard | a412ac5 | 2003-07-26 18:01:40 +0000 | [diff] [blame] | 824 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 825 | selector &= 0xffff; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 826 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 827 | (selector << 4), 0xffff, 0); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 828 | } else { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 829 | load_seg(seg_reg, selector); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 830 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 831 | env = saved_env; |
| 832 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 833 | |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 834 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
| 835 | { |
| 836 | CPUX86State *saved_env; |
| 837 | |
| 838 | saved_env = env; |
| 839 | env = s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 840 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 841 | helper_fsave((target_ulong)ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 842 | |
| 843 | env = saved_env; |
| 844 | } |
| 845 | |
| 846 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
| 847 | { |
| 848 | CPUX86State *saved_env; |
| 849 | |
| 850 | saved_env = env; |
| 851 | env = s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 852 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 853 | helper_frstor((target_ulong)ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 854 | |
| 855 | env = saved_env; |
| 856 | } |
| 857 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 858 | #endif /* TARGET_I386 */ |
| 859 | |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 860 | #if !defined(CONFIG_SOFTMMU) |
| 861 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 862 | #if defined(TARGET_I386) |
| 863 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 864 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 865 | the effective address of the memory exception. 'is_write' is 1 if a |
| 866 | write caused the exception and otherwise 0'. 'old_set' is the |
| 867 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 868 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 869 | int is_write, sigset_t *old_set, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 870 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 871 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 872 | TranslationBlock *tb; |
| 873 | int ret; |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 874 | |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 875 | if (cpu_single_env) |
| 876 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 877 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 878 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 879 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 880 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 881 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 882 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 883 | return 1; |
| 884 | } |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 885 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 886 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 887 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 888 | if (ret < 0) |
| 889 | return 0; /* not an MMU fault */ |
| 890 | if (ret == 0) |
| 891 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 892 | /* now we have a real cpu fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 893 | tb = tb_find_pc(pc); |
| 894 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 895 | /* the PC is inside the translated code. It means that we have |
| 896 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 897 | cpu_restore_state(tb, env, pc, puc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 898 | } |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 899 | if (ret == 1) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 900 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 901 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 902 | env->eip, env->cr[2], env->error_code); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 903 | #endif |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 904 | /* we restore the process signal mask as the sigreturn should |
| 905 | do it (XXX: use sigsetjmp) */ |
| 906 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | 54ca909 | 2005-12-04 18:46:06 +0000 | [diff] [blame] | 907 | raise_exception_err(env->exception_index, env->error_code); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 908 | } else { |
| 909 | /* activate soft MMU for this block */ |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 910 | env->hflags |= HF_SOFTMMU_MASK; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 911 | cpu_resume_from_signal(env, puc); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 912 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 913 | /* never comes here */ |
| 914 | return 1; |
| 915 | } |
| 916 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 917 | #elif defined(TARGET_ARM) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 918 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 919 | int is_write, sigset_t *old_set, |
| 920 | void *puc) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 921 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 922 | TranslationBlock *tb; |
| 923 | int ret; |
| 924 | |
| 925 | if (cpu_single_env) |
| 926 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 927 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 928 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 929 | pc, address, is_write, *(unsigned long *)old_set); |
| 930 | #endif |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 931 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 932 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 933 | return 1; |
| 934 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 935 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 936 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 937 | if (ret < 0) |
| 938 | return 0; /* not an MMU fault */ |
| 939 | if (ret == 0) |
| 940 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 941 | /* now we have a real cpu fault */ |
| 942 | tb = tb_find_pc(pc); |
| 943 | if (tb) { |
| 944 | /* the PC is inside the translated code. It means that we have |
| 945 | a virtual CPU fault */ |
| 946 | cpu_restore_state(tb, env, pc, puc); |
| 947 | } |
| 948 | /* we restore the process signal mask as the sigreturn should |
| 949 | do it (XXX: use sigsetjmp) */ |
| 950 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 951 | cpu_loop_exit(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 952 | } |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 953 | #elif defined(TARGET_SPARC) |
| 954 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 955 | int is_write, sigset_t *old_set, |
| 956 | void *puc) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 957 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 958 | TranslationBlock *tb; |
| 959 | int ret; |
| 960 | |
| 961 | if (cpu_single_env) |
| 962 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 963 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 964 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 965 | pc, address, is_write, *(unsigned long *)old_set); |
| 966 | #endif |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 967 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 968 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 969 | return 1; |
| 970 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 971 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 972 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 973 | if (ret < 0) |
| 974 | return 0; /* not an MMU fault */ |
| 975 | if (ret == 0) |
| 976 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 977 | /* now we have a real cpu fault */ |
| 978 | tb = tb_find_pc(pc); |
| 979 | if (tb) { |
| 980 | /* the PC is inside the translated code. It means that we have |
| 981 | a virtual CPU fault */ |
| 982 | cpu_restore_state(tb, env, pc, puc); |
| 983 | } |
| 984 | /* we restore the process signal mask as the sigreturn should |
| 985 | do it (XXX: use sigsetjmp) */ |
| 986 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 987 | cpu_loop_exit(); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 988 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 989 | #elif defined (TARGET_PPC) |
| 990 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 991 | int is_write, sigset_t *old_set, |
| 992 | void *puc) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 993 | { |
| 994 | TranslationBlock *tb; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 995 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 996 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 997 | if (cpu_single_env) |
| 998 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 999 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1000 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1001 | pc, address, is_write, *(unsigned long *)old_set); |
| 1002 | #endif |
| 1003 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1004 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1005 | return 1; |
| 1006 | } |
| 1007 | |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1008 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1009 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1010 | if (ret < 0) |
| 1011 | return 0; /* not an MMU fault */ |
| 1012 | if (ret == 0) |
| 1013 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1014 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1015 | /* now we have a real cpu fault */ |
| 1016 | tb = tb_find_pc(pc); |
| 1017 | if (tb) { |
| 1018 | /* the PC is inside the translated code. It means that we have |
| 1019 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1020 | cpu_restore_state(tb, env, pc, puc); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1021 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1022 | if (ret == 1) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1023 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1024 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1025 | env->nip, env->error_code, tb); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1026 | #endif |
| 1027 | /* we restore the process signal mask as the sigreturn should |
| 1028 | do it (XXX: use sigsetjmp) */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1029 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1030 | do_raise_exception_err(env->exception_index, env->error_code); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1031 | } else { |
| 1032 | /* activate soft MMU for this block */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 1033 | cpu_resume_from_signal(env, puc); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1034 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1035 | /* never comes here */ |
| 1036 | return 1; |
| 1037 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1038 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 1039 | #elif defined(TARGET_M68K) |
| 1040 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1041 | int is_write, sigset_t *old_set, |
| 1042 | void *puc) |
| 1043 | { |
| 1044 | TranslationBlock *tb; |
| 1045 | int ret; |
| 1046 | |
| 1047 | if (cpu_single_env) |
| 1048 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1049 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1050 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 1051 | pc, address, is_write, *(unsigned long *)old_set); |
| 1052 | #endif |
| 1053 | /* XXX: locking issue */ |
| 1054 | if (is_write && page_unprotect(address, pc, puc)) { |
| 1055 | return 1; |
| 1056 | } |
| 1057 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1058 | ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 1059 | if (ret < 0) |
| 1060 | return 0; /* not an MMU fault */ |
| 1061 | if (ret == 0) |
| 1062 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1063 | /* now we have a real cpu fault */ |
| 1064 | tb = tb_find_pc(pc); |
| 1065 | if (tb) { |
| 1066 | /* the PC is inside the translated code. It means that we have |
| 1067 | a virtual CPU fault */ |
| 1068 | cpu_restore_state(tb, env, pc, puc); |
| 1069 | } |
| 1070 | /* we restore the process signal mask as the sigreturn should |
| 1071 | do it (XXX: use sigsetjmp) */ |
| 1072 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1073 | cpu_loop_exit(); |
| 1074 | /* never comes here */ |
| 1075 | return 1; |
| 1076 | } |
| 1077 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1078 | #elif defined (TARGET_MIPS) |
| 1079 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1080 | int is_write, sigset_t *old_set, |
| 1081 | void *puc) |
| 1082 | { |
| 1083 | TranslationBlock *tb; |
| 1084 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1085 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1086 | if (cpu_single_env) |
| 1087 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1088 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1089 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1090 | pc, address, is_write, *(unsigned long *)old_set); |
| 1091 | #endif |
| 1092 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1093 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1094 | return 1; |
| 1095 | } |
| 1096 | |
| 1097 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1098 | ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1099 | if (ret < 0) |
| 1100 | return 0; /* not an MMU fault */ |
| 1101 | if (ret == 0) |
| 1102 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1103 | |
| 1104 | /* now we have a real cpu fault */ |
| 1105 | tb = tb_find_pc(pc); |
| 1106 | if (tb) { |
| 1107 | /* the PC is inside the translated code. It means that we have |
| 1108 | a virtual CPU fault */ |
| 1109 | cpu_restore_state(tb, env, pc, puc); |
| 1110 | } |
| 1111 | if (ret == 1) { |
| 1112 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1113 | printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n", |
ths | 1eb5207 | 2007-05-12 16:57:42 +0000 | [diff] [blame] | 1114 | env->PC, env->error_code, tb); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1115 | #endif |
| 1116 | /* we restore the process signal mask as the sigreturn should |
| 1117 | do it (XXX: use sigsetjmp) */ |
| 1118 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1119 | do_raise_exception_err(env->exception_index, env->error_code); |
| 1120 | } else { |
| 1121 | /* activate soft MMU for this block */ |
| 1122 | cpu_resume_from_signal(env, puc); |
| 1123 | } |
| 1124 | /* never comes here */ |
| 1125 | return 1; |
| 1126 | } |
| 1127 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1128 | #elif defined (TARGET_SH4) |
| 1129 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1130 | int is_write, sigset_t *old_set, |
| 1131 | void *puc) |
| 1132 | { |
| 1133 | TranslationBlock *tb; |
| 1134 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1135 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1136 | if (cpu_single_env) |
| 1137 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1138 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1139 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1140 | pc, address, is_write, *(unsigned long *)old_set); |
| 1141 | #endif |
| 1142 | /* XXX: locking issue */ |
| 1143 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1144 | return 1; |
| 1145 | } |
| 1146 | |
| 1147 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1148 | ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1149 | if (ret < 0) |
| 1150 | return 0; /* not an MMU fault */ |
| 1151 | if (ret == 0) |
| 1152 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1153 | |
| 1154 | /* now we have a real cpu fault */ |
| 1155 | tb = tb_find_pc(pc); |
| 1156 | if (tb) { |
| 1157 | /* the PC is inside the translated code. It means that we have |
| 1158 | a virtual CPU fault */ |
| 1159 | cpu_restore_state(tb, env, pc, puc); |
| 1160 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1161 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1162 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1163 | env->nip, env->error_code, tb); |
| 1164 | #endif |
| 1165 | /* we restore the process signal mask as the sigreturn should |
| 1166 | do it (XXX: use sigsetjmp) */ |
pbrook | 355fb23 | 2006-06-17 19:58:25 +0000 | [diff] [blame] | 1167 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1168 | cpu_loop_exit(); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1169 | /* never comes here */ |
| 1170 | return 1; |
| 1171 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1172 | |
| 1173 | #elif defined (TARGET_ALPHA) |
| 1174 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1175 | int is_write, sigset_t *old_set, |
| 1176 | void *puc) |
| 1177 | { |
| 1178 | TranslationBlock *tb; |
| 1179 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1180 | |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1181 | if (cpu_single_env) |
| 1182 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1183 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1184 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1185 | pc, address, is_write, *(unsigned long *)old_set); |
| 1186 | #endif |
| 1187 | /* XXX: locking issue */ |
| 1188 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1189 | return 1; |
| 1190 | } |
| 1191 | |
| 1192 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1193 | ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1194 | if (ret < 0) |
| 1195 | return 0; /* not an MMU fault */ |
| 1196 | if (ret == 0) |
| 1197 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1198 | |
| 1199 | /* now we have a real cpu fault */ |
| 1200 | tb = tb_find_pc(pc); |
| 1201 | if (tb) { |
| 1202 | /* the PC is inside the translated code. It means that we have |
| 1203 | a virtual CPU fault */ |
| 1204 | cpu_restore_state(tb, env, pc, puc); |
| 1205 | } |
| 1206 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1207 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1208 | env->nip, env->error_code, tb); |
| 1209 | #endif |
| 1210 | /* we restore the process signal mask as the sigreturn should |
| 1211 | do it (XXX: use sigsetjmp) */ |
| 1212 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1213 | cpu_loop_exit(); |
| 1214 | /* never comes here */ |
| 1215 | return 1; |
| 1216 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 1217 | #elif defined (TARGET_CRIS) |
| 1218 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1219 | int is_write, sigset_t *old_set, |
| 1220 | void *puc) |
| 1221 | { |
| 1222 | TranslationBlock *tb; |
| 1223 | int ret; |
| 1224 | |
| 1225 | if (cpu_single_env) |
| 1226 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1227 | #if defined(DEBUG_SIGNAL) |
| 1228 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1229 | pc, address, is_write, *(unsigned long *)old_set); |
| 1230 | #endif |
| 1231 | /* XXX: locking issue */ |
| 1232 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1233 | return 1; |
| 1234 | } |
| 1235 | |
| 1236 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1237 | ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 1238 | if (ret < 0) |
| 1239 | return 0; /* not an MMU fault */ |
| 1240 | if (ret == 0) |
| 1241 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1242 | |
| 1243 | /* now we have a real cpu fault */ |
| 1244 | tb = tb_find_pc(pc); |
| 1245 | if (tb) { |
| 1246 | /* the PC is inside the translated code. It means that we have |
| 1247 | a virtual CPU fault */ |
| 1248 | cpu_restore_state(tb, env, pc, puc); |
| 1249 | } |
| 1250 | #if 0 |
| 1251 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
| 1252 | env->nip, env->error_code, tb); |
| 1253 | #endif |
| 1254 | /* we restore the process signal mask as the sigreturn should |
| 1255 | do it (XXX: use sigsetjmp) */ |
| 1256 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1257 | cpu_loop_exit(); |
| 1258 | /* never comes here */ |
| 1259 | return 1; |
| 1260 | } |
| 1261 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1262 | #else |
| 1263 | #error unsupported target CPU |
| 1264 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1265 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1266 | #if defined(__i386__) |
| 1267 | |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1268 | #if defined(__APPLE__) |
| 1269 | # include <sys/ucontext.h> |
| 1270 | |
| 1271 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) |
| 1272 | # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) |
| 1273 | # define ERROR_sig(context) ((context)->uc_mcontext->es.err) |
| 1274 | #else |
| 1275 | # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) |
| 1276 | # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
| 1277 | # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
| 1278 | #endif |
| 1279 | |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1280 | #if defined(USE_CODE_COPY) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1281 | static void cpu_send_trap(unsigned long pc, int trap, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1282 | struct ucontext *uc) |
| 1283 | { |
| 1284 | TranslationBlock *tb; |
| 1285 | |
| 1286 | if (cpu_single_env) |
| 1287 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1288 | /* now we have a real cpu fault */ |
| 1289 | tb = tb_find_pc(pc); |
| 1290 | if (tb) { |
| 1291 | /* the PC is inside the translated code. It means that we have |
| 1292 | a virtual CPU fault */ |
| 1293 | cpu_restore_state(tb, env, pc, uc); |
| 1294 | } |
| 1295 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
| 1296 | raise_exception_err(trap, env->error_code); |
| 1297 | } |
| 1298 | #endif |
| 1299 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1300 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1301 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1302 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1303 | siginfo_t *info = pinfo; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1304 | struct ucontext *uc = puc; |
| 1305 | unsigned long pc; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1306 | int trapno; |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 1307 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 1308 | #ifndef REG_EIP |
| 1309 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1310 | #define REG_EIP EIP |
| 1311 | #define REG_ERR ERR |
| 1312 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 1313 | #endif |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1314 | pc = EIP_sig(uc); |
| 1315 | trapno = TRAP_sig(uc); |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1316 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 1317 | if (trapno == 0x00 || trapno == 0x05) { |
| 1318 | /* send division by zero or bound exception */ |
| 1319 | cpu_send_trap(pc, trapno, uc); |
| 1320 | return 1; |
| 1321 | } else |
| 1322 | #endif |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1323 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1324 | trapno == 0xe ? |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1325 | (ERROR_sig(uc) >> 1) & 1 : 0, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1326 | &uc->uc_sigmask, puc); |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1327 | } |
| 1328 | |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1329 | #elif defined(__x86_64__) |
| 1330 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1331 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1332 | void *puc) |
| 1333 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1334 | siginfo_t *info = pinfo; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1335 | struct ucontext *uc = puc; |
| 1336 | unsigned long pc; |
| 1337 | |
| 1338 | pc = uc->uc_mcontext.gregs[REG_RIP]; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1339 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1340 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1341 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
| 1342 | &uc->uc_sigmask, puc); |
| 1343 | } |
| 1344 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1345 | #elif defined(__powerpc__) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1346 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1347 | /*********************************************************************** |
| 1348 | * signal context platform-specific definitions |
| 1349 | * From Wine |
| 1350 | */ |
| 1351 | #ifdef linux |
| 1352 | /* All Registers access - only for local access */ |
| 1353 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) |
| 1354 | /* Gpr Registers access */ |
| 1355 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) |
| 1356 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
| 1357 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
| 1358 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
| 1359 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
| 1360 | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
| 1361 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
| 1362 | /* Float Registers access */ |
| 1363 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
| 1364 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
| 1365 | /* Exception Registers access */ |
| 1366 | # define DAR_sig(context) REG_sig(dar, context) |
| 1367 | # define DSISR_sig(context) REG_sig(dsisr, context) |
| 1368 | # define TRAP_sig(context) REG_sig(trap, context) |
| 1369 | #endif /* linux */ |
| 1370 | |
| 1371 | #ifdef __APPLE__ |
| 1372 | # include <sys/ucontext.h> |
| 1373 | typedef struct ucontext SIGCONTEXT; |
| 1374 | /* All Registers access - only for local access */ |
| 1375 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) |
| 1376 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) |
| 1377 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) |
| 1378 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) |
| 1379 | /* Gpr Registers access */ |
| 1380 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
| 1381 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
| 1382 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
| 1383 | # define CTR_sig(context) REG_sig(ctr, context) |
| 1384 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
| 1385 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
| 1386 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
| 1387 | /* Float Registers access */ |
| 1388 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) |
| 1389 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
| 1390 | /* Exception Registers access */ |
| 1391 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
| 1392 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) |
| 1393 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
| 1394 | #endif /* __APPLE__ */ |
| 1395 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1396 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1397 | void *puc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1398 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1399 | siginfo_t *info = pinfo; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1400 | struct ucontext *uc = puc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1401 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1402 | int is_write; |
| 1403 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1404 | pc = IAR_sig(uc); |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1405 | is_write = 0; |
| 1406 | #if 0 |
| 1407 | /* ppc 4xx case */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1408 | if (DSISR_sig(uc) & 0x00800000) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1409 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1410 | #else |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1411 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1412 | is_write = 1; |
| 1413 | #endif |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1414 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1415 | is_write, &uc->uc_sigmask, puc); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1416 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1417 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1418 | #elif defined(__alpha__) |
| 1419 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1420 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1421 | void *puc) |
| 1422 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1423 | siginfo_t *info = pinfo; |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1424 | struct ucontext *uc = puc; |
| 1425 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 1426 | uint32_t insn = *pc; |
| 1427 | int is_write = 0; |
| 1428 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1429 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1430 | switch (insn >> 26) { |
| 1431 | case 0x0d: // stw |
| 1432 | case 0x0e: // stb |
| 1433 | case 0x0f: // stq_u |
| 1434 | case 0x24: // stf |
| 1435 | case 0x25: // stg |
| 1436 | case 0x26: // sts |
| 1437 | case 0x27: // stt |
| 1438 | case 0x2c: // stl |
| 1439 | case 0x2d: // stq |
| 1440 | case 0x2e: // stl_c |
| 1441 | case 0x2f: // stq_c |
| 1442 | is_write = 1; |
| 1443 | } |
| 1444 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1445 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1446 | is_write, &uc->uc_sigmask, puc); |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1447 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1448 | #elif defined(__sparc__) |
| 1449 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1450 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1451 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1452 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1453 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1454 | uint32_t *regs = (uint32_t *)(info + 1); |
| 1455 | void *sigmask = (regs + 20); |
| 1456 | unsigned long pc; |
| 1457 | int is_write; |
| 1458 | uint32_t insn; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1459 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1460 | /* XXX: is there a standard glibc define ? */ |
| 1461 | pc = regs[1]; |
| 1462 | /* XXX: need kernel patch to get write flag faster */ |
| 1463 | is_write = 0; |
| 1464 | insn = *(uint32_t *)pc; |
| 1465 | if ((insn >> 30) == 3) { |
| 1466 | switch((insn >> 19) & 0x3f) { |
| 1467 | case 0x05: // stb |
| 1468 | case 0x06: // sth |
| 1469 | case 0x04: // st |
| 1470 | case 0x07: // std |
| 1471 | case 0x24: // stf |
| 1472 | case 0x27: // stdf |
| 1473 | case 0x25: // stfsr |
| 1474 | is_write = 1; |
| 1475 | break; |
| 1476 | } |
| 1477 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1478 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1479 | is_write, sigmask, NULL); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1480 | } |
| 1481 | |
| 1482 | #elif defined(__arm__) |
| 1483 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1484 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1485 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1486 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1487 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1488 | struct ucontext *uc = puc; |
| 1489 | unsigned long pc; |
| 1490 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1491 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1492 | pc = uc->uc_mcontext.gregs[R15]; |
| 1493 | /* XXX: compute is_write */ |
| 1494 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1495 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1496 | is_write, |
pbrook | f3a9676 | 2006-07-29 19:09:31 +0000 | [diff] [blame] | 1497 | &uc->uc_sigmask, puc); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1498 | } |
| 1499 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1500 | #elif defined(__mc68000) |
| 1501 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1502 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1503 | void *puc) |
| 1504 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1505 | siginfo_t *info = pinfo; |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1506 | struct ucontext *uc = puc; |
| 1507 | unsigned long pc; |
| 1508 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1509 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1510 | pc = uc->uc_mcontext.gregs[16]; |
| 1511 | /* XXX: compute is_write */ |
| 1512 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1513 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1514 | is_write, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1515 | &uc->uc_sigmask, puc); |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1516 | } |
| 1517 | |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1518 | #elif defined(__ia64) |
| 1519 | |
| 1520 | #ifndef __ISR_VALID |
| 1521 | /* This ought to be in <bits/siginfo.h>... */ |
| 1522 | # define __ISR_VALID 1 |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1523 | #endif |
| 1524 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1525 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1526 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1527 | siginfo_t *info = pinfo; |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1528 | struct ucontext *uc = puc; |
| 1529 | unsigned long ip; |
| 1530 | int is_write = 0; |
| 1531 | |
| 1532 | ip = uc->uc_mcontext.sc_ip; |
| 1533 | switch (host_signum) { |
| 1534 | case SIGILL: |
| 1535 | case SIGFPE: |
| 1536 | case SIGSEGV: |
| 1537 | case SIGBUS: |
| 1538 | case SIGTRAP: |
bellard | fd4a43e | 2006-04-24 20:32:17 +0000 | [diff] [blame] | 1539 | if (info->si_code && (info->si_segvflags & __ISR_VALID)) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1540 | /* ISR.W (write-access) is bit 33: */ |
| 1541 | is_write = (info->si_isr >> 33) & 1; |
| 1542 | break; |
| 1543 | |
| 1544 | default: |
| 1545 | break; |
| 1546 | } |
| 1547 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 1548 | is_write, |
| 1549 | &uc->uc_sigmask, puc); |
| 1550 | } |
| 1551 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1552 | #elif defined(__s390__) |
| 1553 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1554 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1555 | void *puc) |
| 1556 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1557 | siginfo_t *info = pinfo; |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1558 | struct ucontext *uc = puc; |
| 1559 | unsigned long pc; |
| 1560 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1561 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1562 | pc = uc->uc_mcontext.psw.addr; |
| 1563 | /* XXX: compute is_write */ |
| 1564 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1565 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1566 | is_write, &uc->uc_sigmask, puc); |
| 1567 | } |
| 1568 | |
| 1569 | #elif defined(__mips__) |
| 1570 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1571 | int cpu_signal_handler(int host_signum, void *pinfo, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1572 | void *puc) |
| 1573 | { |
ths | 9617efe | 2007-05-08 21:05:55 +0000 | [diff] [blame] | 1574 | siginfo_t *info = pinfo; |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1575 | struct ucontext *uc = puc; |
| 1576 | greg_t pc = uc->uc_mcontext.pc; |
| 1577 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1578 | |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1579 | /* XXX: compute is_write */ |
| 1580 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1581 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1582 | is_write, &uc->uc_sigmask, puc); |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1583 | } |
| 1584 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1585 | #else |
| 1586 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 1587 | #error host CPU specific signal handler needed |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1588 | |
| 1589 | #endif |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 1590 | |
| 1591 | #endif /* !defined(CONFIG_SOFTMMU) */ |