commit c4b89d18ba3b494545266970fe8714bc3d7f5917
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Sat May 05 19:23:11 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Sat May 05 19:23:11 2007 +0000
tree 85543844ae6a8c7f7e7b3dd73d804a9c8161c835
parent 26ea091859c76d5e1b8a95148aa60b59dc8ee196

Some bits of Linux/MIPS host support, still segfaulty.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2771 c046a42c-6fe2-441c-8c8c-71466251a162

cpu-exec.c

diff --git a/cpu-exec.c b/cpu-exec.c
index 4777bab..cd74412 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -1540,8 +1540,22 @@
     /* XXX: compute is_write */
     is_write = 0;
     return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
-                             is_write,
-                             &uc->uc_sigmask, puc);
+                             is_write, &uc->uc_sigmask, puc);
+}
+
+#elif defined(__mips__)
+
+int cpu_signal_handler(int host_signum, struct siginfo *info, 
+                       void *puc)
+{
+    struct ucontext *uc = puc;
+    greg_t pc = uc->uc_mcontext.pc;
+    int is_write;
+    
+    /* XXX: compute is_write */
+    is_write = 0;
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+                             is_write, &uc->uc_sigmask, puc);
 }
 
 #else