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bellard79aceca2003-11-23 14:55:54 +00001/*
bellard3fc6c082005-07-02 20:59:34 +00002 * PowerPC emulation cpu definitions for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer76a66252007-03-07 08:32:30 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
bellard79aceca2003-11-23 14:55:54 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard79aceca2003-11-23 14:55:54 +000018 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
bellard3fc6c082005-07-02 20:59:34 +000022#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020023#include "qemu-common.h"
bellard3fc6c082005-07-02 20:59:34 +000024
j_mayera4f30712007-11-17 21:14:09 +000025//#define PPC_EMULATE_32BITS_HYPV
26
j_mayer76a66252007-03-07 08:32:30 +000027#if defined (TARGET_PPC64)
j_mayer3cd7d1d2007-11-12 01:56:18 +000028/* PowerPC 64 definitions */
j_mayerd9d72102007-09-18 11:17:30 +000029#define TARGET_LONG_BITS 64
j_mayer35cdaad2007-04-24 06:50:21 +000030#define TARGET_PAGE_BITS 12
j_mayer3cd7d1d2007-11-12 01:56:18 +000031
Richard Henderson52705892010-03-10 14:33:23 -080032/* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35#define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37/* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40#ifdef TARGET_ABI32
41# define TARGET_VIRT_ADDR_SPACE_BITS 32
42#else
43# define TARGET_VIRT_ADDR_SPACE_BITS 64
44#endif
45
David Gibson81762d62011-04-01 15:15:08 +110046#define TARGET_PAGE_BITS_16M 24
47
j_mayer3cd7d1d2007-11-12 01:56:18 +000048#else /* defined (TARGET_PPC64) */
49/* PowerPC 32 definitions */
j_mayerd9d72102007-09-18 11:17:30 +000050#define TARGET_LONG_BITS 32
j_mayer3cd7d1d2007-11-12 01:56:18 +000051
52#if defined(TARGET_PPCEMB)
53/* Specific definitions for PowerPC embedded */
54/* BookE have 36 bits physical address space */
j_mayer3cd7d1d2007-11-12 01:56:18 +000055#if defined(CONFIG_USER_ONLY)
56/* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
j_mayer35cdaad2007-04-24 06:50:21 +000059#define TARGET_PAGE_BITS 12
j_mayer3cd7d1d2007-11-12 01:56:18 +000060#else /* defined(CONFIG_USER_ONLY) */
61/* Pages can be 1 kB small */
62#define TARGET_PAGE_BITS 10
63#endif /* defined(CONFIG_USER_ONLY) */
64#else /* defined(TARGET_PPCEMB) */
65/* "standard" PowerPC 32 definitions */
66#define TARGET_PAGE_BITS 12
67#endif /* defined(TARGET_PPCEMB) */
68
Alexander Graf8b242eb2011-10-18 01:46:08 +020069#define TARGET_PHYS_ADDR_SPACE_BITS 36
Richard Henderson52705892010-03-10 14:33:23 -080070#define TARGET_VIRT_ADDR_SPACE_BITS 32
71
j_mayer3cd7d1d2007-11-12 01:56:18 +000072#endif /* defined (TARGET_PPC64) */
bellard3cf1e032004-01-24 15:19:09 +000073
pbrookc2764712009-03-07 15:24:59 +000074#define CPUState struct CPUPPCState
75
bellard79aceca2003-11-23 14:55:54 +000076#include "cpu-defs.h"
77
bellard4ecc3192005-03-13 17:01:22 +000078#include "softfloat.h"
79
bellard1fddef42005-04-17 19:16:13 +000080#define TARGET_HAS_ICE 1
81
blueswir17f70c932009-03-13 21:16:24 +000082#if defined (TARGET_PPC64)
j_mayer76a66252007-03-07 08:32:30 +000083#define ELF_MACHINE EM_PPC64
84#else
85#define ELF_MACHINE EM_PPC
86#endif
ths9042c0e2006-12-23 14:18:40 +000087
bellard3fc6c082005-07-02 20:59:34 +000088/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +000089/* MMU model */
Anthony Liguoric227f092009-10-01 16:12:16 -050090typedef enum powerpc_mmu_t powerpc_mmu_t;
91enum powerpc_mmu_t {
j_mayeradd78952007-11-19 11:41:10 +000092 POWERPC_MMU_UNKNOWN = 0x00000000,
j_mayera750fc02007-09-26 23:54:22 +000093 /* Standard 32 bits PowerPC MMU */
j_mayeradd78952007-11-19 11:41:10 +000094 POWERPC_MMU_32B = 0x00000001,
j_mayera750fc02007-09-26 23:54:22 +000095 /* PowerPC 6xx MMU with software TLB */
j_mayeradd78952007-11-19 11:41:10 +000096 POWERPC_MMU_SOFT_6xx = 0x00000002,
j_mayera750fc02007-09-26 23:54:22 +000097 /* PowerPC 74xx MMU with software TLB */
j_mayeradd78952007-11-19 11:41:10 +000098 POWERPC_MMU_SOFT_74xx = 0x00000003,
j_mayera750fc02007-09-26 23:54:22 +000099 /* PowerPC 4xx MMU with software TLB */
j_mayeradd78952007-11-19 11:41:10 +0000100 POWERPC_MMU_SOFT_4xx = 0x00000004,
j_mayera750fc02007-09-26 23:54:22 +0000101 /* PowerPC 4xx MMU with software TLB and zones protections */
j_mayeradd78952007-11-19 11:41:10 +0000102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
j_mayerb4095fe2007-11-17 22:42:36 +0000103 /* PowerPC MMU in real mode only */
j_mayeradd78952007-11-19 11:41:10 +0000104 POWERPC_MMU_REAL = 0x00000006,
j_mayerb4095fe2007-11-17 22:42:36 +0000105 /* Freescale MPC8xx MMU model */
j_mayeradd78952007-11-19 11:41:10 +0000106 POWERPC_MMU_MPC8xx = 0x00000007,
j_mayera750fc02007-09-26 23:54:22 +0000107 /* BookE MMU model */
j_mayeradd78952007-11-19 11:41:10 +0000108 POWERPC_MMU_BOOKE = 0x00000008,
Alexander Graf01662f32011-04-30 23:34:58 +0200109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
j_mayerfaadf502007-11-03 13:37:12 +0000111 /* PowerPC 601 MMU model (specific BATs format) */
j_mayeradd78952007-11-19 11:41:10 +0000112 POWERPC_MMU_601 = 0x0000000A,
j_mayer00af6852007-10-03 01:05:39 +0000113#if defined(TARGET_PPC64)
j_mayeradd78952007-11-19 11:41:10 +0000114#define POWERPC_MMU_64 0x00010000
David Gibsoncdaee002011-04-01 15:15:18 +1100115#define POWERPC_MMU_1TSEG 0x00020000
j_mayer12de9a32007-10-05 22:06:02 +0000116 /* 64 bits PowerPC MMU */
j_mayeradd78952007-11-19 11:41:10 +0000117 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
118 /* 620 variant (no segment exceptions) */
119 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
David Gibson9d52e902011-04-01 15:15:19 +1100120 /* Architecture 2.06 variant */
121 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
j_mayer00af6852007-10-03 01:05:39 +0000122#endif /* defined(TARGET_PPC64) */
bellard3fc6c082005-07-02 20:59:34 +0000123};
bellard79aceca2003-11-23 14:55:54 +0000124
bellard3fc6c082005-07-02 20:59:34 +0000125/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +0000126/* Exception model */
Anthony Liguoric227f092009-10-01 16:12:16 -0500127typedef enum powerpc_excp_t powerpc_excp_t;
128enum powerpc_excp_t {
j_mayera750fc02007-09-26 23:54:22 +0000129 POWERPC_EXCP_UNKNOWN = 0,
bellard3fc6c082005-07-02 20:59:34 +0000130 /* Standard PowerPC exception model */
j_mayera750fc02007-09-26 23:54:22 +0000131 POWERPC_EXCP_STD,
j_mayer2662a052007-09-21 05:50:37 +0000132 /* PowerPC 40x exception model */
j_mayera750fc02007-09-26 23:54:22 +0000133 POWERPC_EXCP_40x,
j_mayer2662a052007-09-21 05:50:37 +0000134 /* PowerPC 601 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000135 POWERPC_EXCP_601,
j_mayer2662a052007-09-21 05:50:37 +0000136 /* PowerPC 602 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000137 POWERPC_EXCP_602,
j_mayer2662a052007-09-21 05:50:37 +0000138 /* PowerPC 603 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000139 POWERPC_EXCP_603,
140 /* PowerPC 603e exception model */
141 POWERPC_EXCP_603E,
142 /* PowerPC G2 exception model */
143 POWERPC_EXCP_G2,
j_mayer2662a052007-09-21 05:50:37 +0000144 /* PowerPC 604 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000145 POWERPC_EXCP_604,
j_mayer2662a052007-09-21 05:50:37 +0000146 /* PowerPC 7x0 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000147 POWERPC_EXCP_7x0,
j_mayer2662a052007-09-21 05:50:37 +0000148 /* PowerPC 7x5 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000149 POWERPC_EXCP_7x5,
j_mayer2662a052007-09-21 05:50:37 +0000150 /* PowerPC 74xx exception model */
j_mayera750fc02007-09-26 23:54:22 +0000151 POWERPC_EXCP_74xx,
j_mayer2662a052007-09-21 05:50:37 +0000152 /* BookE exception model */
j_mayera750fc02007-09-26 23:54:22 +0000153 POWERPC_EXCP_BOOKE,
j_mayer00af6852007-10-03 01:05:39 +0000154#if defined(TARGET_PPC64)
155 /* PowerPC 970 exception model */
156 POWERPC_EXCP_970,
David Gibson9d52e902011-04-01 15:15:19 +1100157 /* POWER7 exception model */
158 POWERPC_EXCP_POWER7,
j_mayer00af6852007-10-03 01:05:39 +0000159#endif /* defined(TARGET_PPC64) */
bellard3fc6c082005-07-02 20:59:34 +0000160};
161
bellard3fc6c082005-07-02 20:59:34 +0000162/*****************************************************************************/
j_mayere1833e12007-09-29 13:06:16 +0000163/* Exception vectors definitions */
164enum {
165 POWERPC_EXCP_NONE = -1,
166 /* The 64 first entries are used by the PowerPC embedded specification */
167 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
168 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
169 POWERPC_EXCP_DSI = 2, /* Data storage exception */
170 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
171 POWERPC_EXCP_EXTERNAL = 4, /* External input */
172 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
173 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
174 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
175 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
176 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
177 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
178 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
179 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
j_mayerb4095fe2007-11-17 22:42:36 +0000180 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
181 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
j_mayere1833e12007-09-29 13:06:16 +0000182 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
183 /* Vectors 16 to 31 are reserved */
j_mayere1833e12007-09-29 13:06:16 +0000184 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
185 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
186 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
187 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
188 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
189 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
j_mayere1833e12007-09-29 13:06:16 +0000190 /* Vectors 38 to 63 are reserved */
191 /* Exceptions defined in the PowerPC server specification */
192 POWERPC_EXCP_RESET = 64, /* System reset exception */
j_mayere1833e12007-09-29 13:06:16 +0000193 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
194 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
j_mayere1833e12007-09-29 13:06:16 +0000195 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
j_mayere1833e12007-09-29 13:06:16 +0000196 POWERPC_EXCP_TRACE = 68, /* Trace exception */
j_mayere1833e12007-09-29 13:06:16 +0000197 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
198 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
199 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
200 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
j_mayere1833e12007-09-29 13:06:16 +0000201 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
202 /* 40x specific exceptions */
203 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
204 /* 601 specific exceptions */
205 POWERPC_EXCP_IO = 75, /* IO error exception */
206 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
207 /* 602 specific exceptions */
208 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
209 /* 602/603 specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000210 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
j_mayere1833e12007-09-29 13:06:16 +0000211 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
212 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
213 /* Exceptions available on most PowerPC */
214 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
j_mayerb4095fe2007-11-17 22:42:36 +0000215 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
216 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
217 POWERPC_EXCP_SMI = 84, /* System management interrupt */
218 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
j_mayere1833e12007-09-29 13:06:16 +0000219 /* 7xx/74xx specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000220 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
j_mayere1833e12007-09-29 13:06:16 +0000221 /* 74xx specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000222 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
j_mayere1833e12007-09-29 13:06:16 +0000223 /* 970FX specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000224 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
225 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
Stefan Weil5b46d072011-04-28 17:20:30 +0200226 /* Freescale embedded cores specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000227 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
228 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
229 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
230 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
j_mayere1833e12007-09-29 13:06:16 +0000231 /* EOL */
232 POWERPC_EXCP_NB = 96,
233 /* Qemu exceptions: used internally during code translation */
234 POWERPC_EXCP_STOP = 0x200, /* stop translation */
235 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
236 /* Qemu exceptions: special cases we want to stop translation */
237 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
238 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
Nathan Froyd44252652009-08-03 08:43:26 -0700239 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
j_mayere1833e12007-09-29 13:06:16 +0000240};
241
j_mayere1833e12007-09-29 13:06:16 +0000242/* Exceptions error codes */
243enum {
244 /* Exception subtypes for POWERPC_EXCP_ALIGN */
245 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
246 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
247 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
248 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
249 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
250 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
251 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
252 /* FP exceptions */
253 POWERPC_EXCP_FP = 0x10,
254 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
255 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
256 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
257 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
j_mayer7c580442007-10-27 17:54:30 +0000258 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
j_mayere1833e12007-09-29 13:06:16 +0000259 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
260 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
261 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
262 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
263 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
264 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
265 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
266 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
267 /* Invalid instruction */
268 POWERPC_EXCP_INVAL = 0x20,
269 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
270 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
271 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
272 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
273 /* Privileged instruction */
274 POWERPC_EXCP_PRIV = 0x30,
275 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
276 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
277 /* Trap */
278 POWERPC_EXCP_TRAP = 0x40,
279};
280
281/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +0000282/* Input pins model */
Anthony Liguoric227f092009-10-01 16:12:16 -0500283typedef enum powerpc_input_t powerpc_input_t;
284enum powerpc_input_t {
j_mayera750fc02007-09-26 23:54:22 +0000285 PPC_FLAGS_INPUT_UNKNOWN = 0,
286 /* PowerPC 6xx bus */
287 PPC_FLAGS_INPUT_6xx,
288 /* BookE bus */
289 PPC_FLAGS_INPUT_BookE,
290 /* PowerPC 405 bus */
291 PPC_FLAGS_INPUT_405,
292 /* PowerPC 970 bus */
293 PPC_FLAGS_INPUT_970,
David Gibson9d52e902011-04-01 15:15:19 +1100294 /* PowerPC POWER7 bus */
295 PPC_FLAGS_INPUT_POWER7,
j_mayera750fc02007-09-26 23:54:22 +0000296 /* PowerPC 401 bus */
297 PPC_FLAGS_INPUT_401,
j_mayerb4095fe2007-11-17 22:42:36 +0000298 /* Freescale RCPU bus */
299 PPC_FLAGS_INPUT_RCPU,
j_mayera750fc02007-09-26 23:54:22 +0000300};
bellard3fc6c082005-07-02 20:59:34 +0000301
j_mayera750fc02007-09-26 23:54:22 +0000302#define PPC_INPUT(env) (env->bus_model)
bellard3fc6c082005-07-02 20:59:34 +0000303
j_mayerbe147d02007-09-30 13:03:23 +0000304/*****************************************************************************/
Anthony Liguoric227f092009-10-01 16:12:16 -0500305typedef struct ppc_def_t ppc_def_t;
306typedef struct opc_handler_t opc_handler_t;
bellard3fc6c082005-07-02 20:59:34 +0000307
308/*****************************************************************************/
309/* Types used to describe some PowerPC registers */
310typedef struct CPUPPCState CPUPPCState;
Anthony Liguoric227f092009-10-01 16:12:16 -0500311typedef struct ppc_tb_t ppc_tb_t;
312typedef struct ppc_spr_t ppc_spr_t;
313typedef struct ppc_dcr_t ppc_dcr_t;
314typedef union ppc_avr_t ppc_avr_t;
315typedef union ppc_tlb_t ppc_tlb_t;
j_mayer76a66252007-03-07 08:32:30 +0000316
bellard3fc6c082005-07-02 20:59:34 +0000317/* SPR access micro-ops generations callbacks */
Anthony Liguoric227f092009-10-01 16:12:16 -0500318struct ppc_spr_t {
aurel3245d827d2008-12-07 13:40:29 +0000319 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
320 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
j_mayer76a66252007-03-07 08:32:30 +0000321#if !defined(CONFIG_USER_ONLY)
aurel3245d827d2008-12-07 13:40:29 +0000322 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
323 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
324 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
325 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
j_mayerbe147d02007-09-30 13:03:23 +0000326#endif
blueswir1b55266b2008-09-20 08:07:15 +0000327 const char *name;
bellard3fc6c082005-07-02 20:59:34 +0000328};
329
330/* Altivec registers (128 bits) */
Anthony Liguoric227f092009-10-01 16:12:16 -0500331union ppc_avr_t {
aurel320f6fbcb2009-02-03 19:55:43 +0000332 float32 f[4];
j_mayera9d9eb82007-10-07 18:19:26 +0000333 uint8_t u8[16];
334 uint16_t u16[8];
335 uint32_t u32[4];
aurel32ab5f2652008-12-15 07:03:06 +0000336 int8_t s8[16];
337 int16_t s16[8];
338 int32_t s32[4];
j_mayera9d9eb82007-10-07 18:19:26 +0000339 uint64_t u64[2];
bellard3fc6c082005-07-02 20:59:34 +0000340};
341
Paul Brook3c7b48b2010-03-01 04:11:28 +0000342#if !defined(CONFIG_USER_ONLY)
bellard3fc6c082005-07-02 20:59:34 +0000343/* Software TLB cache */
Anthony Liguoric227f092009-10-01 16:12:16 -0500344typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
345struct ppc6xx_tlb_t {
j_mayer76a66252007-03-07 08:32:30 +0000346 target_ulong pte0;
347 target_ulong pte1;
348 target_ulong EPN;
j_mayer1d0a48f2007-03-31 11:10:49 +0000349};
350
Anthony Liguoric227f092009-10-01 16:12:16 -0500351typedef struct ppcemb_tlb_t ppcemb_tlb_t;
352struct ppcemb_tlb_t {
353 target_phys_addr_t RPN;
j_mayer1d0a48f2007-03-31 11:10:49 +0000354 target_ulong EPN;
j_mayer76a66252007-03-07 08:32:30 +0000355 target_ulong PID;
j_mayerc55e9ae2007-04-16 09:21:46 +0000356 target_ulong size;
357 uint32_t prot;
358 uint32_t attr; /* Storage attributes */
j_mayer1d0a48f2007-03-31 11:10:49 +0000359};
360
Alexander Grafd1e256f2011-06-16 18:45:43 +0200361typedef struct ppcmas_tlb_t {
362 uint32_t mas8;
363 uint32_t mas1;
364 uint64_t mas2;
365 uint64_t mas7_3;
366} ppcmas_tlb_t;
367
Anthony Liguoric227f092009-10-01 16:12:16 -0500368union ppc_tlb_t {
Alexander Graf1c53acc2011-06-17 01:00:28 +0200369 ppc6xx_tlb_t *tlb6;
370 ppcemb_tlb_t *tlbe;
371 ppcmas_tlb_t *tlbm;
bellard3fc6c082005-07-02 20:59:34 +0000372};
Alexander Graf1c53acc2011-06-17 01:00:28 +0200373
374/* possible TLB variants */
375#define TLB_NONE 0
376#define TLB_6XX 1
377#define TLB_EMB 2
378#define TLB_MAS 3
Paul Brook3c7b48b2010-03-01 04:11:28 +0000379#endif
bellard3fc6c082005-07-02 20:59:34 +0000380
David Gibsonbb593902011-04-01 15:15:15 +1100381#define SDR_32_HTABORG 0xFFFF0000UL
382#define SDR_32_HTABMASK 0x000001FFUL
383
384#if defined(TARGET_PPC64)
385#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
386#define SDR_64_HTABSIZE 0x000000000000001FULL
387#endif /* defined(TARGET_PPC64 */
388
David Gibsonfda6a0e2011-04-01 15:15:16 +1100389#define HASH_PTE_SIZE_32 8
390#define HASH_PTE_SIZE_64 16
391
Anthony Liguoric227f092009-10-01 16:12:16 -0500392typedef struct ppc_slb_t ppc_slb_t;
393struct ppc_slb_t {
David Gibson81762d62011-04-01 15:15:08 +1100394 uint64_t esid;
395 uint64_t vsid;
blueswir18eee0af2009-03-07 20:57:42 +0000396};
397
David Gibson81762d62011-04-01 15:15:08 +1100398/* Bits in the SLB ESID word */
399#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
400#define SLB_ESID_V 0x0000000008000000ULL /* valid */
401
402/* Bits in the SLB VSID word */
403#define SLB_VSID_SHIFT 12
David Gibsoncdaee002011-04-01 15:15:18 +1100404#define SLB_VSID_SHIFT_1T 24
David Gibson81762d62011-04-01 15:15:08 +1100405#define SLB_VSID_SSIZE_SHIFT 62
406#define SLB_VSID_B 0xc000000000000000ULL
407#define SLB_VSID_B_256M 0x0000000000000000ULL
David Gibsoncdaee002011-04-01 15:15:18 +1100408#define SLB_VSID_B_1T 0x4000000000000000ULL
David Gibson81762d62011-04-01 15:15:08 +1100409#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
David Gibson256cebe2011-04-01 15:15:17 +1100410#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
David Gibson81762d62011-04-01 15:15:08 +1100411#define SLB_VSID_KS 0x0000000000000800ULL
412#define SLB_VSID_KP 0x0000000000000400ULL
413#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
414#define SLB_VSID_L 0x0000000000000100ULL
415#define SLB_VSID_C 0x0000000000000080ULL /* class */
416#define SLB_VSID_LP 0x0000000000000030ULL
417#define SLB_VSID_ATTR 0x0000000000000FFFULL
418
419#define SEGMENT_SHIFT_256M 28
420#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
421
David Gibsoncdaee002011-04-01 15:15:18 +1100422#define SEGMENT_SHIFT_1T 40
423#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
424
425
bellard3fc6c082005-07-02 20:59:34 +0000426/*****************************************************************************/
427/* Machine state register bits definition */
j_mayer76a66252007-03-07 08:32:30 +0000428#define MSR_SF 63 /* Sixty-four-bit mode hflags */
j_mayerbd928eb2007-11-21 13:08:23 +0000429#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
bellard3fc6c082005-07-02 20:59:34 +0000430#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
j_mayera4f30712007-11-17 21:14:09 +0000431#define MSR_SHV 60 /* hypervisor state hflags */
j_mayer363be492007-03-30 10:07:33 +0000432#define MSR_CM 31 /* Computation mode for BookE hflags */
433#define MSR_ICM 30 /* Interrupt computation mode for BookE */
j_mayera4f30712007-11-17 21:14:09 +0000434#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
Alexander Graf71afeb62011-04-30 23:34:56 +0200435#define MSR_GS 28 /* guest state for BookE */
j_mayer363be492007-03-30 10:07:33 +0000436#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
j_mayerd26bfc92007-10-07 14:41:00 +0000437#define MSR_VR 25 /* altivec available x hflags */
438#define MSR_SPE 25 /* SPE enable for BookE x hflags */
j_mayer76a66252007-03-07 08:32:30 +0000439#define MSR_AP 23 /* Access privilege state on 602 hflags */
440#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
bellard3fc6c082005-07-02 20:59:34 +0000441#define MSR_KEY 19 /* key bit on 603e */
j_mayer25ba3a62007-10-08 02:58:07 +0000442#define MSR_POW 18 /* Power management */
j_mayerd26bfc92007-10-07 14:41:00 +0000443#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
444#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
bellard3fc6c082005-07-02 20:59:34 +0000445#define MSR_ILE 16 /* Interrupt little-endian mode */
446#define MSR_EE 15 /* External interrupt enable */
j_mayer76a66252007-03-07 08:32:30 +0000447#define MSR_PR 14 /* Problem state hflags */
448#define MSR_FP 13 /* Floating point available hflags */
bellard3fc6c082005-07-02 20:59:34 +0000449#define MSR_ME 12 /* Machine check interrupt enable */
j_mayer76a66252007-03-07 08:32:30 +0000450#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
j_mayerd26bfc92007-10-07 14:41:00 +0000451#define MSR_SE 10 /* Single-step trace enable x hflags */
452#define MSR_DWE 10 /* Debug wait enable on 405 x */
453#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
454#define MSR_BE 9 /* Branch trace enable x hflags */
455#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
j_mayer76a66252007-03-07 08:32:30 +0000456#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
bellard3fc6c082005-07-02 20:59:34 +0000457#define MSR_AL 7 /* AL bit on POWER */
j_mayer0411a972007-10-25 21:35:50 +0000458#define MSR_EP 6 /* Exception prefix on 601 */
bellard3fc6c082005-07-02 20:59:34 +0000459#define MSR_IR 5 /* Instruction relocate */
bellard3fc6c082005-07-02 20:59:34 +0000460#define MSR_DR 4 /* Data relocate */
j_mayer25ba3a62007-10-08 02:58:07 +0000461#define MSR_PE 3 /* Protection enable on 403 */
j_mayerd26bfc92007-10-07 14:41:00 +0000462#define MSR_PX 2 /* Protection exclusive on 403 x */
463#define MSR_PMM 2 /* Performance monitor mark on POWER x */
464#define MSR_RI 1 /* Recoverable interrupt 1 */
465#define MSR_LE 0 /* Little-endian mode 1 hflags */
j_mayer0411a972007-10-25 21:35:50 +0000466
467#define msr_sf ((env->msr >> MSR_SF) & 1)
468#define msr_isf ((env->msr >> MSR_ISF) & 1)
j_mayera4f30712007-11-17 21:14:09 +0000469#define msr_shv ((env->msr >> MSR_SHV) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000470#define msr_cm ((env->msr >> MSR_CM) & 1)
471#define msr_icm ((env->msr >> MSR_ICM) & 1)
j_mayera4f30712007-11-17 21:14:09 +0000472#define msr_thv ((env->msr >> MSR_THV) & 1)
Alexander Graf71afeb62011-04-30 23:34:56 +0200473#define msr_gs ((env->msr >> MSR_GS) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000474#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
475#define msr_vr ((env->msr >> MSR_VR) & 1)
aurel32f9320412008-05-06 14:58:15 +0000476#define msr_spe ((env->msr >> MSR_SPE) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000477#define msr_ap ((env->msr >> MSR_AP) & 1)
478#define msr_sa ((env->msr >> MSR_SA) & 1)
479#define msr_key ((env->msr >> MSR_KEY) & 1)
480#define msr_pow ((env->msr >> MSR_POW) & 1)
481#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
482#define msr_ce ((env->msr >> MSR_CE) & 1)
483#define msr_ile ((env->msr >> MSR_ILE) & 1)
484#define msr_ee ((env->msr >> MSR_EE) & 1)
485#define msr_pr ((env->msr >> MSR_PR) & 1)
486#define msr_fp ((env->msr >> MSR_FP) & 1)
487#define msr_me ((env->msr >> MSR_ME) & 1)
488#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
489#define msr_se ((env->msr >> MSR_SE) & 1)
490#define msr_dwe ((env->msr >> MSR_DWE) & 1)
491#define msr_uble ((env->msr >> MSR_UBLE) & 1)
492#define msr_be ((env->msr >> MSR_BE) & 1)
493#define msr_de ((env->msr >> MSR_DE) & 1)
494#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
495#define msr_al ((env->msr >> MSR_AL) & 1)
496#define msr_ep ((env->msr >> MSR_EP) & 1)
497#define msr_ir ((env->msr >> MSR_IR) & 1)
498#define msr_dr ((env->msr >> MSR_DR) & 1)
499#define msr_pe ((env->msr >> MSR_PE) & 1)
500#define msr_px ((env->msr >> MSR_PX) & 1)
501#define msr_pmm ((env->msr >> MSR_PMM) & 1)
502#define msr_ri ((env->msr >> MSR_RI) & 1)
503#define msr_le ((env->msr >> MSR_LE) & 1)
j_mayera4f30712007-11-17 21:14:09 +0000504/* Hypervisor bit is more specific */
505#if defined(TARGET_PPC64)
506#define MSR_HVB (1ULL << MSR_SHV)
507#define msr_hv msr_shv
508#else
509#if defined(PPC_EMULATE_32BITS_HYPV)
510#define MSR_HVB (1ULL << MSR_THV)
511#define msr_hv msr_thv
j_mayera4f30712007-11-17 21:14:09 +0000512#else
513#define MSR_HVB (0ULL)
514#define msr_hv (0)
515#endif
516#endif
bellard79aceca2003-11-23 14:55:54 +0000517
Edgar E. Iglesiasa586e542010-09-20 19:06:32 +0200518/* Exception state register bits definition */
Alexander Graf542df9b2011-08-23 06:55:42 +0200519#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
520#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
521#define ESR_PTR (1 << (63 - 38)) /* Trap */
522#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
523#define ESR_ST (1 << (63 - 40)) /* Store Operation */
524#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
525#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
526#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
527#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
528#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
529#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
530#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
531#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
532#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
533#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
534#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
Edgar E. Iglesiasa586e542010-09-20 19:06:32 +0200535
j_mayerd26bfc92007-10-07 14:41:00 +0000536enum {
j_mayer4018bae2007-11-19 01:48:12 +0000537 POWERPC_FLAG_NONE = 0x00000000,
j_mayerd26bfc92007-10-07 14:41:00 +0000538 /* Flag for MSR bit 25 signification (VRE/SPE) */
j_mayer4018bae2007-11-19 01:48:12 +0000539 POWERPC_FLAG_SPE = 0x00000001,
540 POWERPC_FLAG_VRE = 0x00000002,
j_mayerd26bfc92007-10-07 14:41:00 +0000541 /* Flag for MSR bit 17 signification (TGPR/CE) */
j_mayer4018bae2007-11-19 01:48:12 +0000542 POWERPC_FLAG_TGPR = 0x00000004,
543 POWERPC_FLAG_CE = 0x00000008,
j_mayerd26bfc92007-10-07 14:41:00 +0000544 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
j_mayer4018bae2007-11-19 01:48:12 +0000545 POWERPC_FLAG_SE = 0x00000010,
546 POWERPC_FLAG_DWE = 0x00000020,
547 POWERPC_FLAG_UBLE = 0x00000040,
j_mayerd26bfc92007-10-07 14:41:00 +0000548 /* Flag for MSR bit 9 signification (BE/DE) */
j_mayer4018bae2007-11-19 01:48:12 +0000549 POWERPC_FLAG_BE = 0x00000080,
550 POWERPC_FLAG_DE = 0x00000100,
j_mayera4f30712007-11-17 21:14:09 +0000551 /* Flag for MSR bit 2 signification (PX/PMM) */
j_mayer4018bae2007-11-19 01:48:12 +0000552 POWERPC_FLAG_PX = 0x00000200,
553 POWERPC_FLAG_PMM = 0x00000400,
554 /* Flag for special features */
555 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
556 POWERPC_FLAG_RTC_CLK = 0x00010000,
557 POWERPC_FLAG_BUS_CLK = 0x00020000,
David Gibson697ab892011-08-31 15:45:10 +0000558 /* Has CFAR */
559 POWERPC_FLAG_CFAR = 0x00040000,
j_mayerd26bfc92007-10-07 14:41:00 +0000560};
561
j_mayer7c580442007-10-27 17:54:30 +0000562/*****************************************************************************/
563/* Floating point status and control register */
564#define FPSCR_FX 31 /* Floating-point exception summary */
565#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
566#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
567#define FPSCR_OX 28 /* Floating-point overflow exception */
568#define FPSCR_UX 27 /* Floating-point underflow exception */
569#define FPSCR_ZX 26 /* Floating-point zero divide exception */
570#define FPSCR_XX 25 /* Floating-point inexact exception */
571#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
572#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
573#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
574#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
575#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
576#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
577#define FPSCR_FR 18 /* Floating-point fraction rounded */
578#define FPSCR_FI 17 /* Floating-point fraction inexact */
579#define FPSCR_C 16 /* Floating-point result class descriptor */
580#define FPSCR_FL 15 /* Floating-point less than or negative */
581#define FPSCR_FG 14 /* Floating-point greater than or negative */
582#define FPSCR_FE 13 /* Floating-point equal or zero */
583#define FPSCR_FU 12 /* Floating-point unordered or NaN */
584#define FPSCR_FPCC 12 /* Floating-point condition code */
585#define FPSCR_FPRF 12 /* Floating-point result flags */
586#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
587#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
588#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
589#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
590#define FPSCR_OE 6 /* Floating-point overflow exception enable */
591#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
592#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
593#define FPSCR_XE 3 /* Floating-point inexact exception enable */
594#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
595#define FPSCR_RN1 1
596#define FPSCR_RN 0 /* Floating-point rounding control */
597#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
598#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
599#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
600#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
601#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
602#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
603#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
604#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
605#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
606#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
607#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
608#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
609#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
610#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
611#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
612#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
613#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
614#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
615#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
616#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
617#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
618#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
619#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
620/* Invalid operation exception summary */
621#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
622 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
623 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
624 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
625 (1 << FPSCR_VXCVI)))
626/* exception summary */
627#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
628/* enabled exception summary */
629#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
630 0x1F)
631
632/*****************************************************************************/
aurel326fa724a2009-01-03 14:04:11 +0000633/* Vector status and control register */
634#define VSCR_NJ 16 /* Vector non-java */
635#define VSCR_SAT 0 /* Vector saturation */
636#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
637#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
638
639/*****************************************************************************/
Alexander Graf01662f32011-04-30 23:34:58 +0200640/* BookE e500 MMU registers */
641
642#define MAS0_NV_SHIFT 0
643#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
644
645#define MAS0_WQ_SHIFT 12
646#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
647/* Write TLB entry regardless of reservation */
648#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
649/* Write TLB entry only already in use */
650#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
651/* Clear TLB entry */
652#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
653
654#define MAS0_HES_SHIFT 14
655#define MAS0_HES (1 << MAS0_HES_SHIFT)
656
657#define MAS0_ESEL_SHIFT 16
658#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
659
660#define MAS0_TLBSEL_SHIFT 28
661#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
662#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
663#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
664#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
665#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
666
667#define MAS0_ATSEL_SHIFT 31
668#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
669#define MAS0_ATSEL_TLB 0
670#define MAS0_ATSEL_LRAT MAS0_ATSEL
671
Scott Wood2bd95432011-08-18 10:38:40 +0000672#define MAS1_TSIZE_SHIFT 7
673#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
Alexander Graf01662f32011-04-30 23:34:58 +0200674
675#define MAS1_TS_SHIFT 12
676#define MAS1_TS (1 << MAS1_TS_SHIFT)
677
678#define MAS1_IND_SHIFT 13
679#define MAS1_IND (1 << MAS1_IND_SHIFT)
680
681#define MAS1_TID_SHIFT 16
682#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
683
684#define MAS1_IPROT_SHIFT 30
685#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
686
687#define MAS1_VALID_SHIFT 31
688#define MAS1_VALID 0x80000000
689
690#define MAS2_EPN_SHIFT 12
691#define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT)
692
693#define MAS2_ACM_SHIFT 6
694#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
695
696#define MAS2_VLE_SHIFT 5
697#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
698
699#define MAS2_W_SHIFT 4
700#define MAS2_W (1 << MAS2_W_SHIFT)
701
702#define MAS2_I_SHIFT 3
703#define MAS2_I (1 << MAS2_I_SHIFT)
704
705#define MAS2_M_SHIFT 2
706#define MAS2_M (1 << MAS2_M_SHIFT)
707
708#define MAS2_G_SHIFT 1
709#define MAS2_G (1 << MAS2_G_SHIFT)
710
711#define MAS2_E_SHIFT 0
712#define MAS2_E (1 << MAS2_E_SHIFT)
713
714#define MAS3_RPN_SHIFT 12
715#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
716
717#define MAS3_U0 0x00000200
718#define MAS3_U1 0x00000100
719#define MAS3_U2 0x00000080
720#define MAS3_U3 0x00000040
721#define MAS3_UX 0x00000020
722#define MAS3_SX 0x00000010
723#define MAS3_UW 0x00000008
724#define MAS3_SW 0x00000004
725#define MAS3_UR 0x00000002
726#define MAS3_SR 0x00000001
727#define MAS3_SPSIZE_SHIFT 1
728#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
729
730#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
731#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
732#define MAS4_TIDSELD_MASK 0x00030000
733#define MAS4_TIDSELD_PID0 0x00000000
734#define MAS4_TIDSELD_PID1 0x00010000
735#define MAS4_TIDSELD_PID2 0x00020000
736#define MAS4_TIDSELD_PIDZ 0x00030000
737#define MAS4_INDD 0x00008000 /* Default IND */
738#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
739#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
740#define MAS4_ACMD 0x00000040
741#define MAS4_VLED 0x00000020
742#define MAS4_WD 0x00000010
743#define MAS4_ID 0x00000008
744#define MAS4_MD 0x00000004
745#define MAS4_GD 0x00000002
746#define MAS4_ED 0x00000001
747#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
748#define MAS4_WIMGED_SHIFT 0
749
750#define MAS5_SGS 0x80000000
751#define MAS5_SLPID_MASK 0x00000fff
752
753#define MAS6_SPID0 0x3fff0000
754#define MAS6_SPID1 0x00007ffe
755#define MAS6_ISIZE(x) MAS1_TSIZE(x)
756#define MAS6_SAS 0x00000001
757#define MAS6_SPID MAS6_SPID0
758#define MAS6_SIND 0x00000002 /* Indirect page */
759#define MAS6_SIND_SHIFT 1
760#define MAS6_SPID_MASK 0x3fff0000
761#define MAS6_SPID_SHIFT 16
762#define MAS6_ISIZE_MASK 0x00000f80
763#define MAS6_ISIZE_SHIFT 7
764
765#define MAS7_RPN 0xffffffff
766
767#define MAS8_TGS 0x80000000
768#define MAS8_VF 0x40000000
769#define MAS8_TLBPID 0x00000fff
770
771/* Bit definitions for MMUCFG */
772#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
773#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
774#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
775#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
776#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
777#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
778#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
779#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
780#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
781
782/* Bit definitions for MMUCSR0 */
783#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
784#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
785#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
786#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
787#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
788 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
789#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
790#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
791#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
792#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
793
794/* TLBnCFG encoding */
795#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
796#define TLBnCFG_HES 0x00002000 /* HW select supported */
797#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
798#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
799#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
800#define TLBnCFG_IND 0x00020000 /* IND entries supported */
801#define TLBnCFG_PT 0x00040000 /* Can load from page table */
802#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
803#define TLBnCFG_MINSIZE_SHIFT 20
804#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
805#define TLBnCFG_MAXSIZE_SHIFT 16
806#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
807#define TLBnCFG_ASSOC_SHIFT 24
808
809/* TLBnPS encoding */
810#define TLBnPS_4K 0x00000004
811#define TLBnPS_8K 0x00000008
812#define TLBnPS_16K 0x00000010
813#define TLBnPS_32K 0x00000020
814#define TLBnPS_64K 0x00000040
815#define TLBnPS_128K 0x00000080
816#define TLBnPS_256K 0x00000100
817#define TLBnPS_512K 0x00000200
818#define TLBnPS_1M 0x00000400
819#define TLBnPS_2M 0x00000800
820#define TLBnPS_4M 0x00001000
821#define TLBnPS_8M 0x00002000
822#define TLBnPS_16M 0x00004000
823#define TLBnPS_32M 0x00008000
824#define TLBnPS_64M 0x00010000
825#define TLBnPS_128M 0x00020000
826#define TLBnPS_256M 0x00040000
827#define TLBnPS_512M 0x00080000
828#define TLBnPS_1G 0x00100000
829#define TLBnPS_2G 0x00200000
830#define TLBnPS_4G 0x00400000
831#define TLBnPS_8G 0x00800000
832#define TLBnPS_16G 0x01000000
833#define TLBnPS_32G 0x02000000
834#define TLBnPS_64G 0x04000000
835#define TLBnPS_128G 0x08000000
836#define TLBnPS_256G 0x10000000
837
838/* tlbilx action encoding */
839#define TLBILX_T_ALL 0
840#define TLBILX_T_TID 1
841#define TLBILX_T_FULLMATCH 3
842#define TLBILX_T_CLASS0 4
843#define TLBILX_T_CLASS1 5
844#define TLBILX_T_CLASS2 6
845#define TLBILX_T_CLASS3 7
846
847/* BookE 2.06 helper defines */
848
849#define BOOKE206_FLUSH_TLB0 (1 << 0)
850#define BOOKE206_FLUSH_TLB1 (1 << 1)
851#define BOOKE206_FLUSH_TLB2 (1 << 2)
852#define BOOKE206_FLUSH_TLB3 (1 << 3)
853
854/* number of possible TLBs */
855#define BOOKE206_MAX_TLBN 4
856
857/*****************************************************************************/
j_mayer7c580442007-10-27 17:54:30 +0000858/* The whole PowerPC CPU context */
j_mayer6ebbf392007-10-14 07:07:08 +0000859#define NB_MMU_MODES 3
j_mayer6ebbf392007-10-14 07:07:08 +0000860
David Gibsona7342582011-10-17 18:15:41 +0000861struct ppc_def_t {
862 const char *name;
863 uint32_t pvr;
864 uint32_t svr;
865 uint64_t insns_flags;
866 uint64_t insns_flags2;
867 uint64_t msr_mask;
868 powerpc_mmu_t mmu_model;
869 powerpc_excp_t excp_model;
870 powerpc_input_t bus_model;
871 uint32_t flags;
872 int bfd_mach;
873 void (*init_proc)(CPUPPCState *env);
874 int (*check_pow)(CPUPPCState *env);
875};
876
bellard3fc6c082005-07-02 20:59:34 +0000877struct CPUPPCState {
878 /* First are the most commonly used resources
879 * during translated code execution
880 */
bellard79aceca2003-11-23 14:55:54 +0000881 /* general purpose registers */
aurel32bd7d9a62008-09-04 05:26:09 +0000882 target_ulong gpr[32];
j_mayer65d6c0f2007-11-12 23:29:14 +0000883#if !defined(TARGET_PPC64)
j_mayer3cd7d1d2007-11-12 01:56:18 +0000884 /* Storage for GPR MSB, used by the SPE extension */
aurel32bd7d9a62008-09-04 05:26:09 +0000885 target_ulong gprh[32];
j_mayer3cd7d1d2007-11-12 01:56:18 +0000886#endif
bellard3fc6c082005-07-02 20:59:34 +0000887 /* LR */
888 target_ulong lr;
889 /* CTR */
890 target_ulong ctr;
bellard79aceca2003-11-23 14:55:54 +0000891 /* condition register */
aurel3247e46612008-09-04 17:06:47 +0000892 uint32_t crf[8];
David Gibson697ab892011-08-31 15:45:10 +0000893#if defined(TARGET_PPC64)
894 /* CFAR */
895 target_ulong cfar;
896#endif
bellard3fc6c082005-07-02 20:59:34 +0000897 /* XER */
aurel323d7b4172008-10-21 11:28:46 +0000898 target_ulong xer;
bellard3fc6c082005-07-02 20:59:34 +0000899 /* Reservation address */
Nathan Froyd18b21a22009-08-03 08:43:25 -0700900 target_ulong reserve_addr;
901 /* Reservation value */
902 target_ulong reserve_val;
Nathan Froyd44252652009-08-03 08:43:26 -0700903 /* Reservation store address */
904 target_ulong reserve_ea;
905 /* Reserved store source register and size */
906 target_ulong reserve_info;
bellard3fc6c082005-07-02 20:59:34 +0000907
908 /* Those ones are used in supervisor mode only */
909 /* machine state register */
j_mayer0411a972007-10-25 21:35:50 +0000910 target_ulong msr;
bellard3fc6c082005-07-02 20:59:34 +0000911 /* temporary general purpose registers */
aurel32bd7d9a62008-09-04 05:26:09 +0000912 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
bellard3fc6c082005-07-02 20:59:34 +0000913
914 /* Floating point execution context */
bellard4ecc3192005-03-13 17:01:22 +0000915 float_status fp_status;
bellard3fc6c082005-07-02 20:59:34 +0000916 /* floating point registers */
917 float64 fpr[32];
918 /* floating point status and control register */
j_mayer7c580442007-10-27 17:54:30 +0000919 uint32_t fpscr;
bellard4ecc3192005-03-13 17:01:22 +0000920
Aurelien Jarnocb2dbfc2009-10-22 14:55:37 +0200921 /* Next instruction pointer */
922 target_ulong nip;
bellarda316d332005-11-20 10:32:34 +0000923
bellardac9eb072004-01-04 23:26:24 +0000924 int access_type; /* when a memory exception occurs, the access
925 type is stored here */
bellarda541f292004-04-12 20:39:29 +0000926
Aurelien Jarnocb2dbfc2009-10-22 14:55:37 +0200927 CPU_COMMON
928
j_mayerf2e63a42007-10-07 15:43:50 +0000929 /* MMU context - only relevant for full system emulation */
930#if !defined(CONFIG_USER_ONLY)
931#if defined(TARGET_PPC64)
bellard3fc6c082005-07-02 20:59:34 +0000932 /* Address space register */
933 target_ulong asr;
j_mayerf2e63a42007-10-07 15:43:50 +0000934 /* PowerPC 64 SLB area */
Anthony Liguoric227f092009-10-01 16:12:16 -0500935 ppc_slb_t slb[64];
j_mayerf2e63a42007-10-07 15:43:50 +0000936 int slb_nr;
937#endif
bellard3fc6c082005-07-02 20:59:34 +0000938 /* segment registers */
David Gibsonbb593902011-04-01 15:15:15 +1100939 target_phys_addr_t htab_base;
940 target_phys_addr_t htab_mask;
aurel3274d37792008-12-06 21:46:17 +0000941 target_ulong sr[32];
David Gibsonf43e3522011-04-01 15:15:22 +1100942 /* externally stored hash table */
943 uint8_t *external_htab;
bellard3fc6c082005-07-02 20:59:34 +0000944 /* BATs */
945 int nb_BATs;
946 target_ulong DBAT[2][8];
947 target_ulong IBAT[2][8];
Alexander Graf01662f32011-04-30 23:34:58 +0200948 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
j_mayer76a66252007-03-07 08:32:30 +0000949 int nb_tlb; /* Total number of TLB */
950 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
951 int nb_ways; /* Number of ways in the TLB set */
952 int last_way; /* Last used way used to allocate TLB in a LRU way */
953 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
j_mayer363be492007-03-30 10:07:33 +0000954 int nb_pids; /* Number of available PID registers */
Alexander Graf1c53acc2011-06-17 01:00:28 +0200955 int tlb_type; /* Type of TLB we're dealing with */
956 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
bellard3fc6c082005-07-02 20:59:34 +0000957 /* 403 dedicated access protection registers */
958 target_ulong pb[4];
Scott Wood93dd5e82011-08-31 11:26:56 +0000959 bool tlb_dirty; /* Set to non-zero when modifying TLB */
960 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
j_mayerf2e63a42007-10-07 15:43:50 +0000961#endif
962
963 /* Other registers */
964 /* Special purpose registers */
965 target_ulong spr[1024];
Anthony Liguoric227f092009-10-01 16:12:16 -0500966 ppc_spr_t spr_cb[1024];
j_mayerf2e63a42007-10-07 15:43:50 +0000967 /* Altivec registers */
Anthony Liguoric227f092009-10-01 16:12:16 -0500968 ppc_avr_t avr[32];
j_mayerf2e63a42007-10-07 15:43:50 +0000969 uint32_t vscr;
j_mayerf2e63a42007-10-07 15:43:50 +0000970 /* SPE registers */
aurel322231ef12008-12-18 22:43:25 +0000971 uint64_t spe_acc;
j_mayerf2e63a42007-10-07 15:43:50 +0000972 uint32_t spe_fscr;
aurel32fbd265b2009-02-03 19:55:51 +0000973 /* SPE and Altivec can share a status since they will never be used
974 * simultaneously */
975 float_status vec_status;
j_mayerf2e63a42007-10-07 15:43:50 +0000976
977 /* Internal devices resources */
978 /* Time base and decrementer */
Anthony Liguoric227f092009-10-01 16:12:16 -0500979 ppc_tb_t *tb_env;
j_mayerf2e63a42007-10-07 15:43:50 +0000980 /* Device control registers */
Anthony Liguoric227f092009-10-01 16:12:16 -0500981 ppc_dcr_t *dcr_env;
bellard3fc6c082005-07-02 20:59:34 +0000982
j_mayerd63001d2007-10-04 00:51:58 +0000983 int dcache_line_size;
984 int icache_line_size;
985
bellard3fc6c082005-07-02 20:59:34 +0000986 /* Those resources are used during exception processing */
987 /* CPU model definition */
j_mayera750fc02007-09-26 23:54:22 +0000988 target_ulong msr_mask;
Anthony Liguoric227f092009-10-01 16:12:16 -0500989 powerpc_mmu_t mmu_model;
990 powerpc_excp_t excp_model;
991 powerpc_input_t bus_model;
j_mayer237c0af2007-09-29 12:01:46 +0000992 int bfd_mach;
bellard3fc6c082005-07-02 20:59:34 +0000993 uint32_t flags;
Nathan Froydc29b7352009-05-12 12:26:57 -0700994 uint64_t insns_flags;
Alexander Grafa5858d72011-05-01 00:00:58 +0200995 uint64_t insns_flags2;
bellard3fc6c082005-07-02 20:59:34 +0000996
David Gibsoned120052011-04-01 15:15:33 +1100997#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
998 target_phys_addr_t vpa;
999 target_phys_addr_t slb_shadow;
1000 target_phys_addr_t dispatch_trace_log;
1001 uint32_t dtl_size;
1002#endif /* TARGET_PPC64 */
1003
bellard3fc6c082005-07-02 20:59:34 +00001004 int error_code;
j_mayer47103572007-03-30 09:38:04 +00001005 uint32_t pending_interrupts;
j_mayere9df0142007-04-09 22:45:36 +00001006#if !defined(CONFIG_USER_ONLY)
Dong Xu Wang4abf79a2011-11-22 18:06:21 +08001007 /* This is the IRQ controller, which is implementation dependent
j_mayere9df0142007-04-09 22:45:36 +00001008 * and only relevant when emulating a complete machine.
1009 */
1010 uint32_t irq_input_state;
1011 void **irq_inputs;
j_mayere1833e12007-09-29 13:06:16 +00001012 /* Exception vectors */
1013 target_ulong excp_vectors[POWERPC_EXCP_NB];
1014 target_ulong excp_prefix;
Blue Swirlfc1c67b2009-04-28 18:00:30 +00001015 target_ulong hreset_excp_prefix;
j_mayere1833e12007-09-29 13:06:16 +00001016 target_ulong ivor_mask;
1017 target_ulong ivpr_mask;
j_mayerd63001d2007-10-04 00:51:58 +00001018 target_ulong hreset_vector;
j_mayere9df0142007-04-09 22:45:36 +00001019#endif
bellard3fc6c082005-07-02 20:59:34 +00001020
1021 /* Those resources are used only during code translation */
bellard3fc6c082005-07-02 20:59:34 +00001022 /* opcode handlers */
Anthony Liguoric227f092009-10-01 16:12:16 -05001023 opc_handler_t *opcodes[0x40];
bellard3fc6c082005-07-02 20:59:34 +00001024
1025 /* Those resources are used only in Qemu core */
j_mayer056401e2007-11-04 02:55:33 +00001026 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
Dong Xu Wang4abf79a2011-11-22 18:06:21 +08001027 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
j_mayer6ebbf392007-10-14 07:07:08 +00001028 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
bellard3fc6c082005-07-02 20:59:34 +00001029
bellard9fddaa02004-05-21 12:59:32 +00001030 /* Power management */
1031 int power_mode;
j_mayercd346342007-10-25 23:27:04 +00001032 int (*check_pow)(CPUPPCState *env);
bellarda541f292004-04-12 20:39:29 +00001033
Edgar E. Iglesias2c50e262010-09-29 15:31:44 +02001034#if !defined(CONFIG_USER_ONLY)
1035 void *load_info; /* Holds boot loading state. */
1036#endif
Fabien Chouteauddd10552011-09-13 04:00:32 +00001037
1038 /* booke timers */
1039
1040 /* Specifies bit locations of the Time Base used to signal a fixed timer
1041 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1042 *
1043 * 0 selects the least significant bit.
1044 * 63 selects the most significant bit.
1045 */
1046 uint8_t fit_period[4];
1047 uint8_t wdt_period[4];
bellard3fc6c082005-07-02 20:59:34 +00001048};
bellard79aceca2003-11-23 14:55:54 +00001049
Fabien Chouteauddd10552011-09-13 04:00:32 +00001050#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1051do { \
1052 env->fit_period[0] = (a_); \
1053 env->fit_period[1] = (b_); \
1054 env->fit_period[2] = (c_); \
1055 env->fit_period[3] = (d_); \
1056 } while (0)
1057
1058#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1059do { \
1060 env->wdt_period[0] = (a_); \
1061 env->wdt_period[1] = (b_); \
1062 env->wdt_period[2] = (c_); \
1063 env->wdt_period[3] = (d_); \
1064 } while (0)
1065
Paul Brook3c7b48b2010-03-01 04:11:28 +00001066#if !defined(CONFIG_USER_ONLY)
j_mayer76a66252007-03-07 08:32:30 +00001067/* Context used internally during MMU translations */
Anthony Liguoric227f092009-10-01 16:12:16 -05001068typedef struct mmu_ctx_t mmu_ctx_t;
1069struct mmu_ctx_t {
1070 target_phys_addr_t raddr; /* Real address */
1071 target_phys_addr_t eaddr; /* Effective address */
j_mayer76a66252007-03-07 08:32:30 +00001072 int prot; /* Protection bits */
David Gibsonfda6a0e2011-04-01 15:15:16 +11001073 target_phys_addr_t hash[2]; /* Pagetable hash values */
j_mayer76a66252007-03-07 08:32:30 +00001074 target_ulong ptem; /* Virtual segment ID | API */
1075 int key; /* Access key */
j_mayerb227a8e2007-10-14 10:21:20 +00001076 int nx; /* Non-execute area */
j_mayer76a66252007-03-07 08:32:30 +00001077};
Paul Brook3c7b48b2010-03-01 04:11:28 +00001078#endif
j_mayer76a66252007-03-07 08:32:30 +00001079
bellard3fc6c082005-07-02 20:59:34 +00001080/*****************************************************************************/
bellardaaed9092007-11-10 15:15:54 +00001081CPUPPCState *cpu_ppc_init (const char *cpu_model);
pbrook2e70f6e2008-06-29 01:03:05 +00001082void ppc_translate_init(void);
j_mayer36081602007-09-17 08:21:54 +00001083int cpu_ppc_exec (CPUPPCState *s);
1084void cpu_ppc_close (CPUPPCState *s);
bellard79aceca2003-11-23 14:55:54 +00001085/* you can call this signal handler from your SIGBUS and SIGSEGV
1086 signal handlers to inform the virtual CPU of exceptions. non zero
1087 is returned if the signal was handled by the virtual CPU. */
j_mayer36081602007-09-17 08:21:54 +00001088int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1089 void *puc);
aurel3293220572008-12-11 22:42:33 +00001090int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
Blue Swirl97b348e2011-08-01 16:12:17 +00001091 int mmu_idx);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -07001092#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
Paul Brook3c7b48b2010-03-01 04:11:28 +00001093#if !defined(CONFIG_USER_ONLY)
Anthony Liguoric227f092009-10-01 16:12:16 -05001094int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
aurel3293220572008-12-11 22:42:33 +00001095 int rw, int access_type);
Paul Brook3c7b48b2010-03-01 04:11:28 +00001096#endif
bellard9a64fbe2004-01-04 22:58:38 +00001097void do_interrupt (CPUPPCState *env);
j_mayere9df0142007-04-09 22:45:36 +00001098void ppc_hw_interrupt (CPUPPCState *env);
bellarda541f292004-04-12 20:39:29 +00001099
aurel3293220572008-12-11 22:42:33 +00001100void cpu_dump_rfi (target_ulong RA, target_ulong msr);
bellarda541f292004-04-12 20:39:29 +00001101
j_mayer76a66252007-03-07 08:32:30 +00001102#if !defined(CONFIG_USER_ONLY)
aurel3293220572008-12-11 22:42:33 +00001103void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
1104 target_ulong pte0, target_ulong pte1);
aurel3245d827d2008-12-07 13:40:29 +00001105void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
1106void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
1107void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
1108void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
1109void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
1110void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
1111void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
j_mayerd9bce9d2007-03-17 14:02:15 +00001112#if defined(TARGET_PPC64)
j_mayerd9bce9d2007-03-17 14:02:15 +00001113void ppc_store_asr (CPUPPCState *env, target_ulong value);
j_mayer12de9a32007-10-05 22:06:02 +00001114target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
blueswir1f6b868fc2009-03-07 20:50:01 +00001115target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
David Gibson81762d62011-04-01 15:15:08 +11001116int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
David Gibsonefdef952011-04-01 15:15:11 +11001117int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1118int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
j_mayer12de9a32007-10-05 22:06:02 +00001119#endif /* defined(TARGET_PPC64) */
aurel3245d827d2008-12-07 13:40:29 +00001120void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
j_mayer12de9a32007-10-05 22:06:02 +00001121#endif /* !defined(CONFIG_USER_ONLY) */
j_mayer0411a972007-10-25 21:35:50 +00001122void ppc_store_msr (CPUPPCState *env, target_ulong value);
bellard3fc6c082005-07-02 20:59:34 +00001123
Stefan Weil9a78eea2010-10-22 23:03:33 +02001124void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
bellardaaed9092007-11-10 15:15:54 +00001125
David Gibsona1e98582011-10-12 22:40:32 +00001126const ppc_def_t *ppc_find_by_pvr(uint32_t pvr);
Anthony Liguoric227f092009-10-01 16:12:16 -05001127const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1128int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
bellard85c4adf2004-05-23 21:25:39 +00001129
bellard9fddaa02004-05-21 12:59:32 +00001130/* Time-base and decrementer management */
1131#ifndef NO_CPU_IO_DEFS
Alexander Grafe3ea6522009-12-21 12:24:17 +01001132uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
bellard9fddaa02004-05-21 12:59:32 +00001133uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1134void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1135void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
Aurelien Jarnob711de92009-12-21 13:52:08 +01001136uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
j_mayera062e362007-09-30 00:38:38 +00001137uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1138void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1139void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
bellard9fddaa02004-05-21 12:59:32 +00001140uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1141void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
j_mayer58a7d322007-09-29 13:21:37 +00001142uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1143void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1144uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1145void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
j_mayerd9bce9d2007-03-17 14:02:15 +00001146uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1147uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1148#if !defined(CONFIG_USER_ONLY)
1149void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1150void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1151target_ulong load_40x_pit (CPUPPCState *env);
1152void store_40x_pit (CPUPPCState *env, target_ulong val);
j_mayer8ecc7912007-04-16 20:09:45 +00001153void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
j_mayerc294fc52007-04-24 06:44:14 +00001154void store_40x_sler (CPUPPCState *env, uint32_t val);
j_mayerd9bce9d2007-03-17 14:02:15 +00001155void store_booke_tcr (CPUPPCState *env, target_ulong val);
1156void store_booke_tsr (CPUPPCState *env, target_ulong val);
Alexander Graf01662f32011-04-30 23:34:58 +02001157void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
Alexander Grafd1e256f2011-06-16 18:45:43 +02001158target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb);
Alexander Graf01662f32011-04-30 23:34:58 +02001159int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1160 target_phys_addr_t *raddrp, target_ulong address,
1161 uint32_t pid, int ext, int i);
Alexander Grafd1e256f2011-06-16 18:45:43 +02001162int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
1163 target_phys_addr_t *raddrp, target_ulong address,
1164 uint32_t pid);
j_mayer0a032cb2007-04-16 08:56:52 +00001165void ppc_tlb_invalidate_all (CPUPPCState *env);
j_mayerdaf4f962007-10-01 01:51:12 +00001166void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1167#if defined(TARGET_PPC64)
1168void ppc_slb_invalidate_all (CPUPPCState *env);
1169void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
1170#endif
j_mayer36081602007-09-17 08:21:54 +00001171int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
j_mayerd9bce9d2007-03-17 14:02:15 +00001172#endif
bellard9fddaa02004-05-21 12:59:32 +00001173#endif
bellard79aceca2003-11-23 14:55:54 +00001174
Blue Swirl636aa202009-08-16 09:06:54 +00001175static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
j_mayer6b542af2007-11-24 02:03:55 +00001176{
1177 uint64_t gprv;
1178
1179 gprv = env->gpr[gprn];
1180#if !defined(TARGET_PPC64)
1181 if (env->flags & POWERPC_FLAG_SPE) {
1182 /* If the CPU implements the SPE extension, we have to get the
1183 * high bits of the GPR from the gprh storage area
1184 */
1185 gprv &= 0xFFFFFFFFULL;
1186 gprv |= (uint64_t)env->gprh[gprn] << 32;
1187 }
1188#endif
1189
1190 return gprv;
1191}
1192
j_mayer2e719ba2007-04-12 21:11:03 +00001193/* Device control registers */
Alexander Graf73b01962009-12-21 14:02:39 +01001194int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1195int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
j_mayer2e719ba2007-04-12 21:11:03 +00001196
ths9467d442007-06-03 21:02:38 +00001197#define cpu_init cpu_ppc_init
1198#define cpu_exec cpu_ppc_exec
1199#define cpu_gen_code cpu_ppc_gen_code
1200#define cpu_signal_handler cpu_ppc_signal_handler
j_mayerc732abe2007-10-12 06:47:46 +00001201#define cpu_list ppc_cpu_list
ths9467d442007-06-03 21:02:38 +00001202
Blue Swirlfc1c67b2009-04-28 18:00:30 +00001203#define CPU_SAVE_VERSION 4
pbrookb3c77242008-06-30 16:31:04 +00001204
j_mayer6ebbf392007-10-14 07:07:08 +00001205/* MMU modes definitions */
1206#define MMU_MODE0_SUFFIX _user
1207#define MMU_MODE1_SUFFIX _kernel
j_mayer6ebbf392007-10-14 07:07:08 +00001208#define MMU_MODE2_SUFFIX _hypv
j_mayer6ebbf392007-10-14 07:07:08 +00001209#define MMU_USER_IDX 0
1210static inline int cpu_mmu_index (CPUState *env)
1211{
1212 return env->mmu_idx;
1213}
1214
pbrook6e68e072008-05-30 17:22:15 +00001215#if defined(CONFIG_USER_ONLY)
1216static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
1217{
pbrookf8ed7072008-05-30 17:54:15 +00001218 if (newsp)
pbrook6e68e072008-05-30 17:22:15 +00001219 env->gpr[1] = newsp;
Nathan Froydd11f69b2009-08-03 08:43:23 -07001220 env->gpr[3] = 0;
pbrook6e68e072008-05-30 17:22:15 +00001221}
1222#endif
1223
bellard79aceca2003-11-23 14:55:54 +00001224#include "cpu-all.h"
1225
bellard3fc6c082005-07-02 20:59:34 +00001226/*****************************************************************************/
aurel32e1571902008-10-21 11:31:14 +00001227/* CRF definitions */
aurel3257951c22008-11-10 11:10:23 +00001228#define CRF_LT 3
1229#define CRF_GT 2
1230#define CRF_EQ 1
1231#define CRF_SO 0
Nathan Froyde6bba2e2010-02-23 11:55:14 -08001232#define CRF_CH (1 << CRF_LT)
1233#define CRF_CL (1 << CRF_GT)
1234#define CRF_CH_OR_CL (1 << CRF_EQ)
1235#define CRF_CH_AND_CL (1 << CRF_SO)
aurel32e1571902008-10-21 11:31:14 +00001236
1237/* XER definitions */
aurel323d7b4172008-10-21 11:28:46 +00001238#define XER_SO 31
1239#define XER_OV 30
1240#define XER_CA 29
1241#define XER_CMP 8
1242#define XER_BC 0
1243#define xer_so ((env->xer >> XER_SO) & 1)
1244#define xer_ov ((env->xer >> XER_OV) & 1)
1245#define xer_ca ((env->xer >> XER_CA) & 1)
1246#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1247#define xer_bc ((env->xer >> XER_BC) & 0x7F)
bellard79aceca2003-11-23 14:55:54 +00001248
bellard3fc6c082005-07-02 20:59:34 +00001249/* SPR definitions */
j_mayer80d11f42007-11-17 23:02:20 +00001250#define SPR_MQ (0x000)
1251#define SPR_XER (0x001)
1252#define SPR_601_VRTCU (0x004)
1253#define SPR_601_VRTCL (0x005)
1254#define SPR_601_UDECR (0x006)
1255#define SPR_LR (0x008)
1256#define SPR_CTR (0x009)
David Gibson697ab892011-08-31 15:45:10 +00001257#define SPR_DSCR (0x011)
j_mayer80d11f42007-11-17 23:02:20 +00001258#define SPR_DSISR (0x012)
1259#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1260#define SPR_601_RTCU (0x014)
1261#define SPR_601_RTCL (0x015)
1262#define SPR_DECR (0x016)
1263#define SPR_SDR1 (0x019)
1264#define SPR_SRR0 (0x01A)
1265#define SPR_SRR1 (0x01B)
David Gibson697ab892011-08-31 15:45:10 +00001266#define SPR_CFAR (0x01C)
j_mayer80d11f42007-11-17 23:02:20 +00001267#define SPR_AMR (0x01D)
1268#define SPR_BOOKE_PID (0x030)
1269#define SPR_BOOKE_DECAR (0x036)
1270#define SPR_BOOKE_CSRR0 (0x03A)
1271#define SPR_BOOKE_CSRR1 (0x03B)
1272#define SPR_BOOKE_DEAR (0x03D)
1273#define SPR_BOOKE_ESR (0x03E)
1274#define SPR_BOOKE_IVPR (0x03F)
1275#define SPR_MPC_EIE (0x050)
1276#define SPR_MPC_EID (0x051)
1277#define SPR_MPC_NRI (0x052)
1278#define SPR_CTRL (0x088)
1279#define SPR_MPC_CMPA (0x090)
1280#define SPR_MPC_CMPB (0x091)
1281#define SPR_MPC_CMPC (0x092)
1282#define SPR_MPC_CMPD (0x093)
1283#define SPR_MPC_ECR (0x094)
1284#define SPR_MPC_DER (0x095)
1285#define SPR_MPC_COUNTA (0x096)
1286#define SPR_MPC_COUNTB (0x097)
1287#define SPR_UCTRL (0x098)
1288#define SPR_MPC_CMPE (0x098)
1289#define SPR_MPC_CMPF (0x099)
1290#define SPR_MPC_CMPG (0x09A)
1291#define SPR_MPC_CMPH (0x09B)
1292#define SPR_MPC_LCTRL1 (0x09C)
1293#define SPR_MPC_LCTRL2 (0x09D)
1294#define SPR_MPC_ICTRL (0x09E)
1295#define SPR_MPC_BAR (0x09F)
1296#define SPR_VRSAVE (0x100)
1297#define SPR_USPRG0 (0x100)
1298#define SPR_USPRG1 (0x101)
1299#define SPR_USPRG2 (0x102)
1300#define SPR_USPRG3 (0x103)
1301#define SPR_USPRG4 (0x104)
1302#define SPR_USPRG5 (0x105)
1303#define SPR_USPRG6 (0x106)
1304#define SPR_USPRG7 (0x107)
1305#define SPR_VTBL (0x10C)
1306#define SPR_VTBU (0x10D)
1307#define SPR_SPRG0 (0x110)
1308#define SPR_SPRG1 (0x111)
1309#define SPR_SPRG2 (0x112)
1310#define SPR_SPRG3 (0x113)
1311#define SPR_SPRG4 (0x114)
1312#define SPR_SCOMC (0x114)
1313#define SPR_SPRG5 (0x115)
1314#define SPR_SCOMD (0x115)
1315#define SPR_SPRG6 (0x116)
1316#define SPR_SPRG7 (0x117)
1317#define SPR_ASR (0x118)
1318#define SPR_EAR (0x11A)
1319#define SPR_TBL (0x11C)
1320#define SPR_TBU (0x11D)
1321#define SPR_TBU40 (0x11E)
1322#define SPR_SVR (0x11E)
1323#define SPR_BOOKE_PIR (0x11E)
1324#define SPR_PVR (0x11F)
1325#define SPR_HSPRG0 (0x130)
1326#define SPR_BOOKE_DBSR (0x130)
1327#define SPR_HSPRG1 (0x131)
1328#define SPR_HDSISR (0x132)
1329#define SPR_HDAR (0x133)
Scott Wood90dc8812011-04-29 17:10:23 -05001330#define SPR_BOOKE_EPCR (0x133)
David Gibson9d52e902011-04-01 15:15:19 +11001331#define SPR_SPURR (0x134)
j_mayer80d11f42007-11-17 23:02:20 +00001332#define SPR_BOOKE_DBCR0 (0x134)
1333#define SPR_IBCR (0x135)
1334#define SPR_PURR (0x135)
1335#define SPR_BOOKE_DBCR1 (0x135)
1336#define SPR_DBCR (0x136)
1337#define SPR_HDEC (0x136)
1338#define SPR_BOOKE_DBCR2 (0x136)
1339#define SPR_HIOR (0x137)
1340#define SPR_MBAR (0x137)
1341#define SPR_RMOR (0x138)
1342#define SPR_BOOKE_IAC1 (0x138)
1343#define SPR_HRMOR (0x139)
1344#define SPR_BOOKE_IAC2 (0x139)
1345#define SPR_HSRR0 (0x13A)
1346#define SPR_BOOKE_IAC3 (0x13A)
1347#define SPR_HSRR1 (0x13B)
1348#define SPR_BOOKE_IAC4 (0x13B)
1349#define SPR_LPCR (0x13C)
1350#define SPR_BOOKE_DAC1 (0x13C)
1351#define SPR_LPIDR (0x13D)
1352#define SPR_DABR2 (0x13D)
1353#define SPR_BOOKE_DAC2 (0x13D)
1354#define SPR_BOOKE_DVC1 (0x13E)
1355#define SPR_BOOKE_DVC2 (0x13F)
1356#define SPR_BOOKE_TSR (0x150)
1357#define SPR_BOOKE_TCR (0x154)
1358#define SPR_BOOKE_IVOR0 (0x190)
1359#define SPR_BOOKE_IVOR1 (0x191)
1360#define SPR_BOOKE_IVOR2 (0x192)
1361#define SPR_BOOKE_IVOR3 (0x193)
1362#define SPR_BOOKE_IVOR4 (0x194)
1363#define SPR_BOOKE_IVOR5 (0x195)
1364#define SPR_BOOKE_IVOR6 (0x196)
1365#define SPR_BOOKE_IVOR7 (0x197)
1366#define SPR_BOOKE_IVOR8 (0x198)
1367#define SPR_BOOKE_IVOR9 (0x199)
1368#define SPR_BOOKE_IVOR10 (0x19A)
1369#define SPR_BOOKE_IVOR11 (0x19B)
1370#define SPR_BOOKE_IVOR12 (0x19C)
1371#define SPR_BOOKE_IVOR13 (0x19D)
1372#define SPR_BOOKE_IVOR14 (0x19E)
1373#define SPR_BOOKE_IVOR15 (0x19F)
1374#define SPR_BOOKE_SPEFSCR (0x200)
1375#define SPR_Exxx_BBEAR (0x201)
1376#define SPR_Exxx_BBTAR (0x202)
1377#define SPR_Exxx_L1CFG0 (0x203)
1378#define SPR_Exxx_NPIDR (0x205)
1379#define SPR_ATBL (0x20E)
1380#define SPR_ATBU (0x20F)
1381#define SPR_IBAT0U (0x210)
1382#define SPR_BOOKE_IVOR32 (0x210)
1383#define SPR_RCPU_MI_GRA (0x210)
1384#define SPR_IBAT0L (0x211)
1385#define SPR_BOOKE_IVOR33 (0x211)
1386#define SPR_IBAT1U (0x212)
1387#define SPR_BOOKE_IVOR34 (0x212)
1388#define SPR_IBAT1L (0x213)
1389#define SPR_BOOKE_IVOR35 (0x213)
1390#define SPR_IBAT2U (0x214)
1391#define SPR_BOOKE_IVOR36 (0x214)
1392#define SPR_IBAT2L (0x215)
1393#define SPR_BOOKE_IVOR37 (0x215)
1394#define SPR_IBAT3U (0x216)
1395#define SPR_IBAT3L (0x217)
1396#define SPR_DBAT0U (0x218)
1397#define SPR_RCPU_L2U_GRA (0x218)
1398#define SPR_DBAT0L (0x219)
1399#define SPR_DBAT1U (0x21A)
1400#define SPR_DBAT1L (0x21B)
1401#define SPR_DBAT2U (0x21C)
1402#define SPR_DBAT2L (0x21D)
1403#define SPR_DBAT3U (0x21E)
1404#define SPR_DBAT3L (0x21F)
1405#define SPR_IBAT4U (0x230)
1406#define SPR_RPCU_BBCMCR (0x230)
1407#define SPR_MPC_IC_CST (0x230)
1408#define SPR_Exxx_CTXCR (0x230)
1409#define SPR_IBAT4L (0x231)
1410#define SPR_MPC_IC_ADR (0x231)
1411#define SPR_Exxx_DBCR3 (0x231)
1412#define SPR_IBAT5U (0x232)
1413#define SPR_MPC_IC_DAT (0x232)
1414#define SPR_Exxx_DBCNT (0x232)
1415#define SPR_IBAT5L (0x233)
1416#define SPR_IBAT6U (0x234)
1417#define SPR_IBAT6L (0x235)
1418#define SPR_IBAT7U (0x236)
1419#define SPR_IBAT7L (0x237)
1420#define SPR_DBAT4U (0x238)
1421#define SPR_RCPU_L2U_MCR (0x238)
1422#define SPR_MPC_DC_CST (0x238)
1423#define SPR_Exxx_ALTCTXCR (0x238)
1424#define SPR_DBAT4L (0x239)
1425#define SPR_MPC_DC_ADR (0x239)
1426#define SPR_DBAT5U (0x23A)
1427#define SPR_BOOKE_MCSRR0 (0x23A)
1428#define SPR_MPC_DC_DAT (0x23A)
1429#define SPR_DBAT5L (0x23B)
1430#define SPR_BOOKE_MCSRR1 (0x23B)
1431#define SPR_DBAT6U (0x23C)
1432#define SPR_BOOKE_MCSR (0x23C)
1433#define SPR_DBAT6L (0x23D)
1434#define SPR_Exxx_MCAR (0x23D)
1435#define SPR_DBAT7U (0x23E)
1436#define SPR_BOOKE_DSRR0 (0x23E)
1437#define SPR_DBAT7L (0x23F)
1438#define SPR_BOOKE_DSRR1 (0x23F)
1439#define SPR_BOOKE_SPRG8 (0x25C)
1440#define SPR_BOOKE_SPRG9 (0x25D)
1441#define SPR_BOOKE_MAS0 (0x270)
1442#define SPR_BOOKE_MAS1 (0x271)
1443#define SPR_BOOKE_MAS2 (0x272)
1444#define SPR_BOOKE_MAS3 (0x273)
1445#define SPR_BOOKE_MAS4 (0x274)
1446#define SPR_BOOKE_MAS5 (0x275)
1447#define SPR_BOOKE_MAS6 (0x276)
1448#define SPR_BOOKE_PID1 (0x279)
1449#define SPR_BOOKE_PID2 (0x27A)
1450#define SPR_MPC_DPDR (0x280)
1451#define SPR_MPC_IMMR (0x288)
1452#define SPR_BOOKE_TLB0CFG (0x2B0)
1453#define SPR_BOOKE_TLB1CFG (0x2B1)
1454#define SPR_BOOKE_TLB2CFG (0x2B2)
1455#define SPR_BOOKE_TLB3CFG (0x2B3)
1456#define SPR_BOOKE_EPR (0x2BE)
1457#define SPR_PERF0 (0x300)
1458#define SPR_RCPU_MI_RBA0 (0x300)
1459#define SPR_MPC_MI_CTR (0x300)
1460#define SPR_PERF1 (0x301)
1461#define SPR_RCPU_MI_RBA1 (0x301)
1462#define SPR_PERF2 (0x302)
1463#define SPR_RCPU_MI_RBA2 (0x302)
1464#define SPR_MPC_MI_AP (0x302)
1465#define SPR_PERF3 (0x303)
j_mayer082c6682007-11-19 13:22:47 +00001466#define SPR_620_PMC1R (0x303)
j_mayer80d11f42007-11-17 23:02:20 +00001467#define SPR_RCPU_MI_RBA3 (0x303)
1468#define SPR_MPC_MI_EPN (0x303)
1469#define SPR_PERF4 (0x304)
j_mayer082c6682007-11-19 13:22:47 +00001470#define SPR_620_PMC2R (0x304)
j_mayer80d11f42007-11-17 23:02:20 +00001471#define SPR_PERF5 (0x305)
1472#define SPR_MPC_MI_TWC (0x305)
1473#define SPR_PERF6 (0x306)
1474#define SPR_MPC_MI_RPN (0x306)
1475#define SPR_PERF7 (0x307)
1476#define SPR_PERF8 (0x308)
1477#define SPR_RCPU_L2U_RBA0 (0x308)
1478#define SPR_MPC_MD_CTR (0x308)
1479#define SPR_PERF9 (0x309)
1480#define SPR_RCPU_L2U_RBA1 (0x309)
1481#define SPR_MPC_MD_CASID (0x309)
1482#define SPR_PERFA (0x30A)
1483#define SPR_RCPU_L2U_RBA2 (0x30A)
1484#define SPR_MPC_MD_AP (0x30A)
1485#define SPR_PERFB (0x30B)
j_mayer082c6682007-11-19 13:22:47 +00001486#define SPR_620_MMCR0R (0x30B)
j_mayer80d11f42007-11-17 23:02:20 +00001487#define SPR_RCPU_L2U_RBA3 (0x30B)
1488#define SPR_MPC_MD_EPN (0x30B)
1489#define SPR_PERFC (0x30C)
1490#define SPR_MPC_MD_TWB (0x30C)
1491#define SPR_PERFD (0x30D)
1492#define SPR_MPC_MD_TWC (0x30D)
1493#define SPR_PERFE (0x30E)
1494#define SPR_MPC_MD_RPN (0x30E)
1495#define SPR_PERFF (0x30F)
1496#define SPR_MPC_MD_TW (0x30F)
1497#define SPR_UPERF0 (0x310)
1498#define SPR_UPERF1 (0x311)
1499#define SPR_UPERF2 (0x312)
1500#define SPR_UPERF3 (0x313)
j_mayer082c6682007-11-19 13:22:47 +00001501#define SPR_620_PMC1W (0x313)
j_mayer80d11f42007-11-17 23:02:20 +00001502#define SPR_UPERF4 (0x314)
j_mayer082c6682007-11-19 13:22:47 +00001503#define SPR_620_PMC2W (0x314)
j_mayer80d11f42007-11-17 23:02:20 +00001504#define SPR_UPERF5 (0x315)
1505#define SPR_UPERF6 (0x316)
1506#define SPR_UPERF7 (0x317)
1507#define SPR_UPERF8 (0x318)
1508#define SPR_UPERF9 (0x319)
1509#define SPR_UPERFA (0x31A)
1510#define SPR_UPERFB (0x31B)
j_mayer082c6682007-11-19 13:22:47 +00001511#define SPR_620_MMCR0W (0x31B)
j_mayer80d11f42007-11-17 23:02:20 +00001512#define SPR_UPERFC (0x31C)
1513#define SPR_UPERFD (0x31D)
1514#define SPR_UPERFE (0x31E)
1515#define SPR_UPERFF (0x31F)
1516#define SPR_RCPU_MI_RA0 (0x320)
1517#define SPR_MPC_MI_DBCAM (0x320)
1518#define SPR_RCPU_MI_RA1 (0x321)
1519#define SPR_MPC_MI_DBRAM0 (0x321)
1520#define SPR_RCPU_MI_RA2 (0x322)
1521#define SPR_MPC_MI_DBRAM1 (0x322)
1522#define SPR_RCPU_MI_RA3 (0x323)
1523#define SPR_RCPU_L2U_RA0 (0x328)
1524#define SPR_MPC_MD_DBCAM (0x328)
1525#define SPR_RCPU_L2U_RA1 (0x329)
1526#define SPR_MPC_MD_DBRAM0 (0x329)
1527#define SPR_RCPU_L2U_RA2 (0x32A)
1528#define SPR_MPC_MD_DBRAM1 (0x32A)
1529#define SPR_RCPU_L2U_RA3 (0x32B)
1530#define SPR_440_INV0 (0x370)
1531#define SPR_440_INV1 (0x371)
1532#define SPR_440_INV2 (0x372)
1533#define SPR_440_INV3 (0x373)
1534#define SPR_440_ITV0 (0x374)
1535#define SPR_440_ITV1 (0x375)
1536#define SPR_440_ITV2 (0x376)
1537#define SPR_440_ITV3 (0x377)
1538#define SPR_440_CCR1 (0x378)
1539#define SPR_DCRIPR (0x37B)
1540#define SPR_PPR (0x380)
j_mayerbd928eb2007-11-21 13:08:23 +00001541#define SPR_750_GQR0 (0x390)
j_mayer80d11f42007-11-17 23:02:20 +00001542#define SPR_440_DNV0 (0x390)
j_mayerbd928eb2007-11-21 13:08:23 +00001543#define SPR_750_GQR1 (0x391)
j_mayer80d11f42007-11-17 23:02:20 +00001544#define SPR_440_DNV1 (0x391)
j_mayerbd928eb2007-11-21 13:08:23 +00001545#define SPR_750_GQR2 (0x392)
j_mayer80d11f42007-11-17 23:02:20 +00001546#define SPR_440_DNV2 (0x392)
j_mayerbd928eb2007-11-21 13:08:23 +00001547#define SPR_750_GQR3 (0x393)
j_mayer80d11f42007-11-17 23:02:20 +00001548#define SPR_440_DNV3 (0x393)
j_mayerbd928eb2007-11-21 13:08:23 +00001549#define SPR_750_GQR4 (0x394)
j_mayer80d11f42007-11-17 23:02:20 +00001550#define SPR_440_DTV0 (0x394)
j_mayerbd928eb2007-11-21 13:08:23 +00001551#define SPR_750_GQR5 (0x395)
j_mayer80d11f42007-11-17 23:02:20 +00001552#define SPR_440_DTV1 (0x395)
j_mayerbd928eb2007-11-21 13:08:23 +00001553#define SPR_750_GQR6 (0x396)
j_mayer80d11f42007-11-17 23:02:20 +00001554#define SPR_440_DTV2 (0x396)
j_mayerbd928eb2007-11-21 13:08:23 +00001555#define SPR_750_GQR7 (0x397)
j_mayer80d11f42007-11-17 23:02:20 +00001556#define SPR_440_DTV3 (0x397)
j_mayerbd928eb2007-11-21 13:08:23 +00001557#define SPR_750_THRM4 (0x398)
1558#define SPR_750CL_HID2 (0x398)
j_mayer80d11f42007-11-17 23:02:20 +00001559#define SPR_440_DVLIM (0x398)
j_mayerbd928eb2007-11-21 13:08:23 +00001560#define SPR_750_WPAR (0x399)
j_mayer80d11f42007-11-17 23:02:20 +00001561#define SPR_440_IVLIM (0x399)
j_mayerbd928eb2007-11-21 13:08:23 +00001562#define SPR_750_DMAU (0x39A)
1563#define SPR_750_DMAL (0x39B)
j_mayer80d11f42007-11-17 23:02:20 +00001564#define SPR_440_RSTCFG (0x39B)
1565#define SPR_BOOKE_DCDBTRL (0x39C)
1566#define SPR_BOOKE_DCDBTRH (0x39D)
1567#define SPR_BOOKE_ICDBTRL (0x39E)
1568#define SPR_BOOKE_ICDBTRH (0x39F)
1569#define SPR_UMMCR2 (0x3A0)
1570#define SPR_UPMC5 (0x3A1)
1571#define SPR_UPMC6 (0x3A2)
1572#define SPR_UBAMR (0x3A7)
1573#define SPR_UMMCR0 (0x3A8)
1574#define SPR_UPMC1 (0x3A9)
1575#define SPR_UPMC2 (0x3AA)
1576#define SPR_USIAR (0x3AB)
1577#define SPR_UMMCR1 (0x3AC)
1578#define SPR_UPMC3 (0x3AD)
1579#define SPR_UPMC4 (0x3AE)
1580#define SPR_USDA (0x3AF)
1581#define SPR_40x_ZPR (0x3B0)
1582#define SPR_BOOKE_MAS7 (0x3B0)
1583#define SPR_620_PMR0 (0x3B0)
1584#define SPR_MMCR2 (0x3B0)
1585#define SPR_PMC5 (0x3B1)
1586#define SPR_40x_PID (0x3B1)
1587#define SPR_620_PMR1 (0x3B1)
1588#define SPR_PMC6 (0x3B2)
1589#define SPR_440_MMUCR (0x3B2)
1590#define SPR_620_PMR2 (0x3B2)
1591#define SPR_4xx_CCR0 (0x3B3)
1592#define SPR_BOOKE_EPLC (0x3B3)
1593#define SPR_620_PMR3 (0x3B3)
1594#define SPR_405_IAC3 (0x3B4)
1595#define SPR_BOOKE_EPSC (0x3B4)
1596#define SPR_620_PMR4 (0x3B4)
1597#define SPR_405_IAC4 (0x3B5)
1598#define SPR_620_PMR5 (0x3B5)
1599#define SPR_405_DVC1 (0x3B6)
1600#define SPR_620_PMR6 (0x3B6)
1601#define SPR_405_DVC2 (0x3B7)
1602#define SPR_620_PMR7 (0x3B7)
1603#define SPR_BAMR (0x3B7)
1604#define SPR_MMCR0 (0x3B8)
1605#define SPR_620_PMR8 (0x3B8)
1606#define SPR_PMC1 (0x3B9)
1607#define SPR_40x_SGR (0x3B9)
1608#define SPR_620_PMR9 (0x3B9)
1609#define SPR_PMC2 (0x3BA)
1610#define SPR_40x_DCWR (0x3BA)
1611#define SPR_620_PMRA (0x3BA)
1612#define SPR_SIAR (0x3BB)
1613#define SPR_405_SLER (0x3BB)
1614#define SPR_620_PMRB (0x3BB)
1615#define SPR_MMCR1 (0x3BC)
1616#define SPR_405_SU0R (0x3BC)
1617#define SPR_620_PMRC (0x3BC)
1618#define SPR_401_SKR (0x3BC)
1619#define SPR_PMC3 (0x3BD)
1620#define SPR_405_DBCR1 (0x3BD)
1621#define SPR_620_PMRD (0x3BD)
1622#define SPR_PMC4 (0x3BE)
1623#define SPR_620_PMRE (0x3BE)
1624#define SPR_SDA (0x3BF)
1625#define SPR_620_PMRF (0x3BF)
1626#define SPR_403_VTBL (0x3CC)
1627#define SPR_403_VTBU (0x3CD)
1628#define SPR_DMISS (0x3D0)
1629#define SPR_DCMP (0x3D1)
1630#define SPR_HASH1 (0x3D2)
1631#define SPR_HASH2 (0x3D3)
1632#define SPR_BOOKE_ICDBDR (0x3D3)
1633#define SPR_TLBMISS (0x3D4)
1634#define SPR_IMISS (0x3D4)
1635#define SPR_40x_ESR (0x3D4)
1636#define SPR_PTEHI (0x3D5)
1637#define SPR_ICMP (0x3D5)
1638#define SPR_40x_DEAR (0x3D5)
1639#define SPR_PTELO (0x3D6)
1640#define SPR_RPA (0x3D6)
1641#define SPR_40x_EVPR (0x3D6)
1642#define SPR_L3PM (0x3D7)
1643#define SPR_403_CDBCR (0x3D7)
j_mayer4e777442007-12-10 07:40:16 +00001644#define SPR_L3ITCR0 (0x3D8)
j_mayer80d11f42007-11-17 23:02:20 +00001645#define SPR_TCR (0x3D8)
1646#define SPR_40x_TSR (0x3D8)
1647#define SPR_IBR (0x3DA)
1648#define SPR_40x_TCR (0x3DA)
1649#define SPR_ESASRR (0x3DB)
1650#define SPR_40x_PIT (0x3DB)
1651#define SPR_403_TBL (0x3DC)
1652#define SPR_403_TBU (0x3DD)
1653#define SPR_SEBR (0x3DE)
1654#define SPR_40x_SRR2 (0x3DE)
1655#define SPR_SER (0x3DF)
1656#define SPR_40x_SRR3 (0x3DF)
j_mayer4e777442007-12-10 07:40:16 +00001657#define SPR_L3OHCR (0x3E8)
j_mayer80d11f42007-11-17 23:02:20 +00001658#define SPR_L3ITCR1 (0x3E9)
1659#define SPR_L3ITCR2 (0x3EA)
1660#define SPR_L3ITCR3 (0x3EB)
1661#define SPR_HID0 (0x3F0)
1662#define SPR_40x_DBSR (0x3F0)
1663#define SPR_HID1 (0x3F1)
1664#define SPR_IABR (0x3F2)
1665#define SPR_40x_DBCR0 (0x3F2)
1666#define SPR_601_HID2 (0x3F2)
1667#define SPR_Exxx_L1CSR0 (0x3F2)
1668#define SPR_ICTRL (0x3F3)
1669#define SPR_HID2 (0x3F3)
j_mayerbd928eb2007-11-21 13:08:23 +00001670#define SPR_750CL_HID4 (0x3F3)
j_mayer80d11f42007-11-17 23:02:20 +00001671#define SPR_Exxx_L1CSR1 (0x3F3)
1672#define SPR_440_DBDR (0x3F3)
1673#define SPR_LDSTDB (0x3F4)
j_mayerbd928eb2007-11-21 13:08:23 +00001674#define SPR_750_TDCL (0x3F4)
j_mayer80d11f42007-11-17 23:02:20 +00001675#define SPR_40x_IAC1 (0x3F4)
1676#define SPR_MMUCSR0 (0x3F4)
1677#define SPR_DABR (0x3F5)
bellard3fc6c082005-07-02 20:59:34 +00001678#define DABR_MASK (~(target_ulong)0x7)
j_mayer80d11f42007-11-17 23:02:20 +00001679#define SPR_Exxx_BUCSR (0x3F5)
1680#define SPR_40x_IAC2 (0x3F5)
1681#define SPR_601_HID5 (0x3F5)
1682#define SPR_40x_DAC1 (0x3F6)
1683#define SPR_MSSCR0 (0x3F6)
1684#define SPR_970_HID5 (0x3F6)
1685#define SPR_MSSSR0 (0x3F7)
j_mayer4e777442007-12-10 07:40:16 +00001686#define SPR_MSSCR1 (0x3F7)
j_mayer80d11f42007-11-17 23:02:20 +00001687#define SPR_DABRX (0x3F7)
1688#define SPR_40x_DAC2 (0x3F7)
1689#define SPR_MMUCFG (0x3F7)
1690#define SPR_LDSTCR (0x3F8)
1691#define SPR_L2PMCR (0x3F8)
j_mayerbd928eb2007-11-21 13:08:23 +00001692#define SPR_750FX_HID2 (0x3F8)
j_mayer082c6682007-11-19 13:22:47 +00001693#define SPR_620_BUSCSR (0x3F8)
j_mayer80d11f42007-11-17 23:02:20 +00001694#define SPR_Exxx_L1FINV0 (0x3F8)
1695#define SPR_L2CR (0x3F9)
j_mayer082c6682007-11-19 13:22:47 +00001696#define SPR_620_L2CR (0x3F9)
j_mayer80d11f42007-11-17 23:02:20 +00001697#define SPR_L3CR (0x3FA)
j_mayerbd928eb2007-11-21 13:08:23 +00001698#define SPR_750_TDCH (0x3FA)
j_mayer80d11f42007-11-17 23:02:20 +00001699#define SPR_IABR2 (0x3FA)
1700#define SPR_40x_DCCR (0x3FA)
j_mayer082c6682007-11-19 13:22:47 +00001701#define SPR_620_L2SR (0x3FA)
j_mayer80d11f42007-11-17 23:02:20 +00001702#define SPR_ICTC (0x3FB)
1703#define SPR_40x_ICCR (0x3FB)
1704#define SPR_THRM1 (0x3FC)
1705#define SPR_403_PBL1 (0x3FC)
1706#define SPR_SP (0x3FD)
1707#define SPR_THRM2 (0x3FD)
1708#define SPR_403_PBU1 (0x3FD)
1709#define SPR_604_HID13 (0x3FD)
1710#define SPR_LT (0x3FE)
1711#define SPR_THRM3 (0x3FE)
1712#define SPR_RCPU_FPECR (0x3FE)
1713#define SPR_403_PBL2 (0x3FE)
1714#define SPR_PIR (0x3FF)
1715#define SPR_403_PBU2 (0x3FF)
1716#define SPR_601_HID15 (0x3FF)
1717#define SPR_604_HID15 (0x3FF)
1718#define SPR_E500_SVR (0x3FF)
bellard79aceca2003-11-23 14:55:54 +00001719
j_mayer76a66252007-03-07 08:32:30 +00001720/*****************************************************************************/
Nathan Froydc29b7352009-05-12 12:26:57 -07001721/* PowerPC Instructions types definitions */
1722enum {
1723 PPC_NONE = 0x0000000000000000ULL,
1724 /* PowerPC base instructions set */
1725 PPC_INSNS_BASE = 0x0000000000000001ULL,
1726 /* integer operations instructions */
1727#define PPC_INTEGER PPC_INSNS_BASE
1728 /* flow control instructions */
1729#define PPC_FLOW PPC_INSNS_BASE
1730 /* virtual memory instructions */
1731#define PPC_MEM PPC_INSNS_BASE
1732 /* ld/st with reservation instructions */
1733#define PPC_RES PPC_INSNS_BASE
1734 /* spr/msr access instructions */
1735#define PPC_MISC PPC_INSNS_BASE
1736 /* Deprecated instruction sets */
1737 /* Original POWER instruction set */
1738 PPC_POWER = 0x0000000000000002ULL,
1739 /* POWER2 instruction set extension */
1740 PPC_POWER2 = 0x0000000000000004ULL,
1741 /* Power RTC support */
1742 PPC_POWER_RTC = 0x0000000000000008ULL,
1743 /* Power-to-PowerPC bridge (601) */
1744 PPC_POWER_BR = 0x0000000000000010ULL,
1745 /* 64 bits PowerPC instruction set */
1746 PPC_64B = 0x0000000000000020ULL,
1747 /* New 64 bits extensions (PowerPC 2.0x) */
1748 PPC_64BX = 0x0000000000000040ULL,
1749 /* 64 bits hypervisor extensions */
1750 PPC_64H = 0x0000000000000080ULL,
1751 /* New wait instruction (PowerPC 2.0x) */
1752 PPC_WAIT = 0x0000000000000100ULL,
1753 /* Time base mftb instruction */
1754 PPC_MFTB = 0x0000000000000200ULL,
1755
1756 /* Fixed-point unit extensions */
1757 /* PowerPC 602 specific */
1758 PPC_602_SPEC = 0x0000000000000400ULL,
1759 /* isel instruction */
1760 PPC_ISEL = 0x0000000000000800ULL,
1761 /* popcntb instruction */
1762 PPC_POPCNTB = 0x0000000000001000ULL,
1763 /* string load / store */
1764 PPC_STRING = 0x0000000000002000ULL,
1765
1766 /* Floating-point unit extensions */
1767 /* Optional floating point instructions */
1768 PPC_FLOAT = 0x0000000000010000ULL,
1769 /* New floating-point extensions (PowerPC 2.0x) */
1770 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1771 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1772 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1773 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1774 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1775 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1776 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1777
1778 /* Vector/SIMD extensions */
1779 /* Altivec support */
1780 PPC_ALTIVEC = 0x0000000001000000ULL,
1781 /* PowerPC 2.03 SPE extension */
1782 PPC_SPE = 0x0000000002000000ULL,
1783 /* PowerPC 2.03 SPE single-precision floating-point extension */
1784 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1785 /* PowerPC 2.03 SPE double-precision floating-point extension */
1786 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1787
1788 /* Optional memory control instructions */
1789 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1790 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1791 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1792 /* sync instruction */
1793 PPC_MEM_SYNC = 0x0000000080000000ULL,
1794 /* eieio instruction */
1795 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1796
1797 /* Cache control instructions */
1798 PPC_CACHE = 0x0000000200000000ULL,
1799 /* icbi instruction */
1800 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1801 /* dcbz instruction with fixed cache line size */
1802 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1803 /* dcbz instruction with tunable cache line size */
1804 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1805 /* dcba instruction */
1806 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1807 /* Freescale cache locking instructions */
1808 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1809
1810 /* MMU related extensions */
1811 /* external control instructions */
1812 PPC_EXTERN = 0x0000010000000000ULL,
1813 /* segment register access instructions */
1814 PPC_SEGMENT = 0x0000020000000000ULL,
1815 /* PowerPC 6xx TLB management instructions */
1816 PPC_6xx_TLB = 0x0000040000000000ULL,
1817 /* PowerPC 74xx TLB management instructions */
1818 PPC_74xx_TLB = 0x0000080000000000ULL,
1819 /* PowerPC 40x TLB management instructions */
1820 PPC_40x_TLB = 0x0000100000000000ULL,
1821 /* segment register access instructions for PowerPC 64 "bridge" */
1822 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1823 /* SLB management */
1824 PPC_SLBI = 0x0000400000000000ULL,
1825
1826 /* Embedded PowerPC dedicated instructions */
1827 PPC_WRTEE = 0x0001000000000000ULL,
1828 /* PowerPC 40x exception model */
1829 PPC_40x_EXCP = 0x0002000000000000ULL,
1830 /* PowerPC 405 Mac instructions */
1831 PPC_405_MAC = 0x0004000000000000ULL,
1832 /* PowerPC 440 specific instructions */
1833 PPC_440_SPEC = 0x0008000000000000ULL,
1834 /* BookE (embedded) PowerPC specification */
1835 PPC_BOOKE = 0x0010000000000000ULL,
1836 /* mfapidi instruction */
1837 PPC_MFAPIDI = 0x0020000000000000ULL,
1838 /* tlbiva instruction */
1839 PPC_TLBIVA = 0x0040000000000000ULL,
1840 /* tlbivax instruction */
1841 PPC_TLBIVAX = 0x0080000000000000ULL,
1842 /* PowerPC 4xx dedicated instructions */
1843 PPC_4xx_COMMON = 0x0100000000000000ULL,
1844 /* PowerPC 40x ibct instructions */
1845 PPC_40x_ICBT = 0x0200000000000000ULL,
1846 /* rfmci is not implemented in all BookE PowerPC */
1847 PPC_RFMCI = 0x0400000000000000ULL,
1848 /* rfdi instruction */
1849 PPC_RFDI = 0x0800000000000000ULL,
1850 /* DCR accesses */
1851 PPC_DCR = 0x1000000000000000ULL,
1852 /* DCR extended accesse */
1853 PPC_DCRX = 0x2000000000000000ULL,
1854 /* user-mode DCR access, implemented in PowerPC 460 */
1855 PPC_DCRUX = 0x4000000000000000ULL,
David Gibsoneaabeef2011-04-01 15:15:13 +11001856 /* popcntw and popcntd instructions */
1857 PPC_POPCNTWD = 0x8000000000000000ULL,
Alexander Graf01662f32011-04-30 23:34:58 +02001858
David Gibson02d4eae2011-10-30 15:51:24 +00001859#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1860 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1861 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1862 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1863 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1864 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1865 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1866 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1867 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1868 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1869 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1870 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1871 | PPC_CACHE | PPC_CACHE_ICBI \
1872 | PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \
1873 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1874 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1875 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1876 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1877 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1878 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1879 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1880 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1881 | PPC_POPCNTWD)
1882
Alexander Graf01662f32011-04-30 23:34:58 +02001883 /* extended type values */
1884
1885 /* BookE 2.06 PowerPC specification */
1886 PPC2_BOOKE206 = 0x0000000000000001ULL,
David Gibsona7342582011-10-17 18:15:41 +00001887 /* VSX (extensions to Altivec / VMX) */
1888 PPC2_VSX = 0x0000000000000002ULL,
1889 /* Decimal Floating Point (DFP) */
1890 PPC2_DFP = 0x0000000000000004ULL,
David Gibson02d4eae2011-10-30 15:51:24 +00001891
1892#define PPC_TCG_INSNS2 (PPC2_BOOKE206)
Nathan Froydc29b7352009-05-12 12:26:57 -07001893};
1894
1895/*****************************************************************************/
bellard9a64fbe2004-01-04 22:58:38 +00001896/* Memory access type :
1897 * may be needed for precise access rights control and precise exceptions.
1898 */
bellard79aceca2003-11-23 14:55:54 +00001899enum {
bellard9a64fbe2004-01-04 22:58:38 +00001900 /* 1 bit to define user level / supervisor access */
1901 ACCESS_USER = 0x00,
1902 ACCESS_SUPER = 0x01,
1903 /* Type of instruction that generated the access */
1904 ACCESS_CODE = 0x10, /* Code fetch access */
1905 ACCESS_INT = 0x20, /* Integer load/store access */
1906 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1907 ACCESS_RES = 0x40, /* load/store with reservation */
1908 ACCESS_EXT = 0x50, /* external access */
1909 ACCESS_CACHE = 0x60, /* Cache manipulation */
1910};
1911
j_mayer47103572007-03-30 09:38:04 +00001912/* Hardware interruption sources:
1913 * all those exception can be raised simulteaneously
1914 */
j_mayere9df0142007-04-09 22:45:36 +00001915/* Input pins definitions */
j_mayer47103572007-03-30 09:38:04 +00001916enum {
j_mayere9df0142007-04-09 22:45:36 +00001917 /* 6xx bus input pins */
j_mayer24be5ae2007-04-12 21:24:29 +00001918 PPC6xx_INPUT_HRESET = 0,
1919 PPC6xx_INPUT_SRESET = 1,
1920 PPC6xx_INPUT_CKSTP_IN = 2,
1921 PPC6xx_INPUT_MCP = 3,
1922 PPC6xx_INPUT_SMI = 4,
1923 PPC6xx_INPUT_INT = 5,
j_mayerd68f1302007-10-14 09:27:16 +00001924 PPC6xx_INPUT_TBEN = 6,
1925 PPC6xx_INPUT_WAKEUP = 7,
1926 PPC6xx_INPUT_NB,
j_mayer24be5ae2007-04-12 21:24:29 +00001927};
1928
1929enum {
j_mayere9df0142007-04-09 22:45:36 +00001930 /* Embedded PowerPC input pins */
j_mayer24be5ae2007-04-12 21:24:29 +00001931 PPCBookE_INPUT_HRESET = 0,
1932 PPCBookE_INPUT_SRESET = 1,
1933 PPCBookE_INPUT_CKSTP_IN = 2,
1934 PPCBookE_INPUT_MCP = 3,
1935 PPCBookE_INPUT_SMI = 4,
1936 PPCBookE_INPUT_INT = 5,
1937 PPCBookE_INPUT_CINT = 6,
j_mayerd68f1302007-10-14 09:27:16 +00001938 PPCBookE_INPUT_NB,
j_mayer24be5ae2007-04-12 21:24:29 +00001939};
1940
1941enum {
aurel329fdc60b2009-03-02 16:42:32 +00001942 /* PowerPC E500 input pins */
1943 PPCE500_INPUT_RESET_CORE = 0,
1944 PPCE500_INPUT_MCK = 1,
1945 PPCE500_INPUT_CINT = 3,
1946 PPCE500_INPUT_INT = 4,
1947 PPCE500_INPUT_DEBUG = 6,
1948 PPCE500_INPUT_NB,
1949};
1950
1951enum {
j_mayer4e290a02007-10-01 01:27:10 +00001952 /* PowerPC 40x input pins */
1953 PPC40x_INPUT_RESET_CORE = 0,
1954 PPC40x_INPUT_RESET_CHIP = 1,
1955 PPC40x_INPUT_RESET_SYS = 2,
1956 PPC40x_INPUT_CINT = 3,
1957 PPC40x_INPUT_INT = 4,
1958 PPC40x_INPUT_HALT = 5,
1959 PPC40x_INPUT_DEBUG = 6,
1960 PPC40x_INPUT_NB,
j_mayere9df0142007-04-09 22:45:36 +00001961};
1962
j_mayerb4095fe2007-11-17 22:42:36 +00001963enum {
1964 /* RCPU input pins */
1965 PPCRCPU_INPUT_PORESET = 0,
1966 PPCRCPU_INPUT_HRESET = 1,
1967 PPCRCPU_INPUT_SRESET = 2,
1968 PPCRCPU_INPUT_IRQ0 = 3,
1969 PPCRCPU_INPUT_IRQ1 = 4,
1970 PPCRCPU_INPUT_IRQ2 = 5,
1971 PPCRCPU_INPUT_IRQ3 = 6,
1972 PPCRCPU_INPUT_IRQ4 = 7,
1973 PPCRCPU_INPUT_IRQ5 = 8,
1974 PPCRCPU_INPUT_IRQ6 = 9,
1975 PPCRCPU_INPUT_IRQ7 = 10,
1976 PPCRCPU_INPUT_NB,
1977};
1978
j_mayer00af6852007-10-03 01:05:39 +00001979#if defined(TARGET_PPC64)
j_mayerd0dfae62007-04-16 07:34:39 +00001980enum {
1981 /* PowerPC 970 input pins */
1982 PPC970_INPUT_HRESET = 0,
1983 PPC970_INPUT_SRESET = 1,
1984 PPC970_INPUT_CKSTP = 2,
1985 PPC970_INPUT_TBEN = 3,
1986 PPC970_INPUT_MCP = 4,
1987 PPC970_INPUT_INT = 5,
1988 PPC970_INPUT_THINT = 6,
j_mayer7b62a952007-11-17 02:04:00 +00001989 PPC970_INPUT_NB,
j_mayerd0dfae62007-04-16 07:34:39 +00001990};
David Gibson9d52e902011-04-01 15:15:19 +11001991
1992enum {
1993 /* POWER7 input pins */
1994 POWER7_INPUT_INT = 0,
1995 /* POWER7 probably has other inputs, but we don't care about them
1996 * for any existing machine. We can wire these up when we need
1997 * them */
1998 POWER7_INPUT_NB,
1999};
j_mayer00af6852007-10-03 01:05:39 +00002000#endif
j_mayerd0dfae62007-04-16 07:34:39 +00002001
j_mayere9df0142007-04-09 22:45:36 +00002002/* Hardware exceptions definitions */
2003enum {
2004 /* External hardware exception sources */
j_mayere1833e12007-09-29 13:06:16 +00002005 PPC_INTERRUPT_RESET = 0, /* Reset exception */
j_mayerd68f1302007-10-14 09:27:16 +00002006 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2007 PPC_INTERRUPT_MCK, /* Machine check exception */
2008 PPC_INTERRUPT_EXT, /* External interrupt */
2009 PPC_INTERRUPT_SMI, /* System management interrupt */
2010 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2011 PPC_INTERRUPT_DEBUG, /* External debug exception */
2012 PPC_INTERRUPT_THERM, /* Thermal exception */
j_mayere9df0142007-04-09 22:45:36 +00002013 /* Internal hardware exception sources */
j_mayerd68f1302007-10-14 09:27:16 +00002014 PPC_INTERRUPT_DECR, /* Decrementer exception */
2015 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2016 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2017 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2018 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2019 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2020 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2021 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
j_mayer47103572007-03-30 09:38:04 +00002022};
2023
bellard9a64fbe2004-01-04 22:58:38 +00002024/*****************************************************************************/
bellard79aceca2003-11-23 14:55:54 +00002025
aliguori6b917542008-11-18 19:46:41 +00002026static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
2027 target_ulong *cs_base, int *flags)
2028{
2029 *pc = env->nip;
2030 *cs_base = 0;
2031 *flags = env->hflags;
2032}
2033
Nathan Froyd174c80d2009-08-03 08:43:24 -07002034static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
2035{
2036#if defined(TARGET_PPC64)
2037 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2038 binaries on PPC64 yet. */
2039 env->gpr[13] = newtls;
2040#else
2041 env->gpr[2] = newtls;
2042#endif
2043}
2044
Alexander Graf01662f32011-04-30 23:34:58 +02002045#if !defined(CONFIG_USER_ONLY)
Alexander Grafd1e256f2011-06-16 18:45:43 +02002046static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm)
Alexander Graf01662f32011-04-30 23:34:58 +02002047{
Alexander Grafd1e256f2011-06-16 18:45:43 +02002048 uintptr_t tlbml = (uintptr_t)tlbm;
Alexander Graf1c53acc2011-06-17 01:00:28 +02002049 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
Alexander Graf01662f32011-04-30 23:34:58 +02002050
Alexander Graf1c53acc2011-06-17 01:00:28 +02002051 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
Alexander Graf01662f32011-04-30 23:34:58 +02002052}
2053
2054static inline int booke206_tlb_size(CPUState *env, int tlbn)
2055{
2056 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2057 int r = tlbncfg & TLBnCFG_N_ENTRY;
2058 return r;
2059}
2060
2061static inline int booke206_tlb_ways(CPUState *env, int tlbn)
2062{
2063 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2064 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2065 return r;
2066}
2067
Alexander Grafd1e256f2011-06-16 18:45:43 +02002068static inline int booke206_tlbm_to_tlbn(CPUState *env, ppcmas_tlb_t *tlbm)
Alexander Graf01662f32011-04-30 23:34:58 +02002069{
Alexander Grafd1e256f2011-06-16 18:45:43 +02002070 int id = booke206_tlbm_id(env, tlbm);
Alexander Graf01662f32011-04-30 23:34:58 +02002071 int end = 0;
2072 int i;
2073
2074 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2075 end += booke206_tlb_size(env, i);
2076 if (id < end) {
2077 return i;
2078 }
2079 }
2080
2081 cpu_abort(env, "Unknown TLBe: %d\n", id);
2082 return 0;
2083}
2084
Alexander Grafd1e256f2011-06-16 18:45:43 +02002085static inline int booke206_tlbm_to_way(CPUState *env, ppcmas_tlb_t *tlb)
Alexander Graf01662f32011-04-30 23:34:58 +02002086{
Alexander Grafd1e256f2011-06-16 18:45:43 +02002087 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2088 int tlbid = booke206_tlbm_id(env, tlb);
Alexander Graf01662f32011-04-30 23:34:58 +02002089 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2090}
2091
Alexander Grafd1e256f2011-06-16 18:45:43 +02002092static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
Alexander Graf01662f32011-04-30 23:34:58 +02002093 target_ulong ea, int way)
2094{
2095 int r;
2096 uint32_t ways = booke206_tlb_ways(env, tlbn);
2097 int ways_bits = ffs(ways) - 1;
2098 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2099 int i;
2100
2101 way &= ways - 1;
2102 ea >>= MAS2_EPN_SHIFT;
2103 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2104 r = (ea << ways_bits) | way;
2105
2106 /* bump up to tlbn index */
2107 for (i = 0; i < tlbn; i++) {
2108 r += booke206_tlb_size(env, i);
2109 }
2110
Alexander Graf1c53acc2011-06-17 01:00:28 +02002111 return &env->tlb.tlbm[r];
Alexander Graf01662f32011-04-30 23:34:58 +02002112}
2113
2114#endif
2115
David Gibsond5699562011-04-01 15:15:10 +11002116extern void (*cpu_ppc_hypercall)(CPUState *);
2117
Blue Swirlf081c762011-05-21 07:10:23 +00002118static inline bool cpu_has_work(CPUState *env)
2119{
2120 return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
2121}
2122
2123#include "exec-all.h"
2124
2125static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
2126{
2127 env->nip = tb->pc;
2128}
2129
Scott Woodbebabbc2011-08-18 10:38:42 +00002130void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
2131
bellard79aceca2003-11-23 14:55:54 +00002132#endif /* !defined (__CPU_PPC_H__) */