Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Xilinx Zynq Baseboard System emulation. |
| 3 | * |
| 4 | * Copyright (c) 2010 Xilinx. |
| 5 | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) |
| 6 | * Copyright (c) 2012 Petalogix Pty Ltd. |
| 7 | * Written by Haibing Ma |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
Peter Maydell | 12b1672 | 2015-12-07 16:23:45 +0000 | [diff] [blame] | 18 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 19 | #include "qapi/error.h" |
Paolo Bonzini | 4771d75 | 2016-01-19 21:51:44 +0100 | [diff] [blame] | 20 | #include "qemu-common.h" |
| 21 | #include "cpu.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 22 | #include "hw/sysbus.h" |
Peter Maydell | bd2be15 | 2013-04-09 15:26:55 +0100 | [diff] [blame] | 23 | #include "hw/arm/arm.h" |
Paolo Bonzini | 1422e32 | 2012-10-24 08:43:34 +0200 | [diff] [blame] | 24 | #include "net/net.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 25 | #include "exec/address-spaces.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 26 | #include "sysemu/sysemu.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 27 | #include "hw/boards.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 28 | #include "hw/block/flash.h" |
Markus Armbruster | fa1d36d | 2014-10-07 13:59:13 +0200 | [diff] [blame] | 29 | #include "sysemu/block-backend.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 30 | #include "hw/loader.h" |
Guenter Roeck | 74fcbd2 | 2015-11-12 09:54:55 -0800 | [diff] [blame] | 31 | #include "hw/misc/zynq-xadc.h" |
Alistair Francis | 8fd0671 | 2016-01-21 14:15:03 +0000 | [diff] [blame] | 32 | #include "hw/ssi/ssi.h" |
Peter Crosthwaite | d8bbdcf | 2013-12-17 19:42:28 +0000 | [diff] [blame] | 33 | #include "qemu/error-report.h" |
Peter Maydell | eb4f566 | 2016-02-18 14:16:18 +0000 | [diff] [blame] | 34 | #include "hw/sd/sd.h" |
xiaoqiang zhao | 4be12ea | 2016-06-06 16:59:31 +0100 | [diff] [blame] | 35 | #include "hw/char/cadence_uart.h" |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 36 | |
| 37 | #define NUM_SPI_FLASHES 4 |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 38 | #define NUM_QSPI_FLASHES 2 |
| 39 | #define NUM_QSPI_BUSSES 2 |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 40 | |
| 41 | #define FLASH_SIZE (64 * 1024 * 1024) |
| 42 | #define FLASH_SECTOR_SIZE (128 * 1024) |
| 43 | |
| 44 | #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ |
| 45 | |
Peter Crosthwaite | c257712 | 2013-12-17 19:42:29 +0000 | [diff] [blame] | 46 | #define MPCORE_PERIPHBASE 0xF8F00000 |
Alistair Francis | b48adc0d | 2014-01-31 14:47:33 +0000 | [diff] [blame] | 47 | #define ZYNQ_BOARD_MIDR 0x413FC090 |
Peter Crosthwaite | c257712 | 2013-12-17 19:42:29 +0000 | [diff] [blame] | 48 | |
Peter Crosthwaite | 7451afb | 2013-03-15 16:41:58 +0000 | [diff] [blame] | 49 | static const int dma_irqs[8] = { |
| 50 | 46, 47, 48, 49, 72, 73, 74, 75 |
| 51 | }; |
| 52 | |
Peter Crosthwaite | c3a9a68 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 53 | #define BOARD_SETUP_ADDR 0x100 |
| 54 | |
| 55 | #define SLCR_LOCK_OFFSET 0x004 |
| 56 | #define SLCR_UNLOCK_OFFSET 0x008 |
| 57 | #define SLCR_ARM_PLL_OFFSET 0x100 |
| 58 | |
| 59 | #define SLCR_XILINX_UNLOCK_KEY 0xdf0d |
| 60 | #define SLCR_XILINX_LOCK_KEY 0x767b |
| 61 | |
| 62 | #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ |
| 63 | extract32((x), 12, 4) << 16) |
| 64 | |
| 65 | /* Write immediate val to address r0 + addr. r0 should contain base offset |
| 66 | * of the SLCR block. Clobbers r1. |
| 67 | */ |
| 68 | |
| 69 | #define SLCR_WRITE(addr, val) \ |
| 70 | 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ |
| 71 | 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ |
| 72 | 0xe5801000 + (addr) |
| 73 | |
| 74 | static void zynq_write_board_setup(ARMCPU *cpu, |
| 75 | const struct arm_boot_info *info) |
| 76 | { |
| 77 | int n; |
| 78 | uint32_t board_setup_blob[] = { |
| 79 | 0xe3a004f8, /* mov r0, #0xf8000000 */ |
| 80 | SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), |
| 81 | SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), |
| 82 | SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), |
| 83 | 0xe12fff1e, /* bx lr */ |
| 84 | }; |
| 85 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { |
| 86 | board_setup_blob[n] = tswap32(board_setup_blob[n]); |
| 87 | } |
| 88 | rom_add_blob_fixed("board-setup", board_setup_blob, |
| 89 | sizeof(board_setup_blob), BOARD_SETUP_ADDR); |
| 90 | } |
| 91 | |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 92 | static struct arm_boot_info zynq_binfo = {}; |
| 93 | |
| 94 | static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
| 95 | { |
| 96 | DeviceState *dev; |
| 97 | SysBusDevice *s; |
| 98 | |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 99 | dev = qdev_create(NULL, "cadence_gem"); |
Peter Crosthwaite | 7fcd57e | 2014-01-03 17:58:43 -0800 | [diff] [blame] | 100 | if (nd->used) { |
| 101 | qemu_check_nic_model(nd, "cadence_gem"); |
| 102 | qdev_set_nic_properties(dev, nd); |
| 103 | } |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 104 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 105 | s = SYS_BUS_DEVICE(dev); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 106 | sysbus_mmio_map(s, 0, base); |
| 107 | sysbus_connect_irq(s, 0, irq); |
| 108 | } |
| 109 | |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 110 | static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, |
| 111 | bool is_qspi) |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 112 | { |
| 113 | DeviceState *dev; |
| 114 | SysBusDevice *busdev; |
| 115 | SSIBus *spi; |
walimis | 79f5d67 | 2012-12-11 11:30:37 +0000 | [diff] [blame] | 116 | DeviceState *flash_dev; |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 117 | int i, j; |
| 118 | int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; |
| 119 | int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 120 | |
Peter Crosthwaite | 6b91f01 | 2013-06-03 17:17:41 +0100 | [diff] [blame] | 121 | dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 122 | qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); |
| 123 | qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); |
| 124 | qdev_prop_set_uint8(dev, "num-busses", num_busses); |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 125 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 126 | busdev = SYS_BUS_DEVICE(dev); |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 127 | sysbus_mmio_map(busdev, 0, base_addr); |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 128 | if (is_qspi) { |
| 129 | sysbus_mmio_map(busdev, 1, 0xFC000000); |
| 130 | } |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 131 | sysbus_connect_irq(busdev, 0, irq); |
| 132 | |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 133 | for (i = 0; i < num_busses; ++i) { |
| 134 | char bus_name[16]; |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 135 | qemu_irq cs_line; |
| 136 | |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 137 | snprintf(bus_name, 16, "spi%d", i); |
| 138 | spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 139 | |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 140 | for (j = 0; j < num_ss; ++j) { |
Paolo Bonzini | 73bce51 | 2016-07-04 13:06:37 +0100 | [diff] [blame] | 141 | DriveInfo *dinfo = drive_get_next(IF_MTD); |
| 142 | flash_dev = ssi_create_slave_no_init(spi, "n25q128"); |
| 143 | if (dinfo) { |
| 144 | qdev_prop_set_drive(flash_dev, "drive", |
| 145 | blk_by_legacy_dinfo(dinfo), &error_fatal); |
| 146 | } |
| 147 | qdev_init_nofail(flash_dev); |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 148 | |
Peter Crosthwaite | de77914 | 2014-05-19 23:31:33 -0700 | [diff] [blame] | 149 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 150 | sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); |
| 151 | } |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | } |
| 155 | |
Marcel Apfelbaum | 3ef9622 | 2014-05-07 17:42:57 +0300 | [diff] [blame] | 156 | static void zynq_init(MachineState *machine) |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 157 | { |
Marcel Apfelbaum | 3ef9622 | 2014-05-07 17:42:57 +0300 | [diff] [blame] | 158 | ram_addr_t ram_size = machine->ram_size; |
| 159 | const char *cpu_model = machine->cpu_model; |
| 160 | const char *kernel_filename = machine->kernel_filename; |
| 161 | const char *kernel_cmdline = machine->kernel_cmdline; |
| 162 | const char *initrd_filename = machine->initrd_filename; |
Peter Crosthwaite | d8bbdcf | 2013-12-17 19:42:28 +0000 | [diff] [blame] | 163 | ObjectClass *cpu_oc; |
Andreas Färber | 17c2f0b | 2012-05-14 02:55:25 +0200 | [diff] [blame] | 164 | ARMCPU *cpu; |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 165 | MemoryRegion *address_space_mem = get_system_memory(); |
| 166 | MemoryRegion *ext_ram = g_new(MemoryRegion, 1); |
| 167 | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); |
Peter Maydell | eb4f566 | 2016-02-18 14:16:18 +0000 | [diff] [blame] | 168 | DeviceState *dev, *carddev; |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 169 | SysBusDevice *busdev; |
Peter Maydell | eb4f566 | 2016-02-18 14:16:18 +0000 | [diff] [blame] | 170 | DriveInfo *di; |
| 171 | BlockBackend *blk; |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 172 | qemu_irq pic[64]; |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 173 | int n; |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 174 | |
| 175 | if (!cpu_model) { |
| 176 | cpu_model = "cortex-a9"; |
| 177 | } |
Peter Crosthwaite | d8bbdcf | 2013-12-17 19:42:28 +0000 | [diff] [blame] | 178 | cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 179 | |
Peter Crosthwaite | d8bbdcf | 2013-12-17 19:42:28 +0000 | [diff] [blame] | 180 | cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); |
| 181 | |
Greg Bellows | 61e2f35 | 2014-12-15 17:09:51 -0600 | [diff] [blame] | 182 | /* By default A9 CPUs have EL3 enabled. This board does not |
| 183 | * currently support EL3 so the CPU EL3 property is disabled before |
| 184 | * realization. |
| 185 | */ |
| 186 | if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { |
Markus Armbruster | 007b065 | 2015-09-11 15:04:45 +0200 | [diff] [blame] | 187 | object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); |
Greg Bellows | 61e2f35 | 2014-12-15 17:09:51 -0600 | [diff] [blame] | 188 | } |
| 189 | |
Markus Armbruster | 007b065 | 2015-09-11 15:04:45 +0200 | [diff] [blame] | 190 | object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", |
| 191 | &error_fatal); |
| 192 | object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", |
| 193 | &error_fatal); |
| 194 | object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 195 | |
| 196 | /* max 2GB ram */ |
| 197 | if (ram_size > 0x80000000) { |
| 198 | ram_size = 0x80000000; |
| 199 | } |
| 200 | |
| 201 | /* DDR remapped to address zero. */ |
Dirk Müller | c8623c0 | 2015-04-04 14:24:38 +0200 | [diff] [blame] | 202 | memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", |
| 203 | ram_size); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 204 | memory_region_add_subregion(address_space_mem, 0, ext_ram); |
| 205 | |
| 206 | /* 256K of on-chip memory */ |
Peter Maydell | 1cfe48c | 2017-07-07 15:42:49 +0100 | [diff] [blame] | 207 | memory_region_init_ram_nomigrate(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, |
Markus Armbruster | f8ed85a | 2015-09-11 16:51:43 +0200 | [diff] [blame] | 208 | &error_fatal); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 209 | vmstate_register_ram_global(ocm_ram); |
| 210 | memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); |
| 211 | |
| 212 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
| 213 | |
| 214 | /* AMD */ |
| 215 | pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 216 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
Markus Armbruster | fa1d36d | 2014-10-07 13:59:13 +0200 | [diff] [blame] | 217 | FLASH_SECTOR_SIZE, |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 218 | FLASH_SIZE/FLASH_SECTOR_SIZE, 1, |
| 219 | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, |
| 220 | 0); |
| 221 | |
| 222 | dev = qdev_create(NULL, "xilinx,zynq_slcr"); |
| 223 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 224 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 225 | |
| 226 | dev = qdev_create(NULL, "a9mpcore_priv"); |
| 227 | qdev_prop_set_uint32(dev, "num-cpu", 1); |
| 228 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 229 | busdev = SYS_BUS_DEVICE(dev); |
Peter Crosthwaite | c257712 | 2013-12-17 19:42:29 +0000 | [diff] [blame] | 230 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
Peter Maydell | e4a6540 | 2013-08-20 14:54:30 +0100 | [diff] [blame] | 231 | sysbus_connect_irq(busdev, 0, |
| 232 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 233 | |
| 234 | for (n = 0; n < 64; n++) { |
| 235 | pic[n] = qdev_get_gpio_in(dev, n); |
| 236 | } |
| 237 | |
Peter Crosthwaite | 7b482bc | 2012-10-15 14:40:21 +1000 | [diff] [blame] | 238 | zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); |
| 239 | zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); |
| 240 | zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); |
Peter A. G. Crosthwaite | 559d489 | 2012-08-03 16:08:48 +1000 | [diff] [blame] | 241 | |
Peter Crosthwaite | 892776c | 2012-10-29 11:34:38 +1000 | [diff] [blame] | 242 | sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); |
Liming Wang | 70ef6a5 | 2013-02-07 16:58:15 +1000 | [diff] [blame] | 243 | sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); |
Peter Crosthwaite | 892776c | 2012-10-29 11:34:38 +1000 | [diff] [blame] | 244 | |
xiaoqiang zhao | 4be12ea | 2016-06-06 16:59:31 +0100 | [diff] [blame] | 245 | cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hds[0]); |
| 246 | cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hds[1]); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 247 | |
| 248 | sysbus_create_varargs("cadence_ttc", 0xF8001000, |
| 249 | pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); |
| 250 | sysbus_create_varargs("cadence_ttc", 0xF8002000, |
| 251 | pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); |
| 252 | |
Peter Crosthwaite | 7fcd57e | 2014-01-03 17:58:43 -0800 | [diff] [blame] | 253 | gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); |
| 254 | gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 255 | |
Peter Crosthwaite | b972b4e | 2013-02-28 18:23:14 +0000 | [diff] [blame] | 256 | dev = qdev_create(NULL, "generic-sdhci"); |
| 257 | qdev_init_nofail(dev); |
| 258 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); |
| 259 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); |
| 260 | |
Peter Maydell | eb4f566 | 2016-02-18 14:16:18 +0000 | [diff] [blame] | 261 | di = drive_get_next(IF_SD); |
| 262 | blk = di ? blk_by_legacy_dinfo(di) : NULL; |
| 263 | carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); |
| 264 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); |
| 265 | object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); |
| 266 | |
Peter Crosthwaite | b972b4e | 2013-02-28 18:23:14 +0000 | [diff] [blame] | 267 | dev = qdev_create(NULL, "generic-sdhci"); |
| 268 | qdev_init_nofail(dev); |
| 269 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); |
| 270 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); |
| 271 | |
Peter Maydell | eb4f566 | 2016-02-18 14:16:18 +0000 | [diff] [blame] | 272 | di = drive_get_next(IF_SD); |
| 273 | blk = di ? blk_by_legacy_dinfo(di) : NULL; |
| 274 | carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); |
| 275 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); |
| 276 | object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); |
| 277 | |
Guenter Roeck | 74fcbd2 | 2015-11-12 09:54:55 -0800 | [diff] [blame] | 278 | dev = qdev_create(NULL, TYPE_ZYNQ_XADC); |
| 279 | qdev_init_nofail(dev); |
| 280 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); |
| 281 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); |
| 282 | |
Peter Crosthwaite | 7451afb | 2013-03-15 16:41:58 +0000 | [diff] [blame] | 283 | dev = qdev_create(NULL, "pl330"); |
| 284 | qdev_prop_set_uint8(dev, "num_chnls", 8); |
| 285 | qdev_prop_set_uint8(dev, "num_periph_req", 4); |
| 286 | qdev_prop_set_uint8(dev, "num_events", 16); |
| 287 | |
| 288 | qdev_prop_set_uint8(dev, "data_width", 64); |
| 289 | qdev_prop_set_uint8(dev, "wr_cap", 8); |
| 290 | qdev_prop_set_uint8(dev, "wr_q_dep", 16); |
| 291 | qdev_prop_set_uint8(dev, "rd_cap", 8); |
| 292 | qdev_prop_set_uint8(dev, "rd_q_dep", 16); |
| 293 | qdev_prop_set_uint16(dev, "data_buffer_dep", 256); |
| 294 | |
| 295 | qdev_init_nofail(dev); |
| 296 | busdev = SYS_BUS_DEVICE(dev); |
| 297 | sysbus_mmio_map(busdev, 0, 0xF8003000); |
| 298 | sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ |
| 299 | for (n = 0; n < 8; ++n) { /* event irqs */ |
| 300 | sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); |
| 301 | } |
| 302 | |
Peter Crosthwaite | f4b9953 | 2016-07-04 13:06:37 +0100 | [diff] [blame] | 303 | dev = qdev_create(NULL, "xlnx.ps7-dev-cfg"); |
| 304 | qdev_init_nofail(dev); |
| 305 | busdev = SYS_BUS_DEVICE(dev); |
| 306 | sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); |
| 307 | sysbus_mmio_map(busdev, 0, 0xF8007000); |
| 308 | |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 309 | zynq_binfo.ram_size = ram_size; |
| 310 | zynq_binfo.kernel_filename = kernel_filename; |
| 311 | zynq_binfo.kernel_cmdline = kernel_cmdline; |
| 312 | zynq_binfo.initrd_filename = initrd_filename; |
| 313 | zynq_binfo.nb_cpus = 1; |
| 314 | zynq_binfo.board_id = 0xd32; |
| 315 | zynq_binfo.loader_start = 0; |
Peter Crosthwaite | c3a9a68 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 316 | zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; |
| 317 | zynq_binfo.write_board_setup = zynq_write_board_setup; |
| 318 | |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 319 | arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 320 | } |
| 321 | |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 322 | static void zynq_machine_init(MachineClass *mc) |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 323 | { |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 324 | mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; |
| 325 | mc->init = zynq_init; |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 326 | mc->max_cpus = 1; |
| 327 | mc->no_sdcard = 1; |
Peter A. G. Crosthwaite | e326050 | 2012-03-05 14:39:13 +1000 | [diff] [blame] | 328 | } |
| 329 | |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 330 | DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) |