Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU PowerPC Booke hardware System Emulator |
| 3 | * |
| 4 | * Copyright (c) 2011 AdaCore |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 24 | |
Peter Maydell | 0d75590 | 2016-01-26 18:16:58 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Paolo Bonzini | 4771d75 | 2016-01-19 21:51:44 +0100 | [diff] [blame] | 26 | #include "cpu.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 27 | #include "hw/ppc/ppc.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 28 | #include "qemu/timer.h" |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 29 | #include "sysemu/reset.h" |
Markus Armbruster | 54d3123 | 2019-08-12 07:23:59 +0200 | [diff] [blame] | 30 | #include "sysemu/runstate.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 31 | #include "hw/loader.h" |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 32 | #include "kvm_ppc.h" |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 33 | |
| 34 | |
| 35 | /* Timer Control Register */ |
| 36 | |
| 37 | #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ |
Peter Maydell | a1f7f97 | 2014-03-17 16:00:37 +0000 | [diff] [blame] | 38 | #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 39 | #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ |
Peter Maydell | a1f7f97 | 2014-03-17 16:00:37 +0000 | [diff] [blame] | 40 | #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT) |
| 41 | #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */ |
| 42 | #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 43 | #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ |
Peter Maydell | a1f7f97 | 2014-03-17 16:00:37 +0000 | [diff] [blame] | 44 | #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT) |
| 45 | #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */ |
| 46 | #define TCR_ARE (1U << 22) /* Auto-Reload Enable */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 47 | |
| 48 | /* Timer Control Register (e500 specific fields) */ |
| 49 | |
| 50 | #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ |
| 51 | #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) |
| 52 | #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ |
| 53 | #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) |
| 54 | |
| 55 | /* Timer Status Register */ |
| 56 | |
Peter Maydell | a1f7f97 | 2014-03-17 16:00:37 +0000 | [diff] [blame] | 57 | #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */ |
| 58 | #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 59 | #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ |
Peter Maydell | a1f7f97 | 2014-03-17 16:00:37 +0000 | [diff] [blame] | 60 | #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT) |
| 61 | #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ |
| 62 | #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 63 | |
| 64 | typedef struct booke_timer_t booke_timer_t; |
| 65 | struct booke_timer_t { |
| 66 | |
| 67 | uint64_t fit_next; |
Stefan Weil | 1246b25 | 2013-12-01 08:49:47 +0100 | [diff] [blame] | 68 | QEMUTimer *fit_timer; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 69 | |
| 70 | uint64_t wdt_next; |
Stefan Weil | 1246b25 | 2013-12-01 08:49:47 +0100 | [diff] [blame] | 71 | QEMUTimer *wdt_timer; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 72 | |
| 73 | uint32_t flags; |
| 74 | }; |
| 75 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 76 | static void booke_update_irq(PowerPCCPU *cpu) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 77 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 78 | CPUPPCState *env = &cpu->env; |
| 79 | |
| 80 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 81 | (env->spr[SPR_BOOKE_TSR] & TSR_DIS |
| 82 | && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); |
| 83 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 84 | ppc_set_irq(cpu, PPC_INTERRUPT_WDT, |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 85 | (env->spr[SPR_BOOKE_TSR] & TSR_WIS |
| 86 | && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); |
| 87 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 88 | ppc_set_irq(cpu, PPC_INTERRUPT_FIT, |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 89 | (env->spr[SPR_BOOKE_TSR] & TSR_FIS |
| 90 | && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); |
| 91 | } |
| 92 | |
| 93 | /* Return the location of the bit of time base at which the FIT will raise an |
| 94 | interrupt */ |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 95 | static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 96 | { |
| 97 | uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; |
| 98 | |
| 99 | if (tb_env->flags & PPC_TIMER_E500) { |
| 100 | /* e500 Fixed-interval timer period extension */ |
| 101 | uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) |
| 102 | >> TCR_E500_FPEXT_SHIFT; |
| 103 | fp = 63 - (fp | fpext << 2); |
| 104 | } else { |
| 105 | fp = env->fit_period[fp]; |
| 106 | } |
| 107 | |
| 108 | return fp; |
| 109 | } |
| 110 | |
| 111 | /* Return the location of the bit of time base at which the WDT will raise an |
| 112 | interrupt */ |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 113 | static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 114 | { |
| 115 | uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; |
| 116 | |
| 117 | if (tb_env->flags & PPC_TIMER_E500) { |
| 118 | /* e500 Watchdog timer period extension */ |
| 119 | uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) |
| 120 | >> TCR_E500_WPEXT_SHIFT; |
| 121 | wp = 63 - (wp | wpext << 2); |
| 122 | } else { |
| 123 | wp = env->wdt_period[wp]; |
| 124 | } |
| 125 | |
| 126 | return wp; |
| 127 | } |
| 128 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 129 | static void booke_update_fixed_timer(CPUPPCState *env, |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 130 | uint8_t target_bit, |
| 131 | uint64_t *next, |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 132 | QEMUTimer *timer, |
| 133 | int tsr_bit) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 134 | { |
| 135 | ppc_tb_t *tb_env = env->tb_env; |
Bharat Bhushan | ab8131a | 2013-06-12 18:00:50 +0530 | [diff] [blame] | 136 | uint64_t delta_tick, ticks = 0; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 137 | uint64_t tb; |
Bharat Bhushan | ab8131a | 2013-06-12 18:00:50 +0530 | [diff] [blame] | 138 | uint64_t period; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 139 | uint64_t now; |
| 140 | |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 141 | if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) { |
| 142 | /* |
| 143 | * Don't arm the timer again when the guest has the current |
| 144 | * interrupt still pending. Wait for it to ack it. |
| 145 | */ |
| 146 | return; |
| 147 | } |
| 148 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 149 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 150 | tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); |
Bharat Bhushan | ab8131a | 2013-06-12 18:00:50 +0530 | [diff] [blame] | 151 | period = 1ULL << target_bit; |
| 152 | delta_tick = period - (tb & (period - 1)); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 153 | |
Bharat Bhushan | ab8131a | 2013-06-12 18:00:50 +0530 | [diff] [blame] | 154 | /* the timer triggers only when the selected bit toggles from 0 to 1 */ |
| 155 | if (tb & period) { |
| 156 | ticks = period; |
| 157 | } |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 158 | |
Bharat Bhushan | ab8131a | 2013-06-12 18:00:50 +0530 | [diff] [blame] | 159 | if (ticks + delta_tick < ticks) { |
| 160 | /* Overflow, so assume the biggest number we can express. */ |
| 161 | ticks = UINT64_MAX; |
| 162 | } else { |
| 163 | ticks += delta_tick; |
| 164 | } |
| 165 | |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 166 | *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq); |
Bharat Bhushan | ab8131a | 2013-06-12 18:00:50 +0530 | [diff] [blame] | 167 | if ((*next < now) || (*next > INT64_MAX)) { |
| 168 | /* Overflow, so assume the biggest number the qemu timer supports. */ |
| 169 | *next = INT64_MAX; |
| 170 | } |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 171 | |
| 172 | /* XXX: If expire time is now. We can't run the callback because we don't |
| 173 | * have access to it. So we just set the timer one nanosecond later. |
| 174 | */ |
| 175 | |
| 176 | if (*next == now) { |
| 177 | (*next)++; |
Alexander Graf | 84dc96e | 2013-11-25 22:46:55 +0100 | [diff] [blame] | 178 | } else { |
| 179 | /* |
| 180 | * There's no point to fake any granularity that's more fine grained |
| 181 | * than milliseconds. Anything beyond that just overloads the system. |
| 182 | */ |
| 183 | *next = MAX(*next, now + SCALE_MS); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 184 | } |
| 185 | |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 186 | /* Fire the next timer */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 187 | timer_mod(timer, *next); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | static void booke_decr_cb(void *opaque) |
| 191 | { |
Andreas Färber | ee0c98e | 2012-12-01 04:35:15 +0100 | [diff] [blame] | 192 | PowerPCCPU *cpu = opaque; |
| 193 | CPUPPCState *env = &cpu->env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 194 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 195 | env->spr[SPR_BOOKE_TSR] |= TSR_DIS; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 196 | booke_update_irq(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 197 | |
| 198 | if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) { |
Roman Kapl | 0dfe952 | 2017-01-09 12:23:38 +0100 | [diff] [blame] | 199 | /* Do not reload 0, it is already there. It would just trigger |
| 200 | * the timer again and lead to infinite loop */ |
| 201 | if (env->spr[SPR_BOOKE_DECAR] != 0) { |
| 202 | /* Auto Reload */ |
| 203 | cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); |
| 204 | } |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 205 | } |
| 206 | } |
| 207 | |
| 208 | static void booke_fit_cb(void *opaque) |
| 209 | { |
Andreas Färber | ee0c98e | 2012-12-01 04:35:15 +0100 | [diff] [blame] | 210 | PowerPCCPU *cpu = opaque; |
| 211 | CPUPPCState *env = &cpu->env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 212 | ppc_tb_t *tb_env; |
| 213 | booke_timer_t *booke_timer; |
| 214 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 215 | tb_env = env->tb_env; |
| 216 | booke_timer = tb_env->opaque; |
| 217 | env->spr[SPR_BOOKE_TSR] |= TSR_FIS; |
| 218 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 219 | booke_update_irq(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 220 | |
| 221 | booke_update_fixed_timer(env, |
| 222 | booke_get_fit_target(env, tb_env), |
| 223 | &booke_timer->fit_next, |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 224 | booke_timer->fit_timer, |
| 225 | TSR_FIS); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static void booke_wdt_cb(void *opaque) |
| 229 | { |
Andreas Färber | ee0c98e | 2012-12-01 04:35:15 +0100 | [diff] [blame] | 230 | PowerPCCPU *cpu = opaque; |
| 231 | CPUPPCState *env = &cpu->env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 232 | ppc_tb_t *tb_env; |
| 233 | booke_timer_t *booke_timer; |
| 234 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 235 | tb_env = env->tb_env; |
| 236 | booke_timer = tb_env->opaque; |
| 237 | |
| 238 | /* TODO: There's lots of complicated stuff to do here */ |
| 239 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 240 | booke_update_irq(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 241 | |
| 242 | booke_update_fixed_timer(env, |
| 243 | booke_get_wdt_target(env, tb_env), |
| 244 | &booke_timer->wdt_next, |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 245 | booke_timer->wdt_timer, |
| 246 | TSR_WIS); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 247 | } |
| 248 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 249 | void store_booke_tsr(CPUPPCState *env, target_ulong val) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 250 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 251 | PowerPCCPU *cpu = env_archcpu(env); |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 252 | ppc_tb_t *tb_env = env->tb_env; |
| 253 | booke_timer_t *booke_timer = tb_env->opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 254 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 255 | env->spr[SPR_BOOKE_TSR] &= ~val; |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 256 | kvmppc_clear_tsr_bits(cpu, val); |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 257 | |
| 258 | if (val & TSR_FIS) { |
| 259 | booke_update_fixed_timer(env, |
| 260 | booke_get_fit_target(env, tb_env), |
| 261 | &booke_timer->fit_next, |
| 262 | booke_timer->fit_timer, |
| 263 | TSR_FIS); |
| 264 | } |
| 265 | |
| 266 | if (val & TSR_WIS) { |
| 267 | booke_update_fixed_timer(env, |
| 268 | booke_get_wdt_target(env, tb_env), |
| 269 | &booke_timer->wdt_next, |
| 270 | booke_timer->wdt_timer, |
| 271 | TSR_WIS); |
| 272 | } |
| 273 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 274 | booke_update_irq(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 275 | } |
| 276 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 277 | void store_booke_tcr(CPUPPCState *env, target_ulong val) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 278 | { |
Richard Henderson | db70b31 | 2019-03-22 19:07:57 -0700 | [diff] [blame] | 279 | PowerPCCPU *cpu = env_archcpu(env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 280 | ppc_tb_t *tb_env = env->tb_env; |
| 281 | booke_timer_t *booke_timer = tb_env->opaque; |
| 282 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 283 | env->spr[SPR_BOOKE_TCR] = val; |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 284 | kvmppc_set_tcr(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 285 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 286 | booke_update_irq(cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 287 | |
| 288 | booke_update_fixed_timer(env, |
| 289 | booke_get_fit_target(env, tb_env), |
| 290 | &booke_timer->fit_next, |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 291 | booke_timer->fit_timer, |
| 292 | TSR_FIS); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 293 | |
| 294 | booke_update_fixed_timer(env, |
| 295 | booke_get_wdt_target(env, tb_env), |
| 296 | &booke_timer->wdt_next, |
Alexander Graf | 455df3f | 2013-11-25 22:46:54 +0100 | [diff] [blame] | 297 | booke_timer->wdt_timer, |
| 298 | TSR_WIS); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 299 | } |
| 300 | |
Bharat Bhushan | 88a78d9 | 2012-12-27 19:16:51 +0000 | [diff] [blame] | 301 | static void ppc_booke_timer_reset_handle(void *opaque) |
| 302 | { |
| 303 | PowerPCCPU *cpu = opaque; |
| 304 | CPUPPCState *env = &cpu->env; |
| 305 | |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 306 | store_booke_tcr(env, 0); |
| 307 | store_booke_tsr(env, -1); |
| 308 | } |
Bharat Bhushan | 88a78d9 | 2012-12-27 19:16:51 +0000 | [diff] [blame] | 309 | |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 310 | /* |
| 311 | * This function will be called whenever the CPU state changes. |
| 312 | * CPU states are defined "typedef enum RunState". |
| 313 | * Regarding timer, When CPU state changes to running after debug halt |
| 314 | * or similar cases which takes time then in between final watchdog |
| 315 | * expiry happenes. This will cause exit to QEMU and configured watchdog |
| 316 | * action will be taken. To avoid this we always clear the watchdog state when |
| 317 | * state changes to running. |
| 318 | */ |
Philippe Mathieu-Daudé | 538f049 | 2021-01-11 16:20:20 +0100 | [diff] [blame] | 319 | static void cpu_state_change_handler(void *opaque, bool running, RunState state) |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 320 | { |
| 321 | PowerPCCPU *cpu = opaque; |
| 322 | CPUPPCState *env = &cpu->env; |
| 323 | |
| 324 | if (!running) { |
| 325 | return; |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * Clear watchdog interrupt condition by clearing TSR. |
| 330 | */ |
| 331 | store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); |
Bharat Bhushan | 88a78d9 | 2012-12-27 19:16:51 +0000 | [diff] [blame] | 332 | } |
| 333 | |
Andreas Färber | a34a92b | 2012-12-01 04:43:18 +0100 | [diff] [blame] | 334 | void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 335 | { |
| 336 | ppc_tb_t *tb_env; |
| 337 | booke_timer_t *booke_timer; |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 338 | int ret = 0; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 339 | |
Markus Armbruster | b21e238 | 2022-03-15 15:41:56 +0100 | [diff] [blame] | 340 | tb_env = g_new0(ppc_tb_t, 1); |
| 341 | booke_timer = g_new0(booke_timer_t, 1); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 342 | |
Andreas Färber | a34a92b | 2012-12-01 04:43:18 +0100 | [diff] [blame] | 343 | cpu->env.tb_env = tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 344 | tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; |
| 345 | |
| 346 | tb_env->tb_freq = freq; |
| 347 | tb_env->decr_freq = freq; |
| 348 | tb_env->opaque = booke_timer; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 349 | tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 350 | |
| 351 | booke_timer->fit_timer = |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 352 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 353 | booke_timer->wdt_timer = |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 354 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu); |
Bharat Bhushan | 88a78d9 | 2012-12-27 19:16:51 +0000 | [diff] [blame] | 355 | |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 356 | ret = kvmppc_booke_watchdog_enable(cpu); |
| 357 | |
| 358 | if (ret) { |
| 359 | /* TODO: Start the QEMU emulated watchdog if not running on KVM. |
| 360 | * Also start the QEMU emulated watchdog if KVM does not support |
| 361 | * emulated watchdog or somehow it is not enabled (supported but |
| 362 | * not enabled is though some bug and requires debugging :)). |
| 363 | */ |
| 364 | } |
| 365 | |
| 366 | qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); |
| 367 | |
Bharat Bhushan | 88a78d9 | 2012-12-27 19:16:51 +0000 | [diff] [blame] | 368 | qemu_register_reset(ppc_booke_timer_reset_handle, cpu); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 369 | } |