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bellard2c0262a2003-09-30 20:34:21 +00001/*
2 * i386 translation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard2c0262a2003-09-30 20:34:21 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard2c0262a2003-09-30 20:34:21 +000018 */
19#include <stdarg.h>
20#include <stdlib.h>
21#include <stdio.h>
22#include <string.h>
23#include <inttypes.h>
24#include <signal.h>
bellard2c0262a2003-09-30 20:34:21 +000025
26#include "cpu.h"
27#include "exec-all.h"
28#include "disas.h"
bellard57fec1f2008-02-01 10:50:11 +000029#include "tcg-op.h"
bellard2c0262a2003-09-30 20:34:21 +000030
pbrooka7812ae2008-11-17 14:43:54 +000031#include "helper.h"
32#define GEN_HELPER 1
33#include "helper.h"
34
bellard2c0262a2003-09-30 20:34:21 +000035#define PREFIX_REPZ 0x01
36#define PREFIX_REPNZ 0x02
37#define PREFIX_LOCK 0x04
38#define PREFIX_DATA 0x08
39#define PREFIX_ADR 0x10
40
bellard14ce26e2005-01-03 23:50:08 +000041#ifdef TARGET_X86_64
42#define X86_64_ONLY(x) x
Blue Swirl001faf32009-05-13 17:53:17 +000043#define X86_64_DEF(...) __VA_ARGS__
bellard14ce26e2005-01-03 23:50:08 +000044#define CODE64(s) ((s)->code64)
45#define REX_X(s) ((s)->rex_x)
46#define REX_B(s) ((s)->rex_b)
47/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48#if 1
49#define BUGGY_64(x) NULL
50#endif
51#else
52#define X86_64_ONLY(x) NULL
Blue Swirl001faf32009-05-13 17:53:17 +000053#define X86_64_DEF(...)
bellard14ce26e2005-01-03 23:50:08 +000054#define CODE64(s) 0
55#define REX_X(s) 0
56#define REX_B(s) 0
57#endif
58
bellard57fec1f2008-02-01 10:50:11 +000059//#define MACRO_TEST 1
60
bellard57fec1f2008-02-01 10:50:11 +000061/* global register indexes */
pbrooka7812ae2008-11-17 14:43:54 +000062static TCGv_ptr cpu_env;
63static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
64static TCGv_i32 cpu_cc_op;
Laurent Desnoguescc739bb2009-09-29 11:58:04 +020065static TCGv cpu_regs[CPU_NB_REGS];
bellard1e4840b2008-05-25 17:26:41 +000066/* local temps */
67static TCGv cpu_T[2], cpu_T3;
bellard57fec1f2008-02-01 10:50:11 +000068/* local register indexes (only used inside old micro ops) */
pbrooka7812ae2008-11-17 14:43:54 +000069static TCGv cpu_tmp0, cpu_tmp4;
70static TCGv_ptr cpu_ptr0, cpu_ptr1;
71static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72static TCGv_i64 cpu_tmp1_i64;
Aurelien Jarnobedda792009-09-27 00:56:22 +020073static TCGv cpu_tmp5;
bellard57fec1f2008-02-01 10:50:11 +000074
Paolo Bonzini1a7ff922010-03-31 16:54:11 +020075static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
76
pbrook2e70f6e2008-06-29 01:03:05 +000077#include "gen-icount.h"
78
bellard57fec1f2008-02-01 10:50:11 +000079#ifdef TARGET_X86_64
80static int x86_64_hregs;
bellardae063a62005-01-09 00:07:04 +000081#endif
82
bellard2c0262a2003-09-30 20:34:21 +000083typedef struct DisasContext {
84 /* current insn context */
85 int override; /* -1 if no override */
86 int prefix;
87 int aflag, dflag;
bellard14ce26e2005-01-03 23:50:08 +000088 target_ulong pc; /* pc = eip + cs_base */
bellard2c0262a2003-09-30 20:34:21 +000089 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
90 static state change (stop translation) */
91 /* current block context */
bellard14ce26e2005-01-03 23:50:08 +000092 target_ulong cs_base; /* base of CS segment */
bellard2c0262a2003-09-30 20:34:21 +000093 int pe; /* protected mode */
94 int code32; /* 32 bit code segment */
bellard14ce26e2005-01-03 23:50:08 +000095#ifdef TARGET_X86_64
96 int lma; /* long mode active */
97 int code64; /* 64 bit code segment */
98 int rex_x, rex_b;
99#endif
bellard2c0262a2003-09-30 20:34:21 +0000100 int ss32; /* 32 bit stack segment */
101 int cc_op; /* current CC operation */
102 int addseg; /* non zero if either DS/ES/SS have a non zero base */
103 int f_st; /* currently unused */
104 int vm86; /* vm86 mode */
105 int cpl;
106 int iopl;
107 int tf; /* TF cpu flag */
bellard34865132003-10-05 14:28:56 +0000108 int singlestep_enabled; /* "hardware" single step enabled */
bellard2c0262a2003-09-30 20:34:21 +0000109 int jmp_opt; /* use direct block chaining for direct jumps */
110 int mem_index; /* select memory access functions */
j_mayerc0686882007-09-20 22:47:42 +0000111 uint64_t flags; /* all execution flags */
bellard2c0262a2003-09-30 20:34:21 +0000112 struct TranslationBlock *tb;
113 int popl_esp_hack; /* for correct popl with esp base handling */
bellard14ce26e2005-01-03 23:50:08 +0000114 int rip_offset; /* only used in x86_64, but left for simplicity */
115 int cpuid_features;
bellard3d7374c2006-07-10 19:53:04 +0000116 int cpuid_ext_features;
aurel32e771eda2008-04-09 06:41:37 +0000117 int cpuid_ext2_features;
bellard12e26b72008-05-22 10:13:38 +0000118 int cpuid_ext3_features;
bellard2c0262a2003-09-30 20:34:21 +0000119} DisasContext;
120
121static void gen_eob(DisasContext *s);
bellard14ce26e2005-01-03 23:50:08 +0000122static void gen_jmp(DisasContext *s, target_ulong eip);
123static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
bellard2c0262a2003-09-30 20:34:21 +0000124
125/* i386 arith/logic operations */
126enum {
ths5fafdf22007-09-16 21:08:06 +0000127 OP_ADDL,
128 OP_ORL,
129 OP_ADCL,
bellard2c0262a2003-09-30 20:34:21 +0000130 OP_SBBL,
ths5fafdf22007-09-16 21:08:06 +0000131 OP_ANDL,
132 OP_SUBL,
133 OP_XORL,
bellard2c0262a2003-09-30 20:34:21 +0000134 OP_CMPL,
135};
136
137/* i386 shift ops */
138enum {
ths5fafdf22007-09-16 21:08:06 +0000139 OP_ROL,
140 OP_ROR,
141 OP_RCL,
142 OP_RCR,
143 OP_SHL,
144 OP_SHR,
bellard2c0262a2003-09-30 20:34:21 +0000145 OP_SHL1, /* undocumented */
146 OP_SAR = 7,
147};
148
bellard8e1c85e2008-05-21 19:16:45 +0000149enum {
150 JCC_O,
151 JCC_B,
152 JCC_Z,
153 JCC_BE,
154 JCC_S,
155 JCC_P,
156 JCC_L,
157 JCC_LE,
158};
159
bellard2c0262a2003-09-30 20:34:21 +0000160/* operand size */
161enum {
162 OT_BYTE = 0,
163 OT_WORD,
ths5fafdf22007-09-16 21:08:06 +0000164 OT_LONG,
bellard2c0262a2003-09-30 20:34:21 +0000165 OT_QUAD,
166};
167
168enum {
169 /* I386 int registers */
170 OR_EAX, /* MUST be even numbered */
171 OR_ECX,
172 OR_EDX,
173 OR_EBX,
174 OR_ESP,
175 OR_EBP,
176 OR_ESI,
177 OR_EDI,
bellard14ce26e2005-01-03 23:50:08 +0000178
179 OR_TMP0 = 16, /* temporary operand register */
bellard2c0262a2003-09-30 20:34:21 +0000180 OR_TMP1,
181 OR_A0, /* temporary register used when doing address evaluation */
bellard2c0262a2003-09-30 20:34:21 +0000182};
183
bellard57fec1f2008-02-01 10:50:11 +0000184static inline void gen_op_movl_T0_0(void)
185{
186 tcg_gen_movi_tl(cpu_T[0], 0);
187}
188
189static inline void gen_op_movl_T0_im(int32_t val)
190{
191 tcg_gen_movi_tl(cpu_T[0], val);
192}
193
194static inline void gen_op_movl_T0_imu(uint32_t val)
195{
196 tcg_gen_movi_tl(cpu_T[0], val);
197}
198
199static inline void gen_op_movl_T1_im(int32_t val)
200{
201 tcg_gen_movi_tl(cpu_T[1], val);
202}
203
204static inline void gen_op_movl_T1_imu(uint32_t val)
205{
206 tcg_gen_movi_tl(cpu_T[1], val);
207}
208
209static inline void gen_op_movl_A0_im(uint32_t val)
210{
211 tcg_gen_movi_tl(cpu_A0, val);
212}
213
214#ifdef TARGET_X86_64
215static inline void gen_op_movq_A0_im(int64_t val)
216{
217 tcg_gen_movi_tl(cpu_A0, val);
218}
219#endif
220
221static inline void gen_movtl_T0_im(target_ulong val)
222{
223 tcg_gen_movi_tl(cpu_T[0], val);
224}
225
226static inline void gen_movtl_T1_im(target_ulong val)
227{
228 tcg_gen_movi_tl(cpu_T[1], val);
229}
230
231static inline void gen_op_andl_T0_ffff(void)
232{
233 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
234}
235
236static inline void gen_op_andl_T0_im(uint32_t val)
237{
238 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
239}
240
241static inline void gen_op_movl_T0_T1(void)
242{
243 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
244}
245
246static inline void gen_op_andl_A0_ffff(void)
247{
248 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
249}
250
bellard14ce26e2005-01-03 23:50:08 +0000251#ifdef TARGET_X86_64
252
253#define NB_OP_SIZES 4
254
bellard14ce26e2005-01-03 23:50:08 +0000255#else /* !TARGET_X86_64 */
256
257#define NB_OP_SIZES 3
258
bellard14ce26e2005-01-03 23:50:08 +0000259#endif /* !TARGET_X86_64 */
260
Juan Quintelae2542fe2009-07-27 16:13:06 +0200261#if defined(HOST_WORDS_BIGENDIAN)
bellard57fec1f2008-02-01 10:50:11 +0000262#define REG_B_OFFSET (sizeof(target_ulong) - 1)
263#define REG_H_OFFSET (sizeof(target_ulong) - 2)
264#define REG_W_OFFSET (sizeof(target_ulong) - 2)
265#define REG_L_OFFSET (sizeof(target_ulong) - 4)
266#define REG_LH_OFFSET (sizeof(target_ulong) - 8)
bellard14ce26e2005-01-03 23:50:08 +0000267#else
bellard57fec1f2008-02-01 10:50:11 +0000268#define REG_B_OFFSET 0
269#define REG_H_OFFSET 1
270#define REG_W_OFFSET 0
271#define REG_L_OFFSET 0
272#define REG_LH_OFFSET 4
bellard14ce26e2005-01-03 23:50:08 +0000273#endif
bellard2c0262a2003-09-30 20:34:21 +0000274
bellard1e4840b2008-05-25 17:26:41 +0000275static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
bellard2c0262a2003-09-30 20:34:21 +0000276{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200277 TCGv tmp;
278
bellard57fec1f2008-02-01 10:50:11 +0000279 switch(ot) {
280 case OT_BYTE:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200281 tmp = tcg_temp_new();
282 tcg_gen_ext8u_tl(tmp, t0);
bellard57fec1f2008-02-01 10:50:11 +0000283 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200284 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
285 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
bellard57fec1f2008-02-01 10:50:11 +0000286 } else {
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200287 tcg_gen_shli_tl(tmp, tmp, 8);
288 tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
289 tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp);
bellard57fec1f2008-02-01 10:50:11 +0000290 }
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200291 tcg_temp_free(tmp);
bellard57fec1f2008-02-01 10:50:11 +0000292 break;
293 case OT_WORD:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200294 tmp = tcg_temp_new();
295 tcg_gen_ext16u_tl(tmp, t0);
296 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
297 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
298 tcg_temp_free(tmp);
299 break;
300 default: /* XXX this shouldn't be reached; abort? */
301 case OT_LONG:
302 /* For x86_64, this sets the higher half of register to zero.
303 For i386, this is equivalent to a mov. */
304 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
bellard57fec1f2008-02-01 10:50:11 +0000305 break;
bellard14ce26e2005-01-03 23:50:08 +0000306#ifdef TARGET_X86_64
bellard57fec1f2008-02-01 10:50:11 +0000307 case OT_QUAD:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200308 tcg_gen_mov_tl(cpu_regs[reg], t0);
bellard57fec1f2008-02-01 10:50:11 +0000309 break;
bellard14ce26e2005-01-03 23:50:08 +0000310#endif
bellard57fec1f2008-02-01 10:50:11 +0000311 }
312}
313
314static inline void gen_op_mov_reg_T0(int ot, int reg)
315{
bellard1e4840b2008-05-25 17:26:41 +0000316 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
bellard57fec1f2008-02-01 10:50:11 +0000317}
318
319static inline void gen_op_mov_reg_T1(int ot, int reg)
320{
bellard1e4840b2008-05-25 17:26:41 +0000321 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
bellard57fec1f2008-02-01 10:50:11 +0000322}
323
324static inline void gen_op_mov_reg_A0(int size, int reg)
325{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200326 TCGv tmp;
327
bellard57fec1f2008-02-01 10:50:11 +0000328 switch(size) {
329 case 0:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200330 tmp = tcg_temp_new();
331 tcg_gen_ext16u_tl(tmp, cpu_A0);
332 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
333 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
334 tcg_temp_free(tmp);
335 break;
336 default: /* XXX this shouldn't be reached; abort? */
337 case 1:
338 /* For x86_64, this sets the higher half of register to zero.
339 For i386, this is equivalent to a mov. */
340 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +0000341 break;
bellard14ce26e2005-01-03 23:50:08 +0000342#ifdef TARGET_X86_64
bellard57fec1f2008-02-01 10:50:11 +0000343 case 2:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200344 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +0000345 break;
bellard14ce26e2005-01-03 23:50:08 +0000346#endif
bellard57fec1f2008-02-01 10:50:11 +0000347 }
348}
349
bellard1e4840b2008-05-25 17:26:41 +0000350static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
bellard57fec1f2008-02-01 10:50:11 +0000351{
352 switch(ot) {
353 case OT_BYTE:
354 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
355 goto std_case;
356 } else {
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200357 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
358 tcg_gen_ext8u_tl(t0, t0);
bellard57fec1f2008-02-01 10:50:11 +0000359 }
360 break;
361 default:
362 std_case:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200363 tcg_gen_mov_tl(t0, cpu_regs[reg]);
bellard57fec1f2008-02-01 10:50:11 +0000364 break;
365 }
366}
367
bellard1e4840b2008-05-25 17:26:41 +0000368static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
369{
370 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
371}
372
bellard57fec1f2008-02-01 10:50:11 +0000373static inline void gen_op_movl_A0_reg(int reg)
374{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200375 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
bellard57fec1f2008-02-01 10:50:11 +0000376}
377
378static inline void gen_op_addl_A0_im(int32_t val)
379{
380 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
bellard14ce26e2005-01-03 23:50:08 +0000381#ifdef TARGET_X86_64
bellard57fec1f2008-02-01 10:50:11 +0000382 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
bellard14ce26e2005-01-03 23:50:08 +0000383#endif
bellard57fec1f2008-02-01 10:50:11 +0000384}
bellard2c0262a2003-09-30 20:34:21 +0000385
bellard14ce26e2005-01-03 23:50:08 +0000386#ifdef TARGET_X86_64
bellard57fec1f2008-02-01 10:50:11 +0000387static inline void gen_op_addq_A0_im(int64_t val)
388{
389 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
390}
391#endif
392
393static void gen_add_A0_im(DisasContext *s, int val)
394{
395#ifdef TARGET_X86_64
396 if (CODE64(s))
397 gen_op_addq_A0_im(val);
398 else
399#endif
400 gen_op_addl_A0_im(val);
401}
bellard14ce26e2005-01-03 23:50:08 +0000402
bellard57fec1f2008-02-01 10:50:11 +0000403static inline void gen_op_addl_T0_T1(void)
404{
405 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
406}
407
408static inline void gen_op_jmp_T0(void)
409{
410 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
411}
412
bellard6e0d8672008-05-18 19:28:26 +0000413static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
bellard57fec1f2008-02-01 10:50:11 +0000414{
bellard6e0d8672008-05-18 19:28:26 +0000415 switch(size) {
416 case 0:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200417 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
418 tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
419 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
420 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
bellard6e0d8672008-05-18 19:28:26 +0000421 break;
422 case 1:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200423 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
424 /* For x86_64, this sets the higher half of register to zero.
425 For i386, this is equivalent to a nop. */
426 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
427 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
bellard6e0d8672008-05-18 19:28:26 +0000428 break;
429#ifdef TARGET_X86_64
430 case 2:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200431 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
bellard6e0d8672008-05-18 19:28:26 +0000432 break;
433#endif
434 }
bellard57fec1f2008-02-01 10:50:11 +0000435}
436
bellard6e0d8672008-05-18 19:28:26 +0000437static inline void gen_op_add_reg_T0(int size, int reg)
bellard57fec1f2008-02-01 10:50:11 +0000438{
bellard6e0d8672008-05-18 19:28:26 +0000439 switch(size) {
440 case 0:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200441 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
442 tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
443 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
444 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
bellard6e0d8672008-05-18 19:28:26 +0000445 break;
446 case 1:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200447 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
448 /* For x86_64, this sets the higher half of register to zero.
449 For i386, this is equivalent to a nop. */
450 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
451 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
bellard6e0d8672008-05-18 19:28:26 +0000452 break;
bellard57fec1f2008-02-01 10:50:11 +0000453#ifdef TARGET_X86_64
bellard6e0d8672008-05-18 19:28:26 +0000454 case 2:
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200455 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
bellard6e0d8672008-05-18 19:28:26 +0000456 break;
bellard57fec1f2008-02-01 10:50:11 +0000457#endif
bellard6e0d8672008-05-18 19:28:26 +0000458 }
459}
bellard57fec1f2008-02-01 10:50:11 +0000460
461static inline void gen_op_set_cc_op(int32_t val)
462{
bellardb6abf972008-05-17 12:44:31 +0000463 tcg_gen_movi_i32(cpu_cc_op, val);
bellard57fec1f2008-02-01 10:50:11 +0000464}
465
466static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
467{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200468 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
469 if (shift != 0)
bellard57fec1f2008-02-01 10:50:11 +0000470 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
471 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200472 /* For x86_64, this sets the higher half of register to zero.
473 For i386, this is equivalent to a nop. */
474 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +0000475}
476
477static inline void gen_op_movl_A0_seg(int reg)
478{
479 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
480}
481
482static inline void gen_op_addl_A0_seg(int reg)
483{
484 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
485 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
486#ifdef TARGET_X86_64
487 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
488#endif
489}
490
491#ifdef TARGET_X86_64
492static inline void gen_op_movq_A0_seg(int reg)
493{
494 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
495}
496
497static inline void gen_op_addq_A0_seg(int reg)
498{
499 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
500 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
501}
502
503static inline void gen_op_movq_A0_reg(int reg)
504{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200505 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
bellard57fec1f2008-02-01 10:50:11 +0000506}
507
508static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
509{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200510 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
511 if (shift != 0)
bellard57fec1f2008-02-01 10:50:11 +0000512 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
513 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
514}
bellard14ce26e2005-01-03 23:50:08 +0000515#endif
516
bellard57fec1f2008-02-01 10:50:11 +0000517static inline void gen_op_lds_T0_A0(int idx)
518{
519 int mem_index = (idx >> 2) - 1;
520 switch(idx & 3) {
521 case 0:
522 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
523 break;
524 case 1:
525 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
526 break;
527 default:
528 case 2:
529 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
530 break;
531 }
532}
bellard2c0262a2003-09-30 20:34:21 +0000533
bellard1e4840b2008-05-25 17:26:41 +0000534static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
bellard57fec1f2008-02-01 10:50:11 +0000535{
536 int mem_index = (idx >> 2) - 1;
537 switch(idx & 3) {
538 case 0:
bellard1e4840b2008-05-25 17:26:41 +0000539 tcg_gen_qemu_ld8u(t0, a0, mem_index);
bellard57fec1f2008-02-01 10:50:11 +0000540 break;
541 case 1:
bellard1e4840b2008-05-25 17:26:41 +0000542 tcg_gen_qemu_ld16u(t0, a0, mem_index);
bellard57fec1f2008-02-01 10:50:11 +0000543 break;
544 case 2:
bellard1e4840b2008-05-25 17:26:41 +0000545 tcg_gen_qemu_ld32u(t0, a0, mem_index);
bellard57fec1f2008-02-01 10:50:11 +0000546 break;
547 default:
548 case 3:
pbrooka7812ae2008-11-17 14:43:54 +0000549 /* Should never happen on 32-bit targets. */
550#ifdef TARGET_X86_64
bellard1e4840b2008-05-25 17:26:41 +0000551 tcg_gen_qemu_ld64(t0, a0, mem_index);
pbrooka7812ae2008-11-17 14:43:54 +0000552#endif
bellard57fec1f2008-02-01 10:50:11 +0000553 break;
554 }
555}
bellard2c0262a2003-09-30 20:34:21 +0000556
bellard1e4840b2008-05-25 17:26:41 +0000557/* XXX: always use ldu or lds */
558static inline void gen_op_ld_T0_A0(int idx)
559{
560 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
561}
562
bellard57fec1f2008-02-01 10:50:11 +0000563static inline void gen_op_ldu_T0_A0(int idx)
564{
bellard1e4840b2008-05-25 17:26:41 +0000565 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +0000566}
bellard2c0262a2003-09-30 20:34:21 +0000567
bellard57fec1f2008-02-01 10:50:11 +0000568static inline void gen_op_ld_T1_A0(int idx)
569{
bellard1e4840b2008-05-25 17:26:41 +0000570 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
571}
572
573static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
574{
bellard57fec1f2008-02-01 10:50:11 +0000575 int mem_index = (idx >> 2) - 1;
576 switch(idx & 3) {
577 case 0:
bellard1e4840b2008-05-25 17:26:41 +0000578 tcg_gen_qemu_st8(t0, a0, mem_index);
bellard57fec1f2008-02-01 10:50:11 +0000579 break;
580 case 1:
bellard1e4840b2008-05-25 17:26:41 +0000581 tcg_gen_qemu_st16(t0, a0, mem_index);
bellard57fec1f2008-02-01 10:50:11 +0000582 break;
583 case 2:
bellard1e4840b2008-05-25 17:26:41 +0000584 tcg_gen_qemu_st32(t0, a0, mem_index);
bellard57fec1f2008-02-01 10:50:11 +0000585 break;
586 default:
587 case 3:
pbrooka7812ae2008-11-17 14:43:54 +0000588 /* Should never happen on 32-bit targets. */
589#ifdef TARGET_X86_64
bellard1e4840b2008-05-25 17:26:41 +0000590 tcg_gen_qemu_st64(t0, a0, mem_index);
pbrooka7812ae2008-11-17 14:43:54 +0000591#endif
bellard57fec1f2008-02-01 10:50:11 +0000592 break;
593 }
594}
bellard2c0262a2003-09-30 20:34:21 +0000595
bellard57fec1f2008-02-01 10:50:11 +0000596static inline void gen_op_st_T0_A0(int idx)
597{
bellard1e4840b2008-05-25 17:26:41 +0000598 gen_op_st_v(idx, cpu_T[0], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +0000599}
bellard2c0262a2003-09-30 20:34:21 +0000600
bellard57fec1f2008-02-01 10:50:11 +0000601static inline void gen_op_st_T1_A0(int idx)
602{
bellard1e4840b2008-05-25 17:26:41 +0000603 gen_op_st_v(idx, cpu_T[1], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +0000604}
bellard4f319162004-01-04 17:35:00 +0000605
bellard14ce26e2005-01-03 23:50:08 +0000606static inline void gen_jmp_im(target_ulong pc)
607{
bellard57fec1f2008-02-01 10:50:11 +0000608 tcg_gen_movi_tl(cpu_tmp0, pc);
609 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
bellard14ce26e2005-01-03 23:50:08 +0000610}
611
bellard2c0262a2003-09-30 20:34:21 +0000612static inline void gen_string_movl_A0_ESI(DisasContext *s)
613{
614 int override;
615
616 override = s->override;
bellard14ce26e2005-01-03 23:50:08 +0000617#ifdef TARGET_X86_64
618 if (s->aflag == 2) {
619 if (override >= 0) {
bellard57fec1f2008-02-01 10:50:11 +0000620 gen_op_movq_A0_seg(override);
621 gen_op_addq_A0_reg_sN(0, R_ESI);
bellard14ce26e2005-01-03 23:50:08 +0000622 } else {
bellard57fec1f2008-02-01 10:50:11 +0000623 gen_op_movq_A0_reg(R_ESI);
bellard14ce26e2005-01-03 23:50:08 +0000624 }
625 } else
626#endif
bellard2c0262a2003-09-30 20:34:21 +0000627 if (s->aflag) {
628 /* 32 bit address */
629 if (s->addseg && override < 0)
630 override = R_DS;
631 if (override >= 0) {
bellard57fec1f2008-02-01 10:50:11 +0000632 gen_op_movl_A0_seg(override);
633 gen_op_addl_A0_reg_sN(0, R_ESI);
bellard2c0262a2003-09-30 20:34:21 +0000634 } else {
bellard57fec1f2008-02-01 10:50:11 +0000635 gen_op_movl_A0_reg(R_ESI);
bellard2c0262a2003-09-30 20:34:21 +0000636 }
637 } else {
638 /* 16 address, always override */
639 if (override < 0)
640 override = R_DS;
bellard57fec1f2008-02-01 10:50:11 +0000641 gen_op_movl_A0_reg(R_ESI);
bellard2c0262a2003-09-30 20:34:21 +0000642 gen_op_andl_A0_ffff();
bellard57fec1f2008-02-01 10:50:11 +0000643 gen_op_addl_A0_seg(override);
bellard2c0262a2003-09-30 20:34:21 +0000644 }
645}
646
647static inline void gen_string_movl_A0_EDI(DisasContext *s)
648{
bellard14ce26e2005-01-03 23:50:08 +0000649#ifdef TARGET_X86_64
650 if (s->aflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +0000651 gen_op_movq_A0_reg(R_EDI);
bellard14ce26e2005-01-03 23:50:08 +0000652 } else
653#endif
bellard2c0262a2003-09-30 20:34:21 +0000654 if (s->aflag) {
655 if (s->addseg) {
bellard57fec1f2008-02-01 10:50:11 +0000656 gen_op_movl_A0_seg(R_ES);
657 gen_op_addl_A0_reg_sN(0, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +0000658 } else {
bellard57fec1f2008-02-01 10:50:11 +0000659 gen_op_movl_A0_reg(R_EDI);
bellard2c0262a2003-09-30 20:34:21 +0000660 }
661 } else {
bellard57fec1f2008-02-01 10:50:11 +0000662 gen_op_movl_A0_reg(R_EDI);
bellard2c0262a2003-09-30 20:34:21 +0000663 gen_op_andl_A0_ffff();
bellard57fec1f2008-02-01 10:50:11 +0000664 gen_op_addl_A0_seg(R_ES);
bellard2c0262a2003-09-30 20:34:21 +0000665 }
666}
667
bellard6e0d8672008-05-18 19:28:26 +0000668static inline void gen_op_movl_T0_Dshift(int ot)
669{
670 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
671 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
bellard2c0262a2003-09-30 20:34:21 +0000672};
673
bellard6e0d8672008-05-18 19:28:26 +0000674static void gen_extu(int ot, TCGv reg)
675{
676 switch(ot) {
677 case OT_BYTE:
678 tcg_gen_ext8u_tl(reg, reg);
679 break;
680 case OT_WORD:
681 tcg_gen_ext16u_tl(reg, reg);
682 break;
683 case OT_LONG:
684 tcg_gen_ext32u_tl(reg, reg);
685 break;
686 default:
687 break;
688 }
689}
ths3b46e622007-09-17 08:09:54 +0000690
bellard6e0d8672008-05-18 19:28:26 +0000691static void gen_exts(int ot, TCGv reg)
692{
693 switch(ot) {
694 case OT_BYTE:
695 tcg_gen_ext8s_tl(reg, reg);
696 break;
697 case OT_WORD:
698 tcg_gen_ext16s_tl(reg, reg);
699 break;
700 case OT_LONG:
701 tcg_gen_ext32s_tl(reg, reg);
702 break;
703 default:
704 break;
705 }
706}
bellard2c0262a2003-09-30 20:34:21 +0000707
bellard6e0d8672008-05-18 19:28:26 +0000708static inline void gen_op_jnz_ecx(int size, int label1)
709{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200710 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
bellard6e0d8672008-05-18 19:28:26 +0000711 gen_extu(size + 1, cpu_tmp0);
pbrookcb636692008-05-24 02:22:00 +0000712 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
bellard6e0d8672008-05-18 19:28:26 +0000713}
714
715static inline void gen_op_jz_ecx(int size, int label1)
716{
Laurent Desnoguescc739bb2009-09-29 11:58:04 +0200717 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
bellard6e0d8672008-05-18 19:28:26 +0000718 gen_extu(size + 1, cpu_tmp0);
pbrookcb636692008-05-24 02:22:00 +0000719 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
bellard6e0d8672008-05-18 19:28:26 +0000720}
bellard2c0262a2003-09-30 20:34:21 +0000721
pbrooka7812ae2008-11-17 14:43:54 +0000722static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
723{
724 switch (ot) {
725 case 0: gen_helper_inb(v, n); break;
726 case 1: gen_helper_inw(v, n); break;
727 case 2: gen_helper_inl(v, n); break;
728 }
bellard2c0262a2003-09-30 20:34:21 +0000729
pbrooka7812ae2008-11-17 14:43:54 +0000730}
bellard2c0262a2003-09-30 20:34:21 +0000731
pbrooka7812ae2008-11-17 14:43:54 +0000732static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
733{
734 switch (ot) {
735 case 0: gen_helper_outb(v, n); break;
736 case 1: gen_helper_outw(v, n); break;
737 case 2: gen_helper_outl(v, n); break;
738 }
739
740}
bellardf115e912003-11-13 01:43:28 +0000741
bellardb8b6a502008-05-15 16:46:30 +0000742static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
743 uint32_t svm_flags)
bellardf115e912003-11-13 01:43:28 +0000744{
bellardb8b6a502008-05-15 16:46:30 +0000745 int state_saved;
746 target_ulong next_eip;
747
748 state_saved = 0;
bellardf115e912003-11-13 01:43:28 +0000749 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
750 if (s->cc_op != CC_OP_DYNAMIC)
751 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +0000752 gen_jmp_im(cur_eip);
bellardb8b6a502008-05-15 16:46:30 +0000753 state_saved = 1;
bellardb6abf972008-05-17 12:44:31 +0000754 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +0000755 switch (ot) {
756 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
757 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
758 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
759 }
bellardb8b6a502008-05-15 16:46:30 +0000760 }
bellard872929a2008-05-28 16:16:54 +0000761 if(s->flags & HF_SVMI_MASK) {
bellardb8b6a502008-05-15 16:46:30 +0000762 if (!state_saved) {
763 if (s->cc_op != CC_OP_DYNAMIC)
764 gen_op_set_cc_op(s->cc_op);
765 gen_jmp_im(cur_eip);
bellardb8b6a502008-05-15 16:46:30 +0000766 }
767 svm_flags |= (1 << (4 + ot));
768 next_eip = s->pc - s->cs_base;
bellardb6abf972008-05-17 12:44:31 +0000769 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +0000770 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
771 tcg_const_i32(next_eip - cur_eip));
bellardf115e912003-11-13 01:43:28 +0000772 }
773}
774
bellard2c0262a2003-09-30 20:34:21 +0000775static inline void gen_movs(DisasContext *s, int ot)
776{
777 gen_string_movl_A0_ESI(s);
bellard57fec1f2008-02-01 10:50:11 +0000778 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +0000779 gen_string_movl_A0_EDI(s);
bellard57fec1f2008-02-01 10:50:11 +0000780 gen_op_st_T0_A0(ot + s->mem_index);
bellard6e0d8672008-05-18 19:28:26 +0000781 gen_op_movl_T0_Dshift(ot);
782 gen_op_add_reg_T0(s->aflag, R_ESI);
783 gen_op_add_reg_T0(s->aflag, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +0000784}
785
786static inline void gen_update_cc_op(DisasContext *s)
787{
788 if (s->cc_op != CC_OP_DYNAMIC) {
789 gen_op_set_cc_op(s->cc_op);
790 s->cc_op = CC_OP_DYNAMIC;
791 }
792}
793
bellardb6abf972008-05-17 12:44:31 +0000794static void gen_op_update1_cc(void)
795{
796 tcg_gen_discard_tl(cpu_cc_src);
797 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
798}
799
800static void gen_op_update2_cc(void)
801{
802 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
803 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
804}
805
806static inline void gen_op_cmpl_T0_T1_cc(void)
807{
808 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
809 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
810}
811
812static inline void gen_op_testl_T0_T1_cc(void)
813{
814 tcg_gen_discard_tl(cpu_cc_src);
815 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
816}
817
818static void gen_op_update_neg_cc(void)
819{
820 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
821 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
822}
823
bellard8e1c85e2008-05-21 19:16:45 +0000824/* compute eflags.C to reg */
825static void gen_compute_eflags_c(TCGv reg)
826{
pbrooka7812ae2008-11-17 14:43:54 +0000827 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
bellard8e1c85e2008-05-21 19:16:45 +0000828 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
829}
830
831/* compute all eflags to cc_src */
832static void gen_compute_eflags(TCGv reg)
833{
pbrooka7812ae2008-11-17 14:43:54 +0000834 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
bellard8e1c85e2008-05-21 19:16:45 +0000835 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
836}
837
bellard1e4840b2008-05-25 17:26:41 +0000838static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
bellard8e1c85e2008-05-21 19:16:45 +0000839{
bellard1e4840b2008-05-25 17:26:41 +0000840 if (s->cc_op != CC_OP_DYNAMIC)
841 gen_op_set_cc_op(s->cc_op);
842 switch(jcc_op) {
bellard8e1c85e2008-05-21 19:16:45 +0000843 case JCC_O:
844 gen_compute_eflags(cpu_T[0]);
845 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
846 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
847 break;
848 case JCC_B:
849 gen_compute_eflags_c(cpu_T[0]);
850 break;
851 case JCC_Z:
852 gen_compute_eflags(cpu_T[0]);
853 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
854 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
855 break;
856 case JCC_BE:
857 gen_compute_eflags(cpu_tmp0);
858 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
859 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
860 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
861 break;
862 case JCC_S:
863 gen_compute_eflags(cpu_T[0]);
864 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
865 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
866 break;
867 case JCC_P:
868 gen_compute_eflags(cpu_T[0]);
869 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
870 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
871 break;
872 case JCC_L:
873 gen_compute_eflags(cpu_tmp0);
874 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
875 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
876 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
877 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
878 break;
879 default:
880 case JCC_LE:
881 gen_compute_eflags(cpu_tmp0);
882 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
883 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
884 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
885 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
886 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
887 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
888 break;
889 }
890}
891
892/* return true if setcc_slow is not needed (WARNING: must be kept in
893 sync with gen_jcc1) */
894static int is_fast_jcc_case(DisasContext *s, int b)
895{
896 int jcc_op;
897 jcc_op = (b >> 1) & 7;
898 switch(s->cc_op) {
899 /* we optimize the cmp/jcc case */
900 case CC_OP_SUBB:
901 case CC_OP_SUBW:
902 case CC_OP_SUBL:
903 case CC_OP_SUBQ:
904 if (jcc_op == JCC_O || jcc_op == JCC_P)
905 goto slow_jcc;
906 break;
907
908 /* some jumps are easy to compute */
909 case CC_OP_ADDB:
910 case CC_OP_ADDW:
911 case CC_OP_ADDL:
912 case CC_OP_ADDQ:
913
914 case CC_OP_LOGICB:
915 case CC_OP_LOGICW:
916 case CC_OP_LOGICL:
917 case CC_OP_LOGICQ:
918
919 case CC_OP_INCB:
920 case CC_OP_INCW:
921 case CC_OP_INCL:
922 case CC_OP_INCQ:
923
924 case CC_OP_DECB:
925 case CC_OP_DECW:
926 case CC_OP_DECL:
927 case CC_OP_DECQ:
928
929 case CC_OP_SHLB:
930 case CC_OP_SHLW:
931 case CC_OP_SHLL:
932 case CC_OP_SHLQ:
933 if (jcc_op != JCC_Z && jcc_op != JCC_S)
934 goto slow_jcc;
935 break;
936 default:
937 slow_jcc:
938 return 0;
939 }
940 return 1;
941}
942
943/* generate a conditional jump to label 'l1' according to jump opcode
944 value 'b'. In the fast case, T0 is guaranted not to be used. */
945static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
946{
947 int inv, jcc_op, size, cond;
948 TCGv t0;
949
950 inv = b & 1;
951 jcc_op = (b >> 1) & 7;
952
953 switch(cc_op) {
954 /* we optimize the cmp/jcc case */
955 case CC_OP_SUBB:
956 case CC_OP_SUBW:
957 case CC_OP_SUBL:
958 case CC_OP_SUBQ:
959
960 size = cc_op - CC_OP_SUBB;
961 switch(jcc_op) {
962 case JCC_Z:
963 fast_jcc_z:
964 switch(size) {
965 case 0:
966 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
967 t0 = cpu_tmp0;
968 break;
969 case 1:
970 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
971 t0 = cpu_tmp0;
972 break;
973#ifdef TARGET_X86_64
974 case 2:
975 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
976 t0 = cpu_tmp0;
977 break;
978#endif
979 default:
980 t0 = cpu_cc_dst;
981 break;
982 }
pbrookcb636692008-05-24 02:22:00 +0000983 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
bellard8e1c85e2008-05-21 19:16:45 +0000984 break;
985 case JCC_S:
986 fast_jcc_s:
987 switch(size) {
988 case 0:
989 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
pbrookcb636692008-05-24 02:22:00 +0000990 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
991 0, l1);
bellard8e1c85e2008-05-21 19:16:45 +0000992 break;
993 case 1:
994 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
pbrookcb636692008-05-24 02:22:00 +0000995 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
996 0, l1);
bellard8e1c85e2008-05-21 19:16:45 +0000997 break;
998#ifdef TARGET_X86_64
999 case 2:
1000 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
pbrookcb636692008-05-24 02:22:00 +00001001 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1002 0, l1);
bellard8e1c85e2008-05-21 19:16:45 +00001003 break;
1004#endif
1005 default:
pbrookcb636692008-05-24 02:22:00 +00001006 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1007 0, l1);
bellard8e1c85e2008-05-21 19:16:45 +00001008 break;
1009 }
1010 break;
1011
1012 case JCC_B:
1013 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1014 goto fast_jcc_b;
1015 case JCC_BE:
1016 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1017 fast_jcc_b:
1018 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1019 switch(size) {
1020 case 0:
1021 t0 = cpu_tmp0;
1022 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1023 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1024 break;
1025 case 1:
1026 t0 = cpu_tmp0;
1027 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1028 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1029 break;
1030#ifdef TARGET_X86_64
1031 case 2:
1032 t0 = cpu_tmp0;
1033 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1034 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1035 break;
1036#endif
1037 default:
1038 t0 = cpu_cc_src;
1039 break;
1040 }
1041 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1042 break;
1043
1044 case JCC_L:
1045 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1046 goto fast_jcc_l;
1047 case JCC_LE:
1048 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1049 fast_jcc_l:
1050 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1051 switch(size) {
1052 case 0:
1053 t0 = cpu_tmp0;
1054 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1055 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1056 break;
1057 case 1:
1058 t0 = cpu_tmp0;
1059 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1060 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1061 break;
1062#ifdef TARGET_X86_64
1063 case 2:
1064 t0 = cpu_tmp0;
1065 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1066 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1067 break;
1068#endif
1069 default:
1070 t0 = cpu_cc_src;
1071 break;
1072 }
1073 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1074 break;
1075
1076 default:
1077 goto slow_jcc;
1078 }
1079 break;
1080
1081 /* some jumps are easy to compute */
1082 case CC_OP_ADDB:
1083 case CC_OP_ADDW:
1084 case CC_OP_ADDL:
1085 case CC_OP_ADDQ:
1086
1087 case CC_OP_ADCB:
1088 case CC_OP_ADCW:
1089 case CC_OP_ADCL:
1090 case CC_OP_ADCQ:
1091
1092 case CC_OP_SBBB:
1093 case CC_OP_SBBW:
1094 case CC_OP_SBBL:
1095 case CC_OP_SBBQ:
1096
1097 case CC_OP_LOGICB:
1098 case CC_OP_LOGICW:
1099 case CC_OP_LOGICL:
1100 case CC_OP_LOGICQ:
1101
1102 case CC_OP_INCB:
1103 case CC_OP_INCW:
1104 case CC_OP_INCL:
1105 case CC_OP_INCQ:
1106
1107 case CC_OP_DECB:
1108 case CC_OP_DECW:
1109 case CC_OP_DECL:
1110 case CC_OP_DECQ:
1111
1112 case CC_OP_SHLB:
1113 case CC_OP_SHLW:
1114 case CC_OP_SHLL:
1115 case CC_OP_SHLQ:
1116
1117 case CC_OP_SARB:
1118 case CC_OP_SARW:
1119 case CC_OP_SARL:
1120 case CC_OP_SARQ:
1121 switch(jcc_op) {
1122 case JCC_Z:
1123 size = (cc_op - CC_OP_ADDB) & 3;
1124 goto fast_jcc_z;
1125 case JCC_S:
1126 size = (cc_op - CC_OP_ADDB) & 3;
1127 goto fast_jcc_s;
1128 default:
1129 goto slow_jcc;
1130 }
1131 break;
1132 default:
1133 slow_jcc:
bellard1e4840b2008-05-25 17:26:41 +00001134 gen_setcc_slow_T0(s, jcc_op);
pbrookcb636692008-05-24 02:22:00 +00001135 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1136 cpu_T[0], 0, l1);
bellard8e1c85e2008-05-21 19:16:45 +00001137 break;
1138 }
1139}
1140
bellard14ce26e2005-01-03 23:50:08 +00001141/* XXX: does not work with gdbstub "ice" single step - not a
1142 serious problem */
1143static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
bellard2c0262a2003-09-30 20:34:21 +00001144{
bellard14ce26e2005-01-03 23:50:08 +00001145 int l1, l2;
1146
1147 l1 = gen_new_label();
1148 l2 = gen_new_label();
bellard6e0d8672008-05-18 19:28:26 +00001149 gen_op_jnz_ecx(s->aflag, l1);
bellard14ce26e2005-01-03 23:50:08 +00001150 gen_set_label(l2);
1151 gen_jmp_tb(s, next_eip, 1);
1152 gen_set_label(l1);
1153 return l2;
bellard2c0262a2003-09-30 20:34:21 +00001154}
1155
1156static inline void gen_stos(DisasContext *s, int ot)
1157{
bellard57fec1f2008-02-01 10:50:11 +00001158 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
bellard2c0262a2003-09-30 20:34:21 +00001159 gen_string_movl_A0_EDI(s);
bellard57fec1f2008-02-01 10:50:11 +00001160 gen_op_st_T0_A0(ot + s->mem_index);
bellard6e0d8672008-05-18 19:28:26 +00001161 gen_op_movl_T0_Dshift(ot);
1162 gen_op_add_reg_T0(s->aflag, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +00001163}
1164
1165static inline void gen_lods(DisasContext *s, int ot)
1166{
1167 gen_string_movl_A0_ESI(s);
bellard57fec1f2008-02-01 10:50:11 +00001168 gen_op_ld_T0_A0(ot + s->mem_index);
1169 gen_op_mov_reg_T0(ot, R_EAX);
bellard6e0d8672008-05-18 19:28:26 +00001170 gen_op_movl_T0_Dshift(ot);
1171 gen_op_add_reg_T0(s->aflag, R_ESI);
bellard2c0262a2003-09-30 20:34:21 +00001172}
1173
1174static inline void gen_scas(DisasContext *s, int ot)
1175{
bellard57fec1f2008-02-01 10:50:11 +00001176 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
bellard2c0262a2003-09-30 20:34:21 +00001177 gen_string_movl_A0_EDI(s);
bellard57fec1f2008-02-01 10:50:11 +00001178 gen_op_ld_T1_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00001179 gen_op_cmpl_T0_T1_cc();
bellard6e0d8672008-05-18 19:28:26 +00001180 gen_op_movl_T0_Dshift(ot);
1181 gen_op_add_reg_T0(s->aflag, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +00001182}
1183
1184static inline void gen_cmps(DisasContext *s, int ot)
1185{
1186 gen_string_movl_A0_ESI(s);
bellard57fec1f2008-02-01 10:50:11 +00001187 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00001188 gen_string_movl_A0_EDI(s);
bellard57fec1f2008-02-01 10:50:11 +00001189 gen_op_ld_T1_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00001190 gen_op_cmpl_T0_T1_cc();
bellard6e0d8672008-05-18 19:28:26 +00001191 gen_op_movl_T0_Dshift(ot);
1192 gen_op_add_reg_T0(s->aflag, R_ESI);
1193 gen_op_add_reg_T0(s->aflag, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +00001194}
1195
1196static inline void gen_ins(DisasContext *s, int ot)
1197{
pbrook2e70f6e2008-06-29 01:03:05 +00001198 if (use_icount)
1199 gen_io_start();
bellard2c0262a2003-09-30 20:34:21 +00001200 gen_string_movl_A0_EDI(s);
bellard6e0d8672008-05-18 19:28:26 +00001201 /* Note: we must do this dummy write first to be restartable in
1202 case of page fault. */
bellard9772c732004-12-19 23:03:29 +00001203 gen_op_movl_T0_0();
bellard57fec1f2008-02-01 10:50:11 +00001204 gen_op_st_T0_A0(ot + s->mem_index);
bellardb8b6a502008-05-15 16:46:30 +00001205 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
bellardb6abf972008-05-17 12:44:31 +00001206 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1207 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
pbrooka7812ae2008-11-17 14:43:54 +00001208 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
bellard57fec1f2008-02-01 10:50:11 +00001209 gen_op_st_T0_A0(ot + s->mem_index);
bellard6e0d8672008-05-18 19:28:26 +00001210 gen_op_movl_T0_Dshift(ot);
1211 gen_op_add_reg_T0(s->aflag, R_EDI);
pbrook2e70f6e2008-06-29 01:03:05 +00001212 if (use_icount)
1213 gen_io_end();
bellard2c0262a2003-09-30 20:34:21 +00001214}
1215
1216static inline void gen_outs(DisasContext *s, int ot)
1217{
pbrook2e70f6e2008-06-29 01:03:05 +00001218 if (use_icount)
1219 gen_io_start();
bellard2c0262a2003-09-30 20:34:21 +00001220 gen_string_movl_A0_ESI(s);
bellard57fec1f2008-02-01 10:50:11 +00001221 gen_op_ld_T0_A0(ot + s->mem_index);
bellardb8b6a502008-05-15 16:46:30 +00001222
1223 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
bellardb6abf972008-05-17 12:44:31 +00001224 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1225 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1226 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00001227 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
bellardb8b6a502008-05-15 16:46:30 +00001228
bellard6e0d8672008-05-18 19:28:26 +00001229 gen_op_movl_T0_Dshift(ot);
1230 gen_op_add_reg_T0(s->aflag, R_ESI);
pbrook2e70f6e2008-06-29 01:03:05 +00001231 if (use_icount)
1232 gen_io_end();
bellard2c0262a2003-09-30 20:34:21 +00001233}
1234
1235/* same method as Valgrind : we generate jumps to current or next
1236 instruction */
1237#define GEN_REPZ(op) \
1238static inline void gen_repz_ ## op(DisasContext *s, int ot, \
bellard14ce26e2005-01-03 23:50:08 +00001239 target_ulong cur_eip, target_ulong next_eip) \
bellard2c0262a2003-09-30 20:34:21 +00001240{ \
bellard14ce26e2005-01-03 23:50:08 +00001241 int l2;\
bellard2c0262a2003-09-30 20:34:21 +00001242 gen_update_cc_op(s); \
bellard14ce26e2005-01-03 23:50:08 +00001243 l2 = gen_jz_ecx_string(s, next_eip); \
bellard2c0262a2003-09-30 20:34:21 +00001244 gen_ ## op(s, ot); \
bellard6e0d8672008-05-18 19:28:26 +00001245 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
bellard2c0262a2003-09-30 20:34:21 +00001246 /* a loop would cause two single step exceptions if ECX = 1 \
1247 before rep string_insn */ \
1248 if (!s->jmp_opt) \
bellard6e0d8672008-05-18 19:28:26 +00001249 gen_op_jz_ecx(s->aflag, l2); \
bellard2c0262a2003-09-30 20:34:21 +00001250 gen_jmp(s, cur_eip); \
1251}
1252
1253#define GEN_REPZ2(op) \
1254static inline void gen_repz_ ## op(DisasContext *s, int ot, \
bellard14ce26e2005-01-03 23:50:08 +00001255 target_ulong cur_eip, \
1256 target_ulong next_eip, \
bellard2c0262a2003-09-30 20:34:21 +00001257 int nz) \
1258{ \
bellard14ce26e2005-01-03 23:50:08 +00001259 int l2;\
bellard2c0262a2003-09-30 20:34:21 +00001260 gen_update_cc_op(s); \
bellard14ce26e2005-01-03 23:50:08 +00001261 l2 = gen_jz_ecx_string(s, next_eip); \
bellard2c0262a2003-09-30 20:34:21 +00001262 gen_ ## op(s, ot); \
bellard6e0d8672008-05-18 19:28:26 +00001263 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
bellard2c0262a2003-09-30 20:34:21 +00001264 gen_op_set_cc_op(CC_OP_SUBB + ot); \
bellard8e1c85e2008-05-21 19:16:45 +00001265 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
bellard2c0262a2003-09-30 20:34:21 +00001266 if (!s->jmp_opt) \
bellard6e0d8672008-05-18 19:28:26 +00001267 gen_op_jz_ecx(s->aflag, l2); \
bellard2c0262a2003-09-30 20:34:21 +00001268 gen_jmp(s, cur_eip); \
1269}
1270
1271GEN_REPZ(movs)
1272GEN_REPZ(stos)
1273GEN_REPZ(lods)
1274GEN_REPZ(ins)
1275GEN_REPZ(outs)
1276GEN_REPZ2(scas)
1277GEN_REPZ2(cmps)
1278
pbrooka7812ae2008-11-17 14:43:54 +00001279static void gen_helper_fp_arith_ST0_FT0(int op)
1280{
1281 switch (op) {
1282 case 0: gen_helper_fadd_ST0_FT0(); break;
1283 case 1: gen_helper_fmul_ST0_FT0(); break;
1284 case 2: gen_helper_fcom_ST0_FT0(); break;
1285 case 3: gen_helper_fcom_ST0_FT0(); break;
1286 case 4: gen_helper_fsub_ST0_FT0(); break;
1287 case 5: gen_helper_fsubr_ST0_FT0(); break;
1288 case 6: gen_helper_fdiv_ST0_FT0(); break;
1289 case 7: gen_helper_fdivr_ST0_FT0(); break;
1290 }
1291}
bellard2c0262a2003-09-30 20:34:21 +00001292
1293/* NOTE the exception in "r" op ordering */
pbrooka7812ae2008-11-17 14:43:54 +00001294static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1295{
1296 TCGv_i32 tmp = tcg_const_i32(opreg);
1297 switch (op) {
1298 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1299 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1300 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1301 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1302 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1303 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1304 }
1305}
bellard2c0262a2003-09-30 20:34:21 +00001306
bellardcad3a372008-05-17 13:50:02 +00001307/* if d == OR_TMP0, it means memory operand (address in A0) */
1308static void gen_op(DisasContext *s1, int op, int ot, int d)
1309{
1310 if (d != OR_TMP0) {
1311 gen_op_mov_TN_reg(ot, 0, d);
1312 } else {
1313 gen_op_ld_T0_A0(ot + s1->mem_index);
1314 }
1315 switch(op) {
1316 case OP_ADCL:
1317 if (s1->cc_op != CC_OP_DYNAMIC)
1318 gen_op_set_cc_op(s1->cc_op);
1319 gen_compute_eflags_c(cpu_tmp4);
1320 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1321 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1322 if (d != OR_TMP0)
1323 gen_op_mov_reg_T0(ot, d);
1324 else
1325 gen_op_st_T0_A0(ot + s1->mem_index);
1326 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1327 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1328 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1329 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1330 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1331 s1->cc_op = CC_OP_DYNAMIC;
1332 break;
1333 case OP_SBBL:
1334 if (s1->cc_op != CC_OP_DYNAMIC)
1335 gen_op_set_cc_op(s1->cc_op);
1336 gen_compute_eflags_c(cpu_tmp4);
1337 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1338 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1339 if (d != OR_TMP0)
1340 gen_op_mov_reg_T0(ot, d);
1341 else
1342 gen_op_st_T0_A0(ot + s1->mem_index);
1343 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1344 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1345 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1346 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1347 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1348 s1->cc_op = CC_OP_DYNAMIC;
1349 break;
1350 case OP_ADDL:
1351 gen_op_addl_T0_T1();
1352 if (d != OR_TMP0)
1353 gen_op_mov_reg_T0(ot, d);
1354 else
1355 gen_op_st_T0_A0(ot + s1->mem_index);
1356 gen_op_update2_cc();
1357 s1->cc_op = CC_OP_ADDB + ot;
1358 break;
1359 case OP_SUBL:
1360 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1361 if (d != OR_TMP0)
1362 gen_op_mov_reg_T0(ot, d);
1363 else
1364 gen_op_st_T0_A0(ot + s1->mem_index);
1365 gen_op_update2_cc();
1366 s1->cc_op = CC_OP_SUBB + ot;
1367 break;
1368 default:
1369 case OP_ANDL:
1370 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1371 if (d != OR_TMP0)
1372 gen_op_mov_reg_T0(ot, d);
1373 else
1374 gen_op_st_T0_A0(ot + s1->mem_index);
1375 gen_op_update1_cc();
1376 s1->cc_op = CC_OP_LOGICB + ot;
1377 break;
1378 case OP_ORL:
1379 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1380 if (d != OR_TMP0)
1381 gen_op_mov_reg_T0(ot, d);
1382 else
1383 gen_op_st_T0_A0(ot + s1->mem_index);
1384 gen_op_update1_cc();
1385 s1->cc_op = CC_OP_LOGICB + ot;
1386 break;
1387 case OP_XORL:
1388 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1389 if (d != OR_TMP0)
1390 gen_op_mov_reg_T0(ot, d);
1391 else
1392 gen_op_st_T0_A0(ot + s1->mem_index);
1393 gen_op_update1_cc();
1394 s1->cc_op = CC_OP_LOGICB + ot;
1395 break;
1396 case OP_CMPL:
1397 gen_op_cmpl_T0_T1_cc();
1398 s1->cc_op = CC_OP_SUBB + ot;
1399 break;
1400 }
bellardb6abf972008-05-17 12:44:31 +00001401}
1402
bellard2c0262a2003-09-30 20:34:21 +00001403/* if d == OR_TMP0, it means memory operand (address in A0) */
1404static void gen_inc(DisasContext *s1, int ot, int d, int c)
1405{
1406 if (d != OR_TMP0)
bellard57fec1f2008-02-01 10:50:11 +00001407 gen_op_mov_TN_reg(ot, 0, d);
bellard2c0262a2003-09-30 20:34:21 +00001408 else
bellard57fec1f2008-02-01 10:50:11 +00001409 gen_op_ld_T0_A0(ot + s1->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00001410 if (s1->cc_op != CC_OP_DYNAMIC)
1411 gen_op_set_cc_op(s1->cc_op);
1412 if (c > 0) {
bellardb6abf972008-05-17 12:44:31 +00001413 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
bellard2c0262a2003-09-30 20:34:21 +00001414 s1->cc_op = CC_OP_INCB + ot;
1415 } else {
bellardb6abf972008-05-17 12:44:31 +00001416 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
bellard2c0262a2003-09-30 20:34:21 +00001417 s1->cc_op = CC_OP_DECB + ot;
1418 }
1419 if (d != OR_TMP0)
bellard57fec1f2008-02-01 10:50:11 +00001420 gen_op_mov_reg_T0(ot, d);
bellard2c0262a2003-09-30 20:34:21 +00001421 else
bellard57fec1f2008-02-01 10:50:11 +00001422 gen_op_st_T0_A0(ot + s1->mem_index);
bellardb6abf972008-05-17 12:44:31 +00001423 gen_compute_eflags_c(cpu_cc_src);
bellardcd31fef2008-05-18 19:19:57 +00001424 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
bellardb6abf972008-05-17 12:44:31 +00001425}
1426
bellardb6abf972008-05-17 12:44:31 +00001427static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1428 int is_right, int is_arith)
1429{
1430 target_ulong mask;
1431 int shift_label;
bellard1e4840b2008-05-25 17:26:41 +00001432 TCGv t0, t1;
1433
bellardb6abf972008-05-17 12:44:31 +00001434 if (ot == OT_QUAD)
1435 mask = 0x3f;
1436 else
1437 mask = 0x1f;
1438
1439 /* load */
1440 if (op1 == OR_TMP0)
1441 gen_op_ld_T0_A0(ot + s->mem_index);
1442 else
1443 gen_op_mov_TN_reg(ot, 0, op1);
1444
1445 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1446
1447 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1448
1449 if (is_right) {
1450 if (is_arith) {
bellardf484d382008-05-17 16:10:38 +00001451 gen_exts(ot, cpu_T[0]);
bellardb6abf972008-05-17 12:44:31 +00001452 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1453 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1454 } else {
bellardcad3a372008-05-17 13:50:02 +00001455 gen_extu(ot, cpu_T[0]);
bellardb6abf972008-05-17 12:44:31 +00001456 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1457 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1458 }
1459 } else {
1460 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1461 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1462 }
1463
1464 /* store */
1465 if (op1 == OR_TMP0)
1466 gen_op_st_T0_A0(ot + s->mem_index);
1467 else
1468 gen_op_mov_reg_T0(ot, op1);
1469
1470 /* update eflags if non zero shift */
1471 if (s->cc_op != CC_OP_DYNAMIC)
1472 gen_op_set_cc_op(s->cc_op);
1473
bellard1e4840b2008-05-25 17:26:41 +00001474 /* XXX: inefficient */
pbrooka7812ae2008-11-17 14:43:54 +00001475 t0 = tcg_temp_local_new();
1476 t1 = tcg_temp_local_new();
bellard1e4840b2008-05-25 17:26:41 +00001477
1478 tcg_gen_mov_tl(t0, cpu_T[0]);
1479 tcg_gen_mov_tl(t1, cpu_T3);
1480
bellardb6abf972008-05-17 12:44:31 +00001481 shift_label = gen_new_label();
pbrookcb636692008-05-24 02:22:00 +00001482 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
bellardb6abf972008-05-17 12:44:31 +00001483
bellard1e4840b2008-05-25 17:26:41 +00001484 tcg_gen_mov_tl(cpu_cc_src, t1);
1485 tcg_gen_mov_tl(cpu_cc_dst, t0);
bellardb6abf972008-05-17 12:44:31 +00001486 if (is_right)
1487 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1488 else
1489 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1490
1491 gen_set_label(shift_label);
1492 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
bellard1e4840b2008-05-25 17:26:41 +00001493
1494 tcg_temp_free(t0);
1495 tcg_temp_free(t1);
bellardb6abf972008-05-17 12:44:31 +00001496}
1497
bellardc1c37962008-05-22 12:36:31 +00001498static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1499 int is_right, int is_arith)
1500{
1501 int mask;
1502
1503 if (ot == OT_QUAD)
1504 mask = 0x3f;
1505 else
1506 mask = 0x1f;
1507
1508 /* load */
1509 if (op1 == OR_TMP0)
1510 gen_op_ld_T0_A0(ot + s->mem_index);
1511 else
1512 gen_op_mov_TN_reg(ot, 0, op1);
1513
1514 op2 &= mask;
1515 if (op2 != 0) {
1516 if (is_right) {
1517 if (is_arith) {
1518 gen_exts(ot, cpu_T[0]);
bellard2a449d12008-05-25 21:01:05 +00001519 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
bellardc1c37962008-05-22 12:36:31 +00001520 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1521 } else {
1522 gen_extu(ot, cpu_T[0]);
bellard2a449d12008-05-25 21:01:05 +00001523 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
bellardc1c37962008-05-22 12:36:31 +00001524 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1525 }
1526 } else {
bellard2a449d12008-05-25 21:01:05 +00001527 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
bellardc1c37962008-05-22 12:36:31 +00001528 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1529 }
1530 }
1531
1532 /* store */
1533 if (op1 == OR_TMP0)
1534 gen_op_st_T0_A0(ot + s->mem_index);
1535 else
1536 gen_op_mov_reg_T0(ot, op1);
1537
1538 /* update eflags if non zero shift */
1539 if (op2 != 0) {
bellard2a449d12008-05-25 21:01:05 +00001540 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
bellardc1c37962008-05-22 12:36:31 +00001541 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1542 if (is_right)
1543 s->cc_op = CC_OP_SARB + ot;
1544 else
1545 s->cc_op = CC_OP_SHLB + ot;
1546 }
1547}
1548
bellardb6abf972008-05-17 12:44:31 +00001549static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1550{
1551 if (arg2 >= 0)
1552 tcg_gen_shli_tl(ret, arg1, arg2);
1553 else
1554 tcg_gen_shri_tl(ret, arg1, -arg2);
1555}
1556
bellardb6abf972008-05-17 12:44:31 +00001557static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1558 int is_right)
1559{
1560 target_ulong mask;
1561 int label1, label2, data_bits;
bellard1e4840b2008-05-25 17:26:41 +00001562 TCGv t0, t1, t2, a0;
1563
1564 /* XXX: inefficient, but we must use local temps */
pbrooka7812ae2008-11-17 14:43:54 +00001565 t0 = tcg_temp_local_new();
1566 t1 = tcg_temp_local_new();
1567 t2 = tcg_temp_local_new();
1568 a0 = tcg_temp_local_new();
bellard1e4840b2008-05-25 17:26:41 +00001569
bellardb6abf972008-05-17 12:44:31 +00001570 if (ot == OT_QUAD)
1571 mask = 0x3f;
1572 else
1573 mask = 0x1f;
1574
1575 /* load */
bellard1e4840b2008-05-25 17:26:41 +00001576 if (op1 == OR_TMP0) {
1577 tcg_gen_mov_tl(a0, cpu_A0);
1578 gen_op_ld_v(ot + s->mem_index, t0, a0);
1579 } else {
1580 gen_op_mov_v_reg(ot, t0, op1);
1581 }
bellardb6abf972008-05-17 12:44:31 +00001582
bellard1e4840b2008-05-25 17:26:41 +00001583 tcg_gen_mov_tl(t1, cpu_T[1]);
1584
1585 tcg_gen_andi_tl(t1, t1, mask);
bellardb6abf972008-05-17 12:44:31 +00001586
1587 /* Must test zero case to avoid using undefined behaviour in TCG
1588 shifts. */
1589 label1 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00001590 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
bellardb6abf972008-05-17 12:44:31 +00001591
1592 if (ot <= OT_WORD)
bellard1e4840b2008-05-25 17:26:41 +00001593 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
bellardb6abf972008-05-17 12:44:31 +00001594 else
bellard1e4840b2008-05-25 17:26:41 +00001595 tcg_gen_mov_tl(cpu_tmp0, t1);
bellardb6abf972008-05-17 12:44:31 +00001596
bellard1e4840b2008-05-25 17:26:41 +00001597 gen_extu(ot, t0);
1598 tcg_gen_mov_tl(t2, t0);
bellardb6abf972008-05-17 12:44:31 +00001599
1600 data_bits = 8 << ot;
1601 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1602 fix TCG definition) */
1603 if (is_right) {
bellard1e4840b2008-05-25 17:26:41 +00001604 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001605 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
bellard1e4840b2008-05-25 17:26:41 +00001606 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
bellardb6abf972008-05-17 12:44:31 +00001607 } else {
bellard1e4840b2008-05-25 17:26:41 +00001608 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001609 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
bellard1e4840b2008-05-25 17:26:41 +00001610 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
bellardb6abf972008-05-17 12:44:31 +00001611 }
bellard1e4840b2008-05-25 17:26:41 +00001612 tcg_gen_or_tl(t0, t0, cpu_tmp4);
bellardb6abf972008-05-17 12:44:31 +00001613
1614 gen_set_label(label1);
1615 /* store */
bellard1e4840b2008-05-25 17:26:41 +00001616 if (op1 == OR_TMP0) {
1617 gen_op_st_v(ot + s->mem_index, t0, a0);
1618 } else {
1619 gen_op_mov_reg_v(ot, op1, t0);
1620 }
bellardb6abf972008-05-17 12:44:31 +00001621
1622 /* update eflags */
1623 if (s->cc_op != CC_OP_DYNAMIC)
1624 gen_op_set_cc_op(s->cc_op);
1625
1626 label2 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00001627 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
bellardb6abf972008-05-17 12:44:31 +00001628
1629 gen_compute_eflags(cpu_cc_src);
1630 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
bellard1e4840b2008-05-25 17:26:41 +00001631 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
bellardb6abf972008-05-17 12:44:31 +00001632 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1633 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1634 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1635 if (is_right) {
bellard1e4840b2008-05-25 17:26:41 +00001636 tcg_gen_shri_tl(t0, t0, data_bits - 1);
bellardb6abf972008-05-17 12:44:31 +00001637 }
bellard1e4840b2008-05-25 17:26:41 +00001638 tcg_gen_andi_tl(t0, t0, CC_C);
1639 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
bellardb6abf972008-05-17 12:44:31 +00001640
1641 tcg_gen_discard_tl(cpu_cc_dst);
1642 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1643
1644 gen_set_label(label2);
1645 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
bellard1e4840b2008-05-25 17:26:41 +00001646
1647 tcg_temp_free(t0);
1648 tcg_temp_free(t1);
1649 tcg_temp_free(t2);
1650 tcg_temp_free(a0);
bellardb6abf972008-05-17 12:44:31 +00001651}
1652
malc8cd63452009-04-02 22:54:35 +00001653static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1654 int is_right)
1655{
1656 int mask;
1657 int data_bits;
1658 TCGv t0, t1, a0;
1659
1660 /* XXX: inefficient, but we must use local temps */
1661 t0 = tcg_temp_local_new();
1662 t1 = tcg_temp_local_new();
1663 a0 = tcg_temp_local_new();
1664
1665 if (ot == OT_QUAD)
1666 mask = 0x3f;
1667 else
1668 mask = 0x1f;
1669
1670 /* load */
1671 if (op1 == OR_TMP0) {
1672 tcg_gen_mov_tl(a0, cpu_A0);
1673 gen_op_ld_v(ot + s->mem_index, t0, a0);
1674 } else {
1675 gen_op_mov_v_reg(ot, t0, op1);
1676 }
1677
1678 gen_extu(ot, t0);
1679 tcg_gen_mov_tl(t1, t0);
1680
1681 op2 &= mask;
1682 data_bits = 8 << ot;
1683 if (op2 != 0) {
1684 int shift = op2 & ((1 << (3 + ot)) - 1);
1685 if (is_right) {
1686 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1687 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1688 }
1689 else {
1690 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1691 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1692 }
1693 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1694 }
1695
1696 /* store */
1697 if (op1 == OR_TMP0) {
1698 gen_op_st_v(ot + s->mem_index, t0, a0);
1699 } else {
1700 gen_op_mov_reg_v(ot, op1, t0);
1701 }
1702
1703 if (op2 != 0) {
1704 /* update eflags */
1705 if (s->cc_op != CC_OP_DYNAMIC)
1706 gen_op_set_cc_op(s->cc_op);
1707
1708 gen_compute_eflags(cpu_cc_src);
1709 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1710 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1711 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1712 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1713 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1714 if (is_right) {
1715 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1716 }
1717 tcg_gen_andi_tl(t0, t0, CC_C);
1718 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1719
1720 tcg_gen_discard_tl(cpu_cc_dst);
1721 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1722 s->cc_op = CC_OP_EFLAGS;
1723 }
1724
1725 tcg_temp_free(t0);
1726 tcg_temp_free(t1);
1727 tcg_temp_free(a0);
1728}
1729
bellardb6abf972008-05-17 12:44:31 +00001730/* XXX: add faster immediate = 1 case */
1731static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1732 int is_right)
1733{
1734 int label1;
1735
1736 if (s->cc_op != CC_OP_DYNAMIC)
1737 gen_op_set_cc_op(s->cc_op);
1738
1739 /* load */
1740 if (op1 == OR_TMP0)
1741 gen_op_ld_T0_A0(ot + s->mem_index);
1742 else
1743 gen_op_mov_TN_reg(ot, 0, op1);
1744
pbrooka7812ae2008-11-17 14:43:54 +00001745 if (is_right) {
1746 switch (ot) {
1747 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1750#ifdef TARGET_X86_64
1751 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1752#endif
1753 }
1754 } else {
1755 switch (ot) {
1756 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1757 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1758 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1759#ifdef TARGET_X86_64
1760 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1761#endif
1762 }
1763 }
bellardb6abf972008-05-17 12:44:31 +00001764 /* store */
1765 if (op1 == OR_TMP0)
1766 gen_op_st_T0_A0(ot + s->mem_index);
1767 else
1768 gen_op_mov_reg_T0(ot, op1);
1769
1770 /* update eflags */
1771 label1 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00001772 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
bellardb6abf972008-05-17 12:44:31 +00001773
bellard1e4840b2008-05-25 17:26:41 +00001774 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
bellardb6abf972008-05-17 12:44:31 +00001775 tcg_gen_discard_tl(cpu_cc_dst);
1776 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1777
1778 gen_set_label(label1);
1779 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1780}
1781
1782/* XXX: add faster immediate case */
1783static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1784 int is_right)
1785{
1786 int label1, label2, data_bits;
1787 target_ulong mask;
bellard1e4840b2008-05-25 17:26:41 +00001788 TCGv t0, t1, t2, a0;
1789
pbrooka7812ae2008-11-17 14:43:54 +00001790 t0 = tcg_temp_local_new();
1791 t1 = tcg_temp_local_new();
1792 t2 = tcg_temp_local_new();
1793 a0 = tcg_temp_local_new();
bellardb6abf972008-05-17 12:44:31 +00001794
1795 if (ot == OT_QUAD)
1796 mask = 0x3f;
1797 else
1798 mask = 0x1f;
1799
1800 /* load */
bellard1e4840b2008-05-25 17:26:41 +00001801 if (op1 == OR_TMP0) {
1802 tcg_gen_mov_tl(a0, cpu_A0);
1803 gen_op_ld_v(ot + s->mem_index, t0, a0);
1804 } else {
1805 gen_op_mov_v_reg(ot, t0, op1);
1806 }
bellardb6abf972008-05-17 12:44:31 +00001807
1808 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
bellard1e4840b2008-05-25 17:26:41 +00001809
1810 tcg_gen_mov_tl(t1, cpu_T[1]);
1811 tcg_gen_mov_tl(t2, cpu_T3);
1812
bellardb6abf972008-05-17 12:44:31 +00001813 /* Must test zero case to avoid using undefined behaviour in TCG
1814 shifts. */
1815 label1 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00001816 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
bellardb6abf972008-05-17 12:44:31 +00001817
bellard1e4840b2008-05-25 17:26:41 +00001818 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
bellardb6abf972008-05-17 12:44:31 +00001819 if (ot == OT_WORD) {
1820 /* Note: we implement the Intel behaviour for shift count > 16 */
1821 if (is_right) {
bellard1e4840b2008-05-25 17:26:41 +00001822 tcg_gen_andi_tl(t0, t0, 0xffff);
1823 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1824 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1825 tcg_gen_ext32u_tl(t0, t0);
bellardb6abf972008-05-17 12:44:31 +00001826
bellard1e4840b2008-05-25 17:26:41 +00001827 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
bellardb6abf972008-05-17 12:44:31 +00001828
1829 /* only needed if count > 16, but a test would complicate */
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001830 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
bellard1e4840b2008-05-25 17:26:41 +00001831 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
bellardb6abf972008-05-17 12:44:31 +00001832
bellard1e4840b2008-05-25 17:26:41 +00001833 tcg_gen_shr_tl(t0, t0, t2);
bellardb6abf972008-05-17 12:44:31 +00001834
bellard1e4840b2008-05-25 17:26:41 +00001835 tcg_gen_or_tl(t0, t0, cpu_tmp0);
bellardb6abf972008-05-17 12:44:31 +00001836 } else {
1837 /* XXX: not optimal */
bellard1e4840b2008-05-25 17:26:41 +00001838 tcg_gen_andi_tl(t0, t0, 0xffff);
1839 tcg_gen_shli_tl(t1, t1, 16);
1840 tcg_gen_or_tl(t1, t1, t0);
1841 tcg_gen_ext32u_tl(t1, t1);
bellardb6abf972008-05-17 12:44:31 +00001842
bellard1e4840b2008-05-25 17:26:41 +00001843 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001844 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
Aurelien Jarnobedda792009-09-27 00:56:22 +02001845 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1846 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
bellardb6abf972008-05-17 12:44:31 +00001847
bellard1e4840b2008-05-25 17:26:41 +00001848 tcg_gen_shl_tl(t0, t0, t2);
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001849 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
bellard1e4840b2008-05-25 17:26:41 +00001850 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1851 tcg_gen_or_tl(t0, t0, t1);
bellardb6abf972008-05-17 12:44:31 +00001852 }
1853 } else {
1854 data_bits = 8 << ot;
1855 if (is_right) {
1856 if (ot == OT_LONG)
bellard1e4840b2008-05-25 17:26:41 +00001857 tcg_gen_ext32u_tl(t0, t0);
bellardb6abf972008-05-17 12:44:31 +00001858
bellard1e4840b2008-05-25 17:26:41 +00001859 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
bellardb6abf972008-05-17 12:44:31 +00001860
bellard1e4840b2008-05-25 17:26:41 +00001861 tcg_gen_shr_tl(t0, t0, t2);
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001862 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
bellard1e4840b2008-05-25 17:26:41 +00001863 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1864 tcg_gen_or_tl(t0, t0, t1);
bellardb6abf972008-05-17 12:44:31 +00001865
1866 } else {
1867 if (ot == OT_LONG)
bellard1e4840b2008-05-25 17:26:41 +00001868 tcg_gen_ext32u_tl(t1, t1);
bellardb6abf972008-05-17 12:44:31 +00001869
bellard1e4840b2008-05-25 17:26:41 +00001870 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
bellardb6abf972008-05-17 12:44:31 +00001871
bellard1e4840b2008-05-25 17:26:41 +00001872 tcg_gen_shl_tl(t0, t0, t2);
Aurelien Jarno5b207c02009-09-27 00:48:05 +02001873 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
bellard1e4840b2008-05-25 17:26:41 +00001874 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1875 tcg_gen_or_tl(t0, t0, t1);
bellardb6abf972008-05-17 12:44:31 +00001876 }
1877 }
bellard1e4840b2008-05-25 17:26:41 +00001878 tcg_gen_mov_tl(t1, cpu_tmp4);
bellardb6abf972008-05-17 12:44:31 +00001879
1880 gen_set_label(label1);
1881 /* store */
bellard1e4840b2008-05-25 17:26:41 +00001882 if (op1 == OR_TMP0) {
1883 gen_op_st_v(ot + s->mem_index, t0, a0);
1884 } else {
1885 gen_op_mov_reg_v(ot, op1, t0);
1886 }
bellardb6abf972008-05-17 12:44:31 +00001887
1888 /* update eflags */
1889 if (s->cc_op != CC_OP_DYNAMIC)
1890 gen_op_set_cc_op(s->cc_op);
1891
1892 label2 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00001893 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
bellardb6abf972008-05-17 12:44:31 +00001894
bellard1e4840b2008-05-25 17:26:41 +00001895 tcg_gen_mov_tl(cpu_cc_src, t1);
1896 tcg_gen_mov_tl(cpu_cc_dst, t0);
bellardb6abf972008-05-17 12:44:31 +00001897 if (is_right) {
1898 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1899 } else {
1900 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1901 }
1902 gen_set_label(label2);
1903 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
bellard1e4840b2008-05-25 17:26:41 +00001904
1905 tcg_temp_free(t0);
1906 tcg_temp_free(t1);
1907 tcg_temp_free(t2);
1908 tcg_temp_free(a0);
bellard2c0262a2003-09-30 20:34:21 +00001909}
1910
1911static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1912{
bellard2c0262a2003-09-30 20:34:21 +00001913 if (s != OR_TMP1)
bellard57fec1f2008-02-01 10:50:11 +00001914 gen_op_mov_TN_reg(ot, 1, s);
bellardb6abf972008-05-17 12:44:31 +00001915 switch(op) {
1916 case OP_ROL:
1917 gen_rot_rm_T1(s1, ot, d, 0);
1918 break;
1919 case OP_ROR:
1920 gen_rot_rm_T1(s1, ot, d, 1);
1921 break;
1922 case OP_SHL:
1923 case OP_SHL1:
1924 gen_shift_rm_T1(s1, ot, d, 0, 0);
1925 break;
1926 case OP_SHR:
1927 gen_shift_rm_T1(s1, ot, d, 1, 0);
1928 break;
1929 case OP_SAR:
1930 gen_shift_rm_T1(s1, ot, d, 1, 1);
1931 break;
1932 case OP_RCL:
1933 gen_rotc_rm_T1(s1, ot, d, 0);
1934 break;
1935 case OP_RCR:
1936 gen_rotc_rm_T1(s1, ot, d, 1);
1937 break;
1938 }
bellard2c0262a2003-09-30 20:34:21 +00001939}
1940
1941static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1942{
bellardc1c37962008-05-22 12:36:31 +00001943 switch(op) {
malc8cd63452009-04-02 22:54:35 +00001944 case OP_ROL:
1945 gen_rot_rm_im(s1, ot, d, c, 0);
1946 break;
1947 case OP_ROR:
1948 gen_rot_rm_im(s1, ot, d, c, 1);
1949 break;
bellardc1c37962008-05-22 12:36:31 +00001950 case OP_SHL:
1951 case OP_SHL1:
1952 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1953 break;
1954 case OP_SHR:
1955 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1956 break;
1957 case OP_SAR:
1958 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1959 break;
1960 default:
1961 /* currently not optimized */
1962 gen_op_movl_T1_im(c);
1963 gen_shift(s1, op, ot, d, OR_TMP1);
1964 break;
1965 }
bellard2c0262a2003-09-30 20:34:21 +00001966}
1967
1968static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1969{
bellard14ce26e2005-01-03 23:50:08 +00001970 target_long disp;
bellard2c0262a2003-09-30 20:34:21 +00001971 int havesib;
bellard14ce26e2005-01-03 23:50:08 +00001972 int base;
bellard2c0262a2003-09-30 20:34:21 +00001973 int index;
1974 int scale;
1975 int opreg;
1976 int mod, rm, code, override, must_add_seg;
1977
1978 override = s->override;
1979 must_add_seg = s->addseg;
1980 if (override >= 0)
1981 must_add_seg = 1;
1982 mod = (modrm >> 6) & 3;
1983 rm = modrm & 7;
1984
1985 if (s->aflag) {
1986
1987 havesib = 0;
1988 base = rm;
1989 index = 0;
1990 scale = 0;
ths3b46e622007-09-17 08:09:54 +00001991
bellard2c0262a2003-09-30 20:34:21 +00001992 if (base == 4) {
1993 havesib = 1;
bellard61382a52003-10-27 21:22:23 +00001994 code = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00001995 scale = (code >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00001996 index = ((code >> 3) & 7) | REX_X(s);
1997 base = (code & 7);
bellard2c0262a2003-09-30 20:34:21 +00001998 }
bellard14ce26e2005-01-03 23:50:08 +00001999 base |= REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00002000
2001 switch (mod) {
2002 case 0:
bellard14ce26e2005-01-03 23:50:08 +00002003 if ((base & 7) == 5) {
bellard2c0262a2003-09-30 20:34:21 +00002004 base = -1;
bellard14ce26e2005-01-03 23:50:08 +00002005 disp = (int32_t)ldl_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002006 s->pc += 4;
bellard14ce26e2005-01-03 23:50:08 +00002007 if (CODE64(s) && !havesib) {
2008 disp += s->pc + s->rip_offset;
2009 }
bellard2c0262a2003-09-30 20:34:21 +00002010 } else {
2011 disp = 0;
2012 }
2013 break;
2014 case 1:
bellard61382a52003-10-27 21:22:23 +00002015 disp = (int8_t)ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00002016 break;
2017 default:
2018 case 2:
Paolo Bonzini8c0e6342010-06-04 16:27:33 +02002019 disp = (int32_t)ldl_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002020 s->pc += 4;
2021 break;
2022 }
ths3b46e622007-09-17 08:09:54 +00002023
bellard2c0262a2003-09-30 20:34:21 +00002024 if (base >= 0) {
2025 /* for correct popl handling with esp */
2026 if (base == 4 && s->popl_esp_hack)
2027 disp += s->popl_esp_hack;
bellard14ce26e2005-01-03 23:50:08 +00002028#ifdef TARGET_X86_64
2029 if (s->aflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +00002030 gen_op_movq_A0_reg(base);
bellard14ce26e2005-01-03 23:50:08 +00002031 if (disp != 0) {
bellard57fec1f2008-02-01 10:50:11 +00002032 gen_op_addq_A0_im(disp);
bellard14ce26e2005-01-03 23:50:08 +00002033 }
ths5fafdf22007-09-16 21:08:06 +00002034 } else
bellard14ce26e2005-01-03 23:50:08 +00002035#endif
2036 {
bellard57fec1f2008-02-01 10:50:11 +00002037 gen_op_movl_A0_reg(base);
bellard14ce26e2005-01-03 23:50:08 +00002038 if (disp != 0)
2039 gen_op_addl_A0_im(disp);
2040 }
bellard2c0262a2003-09-30 20:34:21 +00002041 } else {
bellard14ce26e2005-01-03 23:50:08 +00002042#ifdef TARGET_X86_64
2043 if (s->aflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +00002044 gen_op_movq_A0_im(disp);
ths5fafdf22007-09-16 21:08:06 +00002045 } else
bellard14ce26e2005-01-03 23:50:08 +00002046#endif
2047 {
2048 gen_op_movl_A0_im(disp);
2049 }
bellard2c0262a2003-09-30 20:34:21 +00002050 }
Aurelien Jarnob16f8272010-03-06 18:02:31 +01002051 /* index == 4 means no index */
2052 if (havesib && (index != 4)) {
bellard14ce26e2005-01-03 23:50:08 +00002053#ifdef TARGET_X86_64
2054 if (s->aflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +00002055 gen_op_addq_A0_reg_sN(scale, index);
ths5fafdf22007-09-16 21:08:06 +00002056 } else
bellard14ce26e2005-01-03 23:50:08 +00002057#endif
2058 {
bellard57fec1f2008-02-01 10:50:11 +00002059 gen_op_addl_A0_reg_sN(scale, index);
bellard14ce26e2005-01-03 23:50:08 +00002060 }
bellard2c0262a2003-09-30 20:34:21 +00002061 }
2062 if (must_add_seg) {
2063 if (override < 0) {
2064 if (base == R_EBP || base == R_ESP)
2065 override = R_SS;
2066 else
2067 override = R_DS;
2068 }
bellard14ce26e2005-01-03 23:50:08 +00002069#ifdef TARGET_X86_64
2070 if (s->aflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +00002071 gen_op_addq_A0_seg(override);
ths5fafdf22007-09-16 21:08:06 +00002072 } else
bellard14ce26e2005-01-03 23:50:08 +00002073#endif
2074 {
bellard57fec1f2008-02-01 10:50:11 +00002075 gen_op_addl_A0_seg(override);
bellard14ce26e2005-01-03 23:50:08 +00002076 }
bellard2c0262a2003-09-30 20:34:21 +00002077 }
2078 } else {
2079 switch (mod) {
2080 case 0:
2081 if (rm == 6) {
bellard61382a52003-10-27 21:22:23 +00002082 disp = lduw_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002083 s->pc += 2;
2084 gen_op_movl_A0_im(disp);
2085 rm = 0; /* avoid SS override */
2086 goto no_rm;
2087 } else {
2088 disp = 0;
2089 }
2090 break;
2091 case 1:
bellard61382a52003-10-27 21:22:23 +00002092 disp = (int8_t)ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00002093 break;
2094 default:
2095 case 2:
bellard61382a52003-10-27 21:22:23 +00002096 disp = lduw_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002097 s->pc += 2;
2098 break;
2099 }
2100 switch(rm) {
2101 case 0:
bellard57fec1f2008-02-01 10:50:11 +00002102 gen_op_movl_A0_reg(R_EBX);
2103 gen_op_addl_A0_reg_sN(0, R_ESI);
bellard2c0262a2003-09-30 20:34:21 +00002104 break;
2105 case 1:
bellard57fec1f2008-02-01 10:50:11 +00002106 gen_op_movl_A0_reg(R_EBX);
2107 gen_op_addl_A0_reg_sN(0, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +00002108 break;
2109 case 2:
bellard57fec1f2008-02-01 10:50:11 +00002110 gen_op_movl_A0_reg(R_EBP);
2111 gen_op_addl_A0_reg_sN(0, R_ESI);
bellard2c0262a2003-09-30 20:34:21 +00002112 break;
2113 case 3:
bellard57fec1f2008-02-01 10:50:11 +00002114 gen_op_movl_A0_reg(R_EBP);
2115 gen_op_addl_A0_reg_sN(0, R_EDI);
bellard2c0262a2003-09-30 20:34:21 +00002116 break;
2117 case 4:
bellard57fec1f2008-02-01 10:50:11 +00002118 gen_op_movl_A0_reg(R_ESI);
bellard2c0262a2003-09-30 20:34:21 +00002119 break;
2120 case 5:
bellard57fec1f2008-02-01 10:50:11 +00002121 gen_op_movl_A0_reg(R_EDI);
bellard2c0262a2003-09-30 20:34:21 +00002122 break;
2123 case 6:
bellard57fec1f2008-02-01 10:50:11 +00002124 gen_op_movl_A0_reg(R_EBP);
bellard2c0262a2003-09-30 20:34:21 +00002125 break;
2126 default:
2127 case 7:
bellard57fec1f2008-02-01 10:50:11 +00002128 gen_op_movl_A0_reg(R_EBX);
bellard2c0262a2003-09-30 20:34:21 +00002129 break;
2130 }
2131 if (disp != 0)
2132 gen_op_addl_A0_im(disp);
2133 gen_op_andl_A0_ffff();
2134 no_rm:
2135 if (must_add_seg) {
2136 if (override < 0) {
2137 if (rm == 2 || rm == 3 || rm == 6)
2138 override = R_SS;
2139 else
2140 override = R_DS;
2141 }
bellard57fec1f2008-02-01 10:50:11 +00002142 gen_op_addl_A0_seg(override);
bellard2c0262a2003-09-30 20:34:21 +00002143 }
2144 }
2145
2146 opreg = OR_A0;
2147 disp = 0;
2148 *reg_ptr = opreg;
2149 *offset_ptr = disp;
2150}
2151
bellarde17a36c2006-09-03 17:09:02 +00002152static void gen_nop_modrm(DisasContext *s, int modrm)
2153{
2154 int mod, rm, base, code;
2155
2156 mod = (modrm >> 6) & 3;
2157 if (mod == 3)
2158 return;
2159 rm = modrm & 7;
2160
2161 if (s->aflag) {
2162
2163 base = rm;
ths3b46e622007-09-17 08:09:54 +00002164
bellarde17a36c2006-09-03 17:09:02 +00002165 if (base == 4) {
2166 code = ldub_code(s->pc++);
2167 base = (code & 7);
2168 }
ths3b46e622007-09-17 08:09:54 +00002169
bellarde17a36c2006-09-03 17:09:02 +00002170 switch (mod) {
2171 case 0:
2172 if (base == 5) {
2173 s->pc += 4;
2174 }
2175 break;
2176 case 1:
2177 s->pc++;
2178 break;
2179 default:
2180 case 2:
2181 s->pc += 4;
2182 break;
2183 }
2184 } else {
2185 switch (mod) {
2186 case 0:
2187 if (rm == 6) {
2188 s->pc += 2;
2189 }
2190 break;
2191 case 1:
2192 s->pc++;
2193 break;
2194 default:
2195 case 2:
2196 s->pc += 2;
2197 break;
2198 }
2199 }
2200}
2201
bellard664e0f12005-01-08 18:58:29 +00002202/* used for LEA and MOV AX, mem */
2203static void gen_add_A0_ds_seg(DisasContext *s)
2204{
2205 int override, must_add_seg;
2206 must_add_seg = s->addseg;
2207 override = R_DS;
2208 if (s->override >= 0) {
2209 override = s->override;
2210 must_add_seg = 1;
bellard664e0f12005-01-08 18:58:29 +00002211 }
2212 if (must_add_seg) {
bellard8f091a52005-07-23 17:41:26 +00002213#ifdef TARGET_X86_64
2214 if (CODE64(s)) {
bellard57fec1f2008-02-01 10:50:11 +00002215 gen_op_addq_A0_seg(override);
ths5fafdf22007-09-16 21:08:06 +00002216 } else
bellard8f091a52005-07-23 17:41:26 +00002217#endif
2218 {
bellard57fec1f2008-02-01 10:50:11 +00002219 gen_op_addl_A0_seg(override);
bellard8f091a52005-07-23 17:41:26 +00002220 }
bellard664e0f12005-01-08 18:58:29 +00002221 }
2222}
2223
balrog222a3332008-10-04 03:27:44 +00002224/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
bellard2c0262a2003-09-30 20:34:21 +00002225 OR_TMP0 */
2226static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2227{
2228 int mod, rm, opreg, disp;
2229
2230 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00002231 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00002232 if (mod == 3) {
2233 if (is_store) {
2234 if (reg != OR_TMP0)
bellard57fec1f2008-02-01 10:50:11 +00002235 gen_op_mov_TN_reg(ot, 0, reg);
2236 gen_op_mov_reg_T0(ot, rm);
bellard2c0262a2003-09-30 20:34:21 +00002237 } else {
bellard57fec1f2008-02-01 10:50:11 +00002238 gen_op_mov_TN_reg(ot, 0, rm);
bellard2c0262a2003-09-30 20:34:21 +00002239 if (reg != OR_TMP0)
bellard57fec1f2008-02-01 10:50:11 +00002240 gen_op_mov_reg_T0(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00002241 }
2242 } else {
2243 gen_lea_modrm(s, modrm, &opreg, &disp);
2244 if (is_store) {
2245 if (reg != OR_TMP0)
bellard57fec1f2008-02-01 10:50:11 +00002246 gen_op_mov_TN_reg(ot, 0, reg);
2247 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00002248 } else {
bellard57fec1f2008-02-01 10:50:11 +00002249 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00002250 if (reg != OR_TMP0)
bellard57fec1f2008-02-01 10:50:11 +00002251 gen_op_mov_reg_T0(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00002252 }
2253 }
2254}
2255
2256static inline uint32_t insn_get(DisasContext *s, int ot)
2257{
2258 uint32_t ret;
2259
2260 switch(ot) {
2261 case OT_BYTE:
bellard61382a52003-10-27 21:22:23 +00002262 ret = ldub_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002263 s->pc++;
2264 break;
2265 case OT_WORD:
bellard61382a52003-10-27 21:22:23 +00002266 ret = lduw_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002267 s->pc += 2;
2268 break;
2269 default:
2270 case OT_LONG:
bellard61382a52003-10-27 21:22:23 +00002271 ret = ldl_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00002272 s->pc += 4;
2273 break;
2274 }
2275 return ret;
2276}
2277
bellard14ce26e2005-01-03 23:50:08 +00002278static inline int insn_const_size(unsigned int ot)
2279{
2280 if (ot <= OT_LONG)
2281 return 1 << ot;
2282 else
2283 return 4;
2284}
2285
bellard6e256c92005-11-20 10:32:05 +00002286static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2287{
2288 TranslationBlock *tb;
2289 target_ulong pc;
2290
2291 pc = s->cs_base + eip;
2292 tb = s->tb;
2293 /* NOTE: we handle the case where the TB spans two pages here */
2294 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2295 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2296 /* jump to same page: we can use a direct jump */
bellard57fec1f2008-02-01 10:50:11 +00002297 tcg_gen_goto_tb(tb_num);
bellard6e256c92005-11-20 10:32:05 +00002298 gen_jmp_im(eip);
bellard57fec1f2008-02-01 10:50:11 +00002299 tcg_gen_exit_tb((long)tb + tb_num);
bellard6e256c92005-11-20 10:32:05 +00002300 } else {
2301 /* jump to another page: currently not optimized */
2302 gen_jmp_im(eip);
2303 gen_eob(s);
2304 }
2305}
2306
ths5fafdf22007-09-16 21:08:06 +00002307static inline void gen_jcc(DisasContext *s, int b,
bellard14ce26e2005-01-03 23:50:08 +00002308 target_ulong val, target_ulong next_eip)
bellard2c0262a2003-09-30 20:34:21 +00002309{
bellard8e1c85e2008-05-21 19:16:45 +00002310 int l1, l2, cc_op;
bellard2c0262a2003-09-30 20:34:21 +00002311
bellard8e1c85e2008-05-21 19:16:45 +00002312 cc_op = s->cc_op;
Jun Koi728d8032010-07-25 12:30:03 +09002313 gen_update_cc_op(s);
bellard2c0262a2003-09-30 20:34:21 +00002314 if (s->jmp_opt) {
bellard14ce26e2005-01-03 23:50:08 +00002315 l1 = gen_new_label();
bellard8e1c85e2008-05-21 19:16:45 +00002316 gen_jcc1(s, cc_op, b, l1);
2317
bellard6e256c92005-11-20 10:32:05 +00002318 gen_goto_tb(s, 0, next_eip);
bellard14ce26e2005-01-03 23:50:08 +00002319
2320 gen_set_label(l1);
bellard6e256c92005-11-20 10:32:05 +00002321 gen_goto_tb(s, 1, val);
Jun Koi57794062010-07-24 00:17:00 +09002322 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00002323 } else {
bellard14ce26e2005-01-03 23:50:08 +00002324
bellard14ce26e2005-01-03 23:50:08 +00002325 l1 = gen_new_label();
2326 l2 = gen_new_label();
bellard8e1c85e2008-05-21 19:16:45 +00002327 gen_jcc1(s, cc_op, b, l1);
2328
bellard14ce26e2005-01-03 23:50:08 +00002329 gen_jmp_im(next_eip);
bellard8e1c85e2008-05-21 19:16:45 +00002330 tcg_gen_br(l2);
2331
bellard14ce26e2005-01-03 23:50:08 +00002332 gen_set_label(l1);
2333 gen_jmp_im(val);
2334 gen_set_label(l2);
bellard2c0262a2003-09-30 20:34:21 +00002335 gen_eob(s);
2336 }
2337}
2338
2339static void gen_setcc(DisasContext *s, int b)
2340{
bellard8e1c85e2008-05-21 19:16:45 +00002341 int inv, jcc_op, l1;
bellard1e4840b2008-05-25 17:26:41 +00002342 TCGv t0;
bellard2c0262a2003-09-30 20:34:21 +00002343
bellard8e1c85e2008-05-21 19:16:45 +00002344 if (is_fast_jcc_case(s, b)) {
2345 /* nominal case: we use a jump */
bellard1e4840b2008-05-25 17:26:41 +00002346 /* XXX: make it faster by adding new instructions in TCG */
pbrooka7812ae2008-11-17 14:43:54 +00002347 t0 = tcg_temp_local_new();
bellard1e4840b2008-05-25 17:26:41 +00002348 tcg_gen_movi_tl(t0, 0);
bellard8e1c85e2008-05-21 19:16:45 +00002349 l1 = gen_new_label();
2350 gen_jcc1(s, s->cc_op, b ^ 1, l1);
bellard1e4840b2008-05-25 17:26:41 +00002351 tcg_gen_movi_tl(t0, 1);
bellard8e1c85e2008-05-21 19:16:45 +00002352 gen_set_label(l1);
bellard1e4840b2008-05-25 17:26:41 +00002353 tcg_gen_mov_tl(cpu_T[0], t0);
2354 tcg_temp_free(t0);
bellard8e1c85e2008-05-21 19:16:45 +00002355 } else {
2356 /* slow case: it is more efficient not to generate a jump,
2357 although it is questionnable whether this optimization is
2358 worth to */
2359 inv = b & 1;
2360 jcc_op = (b >> 1) & 7;
bellard1e4840b2008-05-25 17:26:41 +00002361 gen_setcc_slow_T0(s, jcc_op);
bellard8e1c85e2008-05-21 19:16:45 +00002362 if (inv) {
2363 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2364 }
bellard2c0262a2003-09-30 20:34:21 +00002365 }
2366}
2367
bellard3bd7da92008-05-21 16:34:06 +00002368static inline void gen_op_movl_T0_seg(int seg_reg)
2369{
2370 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2371 offsetof(CPUX86State,segs[seg_reg].selector));
2372}
2373
2374static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2375{
2376 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2377 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2378 offsetof(CPUX86State,segs[seg_reg].selector));
2379 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2380 tcg_gen_st_tl(cpu_T[0], cpu_env,
2381 offsetof(CPUX86State,segs[seg_reg].base));
2382}
2383
bellard2c0262a2003-09-30 20:34:21 +00002384/* move T0 to seg_reg and compute if the CPU state may change. Never
2385 call this function with seg_reg == R_CS */
bellard14ce26e2005-01-03 23:50:08 +00002386static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
bellard2c0262a2003-09-30 20:34:21 +00002387{
bellard3415a4d2004-01-04 15:21:33 +00002388 if (s->pe && !s->vm86) {
2389 /* XXX: optimize by finding processor state dynamically */
2390 if (s->cc_op != CC_OP_DYNAMIC)
2391 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00002392 gen_jmp_im(cur_eip);
bellardb6abf972008-05-17 12:44:31 +00002393 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00002394 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
bellarddc196a52004-06-13 13:26:14 +00002395 /* abort translation because the addseg value may change or
2396 because ss32 may change. For R_SS, translation must always
2397 stop as a special handling must be done to disable hardware
2398 interrupts for the next instruction */
2399 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
Jun Koi57794062010-07-24 00:17:00 +09002400 s->is_jmp = DISAS_TB_JUMP;
bellard3415a4d2004-01-04 15:21:33 +00002401 } else {
bellard3bd7da92008-05-21 16:34:06 +00002402 gen_op_movl_seg_T0_vm(seg_reg);
bellarddc196a52004-06-13 13:26:14 +00002403 if (seg_reg == R_SS)
Jun Koi57794062010-07-24 00:17:00 +09002404 s->is_jmp = DISAS_TB_JUMP;
bellard3415a4d2004-01-04 15:21:33 +00002405 }
bellard2c0262a2003-09-30 20:34:21 +00002406}
2407
ths0573fbf2007-09-23 15:28:04 +00002408static inline int svm_is_rep(int prefixes)
2409{
2410 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2411}
2412
bellard872929a2008-05-28 16:16:54 +00002413static inline void
ths0573fbf2007-09-23 15:28:04 +00002414gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
bellardb8b6a502008-05-15 16:46:30 +00002415 uint32_t type, uint64_t param)
ths0573fbf2007-09-23 15:28:04 +00002416{
bellard872929a2008-05-28 16:16:54 +00002417 /* no SVM activated; fast case */
2418 if (likely(!(s->flags & HF_SVMI_MASK)))
2419 return;
2420 if (s->cc_op != CC_OP_DYNAMIC)
2421 gen_op_set_cc_op(s->cc_op);
2422 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00002423 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2424 tcg_const_i64(param));
ths0573fbf2007-09-23 15:28:04 +00002425}
2426
bellard872929a2008-05-28 16:16:54 +00002427static inline void
ths0573fbf2007-09-23 15:28:04 +00002428gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2429{
bellard872929a2008-05-28 16:16:54 +00002430 gen_svm_check_intercept_param(s, pc_start, type, 0);
ths0573fbf2007-09-23 15:28:04 +00002431}
2432
bellard2c0262a2003-09-30 20:34:21 +00002433static inline void gen_stack_update(DisasContext *s, int addend)
2434{
bellard14ce26e2005-01-03 23:50:08 +00002435#ifdef TARGET_X86_64
2436 if (CODE64(s)) {
bellard6e0d8672008-05-18 19:28:26 +00002437 gen_op_add_reg_im(2, R_ESP, addend);
bellard14ce26e2005-01-03 23:50:08 +00002438 } else
2439#endif
bellard2c0262a2003-09-30 20:34:21 +00002440 if (s->ss32) {
bellard6e0d8672008-05-18 19:28:26 +00002441 gen_op_add_reg_im(1, R_ESP, addend);
bellard2c0262a2003-09-30 20:34:21 +00002442 } else {
bellard6e0d8672008-05-18 19:28:26 +00002443 gen_op_add_reg_im(0, R_ESP, addend);
bellard2c0262a2003-09-30 20:34:21 +00002444 }
2445}
2446
bellard4f319162004-01-04 17:35:00 +00002447/* generate a push. It depends on ss32, addseg and dflag */
2448static void gen_push_T0(DisasContext *s)
2449{
bellard14ce26e2005-01-03 23:50:08 +00002450#ifdef TARGET_X86_64
2451 if (CODE64(s)) {
bellard57fec1f2008-02-01 10:50:11 +00002452 gen_op_movq_A0_reg(R_ESP);
bellard8f091a52005-07-23 17:41:26 +00002453 if (s->dflag) {
bellard57fec1f2008-02-01 10:50:11 +00002454 gen_op_addq_A0_im(-8);
2455 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
bellard8f091a52005-07-23 17:41:26 +00002456 } else {
bellard57fec1f2008-02-01 10:50:11 +00002457 gen_op_addq_A0_im(-2);
2458 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard8f091a52005-07-23 17:41:26 +00002459 }
bellard57fec1f2008-02-01 10:50:11 +00002460 gen_op_mov_reg_A0(2, R_ESP);
ths5fafdf22007-09-16 21:08:06 +00002461 } else
bellard14ce26e2005-01-03 23:50:08 +00002462#endif
2463 {
bellard57fec1f2008-02-01 10:50:11 +00002464 gen_op_movl_A0_reg(R_ESP);
bellard14ce26e2005-01-03 23:50:08 +00002465 if (!s->dflag)
bellard57fec1f2008-02-01 10:50:11 +00002466 gen_op_addl_A0_im(-2);
bellard14ce26e2005-01-03 23:50:08 +00002467 else
bellard57fec1f2008-02-01 10:50:11 +00002468 gen_op_addl_A0_im(-4);
bellard14ce26e2005-01-03 23:50:08 +00002469 if (s->ss32) {
2470 if (s->addseg) {
bellardbbf662e2008-05-17 19:05:28 +00002471 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +00002472 gen_op_addl_A0_seg(R_SS);
bellard14ce26e2005-01-03 23:50:08 +00002473 }
2474 } else {
2475 gen_op_andl_A0_ffff();
bellardbbf662e2008-05-17 19:05:28 +00002476 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
bellard57fec1f2008-02-01 10:50:11 +00002477 gen_op_addl_A0_seg(R_SS);
bellard4f319162004-01-04 17:35:00 +00002478 }
bellard57fec1f2008-02-01 10:50:11 +00002479 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
bellard14ce26e2005-01-03 23:50:08 +00002480 if (s->ss32 && !s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002481 gen_op_mov_reg_A0(1, R_ESP);
bellard14ce26e2005-01-03 23:50:08 +00002482 else
bellard57fec1f2008-02-01 10:50:11 +00002483 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
bellard4f319162004-01-04 17:35:00 +00002484 }
bellard4f319162004-01-04 17:35:00 +00002485}
2486
2487/* generate a push. It depends on ss32, addseg and dflag */
2488/* slower version for T1, only used for call Ev */
2489static void gen_push_T1(DisasContext *s)
2490{
bellard14ce26e2005-01-03 23:50:08 +00002491#ifdef TARGET_X86_64
2492 if (CODE64(s)) {
bellard57fec1f2008-02-01 10:50:11 +00002493 gen_op_movq_A0_reg(R_ESP);
bellard8f091a52005-07-23 17:41:26 +00002494 if (s->dflag) {
bellard57fec1f2008-02-01 10:50:11 +00002495 gen_op_addq_A0_im(-8);
2496 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
bellard8f091a52005-07-23 17:41:26 +00002497 } else {
bellard57fec1f2008-02-01 10:50:11 +00002498 gen_op_addq_A0_im(-2);
2499 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard8f091a52005-07-23 17:41:26 +00002500 }
bellard57fec1f2008-02-01 10:50:11 +00002501 gen_op_mov_reg_A0(2, R_ESP);
ths5fafdf22007-09-16 21:08:06 +00002502 } else
bellard14ce26e2005-01-03 23:50:08 +00002503#endif
2504 {
bellard57fec1f2008-02-01 10:50:11 +00002505 gen_op_movl_A0_reg(R_ESP);
bellard14ce26e2005-01-03 23:50:08 +00002506 if (!s->dflag)
bellard57fec1f2008-02-01 10:50:11 +00002507 gen_op_addl_A0_im(-2);
bellard14ce26e2005-01-03 23:50:08 +00002508 else
bellard57fec1f2008-02-01 10:50:11 +00002509 gen_op_addl_A0_im(-4);
bellard14ce26e2005-01-03 23:50:08 +00002510 if (s->ss32) {
2511 if (s->addseg) {
bellard57fec1f2008-02-01 10:50:11 +00002512 gen_op_addl_A0_seg(R_SS);
bellard14ce26e2005-01-03 23:50:08 +00002513 }
2514 } else {
2515 gen_op_andl_A0_ffff();
bellard57fec1f2008-02-01 10:50:11 +00002516 gen_op_addl_A0_seg(R_SS);
bellard4f319162004-01-04 17:35:00 +00002517 }
bellard57fec1f2008-02-01 10:50:11 +00002518 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
ths3b46e622007-09-17 08:09:54 +00002519
bellard14ce26e2005-01-03 23:50:08 +00002520 if (s->ss32 && !s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002521 gen_op_mov_reg_A0(1, R_ESP);
bellard14ce26e2005-01-03 23:50:08 +00002522 else
2523 gen_stack_update(s, (-2) << s->dflag);
bellard4f319162004-01-04 17:35:00 +00002524 }
bellard4f319162004-01-04 17:35:00 +00002525}
2526
2527/* two step pop is necessary for precise exceptions */
2528static void gen_pop_T0(DisasContext *s)
2529{
bellard14ce26e2005-01-03 23:50:08 +00002530#ifdef TARGET_X86_64
2531 if (CODE64(s)) {
bellard57fec1f2008-02-01 10:50:11 +00002532 gen_op_movq_A0_reg(R_ESP);
2533 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
ths5fafdf22007-09-16 21:08:06 +00002534 } else
bellard14ce26e2005-01-03 23:50:08 +00002535#endif
2536 {
bellard57fec1f2008-02-01 10:50:11 +00002537 gen_op_movl_A0_reg(R_ESP);
bellard14ce26e2005-01-03 23:50:08 +00002538 if (s->ss32) {
2539 if (s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002540 gen_op_addl_A0_seg(R_SS);
bellard14ce26e2005-01-03 23:50:08 +00002541 } else {
2542 gen_op_andl_A0_ffff();
bellard57fec1f2008-02-01 10:50:11 +00002543 gen_op_addl_A0_seg(R_SS);
bellard14ce26e2005-01-03 23:50:08 +00002544 }
bellard57fec1f2008-02-01 10:50:11 +00002545 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
bellard4f319162004-01-04 17:35:00 +00002546 }
bellard4f319162004-01-04 17:35:00 +00002547}
2548
bellard2c0262a2003-09-30 20:34:21 +00002549static void gen_pop_update(DisasContext *s)
2550{
bellard14ce26e2005-01-03 23:50:08 +00002551#ifdef TARGET_X86_64
bellard8f091a52005-07-23 17:41:26 +00002552 if (CODE64(s) && s->dflag) {
bellard14ce26e2005-01-03 23:50:08 +00002553 gen_stack_update(s, 8);
2554 } else
2555#endif
2556 {
2557 gen_stack_update(s, 2 << s->dflag);
2558 }
bellard2c0262a2003-09-30 20:34:21 +00002559}
2560
2561static void gen_stack_A0(DisasContext *s)
2562{
bellard57fec1f2008-02-01 10:50:11 +00002563 gen_op_movl_A0_reg(R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00002564 if (!s->ss32)
2565 gen_op_andl_A0_ffff();
bellardbbf662e2008-05-17 19:05:28 +00002566 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
bellard2c0262a2003-09-30 20:34:21 +00002567 if (s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002568 gen_op_addl_A0_seg(R_SS);
bellard2c0262a2003-09-30 20:34:21 +00002569}
2570
2571/* NOTE: wrap around in 16 bit not fully handled */
2572static void gen_pusha(DisasContext *s)
2573{
2574 int i;
bellard57fec1f2008-02-01 10:50:11 +00002575 gen_op_movl_A0_reg(R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00002576 gen_op_addl_A0_im(-16 << s->dflag);
2577 if (!s->ss32)
2578 gen_op_andl_A0_ffff();
bellardbbf662e2008-05-17 19:05:28 +00002579 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
bellard2c0262a2003-09-30 20:34:21 +00002580 if (s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002581 gen_op_addl_A0_seg(R_SS);
bellard2c0262a2003-09-30 20:34:21 +00002582 for(i = 0;i < 8; i++) {
bellard57fec1f2008-02-01 10:50:11 +00002583 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2584 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00002585 gen_op_addl_A0_im(2 << s->dflag);
2586 }
bellard57fec1f2008-02-01 10:50:11 +00002587 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00002588}
2589
2590/* NOTE: wrap around in 16 bit not fully handled */
2591static void gen_popa(DisasContext *s)
2592{
2593 int i;
bellard57fec1f2008-02-01 10:50:11 +00002594 gen_op_movl_A0_reg(R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00002595 if (!s->ss32)
2596 gen_op_andl_A0_ffff();
bellardbbf662e2008-05-17 19:05:28 +00002597 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2598 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
bellard2c0262a2003-09-30 20:34:21 +00002599 if (s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002600 gen_op_addl_A0_seg(R_SS);
bellard2c0262a2003-09-30 20:34:21 +00002601 for(i = 0;i < 8; i++) {
2602 /* ESP is not reloaded */
2603 if (i != 3) {
bellard57fec1f2008-02-01 10:50:11 +00002604 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2605 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
bellard2c0262a2003-09-30 20:34:21 +00002606 }
2607 gen_op_addl_A0_im(2 << s->dflag);
2608 }
bellard57fec1f2008-02-01 10:50:11 +00002609 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00002610}
2611
bellard2c0262a2003-09-30 20:34:21 +00002612static void gen_enter(DisasContext *s, int esp_addend, int level)
2613{
bellard61a8c4e2004-11-14 15:39:16 +00002614 int ot, opsize;
bellard2c0262a2003-09-30 20:34:21 +00002615
bellard2c0262a2003-09-30 20:34:21 +00002616 level &= 0x1f;
bellard8f091a52005-07-23 17:41:26 +00002617#ifdef TARGET_X86_64
2618 if (CODE64(s)) {
2619 ot = s->dflag ? OT_QUAD : OT_WORD;
2620 opsize = 1 << ot;
ths3b46e622007-09-17 08:09:54 +00002621
bellard57fec1f2008-02-01 10:50:11 +00002622 gen_op_movl_A0_reg(R_ESP);
bellard8f091a52005-07-23 17:41:26 +00002623 gen_op_addq_A0_im(-opsize);
bellardbbf662e2008-05-17 19:05:28 +00002624 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
bellard2c0262a2003-09-30 20:34:21 +00002625
bellard8f091a52005-07-23 17:41:26 +00002626 /* push bp */
bellard57fec1f2008-02-01 10:50:11 +00002627 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2628 gen_op_st_T0_A0(ot + s->mem_index);
bellard8f091a52005-07-23 17:41:26 +00002629 if (level) {
bellardb5b38f62008-05-12 22:05:13 +00002630 /* XXX: must save state */
pbrooka7812ae2008-11-17 14:43:54 +00002631 gen_helper_enter64_level(tcg_const_i32(level),
2632 tcg_const_i32((ot == OT_QUAD)),
2633 cpu_T[1]);
bellard8f091a52005-07-23 17:41:26 +00002634 }
bellard57fec1f2008-02-01 10:50:11 +00002635 gen_op_mov_reg_T1(ot, R_EBP);
bellardbbf662e2008-05-17 19:05:28 +00002636 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
bellard57fec1f2008-02-01 10:50:11 +00002637 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
ths5fafdf22007-09-16 21:08:06 +00002638 } else
bellard8f091a52005-07-23 17:41:26 +00002639#endif
2640 {
2641 ot = s->dflag + OT_WORD;
2642 opsize = 2 << s->dflag;
ths3b46e622007-09-17 08:09:54 +00002643
bellard57fec1f2008-02-01 10:50:11 +00002644 gen_op_movl_A0_reg(R_ESP);
bellard8f091a52005-07-23 17:41:26 +00002645 gen_op_addl_A0_im(-opsize);
2646 if (!s->ss32)
2647 gen_op_andl_A0_ffff();
bellardbbf662e2008-05-17 19:05:28 +00002648 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
bellard8f091a52005-07-23 17:41:26 +00002649 if (s->addseg)
bellard57fec1f2008-02-01 10:50:11 +00002650 gen_op_addl_A0_seg(R_SS);
bellard8f091a52005-07-23 17:41:26 +00002651 /* push bp */
bellard57fec1f2008-02-01 10:50:11 +00002652 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2653 gen_op_st_T0_A0(ot + s->mem_index);
bellard8f091a52005-07-23 17:41:26 +00002654 if (level) {
bellardb5b38f62008-05-12 22:05:13 +00002655 /* XXX: must save state */
pbrooka7812ae2008-11-17 14:43:54 +00002656 gen_helper_enter_level(tcg_const_i32(level),
2657 tcg_const_i32(s->dflag),
2658 cpu_T[1]);
bellard8f091a52005-07-23 17:41:26 +00002659 }
bellard57fec1f2008-02-01 10:50:11 +00002660 gen_op_mov_reg_T1(ot, R_EBP);
bellardbbf662e2008-05-17 19:05:28 +00002661 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
bellard57fec1f2008-02-01 10:50:11 +00002662 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00002663 }
bellard2c0262a2003-09-30 20:34:21 +00002664}
2665
bellard14ce26e2005-01-03 23:50:08 +00002666static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
bellard2c0262a2003-09-30 20:34:21 +00002667{
2668 if (s->cc_op != CC_OP_DYNAMIC)
2669 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00002670 gen_jmp_im(cur_eip);
pbrooka7812ae2008-11-17 14:43:54 +00002671 gen_helper_raise_exception(tcg_const_i32(trapno));
Jun Koi57794062010-07-24 00:17:00 +09002672 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00002673}
2674
2675/* an interrupt is different from an exception because of the
blueswir17f75ffd2007-05-27 19:39:27 +00002676 privilege checks */
ths5fafdf22007-09-16 21:08:06 +00002677static void gen_interrupt(DisasContext *s, int intno,
bellard14ce26e2005-01-03 23:50:08 +00002678 target_ulong cur_eip, target_ulong next_eip)
bellard2c0262a2003-09-30 20:34:21 +00002679{
2680 if (s->cc_op != CC_OP_DYNAMIC)
2681 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00002682 gen_jmp_im(cur_eip);
pbrooka7812ae2008-11-17 14:43:54 +00002683 gen_helper_raise_interrupt(tcg_const_i32(intno),
2684 tcg_const_i32(next_eip - cur_eip));
Jun Koi57794062010-07-24 00:17:00 +09002685 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00002686}
2687
bellard14ce26e2005-01-03 23:50:08 +00002688static void gen_debug(DisasContext *s, target_ulong cur_eip)
bellard2c0262a2003-09-30 20:34:21 +00002689{
2690 if (s->cc_op != CC_OP_DYNAMIC)
2691 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00002692 gen_jmp_im(cur_eip);
pbrooka7812ae2008-11-17 14:43:54 +00002693 gen_helper_debug();
Jun Koi57794062010-07-24 00:17:00 +09002694 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00002695}
2696
2697/* generate a generic end of block. Trace exception is also generated
2698 if needed */
2699static void gen_eob(DisasContext *s)
2700{
2701 if (s->cc_op != CC_OP_DYNAMIC)
2702 gen_op_set_cc_op(s->cc_op);
bellarda2cc3b22003-11-19 22:08:13 +00002703 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
pbrooka7812ae2008-11-17 14:43:54 +00002704 gen_helper_reset_inhibit_irq();
bellarda2cc3b22003-11-19 22:08:13 +00002705 }
Jan Kiszkaa2397802009-05-10 22:30:53 +02002706 if (s->tb->flags & HF_RF_MASK) {
2707 gen_helper_reset_rf();
2708 }
bellard34865132003-10-05 14:28:56 +00002709 if (s->singlestep_enabled) {
pbrooka7812ae2008-11-17 14:43:54 +00002710 gen_helper_debug();
bellard34865132003-10-05 14:28:56 +00002711 } else if (s->tf) {
pbrooka7812ae2008-11-17 14:43:54 +00002712 gen_helper_single_step();
bellard2c0262a2003-09-30 20:34:21 +00002713 } else {
bellard57fec1f2008-02-01 10:50:11 +00002714 tcg_gen_exit_tb(0);
bellard2c0262a2003-09-30 20:34:21 +00002715 }
Jun Koi57794062010-07-24 00:17:00 +09002716 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00002717}
2718
2719/* generate a jump to eip. No segment change must happen before as a
2720 direct call to the next block may occur */
bellard14ce26e2005-01-03 23:50:08 +00002721static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
bellard2c0262a2003-09-30 20:34:21 +00002722{
bellard2c0262a2003-09-30 20:34:21 +00002723 if (s->jmp_opt) {
Jun Koi728d8032010-07-25 12:30:03 +09002724 gen_update_cc_op(s);
bellard6e256c92005-11-20 10:32:05 +00002725 gen_goto_tb(s, tb_num, eip);
Jun Koi57794062010-07-24 00:17:00 +09002726 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00002727 } else {
bellard14ce26e2005-01-03 23:50:08 +00002728 gen_jmp_im(eip);
bellard2c0262a2003-09-30 20:34:21 +00002729 gen_eob(s);
2730 }
2731}
2732
bellard14ce26e2005-01-03 23:50:08 +00002733static void gen_jmp(DisasContext *s, target_ulong eip)
2734{
2735 gen_jmp_tb(s, eip, 0);
2736}
2737
bellard8686c492008-05-12 13:55:27 +00002738static inline void gen_ldq_env_A0(int idx, int offset)
2739{
2740 int mem_index = (idx >> 2) - 1;
bellardb6abf972008-05-17 12:44:31 +00002741 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2742 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
bellard8686c492008-05-12 13:55:27 +00002743}
bellard664e0f12005-01-08 18:58:29 +00002744
bellard8686c492008-05-12 13:55:27 +00002745static inline void gen_stq_env_A0(int idx, int offset)
2746{
2747 int mem_index = (idx >> 2) - 1;
bellardb6abf972008-05-17 12:44:31 +00002748 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2749 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
bellard8686c492008-05-12 13:55:27 +00002750}
bellard664e0f12005-01-08 18:58:29 +00002751
bellard8686c492008-05-12 13:55:27 +00002752static inline void gen_ldo_env_A0(int idx, int offset)
2753{
2754 int mem_index = (idx >> 2) - 1;
bellardb6abf972008-05-17 12:44:31 +00002755 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2756 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
bellard8686c492008-05-12 13:55:27 +00002757 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
bellardb6abf972008-05-17 12:44:31 +00002758 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2759 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
bellard8686c492008-05-12 13:55:27 +00002760}
bellard14ce26e2005-01-03 23:50:08 +00002761
bellard8686c492008-05-12 13:55:27 +00002762static inline void gen_sto_env_A0(int idx, int offset)
2763{
2764 int mem_index = (idx >> 2) - 1;
bellardb6abf972008-05-17 12:44:31 +00002765 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2766 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
bellard8686c492008-05-12 13:55:27 +00002767 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
bellardb6abf972008-05-17 12:44:31 +00002768 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2769 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
bellard8686c492008-05-12 13:55:27 +00002770}
bellard14ce26e2005-01-03 23:50:08 +00002771
bellard5af45182008-05-12 16:47:36 +00002772static inline void gen_op_movo(int d_offset, int s_offset)
2773{
bellardb6abf972008-05-17 12:44:31 +00002774 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2775 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2776 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2777 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
bellard5af45182008-05-12 16:47:36 +00002778}
bellard664e0f12005-01-08 18:58:29 +00002779
bellard5af45182008-05-12 16:47:36 +00002780static inline void gen_op_movq(int d_offset, int s_offset)
2781{
bellardb6abf972008-05-17 12:44:31 +00002782 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2783 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
bellard5af45182008-05-12 16:47:36 +00002784}
bellard664e0f12005-01-08 18:58:29 +00002785
bellard5af45182008-05-12 16:47:36 +00002786static inline void gen_op_movl(int d_offset, int s_offset)
2787{
bellardb6abf972008-05-17 12:44:31 +00002788 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2789 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
bellard5af45182008-05-12 16:47:36 +00002790}
2791
2792static inline void gen_op_movq_env_0(int d_offset)
2793{
bellardb6abf972008-05-17 12:44:31 +00002794 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2795 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
bellard5af45182008-05-12 16:47:36 +00002796}
2797
2798#define SSE_SPECIAL ((void *)1)
2799#define SSE_DUMMY ((void *)2)
2800
pbrooka7812ae2008-11-17 14:43:54 +00002801#define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2802#define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2803 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
bellard5af45182008-05-12 16:47:36 +00002804
2805static void *sse_op_table1[256][4] = {
aurel32a35f3ec2008-04-08 19:51:29 +00002806 /* 3DNow! extensions */
2807 [0x0e] = { SSE_DUMMY }, /* femms */
2808 [0x0f] = { SSE_DUMMY }, /* pf... */
bellard664e0f12005-01-08 18:58:29 +00002809 /* pure SSE operations */
2810 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2811 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
bellard465e9832006-04-23 21:54:01 +00002812 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
bellard664e0f12005-01-08 18:58:29 +00002813 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
pbrooka7812ae2008-11-17 14:43:54 +00002814 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2815 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
bellard664e0f12005-01-08 18:58:29 +00002816 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2817 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2818
2819 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2820 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2821 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
Andre Przywarad9f4bb22009-09-19 00:30:48 +02002822 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
bellard664e0f12005-01-08 18:58:29 +00002823 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2824 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
pbrooka7812ae2008-11-17 14:43:54 +00002825 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2826 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
bellard664e0f12005-01-08 18:58:29 +00002827 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2828 [0x51] = SSE_FOP(sqrt),
pbrooka7812ae2008-11-17 14:43:54 +00002829 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2830 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2831 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2832 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2833 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2834 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
bellard664e0f12005-01-08 18:58:29 +00002835 [0x58] = SSE_FOP(add),
2836 [0x59] = SSE_FOP(mul),
pbrooka7812ae2008-11-17 14:43:54 +00002837 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2838 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2839 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
bellard664e0f12005-01-08 18:58:29 +00002840 [0x5c] = SSE_FOP(sub),
2841 [0x5d] = SSE_FOP(min),
2842 [0x5e] = SSE_FOP(div),
2843 [0x5f] = SSE_FOP(max),
2844
2845 [0xc2] = SSE_FOP(cmpeq),
pbrooka7812ae2008-11-17 14:43:54 +00002846 [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
bellard664e0f12005-01-08 18:58:29 +00002847
balrog222a3332008-10-04 03:27:44 +00002848 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2849 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
balrog4242b1b2008-09-25 18:01:46 +00002850
bellard664e0f12005-01-08 18:58:29 +00002851 /* MMX ops and their SSE extensions */
2852 [0x60] = MMX_OP2(punpcklbw),
2853 [0x61] = MMX_OP2(punpcklwd),
2854 [0x62] = MMX_OP2(punpckldq),
2855 [0x63] = MMX_OP2(packsswb),
2856 [0x64] = MMX_OP2(pcmpgtb),
2857 [0x65] = MMX_OP2(pcmpgtw),
2858 [0x66] = MMX_OP2(pcmpgtl),
2859 [0x67] = MMX_OP2(packuswb),
2860 [0x68] = MMX_OP2(punpckhbw),
2861 [0x69] = MMX_OP2(punpckhwd),
2862 [0x6a] = MMX_OP2(punpckhdq),
2863 [0x6b] = MMX_OP2(packssdw),
pbrooka7812ae2008-11-17 14:43:54 +00002864 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2865 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
bellard664e0f12005-01-08 18:58:29 +00002866 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2867 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
pbrooka7812ae2008-11-17 14:43:54 +00002868 [0x70] = { gen_helper_pshufw_mmx,
2869 gen_helper_pshufd_xmm,
2870 gen_helper_pshufhw_xmm,
2871 gen_helper_pshuflw_xmm },
bellard664e0f12005-01-08 18:58:29 +00002872 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2873 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2874 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2875 [0x74] = MMX_OP2(pcmpeqb),
2876 [0x75] = MMX_OP2(pcmpeqw),
2877 [0x76] = MMX_OP2(pcmpeql),
aurel32a35f3ec2008-04-08 19:51:29 +00002878 [0x77] = { SSE_DUMMY }, /* emms */
Andre Przywarad9f4bb22009-09-19 00:30:48 +02002879 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2880 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
pbrooka7812ae2008-11-17 14:43:54 +00002881 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2882 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
bellard664e0f12005-01-08 18:58:29 +00002883 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2884 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2885 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2886 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
pbrooka7812ae2008-11-17 14:43:54 +00002887 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
bellard664e0f12005-01-08 18:58:29 +00002888 [0xd1] = MMX_OP2(psrlw),
2889 [0xd2] = MMX_OP2(psrld),
2890 [0xd3] = MMX_OP2(psrlq),
2891 [0xd4] = MMX_OP2(paddq),
2892 [0xd5] = MMX_OP2(pmullw),
2893 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2894 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2895 [0xd8] = MMX_OP2(psubusb),
2896 [0xd9] = MMX_OP2(psubusw),
2897 [0xda] = MMX_OP2(pminub),
2898 [0xdb] = MMX_OP2(pand),
2899 [0xdc] = MMX_OP2(paddusb),
2900 [0xdd] = MMX_OP2(paddusw),
2901 [0xde] = MMX_OP2(pmaxub),
2902 [0xdf] = MMX_OP2(pandn),
2903 [0xe0] = MMX_OP2(pavgb),
2904 [0xe1] = MMX_OP2(psraw),
2905 [0xe2] = MMX_OP2(psrad),
2906 [0xe3] = MMX_OP2(pavgw),
2907 [0xe4] = MMX_OP2(pmulhuw),
2908 [0xe5] = MMX_OP2(pmulhw),
pbrooka7812ae2008-11-17 14:43:54 +00002909 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
bellard664e0f12005-01-08 18:58:29 +00002910 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2911 [0xe8] = MMX_OP2(psubsb),
2912 [0xe9] = MMX_OP2(psubsw),
2913 [0xea] = MMX_OP2(pminsw),
2914 [0xeb] = MMX_OP2(por),
2915 [0xec] = MMX_OP2(paddsb),
2916 [0xed] = MMX_OP2(paddsw),
2917 [0xee] = MMX_OP2(pmaxsw),
2918 [0xef] = MMX_OP2(pxor),
bellard465e9832006-04-23 21:54:01 +00002919 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
bellard664e0f12005-01-08 18:58:29 +00002920 [0xf1] = MMX_OP2(psllw),
2921 [0xf2] = MMX_OP2(pslld),
2922 [0xf3] = MMX_OP2(psllq),
2923 [0xf4] = MMX_OP2(pmuludq),
2924 [0xf5] = MMX_OP2(pmaddwd),
2925 [0xf6] = MMX_OP2(psadbw),
2926 [0xf7] = MMX_OP2(maskmov),
2927 [0xf8] = MMX_OP2(psubb),
2928 [0xf9] = MMX_OP2(psubw),
2929 [0xfa] = MMX_OP2(psubl),
2930 [0xfb] = MMX_OP2(psubq),
2931 [0xfc] = MMX_OP2(paddb),
2932 [0xfd] = MMX_OP2(paddw),
2933 [0xfe] = MMX_OP2(paddl),
2934};
2935
bellard5af45182008-05-12 16:47:36 +00002936static void *sse_op_table2[3 * 8][2] = {
bellard664e0f12005-01-08 18:58:29 +00002937 [0 + 2] = MMX_OP2(psrlw),
2938 [0 + 4] = MMX_OP2(psraw),
2939 [0 + 6] = MMX_OP2(psllw),
2940 [8 + 2] = MMX_OP2(psrld),
2941 [8 + 4] = MMX_OP2(psrad),
2942 [8 + 6] = MMX_OP2(pslld),
2943 [16 + 2] = MMX_OP2(psrlq),
pbrooka7812ae2008-11-17 14:43:54 +00002944 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
bellard664e0f12005-01-08 18:58:29 +00002945 [16 + 6] = MMX_OP2(psllq),
pbrooka7812ae2008-11-17 14:43:54 +00002946 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
bellard664e0f12005-01-08 18:58:29 +00002947};
2948
bellard5af45182008-05-12 16:47:36 +00002949static void *sse_op_table3[4 * 3] = {
pbrooka7812ae2008-11-17 14:43:54 +00002950 gen_helper_cvtsi2ss,
2951 gen_helper_cvtsi2sd,
2952 X86_64_ONLY(gen_helper_cvtsq2ss),
2953 X86_64_ONLY(gen_helper_cvtsq2sd),
ths3b46e622007-09-17 08:09:54 +00002954
pbrooka7812ae2008-11-17 14:43:54 +00002955 gen_helper_cvttss2si,
2956 gen_helper_cvttsd2si,
2957 X86_64_ONLY(gen_helper_cvttss2sq),
2958 X86_64_ONLY(gen_helper_cvttsd2sq),
bellard664e0f12005-01-08 18:58:29 +00002959
pbrooka7812ae2008-11-17 14:43:54 +00002960 gen_helper_cvtss2si,
2961 gen_helper_cvtsd2si,
2962 X86_64_ONLY(gen_helper_cvtss2sq),
2963 X86_64_ONLY(gen_helper_cvtsd2sq),
bellard664e0f12005-01-08 18:58:29 +00002964};
ths3b46e622007-09-17 08:09:54 +00002965
bellard5af45182008-05-12 16:47:36 +00002966static void *sse_op_table4[8][4] = {
bellard664e0f12005-01-08 18:58:29 +00002967 SSE_FOP(cmpeq),
2968 SSE_FOP(cmplt),
2969 SSE_FOP(cmple),
2970 SSE_FOP(cmpunord),
2971 SSE_FOP(cmpneq),
2972 SSE_FOP(cmpnlt),
2973 SSE_FOP(cmpnle),
2974 SSE_FOP(cmpord),
2975};
ths3b46e622007-09-17 08:09:54 +00002976
bellard5af45182008-05-12 16:47:36 +00002977static void *sse_op_table5[256] = {
pbrooka7812ae2008-11-17 14:43:54 +00002978 [0x0c] = gen_helper_pi2fw,
2979 [0x0d] = gen_helper_pi2fd,
2980 [0x1c] = gen_helper_pf2iw,
2981 [0x1d] = gen_helper_pf2id,
2982 [0x8a] = gen_helper_pfnacc,
2983 [0x8e] = gen_helper_pfpnacc,
2984 [0x90] = gen_helper_pfcmpge,
2985 [0x94] = gen_helper_pfmin,
2986 [0x96] = gen_helper_pfrcp,
2987 [0x97] = gen_helper_pfrsqrt,
2988 [0x9a] = gen_helper_pfsub,
2989 [0x9e] = gen_helper_pfadd,
2990 [0xa0] = gen_helper_pfcmpgt,
2991 [0xa4] = gen_helper_pfmax,
2992 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2993 [0xa7] = gen_helper_movq, /* pfrsqit1 */
2994 [0xaa] = gen_helper_pfsubr,
2995 [0xae] = gen_helper_pfacc,
2996 [0xb0] = gen_helper_pfcmpeq,
2997 [0xb4] = gen_helper_pfmul,
2998 [0xb6] = gen_helper_movq, /* pfrcpit2 */
2999 [0xb7] = gen_helper_pmulhrw_mmx,
3000 [0xbb] = gen_helper_pswapd,
3001 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
aurel32a35f3ec2008-04-08 19:51:29 +00003002};
3003
balrog222a3332008-10-04 03:27:44 +00003004struct sse_op_helper_s {
3005 void *op[2]; uint32_t ext_mask;
3006};
3007#define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
pbrooka7812ae2008-11-17 14:43:54 +00003008#define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3009#define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
balrog222a3332008-10-04 03:27:44 +00003010#define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3011static struct sse_op_helper_s sse_op_table6[256] = {
3012 [0x00] = SSSE3_OP(pshufb),
3013 [0x01] = SSSE3_OP(phaddw),
3014 [0x02] = SSSE3_OP(phaddd),
3015 [0x03] = SSSE3_OP(phaddsw),
3016 [0x04] = SSSE3_OP(pmaddubsw),
3017 [0x05] = SSSE3_OP(phsubw),
3018 [0x06] = SSSE3_OP(phsubd),
3019 [0x07] = SSSE3_OP(phsubsw),
3020 [0x08] = SSSE3_OP(psignb),
3021 [0x09] = SSSE3_OP(psignw),
3022 [0x0a] = SSSE3_OP(psignd),
3023 [0x0b] = SSSE3_OP(pmulhrsw),
3024 [0x10] = SSE41_OP(pblendvb),
3025 [0x14] = SSE41_OP(blendvps),
3026 [0x15] = SSE41_OP(blendvpd),
3027 [0x17] = SSE41_OP(ptest),
3028 [0x1c] = SSSE3_OP(pabsb),
3029 [0x1d] = SSSE3_OP(pabsw),
3030 [0x1e] = SSSE3_OP(pabsd),
3031 [0x20] = SSE41_OP(pmovsxbw),
3032 [0x21] = SSE41_OP(pmovsxbd),
3033 [0x22] = SSE41_OP(pmovsxbq),
3034 [0x23] = SSE41_OP(pmovsxwd),
3035 [0x24] = SSE41_OP(pmovsxwq),
3036 [0x25] = SSE41_OP(pmovsxdq),
3037 [0x28] = SSE41_OP(pmuldq),
3038 [0x29] = SSE41_OP(pcmpeqq),
3039 [0x2a] = SSE41_SPECIAL, /* movntqda */
3040 [0x2b] = SSE41_OP(packusdw),
3041 [0x30] = SSE41_OP(pmovzxbw),
3042 [0x31] = SSE41_OP(pmovzxbd),
3043 [0x32] = SSE41_OP(pmovzxbq),
3044 [0x33] = SSE41_OP(pmovzxwd),
3045 [0x34] = SSE41_OP(pmovzxwq),
3046 [0x35] = SSE41_OP(pmovzxdq),
3047 [0x37] = SSE42_OP(pcmpgtq),
3048 [0x38] = SSE41_OP(pminsb),
3049 [0x39] = SSE41_OP(pminsd),
3050 [0x3a] = SSE41_OP(pminuw),
3051 [0x3b] = SSE41_OP(pminud),
3052 [0x3c] = SSE41_OP(pmaxsb),
3053 [0x3d] = SSE41_OP(pmaxsd),
3054 [0x3e] = SSE41_OP(pmaxuw),
3055 [0x3f] = SSE41_OP(pmaxud),
3056 [0x40] = SSE41_OP(pmulld),
3057 [0x41] = SSE41_OP(phminposuw),
balrog4242b1b2008-09-25 18:01:46 +00003058};
3059
balrog222a3332008-10-04 03:27:44 +00003060static struct sse_op_helper_s sse_op_table7[256] = {
3061 [0x08] = SSE41_OP(roundps),
3062 [0x09] = SSE41_OP(roundpd),
3063 [0x0a] = SSE41_OP(roundss),
3064 [0x0b] = SSE41_OP(roundsd),
3065 [0x0c] = SSE41_OP(blendps),
3066 [0x0d] = SSE41_OP(blendpd),
3067 [0x0e] = SSE41_OP(pblendw),
3068 [0x0f] = SSSE3_OP(palignr),
3069 [0x14] = SSE41_SPECIAL, /* pextrb */
3070 [0x15] = SSE41_SPECIAL, /* pextrw */
3071 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3072 [0x17] = SSE41_SPECIAL, /* extractps */
3073 [0x20] = SSE41_SPECIAL, /* pinsrb */
3074 [0x21] = SSE41_SPECIAL, /* insertps */
3075 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3076 [0x40] = SSE41_OP(dpps),
3077 [0x41] = SSE41_OP(dppd),
3078 [0x42] = SSE41_OP(mpsadbw),
3079 [0x60] = SSE42_OP(pcmpestrm),
3080 [0x61] = SSE42_OP(pcmpestri),
3081 [0x62] = SSE42_OP(pcmpistrm),
3082 [0x63] = SSE42_OP(pcmpistri),
balrog4242b1b2008-09-25 18:01:46 +00003083};
3084
bellard664e0f12005-01-08 18:58:29 +00003085static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3086{
3087 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3088 int modrm, mod, rm, reg, reg_addr, offset_addr;
bellard5af45182008-05-12 16:47:36 +00003089 void *sse_op2;
bellard664e0f12005-01-08 18:58:29 +00003090
3091 b &= 0xff;
ths5fafdf22007-09-16 21:08:06 +00003092 if (s->prefix & PREFIX_DATA)
bellard664e0f12005-01-08 18:58:29 +00003093 b1 = 1;
ths5fafdf22007-09-16 21:08:06 +00003094 else if (s->prefix & PREFIX_REPZ)
bellard664e0f12005-01-08 18:58:29 +00003095 b1 = 2;
ths5fafdf22007-09-16 21:08:06 +00003096 else if (s->prefix & PREFIX_REPNZ)
bellard664e0f12005-01-08 18:58:29 +00003097 b1 = 3;
3098 else
3099 b1 = 0;
3100 sse_op2 = sse_op_table1[b][b1];
ths5fafdf22007-09-16 21:08:06 +00003101 if (!sse_op2)
bellard664e0f12005-01-08 18:58:29 +00003102 goto illegal_op;
aurel32a35f3ec2008-04-08 19:51:29 +00003103 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
bellard664e0f12005-01-08 18:58:29 +00003104 is_xmm = 1;
3105 } else {
3106 if (b1 == 0) {
3107 /* MMX case */
3108 is_xmm = 0;
3109 } else {
3110 is_xmm = 1;
3111 }
3112 }
3113 /* simple MMX/SSE operation */
3114 if (s->flags & HF_TS_MASK) {
3115 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3116 return;
3117 }
3118 if (s->flags & HF_EM_MASK) {
3119 illegal_op:
3120 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3121 return;
3122 }
3123 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
balrog4242b1b2008-09-25 18:01:46 +00003124 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3125 goto illegal_op;
aurel32e771eda2008-04-09 06:41:37 +00003126 if (b == 0x0e) {
3127 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3128 goto illegal_op;
3129 /* femms */
pbrooka7812ae2008-11-17 14:43:54 +00003130 gen_helper_emms();
aurel32e771eda2008-04-09 06:41:37 +00003131 return;
3132 }
3133 if (b == 0x77) {
3134 /* emms */
pbrooka7812ae2008-11-17 14:43:54 +00003135 gen_helper_emms();
bellard664e0f12005-01-08 18:58:29 +00003136 return;
3137 }
3138 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3139 the static cpu state) */
3140 if (!is_xmm) {
pbrooka7812ae2008-11-17 14:43:54 +00003141 gen_helper_enter_mmx();
bellard664e0f12005-01-08 18:58:29 +00003142 }
3143
3144 modrm = ldub_code(s->pc++);
3145 reg = ((modrm >> 3) & 7);
3146 if (is_xmm)
3147 reg |= rex_r;
3148 mod = (modrm >> 6) & 3;
3149 if (sse_op2 == SSE_SPECIAL) {
3150 b |= (b1 << 8);
3151 switch(b) {
3152 case 0x0e7: /* movntq */
ths5fafdf22007-09-16 21:08:06 +00003153 if (mod == 3)
bellard664e0f12005-01-08 18:58:29 +00003154 goto illegal_op;
3155 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003156 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
bellard664e0f12005-01-08 18:58:29 +00003157 break;
3158 case 0x1e7: /* movntdq */
3159 case 0x02b: /* movntps */
3160 case 0x12b: /* movntps */
TeLeMan2e21e742010-03-12 19:38:06 +08003161 if (mod == 3)
3162 goto illegal_op;
3163 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3164 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3165 break;
bellard465e9832006-04-23 21:54:01 +00003166 case 0x3f0: /* lddqu */
3167 if (mod == 3)
bellard664e0f12005-01-08 18:58:29 +00003168 goto illegal_op;
3169 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
Aurelien Jarnoc2254922010-03-06 18:33:53 +01003170 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
bellard664e0f12005-01-08 18:58:29 +00003171 break;
Andre Przywarad9f4bb22009-09-19 00:30:48 +02003172 case 0x22b: /* movntss */
3173 case 0x32b: /* movntsd */
3174 if (mod == 3)
3175 goto illegal_op;
3176 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3177 if (b1 & 1) {
3178 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3179 xmm_regs[reg]));
3180 } else {
3181 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3182 xmm_regs[reg].XMM_L(0)));
3183 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3184 }
3185 break;
bellard664e0f12005-01-08 18:58:29 +00003186 case 0x6e: /* movd mm, ea */
bellarddabd98d2007-01-16 19:28:58 +00003187#ifdef TARGET_X86_64
3188 if (s->dflag == 2) {
3189 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
bellard5af45182008-05-12 16:47:36 +00003190 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
ths5fafdf22007-09-16 21:08:06 +00003191 } else
bellarddabd98d2007-01-16 19:28:58 +00003192#endif
3193 {
3194 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
bellard5af45182008-05-12 16:47:36 +00003195 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3196 offsetof(CPUX86State,fpregs[reg].mmx));
pbrooka7812ae2008-11-17 14:43:54 +00003197 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3198 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
bellarddabd98d2007-01-16 19:28:58 +00003199 }
bellard664e0f12005-01-08 18:58:29 +00003200 break;
3201 case 0x16e: /* movd xmm, ea */
bellarddabd98d2007-01-16 19:28:58 +00003202#ifdef TARGET_X86_64
3203 if (s->dflag == 2) {
3204 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
bellard5af45182008-05-12 16:47:36 +00003205 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3206 offsetof(CPUX86State,xmm_regs[reg]));
pbrooka7812ae2008-11-17 14:43:54 +00003207 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
ths5fafdf22007-09-16 21:08:06 +00003208 } else
bellarddabd98d2007-01-16 19:28:58 +00003209#endif
3210 {
3211 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
bellard5af45182008-05-12 16:47:36 +00003212 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3213 offsetof(CPUX86State,xmm_regs[reg]));
bellardb6abf972008-05-17 12:44:31 +00003214 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00003215 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
bellarddabd98d2007-01-16 19:28:58 +00003216 }
bellard664e0f12005-01-08 18:58:29 +00003217 break;
3218 case 0x6f: /* movq mm, ea */
3219 if (mod != 3) {
3220 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003221 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
bellard664e0f12005-01-08 18:58:29 +00003222 } else {
3223 rm = (modrm & 7);
bellardb6abf972008-05-17 12:44:31 +00003224 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
bellard5af45182008-05-12 16:47:36 +00003225 offsetof(CPUX86State,fpregs[rm].mmx));
bellardb6abf972008-05-17 12:44:31 +00003226 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
bellard5af45182008-05-12 16:47:36 +00003227 offsetof(CPUX86State,fpregs[reg].mmx));
bellard664e0f12005-01-08 18:58:29 +00003228 }
3229 break;
3230 case 0x010: /* movups */
3231 case 0x110: /* movupd */
3232 case 0x028: /* movaps */
3233 case 0x128: /* movapd */
3234 case 0x16f: /* movdqa xmm, ea */
3235 case 0x26f: /* movdqu xmm, ea */
3236 if (mod != 3) {
3237 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003238 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
bellard664e0f12005-01-08 18:58:29 +00003239 } else {
3240 rm = (modrm & 7) | REX_B(s);
3241 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3242 offsetof(CPUX86State,xmm_regs[rm]));
3243 }
3244 break;
3245 case 0x210: /* movss xmm, ea */
3246 if (mod != 3) {
3247 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00003248 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellard651ba602008-05-21 17:16:11 +00003249 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
bellard664e0f12005-01-08 18:58:29 +00003250 gen_op_movl_T0_0();
bellard651ba602008-05-21 17:16:11 +00003251 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3252 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3253 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
bellard664e0f12005-01-08 18:58:29 +00003254 } else {
3255 rm = (modrm & 7) | REX_B(s);
3256 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3257 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3258 }
3259 break;
3260 case 0x310: /* movsd xmm, ea */
3261 if (mod != 3) {
3262 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003263 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003264 gen_op_movl_T0_0();
bellard651ba602008-05-21 17:16:11 +00003265 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3266 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
bellard664e0f12005-01-08 18:58:29 +00003267 } else {
3268 rm = (modrm & 7) | REX_B(s);
3269 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3270 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3271 }
3272 break;
3273 case 0x012: /* movlps */
3274 case 0x112: /* movlpd */
3275 if (mod != 3) {
3276 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003277 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003278 } else {
3279 /* movhlps */
3280 rm = (modrm & 7) | REX_B(s);
3281 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3282 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3283 }
3284 break;
bellard465e9832006-04-23 21:54:01 +00003285 case 0x212: /* movsldup */
3286 if (mod != 3) {
3287 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003288 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
bellard465e9832006-04-23 21:54:01 +00003289 } else {
3290 rm = (modrm & 7) | REX_B(s);
3291 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3292 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3293 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3294 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3295 }
3296 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3297 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3298 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3299 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3300 break;
3301 case 0x312: /* movddup */
3302 if (mod != 3) {
3303 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003304 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard465e9832006-04-23 21:54:01 +00003305 } else {
3306 rm = (modrm & 7) | REX_B(s);
3307 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3308 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3309 }
3310 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
bellardba6526d2006-04-24 20:14:56 +00003311 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard465e9832006-04-23 21:54:01 +00003312 break;
bellard664e0f12005-01-08 18:58:29 +00003313 case 0x016: /* movhps */
3314 case 0x116: /* movhpd */
3315 if (mod != 3) {
3316 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003317 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
bellard664e0f12005-01-08 18:58:29 +00003318 } else {
3319 /* movlhps */
3320 rm = (modrm & 7) | REX_B(s);
3321 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3322 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3323 }
3324 break;
3325 case 0x216: /* movshdup */
3326 if (mod != 3) {
3327 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003328 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
bellard664e0f12005-01-08 18:58:29 +00003329 } else {
3330 rm = (modrm & 7) | REX_B(s);
3331 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3332 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3333 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3334 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3335 }
3336 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3337 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3338 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3339 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3340 break;
Andre Przywarad9f4bb22009-09-19 00:30:48 +02003341 case 0x178:
3342 case 0x378:
3343 {
3344 int bit_index, field_length;
3345
3346 if (b1 == 1 && reg != 0)
3347 goto illegal_op;
3348 field_length = ldub_code(s->pc++) & 0x3F;
3349 bit_index = ldub_code(s->pc++) & 0x3F;
3350 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3351 offsetof(CPUX86State,xmm_regs[reg]));
3352 if (b1 == 1)
3353 gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3354 tcg_const_i32(field_length));
3355 else
3356 gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3357 tcg_const_i32(field_length));
3358 }
3359 break;
bellard664e0f12005-01-08 18:58:29 +00003360 case 0x7e: /* movd ea, mm */
bellarddabd98d2007-01-16 19:28:58 +00003361#ifdef TARGET_X86_64
3362 if (s->dflag == 2) {
bellard5af45182008-05-12 16:47:36 +00003363 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3364 offsetof(CPUX86State,fpregs[reg].mmx));
bellarddabd98d2007-01-16 19:28:58 +00003365 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
ths5fafdf22007-09-16 21:08:06 +00003366 } else
bellarddabd98d2007-01-16 19:28:58 +00003367#endif
3368 {
bellard5af45182008-05-12 16:47:36 +00003369 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3370 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
bellarddabd98d2007-01-16 19:28:58 +00003371 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3372 }
bellard664e0f12005-01-08 18:58:29 +00003373 break;
3374 case 0x17e: /* movd ea, xmm */
bellarddabd98d2007-01-16 19:28:58 +00003375#ifdef TARGET_X86_64
3376 if (s->dflag == 2) {
bellard5af45182008-05-12 16:47:36 +00003377 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3378 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellarddabd98d2007-01-16 19:28:58 +00003379 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
ths5fafdf22007-09-16 21:08:06 +00003380 } else
bellarddabd98d2007-01-16 19:28:58 +00003381#endif
3382 {
bellard5af45182008-05-12 16:47:36 +00003383 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3384 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
bellarddabd98d2007-01-16 19:28:58 +00003385 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3386 }
bellard664e0f12005-01-08 18:58:29 +00003387 break;
3388 case 0x27e: /* movq xmm, ea */
3389 if (mod != 3) {
3390 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003391 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003392 } else {
3393 rm = (modrm & 7) | REX_B(s);
3394 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3395 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3396 }
3397 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3398 break;
3399 case 0x7f: /* movq ea, mm */
3400 if (mod != 3) {
3401 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003402 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
bellard664e0f12005-01-08 18:58:29 +00003403 } else {
3404 rm = (modrm & 7);
3405 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3406 offsetof(CPUX86State,fpregs[reg].mmx));
3407 }
3408 break;
3409 case 0x011: /* movups */
3410 case 0x111: /* movupd */
3411 case 0x029: /* movaps */
3412 case 0x129: /* movapd */
3413 case 0x17f: /* movdqa ea, xmm */
3414 case 0x27f: /* movdqu ea, xmm */
3415 if (mod != 3) {
3416 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003417 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
bellard664e0f12005-01-08 18:58:29 +00003418 } else {
3419 rm = (modrm & 7) | REX_B(s);
3420 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3421 offsetof(CPUX86State,xmm_regs[reg]));
3422 }
3423 break;
3424 case 0x211: /* movss ea, xmm */
3425 if (mod != 3) {
3426 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard651ba602008-05-21 17:16:11 +00003427 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
bellard57fec1f2008-02-01 10:50:11 +00003428 gen_op_st_T0_A0(OT_LONG + s->mem_index);
bellard664e0f12005-01-08 18:58:29 +00003429 } else {
3430 rm = (modrm & 7) | REX_B(s);
3431 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3432 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3433 }
3434 break;
3435 case 0x311: /* movsd ea, xmm */
3436 if (mod != 3) {
3437 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003438 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003439 } else {
3440 rm = (modrm & 7) | REX_B(s);
3441 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3442 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3443 }
3444 break;
3445 case 0x013: /* movlps */
3446 case 0x113: /* movlpd */
3447 if (mod != 3) {
3448 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003449 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003450 } else {
3451 goto illegal_op;
3452 }
3453 break;
3454 case 0x017: /* movhps */
3455 case 0x117: /* movhpd */
3456 if (mod != 3) {
3457 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003458 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
bellard664e0f12005-01-08 18:58:29 +00003459 } else {
3460 goto illegal_op;
3461 }
3462 break;
3463 case 0x71: /* shift mm, im */
3464 case 0x72:
3465 case 0x73:
3466 case 0x171: /* shift xmm, im */
3467 case 0x172:
3468 case 0x173:
Andi Kleenc045af22010-06-27 00:06:11 +02003469 if (b1 >= 2) {
3470 goto illegal_op;
3471 }
bellard664e0f12005-01-08 18:58:29 +00003472 val = ldub_code(s->pc++);
3473 if (is_xmm) {
3474 gen_op_movl_T0_im(val);
bellard651ba602008-05-21 17:16:11 +00003475 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
bellard664e0f12005-01-08 18:58:29 +00003476 gen_op_movl_T0_0();
bellard651ba602008-05-21 17:16:11 +00003477 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
bellard664e0f12005-01-08 18:58:29 +00003478 op1_offset = offsetof(CPUX86State,xmm_t0);
3479 } else {
3480 gen_op_movl_T0_im(val);
bellard651ba602008-05-21 17:16:11 +00003481 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
bellard664e0f12005-01-08 18:58:29 +00003482 gen_op_movl_T0_0();
bellard651ba602008-05-21 17:16:11 +00003483 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
bellard664e0f12005-01-08 18:58:29 +00003484 op1_offset = offsetof(CPUX86State,mmx_t0);
3485 }
3486 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3487 if (!sse_op2)
3488 goto illegal_op;
3489 if (is_xmm) {
3490 rm = (modrm & 7) | REX_B(s);
3491 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3492 } else {
3493 rm = (modrm & 7);
3494 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3495 }
bellard5af45182008-05-12 16:47:36 +00003496 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3497 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
pbrooka7812ae2008-11-17 14:43:54 +00003498 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003499 break;
3500 case 0x050: /* movmskps */
bellard664e0f12005-01-08 18:58:29 +00003501 rm = (modrm & 7) | REX_B(s);
bellard5af45182008-05-12 16:47:36 +00003502 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3503 offsetof(CPUX86State,xmm_regs[rm]));
pbrooka7812ae2008-11-17 14:43:54 +00003504 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
bellardb6abf972008-05-17 12:44:31 +00003505 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard57fec1f2008-02-01 10:50:11 +00003506 gen_op_mov_reg_T0(OT_LONG, reg);
bellard664e0f12005-01-08 18:58:29 +00003507 break;
3508 case 0x150: /* movmskpd */
bellard664e0f12005-01-08 18:58:29 +00003509 rm = (modrm & 7) | REX_B(s);
bellard5af45182008-05-12 16:47:36 +00003510 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3511 offsetof(CPUX86State,xmm_regs[rm]));
pbrooka7812ae2008-11-17 14:43:54 +00003512 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
bellardb6abf972008-05-17 12:44:31 +00003513 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard57fec1f2008-02-01 10:50:11 +00003514 gen_op_mov_reg_T0(OT_LONG, reg);
bellard664e0f12005-01-08 18:58:29 +00003515 break;
3516 case 0x02a: /* cvtpi2ps */
3517 case 0x12a: /* cvtpi2pd */
pbrooka7812ae2008-11-17 14:43:54 +00003518 gen_helper_enter_mmx();
bellard664e0f12005-01-08 18:58:29 +00003519 if (mod != 3) {
3520 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3521 op2_offset = offsetof(CPUX86State,mmx_t0);
bellard8686c492008-05-12 13:55:27 +00003522 gen_ldq_env_A0(s->mem_index, op2_offset);
bellard664e0f12005-01-08 18:58:29 +00003523 } else {
3524 rm = (modrm & 7);
3525 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3526 }
3527 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
bellard5af45182008-05-12 16:47:36 +00003528 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3529 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
bellard664e0f12005-01-08 18:58:29 +00003530 switch(b >> 8) {
3531 case 0x0:
pbrooka7812ae2008-11-17 14:43:54 +00003532 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003533 break;
3534 default:
3535 case 0x1:
pbrooka7812ae2008-11-17 14:43:54 +00003536 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003537 break;
3538 }
3539 break;
3540 case 0x22a: /* cvtsi2ss */
3541 case 0x32a: /* cvtsi2sd */
3542 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3543 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3544 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
bellard5af45182008-05-12 16:47:36 +00003545 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3546 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
bellard28e10712008-07-07 20:25:41 +00003547 if (ot == OT_LONG) {
3548 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00003549 ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
bellard28e10712008-07-07 20:25:41 +00003550 } else {
pbrooka7812ae2008-11-17 14:43:54 +00003551 ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
bellard28e10712008-07-07 20:25:41 +00003552 }
bellard664e0f12005-01-08 18:58:29 +00003553 break;
3554 case 0x02c: /* cvttps2pi */
3555 case 0x12c: /* cvttpd2pi */
3556 case 0x02d: /* cvtps2pi */
3557 case 0x12d: /* cvtpd2pi */
pbrooka7812ae2008-11-17 14:43:54 +00003558 gen_helper_enter_mmx();
bellard664e0f12005-01-08 18:58:29 +00003559 if (mod != 3) {
3560 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3561 op2_offset = offsetof(CPUX86State,xmm_t0);
bellard8686c492008-05-12 13:55:27 +00003562 gen_ldo_env_A0(s->mem_index, op2_offset);
bellard664e0f12005-01-08 18:58:29 +00003563 } else {
3564 rm = (modrm & 7) | REX_B(s);
3565 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3566 }
3567 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
bellard5af45182008-05-12 16:47:36 +00003568 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3569 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
bellard664e0f12005-01-08 18:58:29 +00003570 switch(b) {
3571 case 0x02c:
pbrooka7812ae2008-11-17 14:43:54 +00003572 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003573 break;
3574 case 0x12c:
pbrooka7812ae2008-11-17 14:43:54 +00003575 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003576 break;
3577 case 0x02d:
pbrooka7812ae2008-11-17 14:43:54 +00003578 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003579 break;
3580 case 0x12d:
pbrooka7812ae2008-11-17 14:43:54 +00003581 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00003582 break;
3583 }
3584 break;
3585 case 0x22c: /* cvttss2si */
3586 case 0x32c: /* cvttsd2si */
3587 case 0x22d: /* cvtss2si */
3588 case 0x32d: /* cvtsd2si */
3589 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
bellard31313212005-03-03 01:14:55 +00003590 if (mod != 3) {
3591 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3592 if ((b >> 8) & 1) {
bellard8686c492008-05-12 13:55:27 +00003593 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
bellard31313212005-03-03 01:14:55 +00003594 } else {
bellard57fec1f2008-02-01 10:50:11 +00003595 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellard651ba602008-05-21 17:16:11 +00003596 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
bellard31313212005-03-03 01:14:55 +00003597 }
3598 op2_offset = offsetof(CPUX86State,xmm_t0);
3599 } else {
3600 rm = (modrm & 7) | REX_B(s);
3601 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3602 }
bellard5af45182008-05-12 16:47:36 +00003603 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3604 (b & 1) * 4];
3605 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3606 if (ot == OT_LONG) {
pbrooka7812ae2008-11-17 14:43:54 +00003607 ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
bellardb6abf972008-05-17 12:44:31 +00003608 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard5af45182008-05-12 16:47:36 +00003609 } else {
pbrooka7812ae2008-11-17 14:43:54 +00003610 ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
bellard5af45182008-05-12 16:47:36 +00003611 }
bellard57fec1f2008-02-01 10:50:11 +00003612 gen_op_mov_reg_T0(ot, reg);
bellard664e0f12005-01-08 18:58:29 +00003613 break;
3614 case 0xc4: /* pinsrw */
ths5fafdf22007-09-16 21:08:06 +00003615 case 0x1c4:
bellardd1e42c52006-06-14 14:29:34 +00003616 s->rip_offset = 1;
bellard664e0f12005-01-08 18:58:29 +00003617 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3618 val = ldub_code(s->pc++);
3619 if (b1) {
3620 val &= 7;
bellard5af45182008-05-12 16:47:36 +00003621 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3622 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
bellard664e0f12005-01-08 18:58:29 +00003623 } else {
3624 val &= 3;
bellard5af45182008-05-12 16:47:36 +00003625 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3626 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
bellard664e0f12005-01-08 18:58:29 +00003627 }
3628 break;
3629 case 0xc5: /* pextrw */
ths5fafdf22007-09-16 21:08:06 +00003630 case 0x1c5:
bellard664e0f12005-01-08 18:58:29 +00003631 if (mod != 3)
3632 goto illegal_op;
balrog6dc2d0d2008-10-01 00:14:39 +00003633 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
bellard664e0f12005-01-08 18:58:29 +00003634 val = ldub_code(s->pc++);
3635 if (b1) {
3636 val &= 7;
3637 rm = (modrm & 7) | REX_B(s);
bellard5af45182008-05-12 16:47:36 +00003638 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3639 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
bellard664e0f12005-01-08 18:58:29 +00003640 } else {
3641 val &= 3;
3642 rm = (modrm & 7);
bellard5af45182008-05-12 16:47:36 +00003643 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3644 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
bellard664e0f12005-01-08 18:58:29 +00003645 }
3646 reg = ((modrm >> 3) & 7) | rex_r;
balrog6dc2d0d2008-10-01 00:14:39 +00003647 gen_op_mov_reg_T0(ot, reg);
bellard664e0f12005-01-08 18:58:29 +00003648 break;
3649 case 0x1d6: /* movq ea, xmm */
3650 if (mod != 3) {
3651 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard8686c492008-05-12 13:55:27 +00003652 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003653 } else {
3654 rm = (modrm & 7) | REX_B(s);
3655 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3656 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3657 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3658 }
3659 break;
3660 case 0x2d6: /* movq2dq */
pbrooka7812ae2008-11-17 14:43:54 +00003661 gen_helper_enter_mmx();
bellard480c1cd2006-06-24 14:03:10 +00003662 rm = (modrm & 7);
3663 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3664 offsetof(CPUX86State,fpregs[rm].mmx));
3665 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
bellard664e0f12005-01-08 18:58:29 +00003666 break;
3667 case 0x3d6: /* movdq2q */
pbrooka7812ae2008-11-17 14:43:54 +00003668 gen_helper_enter_mmx();
bellard480c1cd2006-06-24 14:03:10 +00003669 rm = (modrm & 7) | REX_B(s);
3670 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3671 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
bellard664e0f12005-01-08 18:58:29 +00003672 break;
3673 case 0xd7: /* pmovmskb */
3674 case 0x1d7:
3675 if (mod != 3)
3676 goto illegal_op;
3677 if (b1) {
3678 rm = (modrm & 7) | REX_B(s);
bellard5af45182008-05-12 16:47:36 +00003679 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
pbrooka7812ae2008-11-17 14:43:54 +00003680 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
bellard664e0f12005-01-08 18:58:29 +00003681 } else {
3682 rm = (modrm & 7);
bellard5af45182008-05-12 16:47:36 +00003683 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
pbrooka7812ae2008-11-17 14:43:54 +00003684 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
bellard664e0f12005-01-08 18:58:29 +00003685 }
bellardb6abf972008-05-17 12:44:31 +00003686 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard664e0f12005-01-08 18:58:29 +00003687 reg = ((modrm >> 3) & 7) | rex_r;
bellard57fec1f2008-02-01 10:50:11 +00003688 gen_op_mov_reg_T0(OT_LONG, reg);
bellard664e0f12005-01-08 18:58:29 +00003689 break;
balrog4242b1b2008-09-25 18:01:46 +00003690 case 0x138:
balrog000cacf2008-10-04 11:33:52 +00003691 if (s->prefix & PREFIX_REPNZ)
3692 goto crc32;
3693 case 0x038:
balrog4242b1b2008-09-25 18:01:46 +00003694 b = modrm;
3695 modrm = ldub_code(s->pc++);
3696 rm = modrm & 7;
3697 reg = ((modrm >> 3) & 7) | rex_r;
3698 mod = (modrm >> 6) & 3;
Andi Kleenc045af22010-06-27 00:06:11 +02003699 if (b1 >= 2) {
3700 goto illegal_op;
3701 }
balrog4242b1b2008-09-25 18:01:46 +00003702
balrog222a3332008-10-04 03:27:44 +00003703 sse_op2 = sse_op_table6[b].op[b1];
balrog4242b1b2008-09-25 18:01:46 +00003704 if (!sse_op2)
3705 goto illegal_op;
balrog222a3332008-10-04 03:27:44 +00003706 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3707 goto illegal_op;
balrog4242b1b2008-09-25 18:01:46 +00003708
3709 if (b1) {
3710 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3711 if (mod == 3) {
3712 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3713 } else {
3714 op2_offset = offsetof(CPUX86State,xmm_t0);
3715 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
balrog222a3332008-10-04 03:27:44 +00003716 switch (b) {
3717 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3718 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3719 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3720 gen_ldq_env_A0(s->mem_index, op2_offset +
3721 offsetof(XMMReg, XMM_Q(0)));
3722 break;
3723 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3724 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
pbrooka7812ae2008-11-17 14:43:54 +00003725 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
balrog222a3332008-10-04 03:27:44 +00003726 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00003727 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
balrog222a3332008-10-04 03:27:44 +00003728 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3729 offsetof(XMMReg, XMM_L(0)));
3730 break;
3731 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3732 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3733 (s->mem_index >> 2) - 1);
3734 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3735 offsetof(XMMReg, XMM_W(0)));
3736 break;
3737 case 0x2a: /* movntqda */
3738 gen_ldo_env_A0(s->mem_index, op1_offset);
3739 return;
3740 default:
3741 gen_ldo_env_A0(s->mem_index, op2_offset);
3742 }
balrog4242b1b2008-09-25 18:01:46 +00003743 }
3744 } else {
3745 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3746 if (mod == 3) {
3747 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3748 } else {
3749 op2_offset = offsetof(CPUX86State,mmx_t0);
3750 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3751 gen_ldq_env_A0(s->mem_index, op2_offset);
3752 }
3753 }
balrog222a3332008-10-04 03:27:44 +00003754 if (sse_op2 == SSE_SPECIAL)
3755 goto illegal_op;
3756
balrog4242b1b2008-09-25 18:01:46 +00003757 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3758 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00003759 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
balrog222a3332008-10-04 03:27:44 +00003760
3761 if (b == 0x17)
3762 s->cc_op = CC_OP_EFLAGS;
3763 break;
3764 case 0x338: /* crc32 */
3765 crc32:
3766 b = modrm;
3767 modrm = ldub_code(s->pc++);
3768 reg = ((modrm >> 3) & 7) | rex_r;
3769
3770 if (b != 0xf0 && b != 0xf1)
3771 goto illegal_op;
3772 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3773 goto illegal_op;
3774
3775 if (b == 0xf0)
3776 ot = OT_BYTE;
3777 else if (b == 0xf1 && s->dflag != 2)
3778 if (s->prefix & PREFIX_DATA)
3779 ot = OT_WORD;
3780 else
3781 ot = OT_LONG;
3782 else
3783 ot = OT_QUAD;
3784
3785 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3786 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3787 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
pbrooka7812ae2008-11-17 14:43:54 +00003788 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3789 cpu_T[0], tcg_const_i32(8 << ot));
balrog222a3332008-10-04 03:27:44 +00003790
3791 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3792 gen_op_mov_reg_T0(ot, reg);
balrog4242b1b2008-09-25 18:01:46 +00003793 break;
3794 case 0x03a:
3795 case 0x13a:
balrog4242b1b2008-09-25 18:01:46 +00003796 b = modrm;
3797 modrm = ldub_code(s->pc++);
3798 rm = modrm & 7;
3799 reg = ((modrm >> 3) & 7) | rex_r;
3800 mod = (modrm >> 6) & 3;
Andi Kleenc045af22010-06-27 00:06:11 +02003801 if (b1 >= 2) {
3802 goto illegal_op;
3803 }
balrog4242b1b2008-09-25 18:01:46 +00003804
balrog222a3332008-10-04 03:27:44 +00003805 sse_op2 = sse_op_table7[b].op[b1];
balrog4242b1b2008-09-25 18:01:46 +00003806 if (!sse_op2)
3807 goto illegal_op;
balrog222a3332008-10-04 03:27:44 +00003808 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3809 goto illegal_op;
3810
3811 if (sse_op2 == SSE_SPECIAL) {
3812 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3813 rm = (modrm & 7) | REX_B(s);
3814 if (mod != 3)
3815 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3816 reg = ((modrm >> 3) & 7) | rex_r;
3817 val = ldub_code(s->pc++);
3818 switch (b) {
3819 case 0x14: /* pextrb */
3820 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3821 xmm_regs[reg].XMM_B(val & 15)));
3822 if (mod == 3)
3823 gen_op_mov_reg_T0(ot, rm);
3824 else
3825 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3826 (s->mem_index >> 2) - 1);
3827 break;
3828 case 0x15: /* pextrw */
3829 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3830 xmm_regs[reg].XMM_W(val & 7)));
3831 if (mod == 3)
3832 gen_op_mov_reg_T0(ot, rm);
3833 else
3834 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3835 (s->mem_index >> 2) - 1);
3836 break;
3837 case 0x16:
3838 if (ot == OT_LONG) { /* pextrd */
3839 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3840 offsetof(CPUX86State,
3841 xmm_regs[reg].XMM_L(val & 3)));
pbrooka7812ae2008-11-17 14:43:54 +00003842 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
balrog222a3332008-10-04 03:27:44 +00003843 if (mod == 3)
pbrooka7812ae2008-11-17 14:43:54 +00003844 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
balrog222a3332008-10-04 03:27:44 +00003845 else
pbrooka7812ae2008-11-17 14:43:54 +00003846 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
balrog222a3332008-10-04 03:27:44 +00003847 (s->mem_index >> 2) - 1);
3848 } else { /* pextrq */
pbrooka7812ae2008-11-17 14:43:54 +00003849#ifdef TARGET_X86_64
balrog222a3332008-10-04 03:27:44 +00003850 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3851 offsetof(CPUX86State,
3852 xmm_regs[reg].XMM_Q(val & 1)));
3853 if (mod == 3)
3854 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3855 else
3856 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3857 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00003858#else
3859 goto illegal_op;
3860#endif
balrog222a3332008-10-04 03:27:44 +00003861 }
3862 break;
3863 case 0x17: /* extractps */
3864 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3865 xmm_regs[reg].XMM_L(val & 3)));
3866 if (mod == 3)
3867 gen_op_mov_reg_T0(ot, rm);
3868 else
3869 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3870 (s->mem_index >> 2) - 1);
3871 break;
3872 case 0x20: /* pinsrb */
3873 if (mod == 3)
3874 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3875 else
pbrooka7812ae2008-11-17 14:43:54 +00003876 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
balrog222a3332008-10-04 03:27:44 +00003877 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00003878 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
balrog222a3332008-10-04 03:27:44 +00003879 xmm_regs[reg].XMM_B(val & 15)));
3880 break;
3881 case 0x21: /* insertps */
pbrooka7812ae2008-11-17 14:43:54 +00003882 if (mod == 3) {
balrog222a3332008-10-04 03:27:44 +00003883 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3884 offsetof(CPUX86State,xmm_regs[rm]
3885 .XMM_L((val >> 6) & 3)));
pbrooka7812ae2008-11-17 14:43:54 +00003886 } else {
3887 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
balrog222a3332008-10-04 03:27:44 +00003888 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00003889 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3890 }
balrog222a3332008-10-04 03:27:44 +00003891 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3892 offsetof(CPUX86State,xmm_regs[reg]
3893 .XMM_L((val >> 4) & 3)));
3894 if ((val >> 0) & 1)
3895 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3896 cpu_env, offsetof(CPUX86State,
3897 xmm_regs[reg].XMM_L(0)));
3898 if ((val >> 1) & 1)
3899 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3900 cpu_env, offsetof(CPUX86State,
3901 xmm_regs[reg].XMM_L(1)));
3902 if ((val >> 2) & 1)
3903 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3904 cpu_env, offsetof(CPUX86State,
3905 xmm_regs[reg].XMM_L(2)));
3906 if ((val >> 3) & 1)
3907 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3908 cpu_env, offsetof(CPUX86State,
3909 xmm_regs[reg].XMM_L(3)));
3910 break;
3911 case 0x22:
3912 if (ot == OT_LONG) { /* pinsrd */
3913 if (mod == 3)
pbrooka7812ae2008-11-17 14:43:54 +00003914 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
balrog222a3332008-10-04 03:27:44 +00003915 else
pbrooka7812ae2008-11-17 14:43:54 +00003916 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
balrog222a3332008-10-04 03:27:44 +00003917 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00003918 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
balrog222a3332008-10-04 03:27:44 +00003919 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3920 offsetof(CPUX86State,
3921 xmm_regs[reg].XMM_L(val & 3)));
3922 } else { /* pinsrq */
pbrooka7812ae2008-11-17 14:43:54 +00003923#ifdef TARGET_X86_64
balrog222a3332008-10-04 03:27:44 +00003924 if (mod == 3)
3925 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3926 else
3927 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3928 (s->mem_index >> 2) - 1);
3929 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3930 offsetof(CPUX86State,
3931 xmm_regs[reg].XMM_Q(val & 1)));
pbrooka7812ae2008-11-17 14:43:54 +00003932#else
3933 goto illegal_op;
3934#endif
balrog222a3332008-10-04 03:27:44 +00003935 }
3936 break;
3937 }
3938 return;
3939 }
balrog4242b1b2008-09-25 18:01:46 +00003940
3941 if (b1) {
3942 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3943 if (mod == 3) {
3944 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3945 } else {
3946 op2_offset = offsetof(CPUX86State,xmm_t0);
3947 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3948 gen_ldo_env_A0(s->mem_index, op2_offset);
3949 }
3950 } else {
3951 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3952 if (mod == 3) {
3953 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3954 } else {
3955 op2_offset = offsetof(CPUX86State,mmx_t0);
3956 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3957 gen_ldq_env_A0(s->mem_index, op2_offset);
3958 }
3959 }
3960 val = ldub_code(s->pc++);
3961
balrog222a3332008-10-04 03:27:44 +00003962 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3963 s->cc_op = CC_OP_EFLAGS;
3964
3965 if (s->dflag == 2)
3966 /* The helper must use entire 64-bit gp registers */
3967 val |= 1 << 8;
3968 }
3969
balrog4242b1b2008-09-25 18:01:46 +00003970 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3971 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00003972 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
balrog4242b1b2008-09-25 18:01:46 +00003973 break;
bellard664e0f12005-01-08 18:58:29 +00003974 default:
3975 goto illegal_op;
3976 }
3977 } else {
3978 /* generic MMX or SSE operation */
bellardd1e42c52006-06-14 14:29:34 +00003979 switch(b) {
bellardd1e42c52006-06-14 14:29:34 +00003980 case 0x70: /* pshufx insn */
3981 case 0xc6: /* pshufx insn */
3982 case 0xc2: /* compare insns */
3983 s->rip_offset = 1;
3984 break;
3985 default:
3986 break;
bellard664e0f12005-01-08 18:58:29 +00003987 }
3988 if (is_xmm) {
3989 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3990 if (mod != 3) {
3991 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3992 op2_offset = offsetof(CPUX86State,xmm_t0);
bellard480c1cd2006-06-24 14:03:10 +00003993 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
bellard664e0f12005-01-08 18:58:29 +00003994 b == 0xc2)) {
3995 /* specific case for SSE single instructions */
3996 if (b1 == 2) {
3997 /* 32 bit access */
bellard57fec1f2008-02-01 10:50:11 +00003998 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellard651ba602008-05-21 17:16:11 +00003999 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
bellard664e0f12005-01-08 18:58:29 +00004000 } else {
4001 /* 64 bit access */
bellard8686c492008-05-12 13:55:27 +00004002 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
bellard664e0f12005-01-08 18:58:29 +00004003 }
4004 } else {
bellard8686c492008-05-12 13:55:27 +00004005 gen_ldo_env_A0(s->mem_index, op2_offset);
bellard664e0f12005-01-08 18:58:29 +00004006 }
4007 } else {
4008 rm = (modrm & 7) | REX_B(s);
4009 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4010 }
4011 } else {
4012 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4013 if (mod != 3) {
4014 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4015 op2_offset = offsetof(CPUX86State,mmx_t0);
bellard8686c492008-05-12 13:55:27 +00004016 gen_ldq_env_A0(s->mem_index, op2_offset);
bellard664e0f12005-01-08 18:58:29 +00004017 } else {
4018 rm = (modrm & 7);
4019 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4020 }
4021 }
4022 switch(b) {
aurel32a35f3ec2008-04-08 19:51:29 +00004023 case 0x0f: /* 3DNow! data insns */
aurel32e771eda2008-04-09 06:41:37 +00004024 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4025 goto illegal_op;
aurel32a35f3ec2008-04-08 19:51:29 +00004026 val = ldub_code(s->pc++);
4027 sse_op2 = sse_op_table5[val];
4028 if (!sse_op2)
4029 goto illegal_op;
bellard5af45182008-05-12 16:47:36 +00004030 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4031 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00004032 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
aurel32a35f3ec2008-04-08 19:51:29 +00004033 break;
bellard664e0f12005-01-08 18:58:29 +00004034 case 0x70: /* pshufx insn */
4035 case 0xc6: /* pshufx insn */
4036 val = ldub_code(s->pc++);
bellard5af45182008-05-12 16:47:36 +00004037 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4038 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00004039 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
bellard664e0f12005-01-08 18:58:29 +00004040 break;
4041 case 0xc2:
4042 /* compare insns */
4043 val = ldub_code(s->pc++);
4044 if (val >= 8)
4045 goto illegal_op;
4046 sse_op2 = sse_op_table4[val][b1];
bellard5af45182008-05-12 16:47:36 +00004047 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4048 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00004049 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00004050 break;
bellardb8b6a502008-05-15 16:46:30 +00004051 case 0xf7:
4052 /* maskmov : we must prepare A0 */
4053 if (mod != 3)
4054 goto illegal_op;
4055#ifdef TARGET_X86_64
4056 if (s->aflag == 2) {
4057 gen_op_movq_A0_reg(R_EDI);
4058 } else
4059#endif
4060 {
4061 gen_op_movl_A0_reg(R_EDI);
4062 if (s->aflag == 0)
4063 gen_op_andl_A0_ffff();
4064 }
4065 gen_add_A0_ds_seg(s);
4066
4067 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4068 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00004069 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
bellardb8b6a502008-05-15 16:46:30 +00004070 break;
bellard664e0f12005-01-08 18:58:29 +00004071 default:
bellard5af45182008-05-12 16:47:36 +00004072 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4073 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
pbrooka7812ae2008-11-17 14:43:54 +00004074 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
bellard664e0f12005-01-08 18:58:29 +00004075 break;
4076 }
4077 if (b == 0x2e || b == 0x2f) {
4078 s->cc_op = CC_OP_EFLAGS;
4079 }
4080 }
4081}
4082
bellard2c0262a2003-09-30 20:34:21 +00004083/* convert one instruction. s->is_jmp is set if the translation must
4084 be stopped. Return the next pc value */
bellard14ce26e2005-01-03 23:50:08 +00004085static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
bellard2c0262a2003-09-30 20:34:21 +00004086{
4087 int b, prefixes, aflag, dflag;
4088 int shift, ot;
4089 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
bellard14ce26e2005-01-03 23:50:08 +00004090 target_ulong next_eip, tval;
4091 int rex_w, rex_r;
bellard2c0262a2003-09-30 20:34:21 +00004092
aliguori8fec2b82009-01-15 22:36:53 +00004093 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
bellard70cff252008-05-22 17:00:49 +00004094 tcg_gen_debug_insn_start(pc_start);
bellard2c0262a2003-09-30 20:34:21 +00004095 s->pc = pc_start;
4096 prefixes = 0;
4097 aflag = s->code32;
4098 dflag = s->code32;
4099 s->override = -1;
bellard14ce26e2005-01-03 23:50:08 +00004100 rex_w = -1;
4101 rex_r = 0;
4102#ifdef TARGET_X86_64
4103 s->rex_x = 0;
4104 s->rex_b = 0;
ths5fafdf22007-09-16 21:08:06 +00004105 x86_64_hregs = 0;
bellard14ce26e2005-01-03 23:50:08 +00004106#endif
4107 s->rip_offset = 0; /* for relative ip address */
bellard2c0262a2003-09-30 20:34:21 +00004108 next_byte:
bellard61382a52003-10-27 21:22:23 +00004109 b = ldub_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00004110 s->pc++;
4111 /* check prefixes */
bellard14ce26e2005-01-03 23:50:08 +00004112#ifdef TARGET_X86_64
4113 if (CODE64(s)) {
4114 switch (b) {
4115 case 0xf3:
4116 prefixes |= PREFIX_REPZ;
4117 goto next_byte;
4118 case 0xf2:
4119 prefixes |= PREFIX_REPNZ;
4120 goto next_byte;
4121 case 0xf0:
4122 prefixes |= PREFIX_LOCK;
4123 goto next_byte;
4124 case 0x2e:
4125 s->override = R_CS;
4126 goto next_byte;
4127 case 0x36:
4128 s->override = R_SS;
4129 goto next_byte;
4130 case 0x3e:
4131 s->override = R_DS;
4132 goto next_byte;
4133 case 0x26:
4134 s->override = R_ES;
4135 goto next_byte;
4136 case 0x64:
4137 s->override = R_FS;
4138 goto next_byte;
4139 case 0x65:
4140 s->override = R_GS;
4141 goto next_byte;
4142 case 0x66:
4143 prefixes |= PREFIX_DATA;
4144 goto next_byte;
4145 case 0x67:
4146 prefixes |= PREFIX_ADR;
4147 goto next_byte;
4148 case 0x40 ... 0x4f:
4149 /* REX prefix */
4150 rex_w = (b >> 3) & 1;
4151 rex_r = (b & 0x4) << 1;
4152 s->rex_x = (b & 0x2) << 2;
4153 REX_B(s) = (b & 0x1) << 3;
4154 x86_64_hregs = 1; /* select uniform byte register addressing */
4155 goto next_byte;
4156 }
4157 if (rex_w == 1) {
4158 /* 0x66 is ignored if rex.w is set */
4159 dflag = 2;
4160 } else {
4161 if (prefixes & PREFIX_DATA)
4162 dflag ^= 1;
4163 }
4164 if (!(prefixes & PREFIX_ADR))
4165 aflag = 2;
ths5fafdf22007-09-16 21:08:06 +00004166 } else
bellard14ce26e2005-01-03 23:50:08 +00004167#endif
4168 {
4169 switch (b) {
4170 case 0xf3:
4171 prefixes |= PREFIX_REPZ;
4172 goto next_byte;
4173 case 0xf2:
4174 prefixes |= PREFIX_REPNZ;
4175 goto next_byte;
4176 case 0xf0:
4177 prefixes |= PREFIX_LOCK;
4178 goto next_byte;
4179 case 0x2e:
4180 s->override = R_CS;
4181 goto next_byte;
4182 case 0x36:
4183 s->override = R_SS;
4184 goto next_byte;
4185 case 0x3e:
4186 s->override = R_DS;
4187 goto next_byte;
4188 case 0x26:
4189 s->override = R_ES;
4190 goto next_byte;
4191 case 0x64:
4192 s->override = R_FS;
4193 goto next_byte;
4194 case 0x65:
4195 s->override = R_GS;
4196 goto next_byte;
4197 case 0x66:
4198 prefixes |= PREFIX_DATA;
4199 goto next_byte;
4200 case 0x67:
4201 prefixes |= PREFIX_ADR;
4202 goto next_byte;
4203 }
4204 if (prefixes & PREFIX_DATA)
4205 dflag ^= 1;
4206 if (prefixes & PREFIX_ADR)
4207 aflag ^= 1;
bellard2c0262a2003-09-30 20:34:21 +00004208 }
4209
bellard2c0262a2003-09-30 20:34:21 +00004210 s->prefix = prefixes;
4211 s->aflag = aflag;
4212 s->dflag = dflag;
4213
4214 /* lock generation */
4215 if (prefixes & PREFIX_LOCK)
pbrooka7812ae2008-11-17 14:43:54 +00004216 gen_helper_lock();
bellard2c0262a2003-09-30 20:34:21 +00004217
4218 /* now check op code */
4219 reswitch:
4220 switch(b) {
4221 case 0x0f:
4222 /**************************/
4223 /* extended op code */
bellard61382a52003-10-27 21:22:23 +00004224 b = ldub_code(s->pc++) | 0x100;
bellard2c0262a2003-09-30 20:34:21 +00004225 goto reswitch;
ths3b46e622007-09-17 08:09:54 +00004226
bellard2c0262a2003-09-30 20:34:21 +00004227 /**************************/
4228 /* arith & logic */
4229 case 0x00 ... 0x05:
4230 case 0x08 ... 0x0d:
4231 case 0x10 ... 0x15:
4232 case 0x18 ... 0x1d:
4233 case 0x20 ... 0x25:
4234 case 0x28 ... 0x2d:
4235 case 0x30 ... 0x35:
4236 case 0x38 ... 0x3d:
4237 {
4238 int op, f, val;
4239 op = (b >> 3) & 7;
4240 f = (b >> 1) & 3;
4241
4242 if ((b & 1) == 0)
4243 ot = OT_BYTE;
4244 else
bellard14ce26e2005-01-03 23:50:08 +00004245 ot = dflag + OT_WORD;
ths3b46e622007-09-17 08:09:54 +00004246
bellard2c0262a2003-09-30 20:34:21 +00004247 switch(f) {
4248 case 0: /* OP Ev, Gv */
bellard61382a52003-10-27 21:22:23 +00004249 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00004250 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00004251 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00004252 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00004253 if (mod != 3) {
4254 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4255 opreg = OR_TMP0;
4256 } else if (op == OP_XORL && rm == reg) {
4257 xor_zero:
4258 /* xor reg, reg optimisation */
4259 gen_op_movl_T0_0();
4260 s->cc_op = CC_OP_LOGICB + ot;
bellard57fec1f2008-02-01 10:50:11 +00004261 gen_op_mov_reg_T0(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00004262 gen_op_update1_cc();
4263 break;
4264 } else {
4265 opreg = rm;
4266 }
bellard57fec1f2008-02-01 10:50:11 +00004267 gen_op_mov_TN_reg(ot, 1, reg);
bellard2c0262a2003-09-30 20:34:21 +00004268 gen_op(s, op, ot, opreg);
4269 break;
4270 case 1: /* OP Gv, Ev */
bellard61382a52003-10-27 21:22:23 +00004271 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00004272 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00004273 reg = ((modrm >> 3) & 7) | rex_r;
4274 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00004275 if (mod != 3) {
4276 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00004277 gen_op_ld_T1_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004278 } else if (op == OP_XORL && rm == reg) {
4279 goto xor_zero;
4280 } else {
bellard57fec1f2008-02-01 10:50:11 +00004281 gen_op_mov_TN_reg(ot, 1, rm);
bellard2c0262a2003-09-30 20:34:21 +00004282 }
4283 gen_op(s, op, ot, reg);
4284 break;
4285 case 2: /* OP A, Iv */
4286 val = insn_get(s, ot);
4287 gen_op_movl_T1_im(val);
4288 gen_op(s, op, ot, OR_EAX);
4289 break;
4290 }
4291 }
4292 break;
4293
bellardec9d6072008-06-06 12:54:30 +00004294 case 0x82:
4295 if (CODE64(s))
4296 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00004297 case 0x80: /* GRP1 */
4298 case 0x81:
4299 case 0x83:
4300 {
4301 int val;
4302
4303 if ((b & 1) == 0)
4304 ot = OT_BYTE;
4305 else
bellard14ce26e2005-01-03 23:50:08 +00004306 ot = dflag + OT_WORD;
ths3b46e622007-09-17 08:09:54 +00004307
bellard61382a52003-10-27 21:22:23 +00004308 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00004309 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00004310 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00004311 op = (modrm >> 3) & 7;
ths3b46e622007-09-17 08:09:54 +00004312
bellard2c0262a2003-09-30 20:34:21 +00004313 if (mod != 3) {
bellard14ce26e2005-01-03 23:50:08 +00004314 if (b == 0x83)
4315 s->rip_offset = 1;
4316 else
4317 s->rip_offset = insn_const_size(ot);
bellard2c0262a2003-09-30 20:34:21 +00004318 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4319 opreg = OR_TMP0;
4320 } else {
bellard14ce26e2005-01-03 23:50:08 +00004321 opreg = rm;
bellard2c0262a2003-09-30 20:34:21 +00004322 }
4323
4324 switch(b) {
4325 default:
4326 case 0x80:
4327 case 0x81:
bellardd64477a2004-04-22 21:34:25 +00004328 case 0x82:
bellard2c0262a2003-09-30 20:34:21 +00004329 val = insn_get(s, ot);
4330 break;
4331 case 0x83:
4332 val = (int8_t)insn_get(s, OT_BYTE);
4333 break;
4334 }
4335 gen_op_movl_T1_im(val);
4336 gen_op(s, op, ot, opreg);
4337 }
4338 break;
4339
4340 /**************************/
4341 /* inc, dec, and other misc arith */
4342 case 0x40 ... 0x47: /* inc Gv */
4343 ot = dflag ? OT_LONG : OT_WORD;
4344 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4345 break;
4346 case 0x48 ... 0x4f: /* dec Gv */
4347 ot = dflag ? OT_LONG : OT_WORD;
4348 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4349 break;
4350 case 0xf6: /* GRP3 */
4351 case 0xf7:
4352 if ((b & 1) == 0)
4353 ot = OT_BYTE;
4354 else
bellard14ce26e2005-01-03 23:50:08 +00004355 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00004356
bellard61382a52003-10-27 21:22:23 +00004357 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00004358 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00004359 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00004360 op = (modrm >> 3) & 7;
4361 if (mod != 3) {
bellard14ce26e2005-01-03 23:50:08 +00004362 if (op == 0)
4363 s->rip_offset = insn_const_size(ot);
bellard2c0262a2003-09-30 20:34:21 +00004364 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00004365 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004366 } else {
bellard57fec1f2008-02-01 10:50:11 +00004367 gen_op_mov_TN_reg(ot, 0, rm);
bellard2c0262a2003-09-30 20:34:21 +00004368 }
4369
4370 switch(op) {
4371 case 0: /* test */
4372 val = insn_get(s, ot);
4373 gen_op_movl_T1_im(val);
4374 gen_op_testl_T0_T1_cc();
4375 s->cc_op = CC_OP_LOGICB + ot;
4376 break;
4377 case 2: /* not */
bellardb6abf972008-05-17 12:44:31 +00004378 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004379 if (mod != 3) {
bellard57fec1f2008-02-01 10:50:11 +00004380 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004381 } else {
bellard57fec1f2008-02-01 10:50:11 +00004382 gen_op_mov_reg_T0(ot, rm);
bellard2c0262a2003-09-30 20:34:21 +00004383 }
4384 break;
4385 case 3: /* neg */
bellardb6abf972008-05-17 12:44:31 +00004386 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004387 if (mod != 3) {
bellard57fec1f2008-02-01 10:50:11 +00004388 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004389 } else {
bellard57fec1f2008-02-01 10:50:11 +00004390 gen_op_mov_reg_T0(ot, rm);
bellard2c0262a2003-09-30 20:34:21 +00004391 }
4392 gen_op_update_neg_cc();
4393 s->cc_op = CC_OP_SUBB + ot;
4394 break;
4395 case 4: /* mul */
4396 switch(ot) {
4397 case OT_BYTE:
bellard0211e5a2008-05-21 10:12:54 +00004398 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4399 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4400 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4401 /* XXX: use 32 bit mul which could be faster */
4402 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4403 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4404 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4405 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
bellardd36cd602003-12-02 22:01:31 +00004406 s->cc_op = CC_OP_MULB;
bellard2c0262a2003-09-30 20:34:21 +00004407 break;
4408 case OT_WORD:
bellard0211e5a2008-05-21 10:12:54 +00004409 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4410 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4411 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4412 /* XXX: use 32 bit mul which could be faster */
4413 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4414 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4415 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4416 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4417 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4418 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
bellardd36cd602003-12-02 22:01:31 +00004419 s->cc_op = CC_OP_MULW;
bellard2c0262a2003-09-30 20:34:21 +00004420 break;
4421 default:
4422 case OT_LONG:
bellard0211e5a2008-05-21 10:12:54 +00004423#ifdef TARGET_X86_64
4424 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4425 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4426 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4427 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4428 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4429 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4430 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4431 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4432 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4433#else
4434 {
pbrooka7812ae2008-11-17 14:43:54 +00004435 TCGv_i64 t0, t1;
4436 t0 = tcg_temp_new_i64();
4437 t1 = tcg_temp_new_i64();
bellard0211e5a2008-05-21 10:12:54 +00004438 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4439 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4440 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4441 tcg_gen_mul_i64(t0, t0, t1);
4442 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4443 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4444 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4445 tcg_gen_shri_i64(t0, t0, 32);
4446 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4447 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4448 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4449 }
4450#endif
bellardd36cd602003-12-02 22:01:31 +00004451 s->cc_op = CC_OP_MULL;
bellard2c0262a2003-09-30 20:34:21 +00004452 break;
bellard14ce26e2005-01-03 23:50:08 +00004453#ifdef TARGET_X86_64
4454 case OT_QUAD:
pbrooka7812ae2008-11-17 14:43:54 +00004455 gen_helper_mulq_EAX_T0(cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00004456 s->cc_op = CC_OP_MULQ;
4457 break;
4458#endif
bellard2c0262a2003-09-30 20:34:21 +00004459 }
bellard2c0262a2003-09-30 20:34:21 +00004460 break;
4461 case 5: /* imul */
4462 switch(ot) {
4463 case OT_BYTE:
bellard0211e5a2008-05-21 10:12:54 +00004464 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4465 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4466 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4467 /* XXX: use 32 bit mul which could be faster */
4468 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4469 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4470 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4471 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4472 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
bellardd36cd602003-12-02 22:01:31 +00004473 s->cc_op = CC_OP_MULB;
bellard2c0262a2003-09-30 20:34:21 +00004474 break;
4475 case OT_WORD:
bellard0211e5a2008-05-21 10:12:54 +00004476 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4477 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4478 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4479 /* XXX: use 32 bit mul which could be faster */
4480 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4481 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4482 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4483 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4484 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4485 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4486 gen_op_mov_reg_T0(OT_WORD, R_EDX);
bellardd36cd602003-12-02 22:01:31 +00004487 s->cc_op = CC_OP_MULW;
bellard2c0262a2003-09-30 20:34:21 +00004488 break;
4489 default:
4490 case OT_LONG:
bellard0211e5a2008-05-21 10:12:54 +00004491#ifdef TARGET_X86_64
4492 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4493 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4494 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4495 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4496 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4497 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4498 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4499 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4500 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4501 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4502#else
4503 {
pbrooka7812ae2008-11-17 14:43:54 +00004504 TCGv_i64 t0, t1;
4505 t0 = tcg_temp_new_i64();
4506 t1 = tcg_temp_new_i64();
bellard0211e5a2008-05-21 10:12:54 +00004507 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4508 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4509 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4510 tcg_gen_mul_i64(t0, t0, t1);
4511 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4512 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4513 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4514 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4515 tcg_gen_shri_i64(t0, t0, 32);
4516 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4517 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4518 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4519 }
4520#endif
bellardd36cd602003-12-02 22:01:31 +00004521 s->cc_op = CC_OP_MULL;
bellard2c0262a2003-09-30 20:34:21 +00004522 break;
bellard14ce26e2005-01-03 23:50:08 +00004523#ifdef TARGET_X86_64
4524 case OT_QUAD:
pbrooka7812ae2008-11-17 14:43:54 +00004525 gen_helper_imulq_EAX_T0(cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00004526 s->cc_op = CC_OP_MULQ;
4527 break;
4528#endif
bellard2c0262a2003-09-30 20:34:21 +00004529 }
bellard2c0262a2003-09-30 20:34:21 +00004530 break;
4531 case 6: /* div */
4532 switch(ot) {
4533 case OT_BYTE:
bellard14ce26e2005-01-03 23:50:08 +00004534 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004535 gen_helper_divb_AL(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004536 break;
4537 case OT_WORD:
bellard14ce26e2005-01-03 23:50:08 +00004538 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004539 gen_helper_divw_AX(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004540 break;
4541 default:
4542 case OT_LONG:
bellard14ce26e2005-01-03 23:50:08 +00004543 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004544 gen_helper_divl_EAX(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004545 break;
bellard14ce26e2005-01-03 23:50:08 +00004546#ifdef TARGET_X86_64
4547 case OT_QUAD:
4548 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004549 gen_helper_divq_EAX(cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00004550 break;
4551#endif
bellard2c0262a2003-09-30 20:34:21 +00004552 }
4553 break;
4554 case 7: /* idiv */
4555 switch(ot) {
4556 case OT_BYTE:
bellard14ce26e2005-01-03 23:50:08 +00004557 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004558 gen_helper_idivb_AL(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004559 break;
4560 case OT_WORD:
bellard14ce26e2005-01-03 23:50:08 +00004561 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004562 gen_helper_idivw_AX(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004563 break;
4564 default:
4565 case OT_LONG:
bellard14ce26e2005-01-03 23:50:08 +00004566 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004567 gen_helper_idivl_EAX(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00004568 break;
bellard14ce26e2005-01-03 23:50:08 +00004569#ifdef TARGET_X86_64
4570 case OT_QUAD:
4571 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00004572 gen_helper_idivq_EAX(cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00004573 break;
4574#endif
bellard2c0262a2003-09-30 20:34:21 +00004575 }
4576 break;
4577 default:
4578 goto illegal_op;
4579 }
4580 break;
4581
4582 case 0xfe: /* GRP4 */
4583 case 0xff: /* GRP5 */
4584 if ((b & 1) == 0)
4585 ot = OT_BYTE;
4586 else
bellard14ce26e2005-01-03 23:50:08 +00004587 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00004588
bellard61382a52003-10-27 21:22:23 +00004589 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00004590 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00004591 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00004592 op = (modrm >> 3) & 7;
4593 if (op >= 2 && b == 0xfe) {
4594 goto illegal_op;
4595 }
bellard14ce26e2005-01-03 23:50:08 +00004596 if (CODE64(s)) {
bellardaba9d612005-04-23 17:53:12 +00004597 if (op == 2 || op == 4) {
bellard14ce26e2005-01-03 23:50:08 +00004598 /* operand size for jumps is 64 bit */
4599 ot = OT_QUAD;
bellardaba9d612005-04-23 17:53:12 +00004600 } else if (op == 3 || op == 5) {
malc41b1e612010-03-04 15:09:26 +03004601 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
bellard14ce26e2005-01-03 23:50:08 +00004602 } else if (op == 6) {
4603 /* default push size is 64 bit */
4604 ot = dflag ? OT_QUAD : OT_WORD;
4605 }
4606 }
bellard2c0262a2003-09-30 20:34:21 +00004607 if (mod != 3) {
4608 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4609 if (op >= 2 && op != 3 && op != 5)
bellard57fec1f2008-02-01 10:50:11 +00004610 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004611 } else {
bellard57fec1f2008-02-01 10:50:11 +00004612 gen_op_mov_TN_reg(ot, 0, rm);
bellard2c0262a2003-09-30 20:34:21 +00004613 }
4614
4615 switch(op) {
4616 case 0: /* inc Ev */
4617 if (mod != 3)
4618 opreg = OR_TMP0;
4619 else
4620 opreg = rm;
4621 gen_inc(s, ot, opreg, 1);
4622 break;
4623 case 1: /* dec Ev */
4624 if (mod != 3)
4625 opreg = OR_TMP0;
4626 else
4627 opreg = rm;
4628 gen_inc(s, ot, opreg, -1);
4629 break;
4630 case 2: /* call Ev */
bellard4f319162004-01-04 17:35:00 +00004631 /* XXX: optimize if memory (no 'and' is necessary) */
bellard2c0262a2003-09-30 20:34:21 +00004632 if (s->dflag == 0)
4633 gen_op_andl_T0_ffff();
bellard2c0262a2003-09-30 20:34:21 +00004634 next_eip = s->pc - s->cs_base;
bellard1ef38682005-01-31 23:31:02 +00004635 gen_movtl_T1_im(next_eip);
bellard4f319162004-01-04 17:35:00 +00004636 gen_push_T1(s);
4637 gen_op_jmp_T0();
bellard2c0262a2003-09-30 20:34:21 +00004638 gen_eob(s);
4639 break;
bellard61382a52003-10-27 21:22:23 +00004640 case 3: /* lcall Ev */
bellard57fec1f2008-02-01 10:50:11 +00004641 gen_op_ld_T1_A0(ot + s->mem_index);
bellardaba9d612005-04-23 17:53:12 +00004642 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
bellard57fec1f2008-02-01 10:50:11 +00004643 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004644 do_lcall:
4645 if (s->pe && !s->vm86) {
4646 if (s->cc_op != CC_OP_DYNAMIC)
4647 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00004648 gen_jmp_im(pc_start - s->cs_base);
bellardb6abf972008-05-17 12:44:31 +00004649 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00004650 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4651 tcg_const_i32(dflag),
4652 tcg_const_i32(s->pc - pc_start));
bellard2c0262a2003-09-30 20:34:21 +00004653 } else {
bellardb6abf972008-05-17 12:44:31 +00004654 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00004655 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4656 tcg_const_i32(dflag),
4657 tcg_const_i32(s->pc - s->cs_base));
bellard2c0262a2003-09-30 20:34:21 +00004658 }
4659 gen_eob(s);
4660 break;
4661 case 4: /* jmp Ev */
4662 if (s->dflag == 0)
4663 gen_op_andl_T0_ffff();
4664 gen_op_jmp_T0();
4665 gen_eob(s);
4666 break;
4667 case 5: /* ljmp Ev */
bellard57fec1f2008-02-01 10:50:11 +00004668 gen_op_ld_T1_A0(ot + s->mem_index);
bellardaba9d612005-04-23 17:53:12 +00004669 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
bellard57fec1f2008-02-01 10:50:11 +00004670 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004671 do_ljmp:
4672 if (s->pe && !s->vm86) {
4673 if (s->cc_op != CC_OP_DYNAMIC)
4674 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00004675 gen_jmp_im(pc_start - s->cs_base);
bellardb6abf972008-05-17 12:44:31 +00004676 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00004677 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4678 tcg_const_i32(s->pc - pc_start));
bellard2c0262a2003-09-30 20:34:21 +00004679 } else {
bellard3bd7da92008-05-21 16:34:06 +00004680 gen_op_movl_seg_T0_vm(R_CS);
bellard2c0262a2003-09-30 20:34:21 +00004681 gen_op_movl_T0_T1();
4682 gen_op_jmp_T0();
4683 }
4684 gen_eob(s);
4685 break;
4686 case 6: /* push Ev */
4687 gen_push_T0(s);
4688 break;
4689 default:
4690 goto illegal_op;
4691 }
4692 break;
4693
4694 case 0x84: /* test Ev, Gv */
ths5fafdf22007-09-16 21:08:06 +00004695 case 0x85:
bellard2c0262a2003-09-30 20:34:21 +00004696 if ((b & 1) == 0)
4697 ot = OT_BYTE;
4698 else
bellard14ce26e2005-01-03 23:50:08 +00004699 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00004700
bellard61382a52003-10-27 21:22:23 +00004701 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00004702 reg = ((modrm >> 3) & 7) | rex_r;
ths3b46e622007-09-17 08:09:54 +00004703
bellard2c0262a2003-09-30 20:34:21 +00004704 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
bellard57fec1f2008-02-01 10:50:11 +00004705 gen_op_mov_TN_reg(ot, 1, reg);
bellard2c0262a2003-09-30 20:34:21 +00004706 gen_op_testl_T0_T1_cc();
4707 s->cc_op = CC_OP_LOGICB + ot;
4708 break;
ths3b46e622007-09-17 08:09:54 +00004709
bellard2c0262a2003-09-30 20:34:21 +00004710 case 0xa8: /* test eAX, Iv */
4711 case 0xa9:
4712 if ((b & 1) == 0)
4713 ot = OT_BYTE;
4714 else
bellard14ce26e2005-01-03 23:50:08 +00004715 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00004716 val = insn_get(s, ot);
4717
bellard57fec1f2008-02-01 10:50:11 +00004718 gen_op_mov_TN_reg(ot, 0, OR_EAX);
bellard2c0262a2003-09-30 20:34:21 +00004719 gen_op_movl_T1_im(val);
4720 gen_op_testl_T0_T1_cc();
4721 s->cc_op = CC_OP_LOGICB + ot;
4722 break;
ths3b46e622007-09-17 08:09:54 +00004723
bellard2c0262a2003-09-30 20:34:21 +00004724 case 0x98: /* CWDE/CBW */
bellard14ce26e2005-01-03 23:50:08 +00004725#ifdef TARGET_X86_64
4726 if (dflag == 2) {
bellarde108dd02008-05-17 19:24:07 +00004727 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4728 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4729 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
bellard14ce26e2005-01-03 23:50:08 +00004730 } else
4731#endif
bellarde108dd02008-05-17 19:24:07 +00004732 if (dflag == 1) {
4733 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4734 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4735 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4736 } else {
4737 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4738 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4739 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4740 }
bellard2c0262a2003-09-30 20:34:21 +00004741 break;
4742 case 0x99: /* CDQ/CWD */
bellard14ce26e2005-01-03 23:50:08 +00004743#ifdef TARGET_X86_64
4744 if (dflag == 2) {
bellarde108dd02008-05-17 19:24:07 +00004745 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4746 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4747 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
bellard14ce26e2005-01-03 23:50:08 +00004748 } else
4749#endif
bellarde108dd02008-05-17 19:24:07 +00004750 if (dflag == 1) {
4751 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4752 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4753 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4754 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4755 } else {
4756 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4757 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4758 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4759 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4760 }
bellard2c0262a2003-09-30 20:34:21 +00004761 break;
4762 case 0x1af: /* imul Gv, Ev */
4763 case 0x69: /* imul Gv, Ev, I */
4764 case 0x6b:
bellard14ce26e2005-01-03 23:50:08 +00004765 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00004766 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00004767 reg = ((modrm >> 3) & 7) | rex_r;
4768 if (b == 0x69)
4769 s->rip_offset = insn_const_size(ot);
4770 else if (b == 0x6b)
4771 s->rip_offset = 1;
bellard2c0262a2003-09-30 20:34:21 +00004772 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4773 if (b == 0x69) {
4774 val = insn_get(s, ot);
4775 gen_op_movl_T1_im(val);
4776 } else if (b == 0x6b) {
bellardd64477a2004-04-22 21:34:25 +00004777 val = (int8_t)insn_get(s, OT_BYTE);
bellard2c0262a2003-09-30 20:34:21 +00004778 gen_op_movl_T1_im(val);
4779 } else {
bellard57fec1f2008-02-01 10:50:11 +00004780 gen_op_mov_TN_reg(ot, 1, reg);
bellard2c0262a2003-09-30 20:34:21 +00004781 }
4782
bellard14ce26e2005-01-03 23:50:08 +00004783#ifdef TARGET_X86_64
4784 if (ot == OT_QUAD) {
pbrooka7812ae2008-11-17 14:43:54 +00004785 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
bellard14ce26e2005-01-03 23:50:08 +00004786 } else
4787#endif
bellard2c0262a2003-09-30 20:34:21 +00004788 if (ot == OT_LONG) {
bellard0211e5a2008-05-21 10:12:54 +00004789#ifdef TARGET_X86_64
4790 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4791 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4792 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4793 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4794 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4795 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4796#else
4797 {
pbrooka7812ae2008-11-17 14:43:54 +00004798 TCGv_i64 t0, t1;
4799 t0 = tcg_temp_new_i64();
4800 t1 = tcg_temp_new_i64();
bellard0211e5a2008-05-21 10:12:54 +00004801 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4802 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4803 tcg_gen_mul_i64(t0, t0, t1);
4804 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4805 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4806 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4807 tcg_gen_shri_i64(t0, t0, 32);
4808 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4809 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4810 }
4811#endif
bellard2c0262a2003-09-30 20:34:21 +00004812 } else {
bellard0211e5a2008-05-21 10:12:54 +00004813 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4814 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4815 /* XXX: use 32 bit mul which could be faster */
4816 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4817 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4818 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4819 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
bellard2c0262a2003-09-30 20:34:21 +00004820 }
bellard57fec1f2008-02-01 10:50:11 +00004821 gen_op_mov_reg_T0(ot, reg);
bellardd36cd602003-12-02 22:01:31 +00004822 s->cc_op = CC_OP_MULB + ot;
bellard2c0262a2003-09-30 20:34:21 +00004823 break;
4824 case 0x1c0:
4825 case 0x1c1: /* xadd Ev, Gv */
4826 if ((b & 1) == 0)
4827 ot = OT_BYTE;
4828 else
bellard14ce26e2005-01-03 23:50:08 +00004829 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00004830 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00004831 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00004832 mod = (modrm >> 6) & 3;
4833 if (mod == 3) {
bellard14ce26e2005-01-03 23:50:08 +00004834 rm = (modrm & 7) | REX_B(s);
bellard57fec1f2008-02-01 10:50:11 +00004835 gen_op_mov_TN_reg(ot, 0, reg);
4836 gen_op_mov_TN_reg(ot, 1, rm);
bellard2c0262a2003-09-30 20:34:21 +00004837 gen_op_addl_T0_T1();
bellard57fec1f2008-02-01 10:50:11 +00004838 gen_op_mov_reg_T1(ot, reg);
4839 gen_op_mov_reg_T0(ot, rm);
bellard2c0262a2003-09-30 20:34:21 +00004840 } else {
4841 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00004842 gen_op_mov_TN_reg(ot, 0, reg);
4843 gen_op_ld_T1_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00004844 gen_op_addl_T0_T1();
bellard57fec1f2008-02-01 10:50:11 +00004845 gen_op_st_T0_A0(ot + s->mem_index);
4846 gen_op_mov_reg_T1(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00004847 }
4848 gen_op_update2_cc();
4849 s->cc_op = CC_OP_ADDB + ot;
4850 break;
4851 case 0x1b0:
4852 case 0x1b1: /* cmpxchg Ev, Gv */
bellardcad3a372008-05-17 13:50:02 +00004853 {
bellard11303282008-05-22 09:36:08 +00004854 int label1, label2;
bellard1e4840b2008-05-25 17:26:41 +00004855 TCGv t0, t1, t2, a0;
bellardcad3a372008-05-17 13:50:02 +00004856
4857 if ((b & 1) == 0)
4858 ot = OT_BYTE;
4859 else
4860 ot = dflag + OT_WORD;
4861 modrm = ldub_code(s->pc++);
4862 reg = ((modrm >> 3) & 7) | rex_r;
4863 mod = (modrm >> 6) & 3;
pbrooka7812ae2008-11-17 14:43:54 +00004864 t0 = tcg_temp_local_new();
4865 t1 = tcg_temp_local_new();
4866 t2 = tcg_temp_local_new();
4867 a0 = tcg_temp_local_new();
bellard1e4840b2008-05-25 17:26:41 +00004868 gen_op_mov_v_reg(ot, t1, reg);
bellardcad3a372008-05-17 13:50:02 +00004869 if (mod == 3) {
4870 rm = (modrm & 7) | REX_B(s);
bellard1e4840b2008-05-25 17:26:41 +00004871 gen_op_mov_v_reg(ot, t0, rm);
bellardcad3a372008-05-17 13:50:02 +00004872 } else {
4873 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard1e4840b2008-05-25 17:26:41 +00004874 tcg_gen_mov_tl(a0, cpu_A0);
4875 gen_op_ld_v(ot + s->mem_index, t0, a0);
bellardcad3a372008-05-17 13:50:02 +00004876 rm = 0; /* avoid warning */
4877 }
4878 label1 = gen_new_label();
Laurent Desnoguescc739bb2009-09-29 11:58:04 +02004879 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
bellard1e4840b2008-05-25 17:26:41 +00004880 gen_extu(ot, t2);
4881 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
bellardcad3a372008-05-17 13:50:02 +00004882 if (mod == 3) {
bellard11303282008-05-22 09:36:08 +00004883 label2 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00004884 gen_op_mov_reg_v(ot, R_EAX, t0);
bellard11303282008-05-22 09:36:08 +00004885 tcg_gen_br(label2);
4886 gen_set_label(label1);
bellard1e4840b2008-05-25 17:26:41 +00004887 gen_op_mov_reg_v(ot, rm, t1);
bellard11303282008-05-22 09:36:08 +00004888 gen_set_label(label2);
bellardcad3a372008-05-17 13:50:02 +00004889 } else {
bellard1e4840b2008-05-25 17:26:41 +00004890 tcg_gen_mov_tl(t1, t0);
4891 gen_op_mov_reg_v(ot, R_EAX, t0);
bellard11303282008-05-22 09:36:08 +00004892 gen_set_label(label1);
4893 /* always store */
bellard1e4840b2008-05-25 17:26:41 +00004894 gen_op_st_v(ot + s->mem_index, t1, a0);
bellardcad3a372008-05-17 13:50:02 +00004895 }
bellard1e4840b2008-05-25 17:26:41 +00004896 tcg_gen_mov_tl(cpu_cc_src, t0);
4897 tcg_gen_mov_tl(cpu_cc_dst, t2);
bellardcad3a372008-05-17 13:50:02 +00004898 s->cc_op = CC_OP_SUBB + ot;
bellard1e4840b2008-05-25 17:26:41 +00004899 tcg_temp_free(t0);
4900 tcg_temp_free(t1);
4901 tcg_temp_free(t2);
4902 tcg_temp_free(a0);
bellard2c0262a2003-09-30 20:34:21 +00004903 }
bellard2c0262a2003-09-30 20:34:21 +00004904 break;
4905 case 0x1c7: /* cmpxchg8b */
bellard61382a52003-10-27 21:22:23 +00004906 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00004907 mod = (modrm >> 6) & 3;
balrog71c35582007-12-24 13:29:55 +00004908 if ((mod == 3) || ((modrm & 0x38) != 0x8))
bellard2c0262a2003-09-30 20:34:21 +00004909 goto illegal_op;
bellard1b9d9eb2008-05-22 09:52:38 +00004910#ifdef TARGET_X86_64
4911 if (dflag == 2) {
4912 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4913 goto illegal_op;
4914 gen_jmp_im(pc_start - s->cs_base);
4915 if (s->cc_op != CC_OP_DYNAMIC)
4916 gen_op_set_cc_op(s->cc_op);
4917 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
pbrooka7812ae2008-11-17 14:43:54 +00004918 gen_helper_cmpxchg16b(cpu_A0);
bellard1b9d9eb2008-05-22 09:52:38 +00004919 } else
4920#endif
4921 {
4922 if (!(s->cpuid_features & CPUID_CX8))
4923 goto illegal_op;
4924 gen_jmp_im(pc_start - s->cs_base);
4925 if (s->cc_op != CC_OP_DYNAMIC)
4926 gen_op_set_cc_op(s->cc_op);
4927 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
pbrooka7812ae2008-11-17 14:43:54 +00004928 gen_helper_cmpxchg8b(cpu_A0);
bellard1b9d9eb2008-05-22 09:52:38 +00004929 }
bellard2c0262a2003-09-30 20:34:21 +00004930 s->cc_op = CC_OP_EFLAGS;
4931 break;
ths3b46e622007-09-17 08:09:54 +00004932
bellard2c0262a2003-09-30 20:34:21 +00004933 /**************************/
4934 /* push/pop */
4935 case 0x50 ... 0x57: /* push */
bellard57fec1f2008-02-01 10:50:11 +00004936 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
bellard2c0262a2003-09-30 20:34:21 +00004937 gen_push_T0(s);
4938 break;
4939 case 0x58 ... 0x5f: /* pop */
bellard14ce26e2005-01-03 23:50:08 +00004940 if (CODE64(s)) {
4941 ot = dflag ? OT_QUAD : OT_WORD;
4942 } else {
4943 ot = dflag + OT_WORD;
4944 }
bellard2c0262a2003-09-30 20:34:21 +00004945 gen_pop_T0(s);
bellard77729c22003-11-13 23:09:07 +00004946 /* NOTE: order is important for pop %sp */
bellard2c0262a2003-09-30 20:34:21 +00004947 gen_pop_update(s);
bellard57fec1f2008-02-01 10:50:11 +00004948 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
bellard2c0262a2003-09-30 20:34:21 +00004949 break;
4950 case 0x60: /* pusha */
bellard14ce26e2005-01-03 23:50:08 +00004951 if (CODE64(s))
4952 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00004953 gen_pusha(s);
4954 break;
4955 case 0x61: /* popa */
bellard14ce26e2005-01-03 23:50:08 +00004956 if (CODE64(s))
4957 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00004958 gen_popa(s);
4959 break;
4960 case 0x68: /* push Iv */
4961 case 0x6a:
bellard14ce26e2005-01-03 23:50:08 +00004962 if (CODE64(s)) {
4963 ot = dflag ? OT_QUAD : OT_WORD;
4964 } else {
4965 ot = dflag + OT_WORD;
4966 }
bellard2c0262a2003-09-30 20:34:21 +00004967 if (b == 0x68)
4968 val = insn_get(s, ot);
4969 else
4970 val = (int8_t)insn_get(s, OT_BYTE);
4971 gen_op_movl_T0_im(val);
4972 gen_push_T0(s);
4973 break;
4974 case 0x8f: /* pop Ev */
bellard14ce26e2005-01-03 23:50:08 +00004975 if (CODE64(s)) {
4976 ot = dflag ? OT_QUAD : OT_WORD;
4977 } else {
4978 ot = dflag + OT_WORD;
4979 }
bellard61382a52003-10-27 21:22:23 +00004980 modrm = ldub_code(s->pc++);
bellard77729c22003-11-13 23:09:07 +00004981 mod = (modrm >> 6) & 3;
bellard2c0262a2003-09-30 20:34:21 +00004982 gen_pop_T0(s);
bellard77729c22003-11-13 23:09:07 +00004983 if (mod == 3) {
4984 /* NOTE: order is important for pop %sp */
4985 gen_pop_update(s);
bellard14ce26e2005-01-03 23:50:08 +00004986 rm = (modrm & 7) | REX_B(s);
bellard57fec1f2008-02-01 10:50:11 +00004987 gen_op_mov_reg_T0(ot, rm);
bellard77729c22003-11-13 23:09:07 +00004988 } else {
4989 /* NOTE: order is important too for MMU exceptions */
bellard14ce26e2005-01-03 23:50:08 +00004990 s->popl_esp_hack = 1 << ot;
bellard77729c22003-11-13 23:09:07 +00004991 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4992 s->popl_esp_hack = 0;
4993 gen_pop_update(s);
4994 }
bellard2c0262a2003-09-30 20:34:21 +00004995 break;
4996 case 0xc8: /* enter */
4997 {
4998 int level;
bellard61382a52003-10-27 21:22:23 +00004999 val = lduw_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00005000 s->pc += 2;
bellard61382a52003-10-27 21:22:23 +00005001 level = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005002 gen_enter(s, val, level);
5003 }
5004 break;
5005 case 0xc9: /* leave */
5006 /* XXX: exception not precise (ESP is updated before potential exception) */
bellard14ce26e2005-01-03 23:50:08 +00005007 if (CODE64(s)) {
bellard57fec1f2008-02-01 10:50:11 +00005008 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5009 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
bellard14ce26e2005-01-03 23:50:08 +00005010 } else if (s->ss32) {
bellard57fec1f2008-02-01 10:50:11 +00005011 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5012 gen_op_mov_reg_T0(OT_LONG, R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00005013 } else {
bellard57fec1f2008-02-01 10:50:11 +00005014 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5015 gen_op_mov_reg_T0(OT_WORD, R_ESP);
bellard2c0262a2003-09-30 20:34:21 +00005016 }
5017 gen_pop_T0(s);
bellard14ce26e2005-01-03 23:50:08 +00005018 if (CODE64(s)) {
5019 ot = dflag ? OT_QUAD : OT_WORD;
5020 } else {
5021 ot = dflag + OT_WORD;
5022 }
bellard57fec1f2008-02-01 10:50:11 +00005023 gen_op_mov_reg_T0(ot, R_EBP);
bellard2c0262a2003-09-30 20:34:21 +00005024 gen_pop_update(s);
5025 break;
5026 case 0x06: /* push es */
5027 case 0x0e: /* push cs */
5028 case 0x16: /* push ss */
5029 case 0x1e: /* push ds */
bellard14ce26e2005-01-03 23:50:08 +00005030 if (CODE64(s))
5031 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00005032 gen_op_movl_T0_seg(b >> 3);
5033 gen_push_T0(s);
5034 break;
5035 case 0x1a0: /* push fs */
5036 case 0x1a8: /* push gs */
5037 gen_op_movl_T0_seg((b >> 3) & 7);
5038 gen_push_T0(s);
5039 break;
5040 case 0x07: /* pop es */
5041 case 0x17: /* pop ss */
5042 case 0x1f: /* pop ds */
bellard14ce26e2005-01-03 23:50:08 +00005043 if (CODE64(s))
5044 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00005045 reg = b >> 3;
5046 gen_pop_T0(s);
5047 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5048 gen_pop_update(s);
5049 if (reg == R_SS) {
bellarda2cc3b22003-11-19 22:08:13 +00005050 /* if reg == SS, inhibit interrupts/trace. */
5051 /* If several instructions disable interrupts, only the
5052 _first_ does it */
5053 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
pbrooka7812ae2008-11-17 14:43:54 +00005054 gen_helper_set_inhibit_irq();
bellard2c0262a2003-09-30 20:34:21 +00005055 s->tf = 0;
5056 }
5057 if (s->is_jmp) {
bellard14ce26e2005-01-03 23:50:08 +00005058 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00005059 gen_eob(s);
5060 }
5061 break;
5062 case 0x1a1: /* pop fs */
5063 case 0x1a9: /* pop gs */
5064 gen_pop_T0(s);
5065 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5066 gen_pop_update(s);
5067 if (s->is_jmp) {
bellard14ce26e2005-01-03 23:50:08 +00005068 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00005069 gen_eob(s);
5070 }
5071 break;
5072
5073 /**************************/
5074 /* mov */
5075 case 0x88:
5076 case 0x89: /* mov Gv, Ev */
5077 if ((b & 1) == 0)
5078 ot = OT_BYTE;
5079 else
bellard14ce26e2005-01-03 23:50:08 +00005080 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00005081 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00005082 reg = ((modrm >> 3) & 7) | rex_r;
ths3b46e622007-09-17 08:09:54 +00005083
bellard2c0262a2003-09-30 20:34:21 +00005084 /* generate a generic store */
bellard14ce26e2005-01-03 23:50:08 +00005085 gen_ldst_modrm(s, modrm, ot, reg, 1);
bellard2c0262a2003-09-30 20:34:21 +00005086 break;
5087 case 0xc6:
5088 case 0xc7: /* mov Ev, Iv */
5089 if ((b & 1) == 0)
5090 ot = OT_BYTE;
5091 else
bellard14ce26e2005-01-03 23:50:08 +00005092 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00005093 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005094 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00005095 if (mod != 3) {
5096 s->rip_offset = insn_const_size(ot);
bellard2c0262a2003-09-30 20:34:21 +00005097 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard14ce26e2005-01-03 23:50:08 +00005098 }
bellard2c0262a2003-09-30 20:34:21 +00005099 val = insn_get(s, ot);
5100 gen_op_movl_T0_im(val);
5101 if (mod != 3)
bellard57fec1f2008-02-01 10:50:11 +00005102 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005103 else
bellard57fec1f2008-02-01 10:50:11 +00005104 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
bellard2c0262a2003-09-30 20:34:21 +00005105 break;
5106 case 0x8a:
5107 case 0x8b: /* mov Ev, Gv */
5108 if ((b & 1) == 0)
5109 ot = OT_BYTE;
5110 else
bellard14ce26e2005-01-03 23:50:08 +00005111 ot = OT_WORD + dflag;
bellard61382a52003-10-27 21:22:23 +00005112 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00005113 reg = ((modrm >> 3) & 7) | rex_r;
ths3b46e622007-09-17 08:09:54 +00005114
bellard2c0262a2003-09-30 20:34:21 +00005115 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
bellard57fec1f2008-02-01 10:50:11 +00005116 gen_op_mov_reg_T0(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00005117 break;
5118 case 0x8e: /* mov seg, Gv */
bellard61382a52003-10-27 21:22:23 +00005119 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005120 reg = (modrm >> 3) & 7;
5121 if (reg >= 6 || reg == R_CS)
5122 goto illegal_op;
5123 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5124 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5125 if (reg == R_SS) {
5126 /* if reg == SS, inhibit interrupts/trace */
bellarda2cc3b22003-11-19 22:08:13 +00005127 /* If several instructions disable interrupts, only the
5128 _first_ does it */
5129 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
pbrooka7812ae2008-11-17 14:43:54 +00005130 gen_helper_set_inhibit_irq();
bellard2c0262a2003-09-30 20:34:21 +00005131 s->tf = 0;
5132 }
5133 if (s->is_jmp) {
bellard14ce26e2005-01-03 23:50:08 +00005134 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00005135 gen_eob(s);
5136 }
5137 break;
5138 case 0x8c: /* mov Gv, seg */
bellard61382a52003-10-27 21:22:23 +00005139 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005140 reg = (modrm >> 3) & 7;
5141 mod = (modrm >> 6) & 3;
5142 if (reg >= 6)
5143 goto illegal_op;
5144 gen_op_movl_T0_seg(reg);
bellard14ce26e2005-01-03 23:50:08 +00005145 if (mod == 3)
5146 ot = OT_WORD + dflag;
5147 else
5148 ot = OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00005149 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5150 break;
5151
5152 case 0x1b6: /* movzbS Gv, Eb */
5153 case 0x1b7: /* movzwS Gv, Eb */
5154 case 0x1be: /* movsbS Gv, Eb */
5155 case 0x1bf: /* movswS Gv, Eb */
5156 {
5157 int d_ot;
5158 /* d_ot is the size of destination */
5159 d_ot = dflag + OT_WORD;
5160 /* ot is the size of source */
5161 ot = (b & 1) + OT_BYTE;
bellard61382a52003-10-27 21:22:23 +00005162 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00005163 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00005164 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00005165 rm = (modrm & 7) | REX_B(s);
ths3b46e622007-09-17 08:09:54 +00005166
bellard2c0262a2003-09-30 20:34:21 +00005167 if (mod == 3) {
bellard57fec1f2008-02-01 10:50:11 +00005168 gen_op_mov_TN_reg(ot, 0, rm);
bellard2c0262a2003-09-30 20:34:21 +00005169 switch(ot | (b & 8)) {
5170 case OT_BYTE:
bellarde108dd02008-05-17 19:24:07 +00005171 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00005172 break;
5173 case OT_BYTE | 8:
bellarde108dd02008-05-17 19:24:07 +00005174 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00005175 break;
5176 case OT_WORD:
bellarde108dd02008-05-17 19:24:07 +00005177 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00005178 break;
5179 default:
5180 case OT_WORD | 8:
bellarde108dd02008-05-17 19:24:07 +00005181 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00005182 break;
5183 }
bellard57fec1f2008-02-01 10:50:11 +00005184 gen_op_mov_reg_T0(d_ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00005185 } else {
5186 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5187 if (b & 8) {
bellard57fec1f2008-02-01 10:50:11 +00005188 gen_op_lds_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005189 } else {
bellard57fec1f2008-02-01 10:50:11 +00005190 gen_op_ldu_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005191 }
bellard57fec1f2008-02-01 10:50:11 +00005192 gen_op_mov_reg_T0(d_ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00005193 }
5194 }
5195 break;
5196
5197 case 0x8d: /* lea */
bellard14ce26e2005-01-03 23:50:08 +00005198 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00005199 modrm = ldub_code(s->pc++);
bellard3a1d9b82004-02-16 22:10:33 +00005200 mod = (modrm >> 6) & 3;
5201 if (mod == 3)
5202 goto illegal_op;
bellard14ce26e2005-01-03 23:50:08 +00005203 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00005204 /* we must ensure that no segment is added */
5205 s->override = -1;
5206 val = s->addseg;
5207 s->addseg = 0;
5208 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5209 s->addseg = val;
bellard57fec1f2008-02-01 10:50:11 +00005210 gen_op_mov_reg_A0(ot - OT_WORD, reg);
bellard2c0262a2003-09-30 20:34:21 +00005211 break;
ths3b46e622007-09-17 08:09:54 +00005212
bellard2c0262a2003-09-30 20:34:21 +00005213 case 0xa0: /* mov EAX, Ov */
5214 case 0xa1:
5215 case 0xa2: /* mov Ov, EAX */
5216 case 0xa3:
bellard2c0262a2003-09-30 20:34:21 +00005217 {
bellard14ce26e2005-01-03 23:50:08 +00005218 target_ulong offset_addr;
5219
5220 if ((b & 1) == 0)
5221 ot = OT_BYTE;
5222 else
5223 ot = dflag + OT_WORD;
5224#ifdef TARGET_X86_64
bellard8f091a52005-07-23 17:41:26 +00005225 if (s->aflag == 2) {
bellard14ce26e2005-01-03 23:50:08 +00005226 offset_addr = ldq_code(s->pc);
5227 s->pc += 8;
bellard57fec1f2008-02-01 10:50:11 +00005228 gen_op_movq_A0_im(offset_addr);
ths5fafdf22007-09-16 21:08:06 +00005229 } else
bellard14ce26e2005-01-03 23:50:08 +00005230#endif
5231 {
5232 if (s->aflag) {
5233 offset_addr = insn_get(s, OT_LONG);
5234 } else {
5235 offset_addr = insn_get(s, OT_WORD);
5236 }
5237 gen_op_movl_A0_im(offset_addr);
5238 }
bellard664e0f12005-01-08 18:58:29 +00005239 gen_add_A0_ds_seg(s);
bellard14ce26e2005-01-03 23:50:08 +00005240 if ((b & 2) == 0) {
bellard57fec1f2008-02-01 10:50:11 +00005241 gen_op_ld_T0_A0(ot + s->mem_index);
5242 gen_op_mov_reg_T0(ot, R_EAX);
bellard2c0262a2003-09-30 20:34:21 +00005243 } else {
bellard57fec1f2008-02-01 10:50:11 +00005244 gen_op_mov_TN_reg(ot, 0, R_EAX);
5245 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005246 }
bellard2c0262a2003-09-30 20:34:21 +00005247 }
5248 break;
5249 case 0xd7: /* xlat */
bellard14ce26e2005-01-03 23:50:08 +00005250#ifdef TARGET_X86_64
bellard8f091a52005-07-23 17:41:26 +00005251 if (s->aflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +00005252 gen_op_movq_A0_reg(R_EBX);
bellardbbf662e2008-05-17 19:05:28 +00005253 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5254 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5255 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
ths5fafdf22007-09-16 21:08:06 +00005256 } else
bellard14ce26e2005-01-03 23:50:08 +00005257#endif
5258 {
bellard57fec1f2008-02-01 10:50:11 +00005259 gen_op_movl_A0_reg(R_EBX);
bellardbbf662e2008-05-17 19:05:28 +00005260 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5261 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5262 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00005263 if (s->aflag == 0)
5264 gen_op_andl_A0_ffff();
bellardbbf662e2008-05-17 19:05:28 +00005265 else
5266 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
bellard14ce26e2005-01-03 23:50:08 +00005267 }
bellard664e0f12005-01-08 18:58:29 +00005268 gen_add_A0_ds_seg(s);
bellard57fec1f2008-02-01 10:50:11 +00005269 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5270 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
bellard2c0262a2003-09-30 20:34:21 +00005271 break;
5272 case 0xb0 ... 0xb7: /* mov R, Ib */
5273 val = insn_get(s, OT_BYTE);
5274 gen_op_movl_T0_im(val);
bellard57fec1f2008-02-01 10:50:11 +00005275 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
bellard2c0262a2003-09-30 20:34:21 +00005276 break;
5277 case 0xb8 ... 0xbf: /* mov R, Iv */
bellard14ce26e2005-01-03 23:50:08 +00005278#ifdef TARGET_X86_64
5279 if (dflag == 2) {
5280 uint64_t tmp;
5281 /* 64 bit case */
5282 tmp = ldq_code(s->pc);
5283 s->pc += 8;
5284 reg = (b & 7) | REX_B(s);
5285 gen_movtl_T0_im(tmp);
bellard57fec1f2008-02-01 10:50:11 +00005286 gen_op_mov_reg_T0(OT_QUAD, reg);
ths5fafdf22007-09-16 21:08:06 +00005287 } else
bellard14ce26e2005-01-03 23:50:08 +00005288#endif
5289 {
5290 ot = dflag ? OT_LONG : OT_WORD;
5291 val = insn_get(s, ot);
5292 reg = (b & 7) | REX_B(s);
5293 gen_op_movl_T0_im(val);
bellard57fec1f2008-02-01 10:50:11 +00005294 gen_op_mov_reg_T0(ot, reg);
bellard14ce26e2005-01-03 23:50:08 +00005295 }
bellard2c0262a2003-09-30 20:34:21 +00005296 break;
5297
5298 case 0x91 ... 0x97: /* xchg R, EAX */
Richard Henderson74180272010-07-01 09:42:21 -07005299 do_xchg_reg_eax:
bellard14ce26e2005-01-03 23:50:08 +00005300 ot = dflag + OT_WORD;
5301 reg = (b & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00005302 rm = R_EAX;
5303 goto do_xchg_reg;
5304 case 0x86:
5305 case 0x87: /* xchg Ev, Gv */
5306 if ((b & 1) == 0)
5307 ot = OT_BYTE;
5308 else
bellard14ce26e2005-01-03 23:50:08 +00005309 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00005310 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00005311 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00005312 mod = (modrm >> 6) & 3;
5313 if (mod == 3) {
bellard14ce26e2005-01-03 23:50:08 +00005314 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00005315 do_xchg_reg:
bellard57fec1f2008-02-01 10:50:11 +00005316 gen_op_mov_TN_reg(ot, 0, reg);
5317 gen_op_mov_TN_reg(ot, 1, rm);
5318 gen_op_mov_reg_T0(ot, rm);
5319 gen_op_mov_reg_T1(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00005320 } else {
5321 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00005322 gen_op_mov_TN_reg(ot, 0, reg);
bellard2c0262a2003-09-30 20:34:21 +00005323 /* for xchg, lock is implicit */
5324 if (!(prefixes & PREFIX_LOCK))
pbrooka7812ae2008-11-17 14:43:54 +00005325 gen_helper_lock();
bellard57fec1f2008-02-01 10:50:11 +00005326 gen_op_ld_T1_A0(ot + s->mem_index);
5327 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005328 if (!(prefixes & PREFIX_LOCK))
pbrooka7812ae2008-11-17 14:43:54 +00005329 gen_helper_unlock();
bellard57fec1f2008-02-01 10:50:11 +00005330 gen_op_mov_reg_T1(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00005331 }
5332 break;
5333 case 0xc4: /* les Gv */
bellard14ce26e2005-01-03 23:50:08 +00005334 if (CODE64(s))
5335 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00005336 op = R_ES;
5337 goto do_lxx;
5338 case 0xc5: /* lds Gv */
bellard14ce26e2005-01-03 23:50:08 +00005339 if (CODE64(s))
5340 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00005341 op = R_DS;
5342 goto do_lxx;
5343 case 0x1b2: /* lss Gv */
5344 op = R_SS;
5345 goto do_lxx;
5346 case 0x1b4: /* lfs Gv */
5347 op = R_FS;
5348 goto do_lxx;
5349 case 0x1b5: /* lgs Gv */
5350 op = R_GS;
5351 do_lxx:
5352 ot = dflag ? OT_LONG : OT_WORD;
bellard61382a52003-10-27 21:22:23 +00005353 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00005354 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00005355 mod = (modrm >> 6) & 3;
5356 if (mod == 3)
5357 goto illegal_op;
5358 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00005359 gen_op_ld_T1_A0(ot + s->mem_index);
bellardaba9d612005-04-23 17:53:12 +00005360 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
bellard2c0262a2003-09-30 20:34:21 +00005361 /* load the segment first to handle exceptions properly */
bellard57fec1f2008-02-01 10:50:11 +00005362 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005363 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5364 /* then put the data */
bellard57fec1f2008-02-01 10:50:11 +00005365 gen_op_mov_reg_T1(ot, reg);
bellard2c0262a2003-09-30 20:34:21 +00005366 if (s->is_jmp) {
bellard14ce26e2005-01-03 23:50:08 +00005367 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00005368 gen_eob(s);
5369 }
5370 break;
ths3b46e622007-09-17 08:09:54 +00005371
bellard2c0262a2003-09-30 20:34:21 +00005372 /************************/
5373 /* shifts */
5374 case 0xc0:
5375 case 0xc1:
5376 /* shift Ev,Ib */
5377 shift = 2;
5378 grp2:
5379 {
5380 if ((b & 1) == 0)
5381 ot = OT_BYTE;
5382 else
bellard14ce26e2005-01-03 23:50:08 +00005383 ot = dflag + OT_WORD;
ths3b46e622007-09-17 08:09:54 +00005384
bellard61382a52003-10-27 21:22:23 +00005385 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005386 mod = (modrm >> 6) & 3;
bellard2c0262a2003-09-30 20:34:21 +00005387 op = (modrm >> 3) & 7;
ths3b46e622007-09-17 08:09:54 +00005388
bellard2c0262a2003-09-30 20:34:21 +00005389 if (mod != 3) {
bellard14ce26e2005-01-03 23:50:08 +00005390 if (shift == 2) {
5391 s->rip_offset = 1;
5392 }
bellard2c0262a2003-09-30 20:34:21 +00005393 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5394 opreg = OR_TMP0;
5395 } else {
bellard14ce26e2005-01-03 23:50:08 +00005396 opreg = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00005397 }
5398
5399 /* simpler op */
5400 if (shift == 0) {
5401 gen_shift(s, op, ot, opreg, OR_ECX);
5402 } else {
5403 if (shift == 2) {
bellard61382a52003-10-27 21:22:23 +00005404 shift = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005405 }
5406 gen_shifti(s, op, ot, opreg, shift);
5407 }
5408 }
5409 break;
5410 case 0xd0:
5411 case 0xd1:
5412 /* shift Ev,1 */
5413 shift = 1;
5414 goto grp2;
5415 case 0xd2:
5416 case 0xd3:
5417 /* shift Ev,cl */
5418 shift = 0;
5419 goto grp2;
5420
5421 case 0x1a4: /* shld imm */
5422 op = 0;
5423 shift = 1;
5424 goto do_shiftd;
5425 case 0x1a5: /* shld cl */
5426 op = 0;
5427 shift = 0;
5428 goto do_shiftd;
5429 case 0x1ac: /* shrd imm */
5430 op = 1;
5431 shift = 1;
5432 goto do_shiftd;
5433 case 0x1ad: /* shrd cl */
5434 op = 1;
5435 shift = 0;
5436 do_shiftd:
bellard14ce26e2005-01-03 23:50:08 +00005437 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00005438 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005439 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00005440 rm = (modrm & 7) | REX_B(s);
5441 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00005442 if (mod != 3) {
5443 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellardb6abf972008-05-17 12:44:31 +00005444 opreg = OR_TMP0;
bellard2c0262a2003-09-30 20:34:21 +00005445 } else {
bellardb6abf972008-05-17 12:44:31 +00005446 opreg = rm;
bellard2c0262a2003-09-30 20:34:21 +00005447 }
bellard57fec1f2008-02-01 10:50:11 +00005448 gen_op_mov_TN_reg(ot, 1, reg);
ths3b46e622007-09-17 08:09:54 +00005449
bellard2c0262a2003-09-30 20:34:21 +00005450 if (shift) {
bellard61382a52003-10-27 21:22:23 +00005451 val = ldub_code(s->pc++);
bellardb6abf972008-05-17 12:44:31 +00005452 tcg_gen_movi_tl(cpu_T3, val);
bellard2c0262a2003-09-30 20:34:21 +00005453 } else {
Laurent Desnoguescc739bb2009-09-29 11:58:04 +02005454 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
bellard2c0262a2003-09-30 20:34:21 +00005455 }
bellardb6abf972008-05-17 12:44:31 +00005456 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
bellard2c0262a2003-09-30 20:34:21 +00005457 break;
5458
5459 /************************/
5460 /* floats */
ths5fafdf22007-09-16 21:08:06 +00005461 case 0xd8 ... 0xdf:
bellard7eee2a52004-02-25 23:17:58 +00005462 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5463 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5464 /* XXX: what to do if illegal op ? */
5465 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5466 break;
5467 }
bellard61382a52003-10-27 21:22:23 +00005468 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00005469 mod = (modrm >> 6) & 3;
5470 rm = modrm & 7;
5471 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
bellard2c0262a2003-09-30 20:34:21 +00005472 if (mod != 3) {
5473 /* memory op */
5474 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5475 switch(op) {
5476 case 0x00 ... 0x07: /* fxxxs */
5477 case 0x10 ... 0x17: /* fixxxl */
5478 case 0x20 ... 0x27: /* fxxxl */
5479 case 0x30 ... 0x37: /* fixxx */
5480 {
5481 int op1;
5482 op1 = op & 7;
5483
5484 switch(op >> 4) {
5485 case 0:
bellardba7cd152008-05-12 20:30:28 +00005486 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005487 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005488 gen_helper_flds_FT0(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005489 break;
5490 case 1:
bellardba7cd152008-05-12 20:30:28 +00005491 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005492 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005493 gen_helper_fildl_FT0(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005494 break;
5495 case 2:
bellardb6abf972008-05-17 12:44:31 +00005496 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
bellard19e6c4b2008-05-12 19:10:44 +00005497 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00005498 gen_helper_fldl_FT0(cpu_tmp1_i64);
bellard2c0262a2003-09-30 20:34:21 +00005499 break;
5500 case 3:
5501 default:
bellardba7cd152008-05-12 20:30:28 +00005502 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005503 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005504 gen_helper_fildl_FT0(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005505 break;
5506 }
ths3b46e622007-09-17 08:09:54 +00005507
pbrooka7812ae2008-11-17 14:43:54 +00005508 gen_helper_fp_arith_ST0_FT0(op1);
bellard2c0262a2003-09-30 20:34:21 +00005509 if (op1 == 3) {
5510 /* fcomp needs pop */
pbrooka7812ae2008-11-17 14:43:54 +00005511 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005512 }
5513 }
5514 break;
5515 case 0x08: /* flds */
5516 case 0x0a: /* fsts */
5517 case 0x0b: /* fstps */
bellard465e9832006-04-23 21:54:01 +00005518 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5519 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5520 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
bellard2c0262a2003-09-30 20:34:21 +00005521 switch(op & 7) {
5522 case 0:
5523 switch(op >> 4) {
5524 case 0:
bellardba7cd152008-05-12 20:30:28 +00005525 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005526 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005527 gen_helper_flds_ST0(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005528 break;
5529 case 1:
bellardba7cd152008-05-12 20:30:28 +00005530 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005531 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005532 gen_helper_fildl_ST0(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005533 break;
5534 case 2:
bellardb6abf972008-05-17 12:44:31 +00005535 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
bellard19e6c4b2008-05-12 19:10:44 +00005536 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00005537 gen_helper_fldl_ST0(cpu_tmp1_i64);
bellard2c0262a2003-09-30 20:34:21 +00005538 break;
5539 case 3:
5540 default:
bellardba7cd152008-05-12 20:30:28 +00005541 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005542 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005543 gen_helper_fildl_ST0(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005544 break;
5545 }
5546 break;
bellard465e9832006-04-23 21:54:01 +00005547 case 1:
bellard19e6c4b2008-05-12 19:10:44 +00005548 /* XXX: the corresponding CPUID bit must be tested ! */
bellard465e9832006-04-23 21:54:01 +00005549 switch(op >> 4) {
5550 case 1:
pbrooka7812ae2008-11-17 14:43:54 +00005551 gen_helper_fisttl_ST0(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005552 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellardba7cd152008-05-12 20:30:28 +00005553 gen_op_st_T0_A0(OT_LONG + s->mem_index);
bellard465e9832006-04-23 21:54:01 +00005554 break;
5555 case 2:
pbrooka7812ae2008-11-17 14:43:54 +00005556 gen_helper_fisttll_ST0(cpu_tmp1_i64);
bellardb6abf972008-05-17 12:44:31 +00005557 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
bellard19e6c4b2008-05-12 19:10:44 +00005558 (s->mem_index >> 2) - 1);
bellard465e9832006-04-23 21:54:01 +00005559 break;
5560 case 3:
5561 default:
pbrooka7812ae2008-11-17 14:43:54 +00005562 gen_helper_fistt_ST0(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005563 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellardba7cd152008-05-12 20:30:28 +00005564 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard19e6c4b2008-05-12 19:10:44 +00005565 break;
bellard465e9832006-04-23 21:54:01 +00005566 }
pbrooka7812ae2008-11-17 14:43:54 +00005567 gen_helper_fpop();
bellard465e9832006-04-23 21:54:01 +00005568 break;
bellard2c0262a2003-09-30 20:34:21 +00005569 default:
5570 switch(op >> 4) {
5571 case 0:
pbrooka7812ae2008-11-17 14:43:54 +00005572 gen_helper_fsts_ST0(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005573 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellardba7cd152008-05-12 20:30:28 +00005574 gen_op_st_T0_A0(OT_LONG + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005575 break;
5576 case 1:
pbrooka7812ae2008-11-17 14:43:54 +00005577 gen_helper_fistl_ST0(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005578 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellardba7cd152008-05-12 20:30:28 +00005579 gen_op_st_T0_A0(OT_LONG + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005580 break;
5581 case 2:
pbrooka7812ae2008-11-17 14:43:54 +00005582 gen_helper_fstl_ST0(cpu_tmp1_i64);
bellardb6abf972008-05-17 12:44:31 +00005583 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
bellard19e6c4b2008-05-12 19:10:44 +00005584 (s->mem_index >> 2) - 1);
bellard2c0262a2003-09-30 20:34:21 +00005585 break;
5586 case 3:
5587 default:
pbrooka7812ae2008-11-17 14:43:54 +00005588 gen_helper_fist_ST0(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005589 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellardba7cd152008-05-12 20:30:28 +00005590 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005591 break;
5592 }
5593 if ((op & 7) == 3)
pbrooka7812ae2008-11-17 14:43:54 +00005594 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005595 break;
5596 }
5597 break;
5598 case 0x0c: /* fldenv mem */
bellard19e6c4b2008-05-12 19:10:44 +00005599 if (s->cc_op != CC_OP_DYNAMIC)
5600 gen_op_set_cc_op(s->cc_op);
5601 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005602 gen_helper_fldenv(
bellard19e6c4b2008-05-12 19:10:44 +00005603 cpu_A0, tcg_const_i32(s->dflag));
bellard2c0262a2003-09-30 20:34:21 +00005604 break;
5605 case 0x0d: /* fldcw mem */
bellard19e6c4b2008-05-12 19:10:44 +00005606 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
bellardb6abf972008-05-17 12:44:31 +00005607 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00005608 gen_helper_fldcw(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00005609 break;
5610 case 0x0e: /* fnstenv mem */
bellard19e6c4b2008-05-12 19:10:44 +00005611 if (s->cc_op != CC_OP_DYNAMIC)
5612 gen_op_set_cc_op(s->cc_op);
5613 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005614 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
bellard2c0262a2003-09-30 20:34:21 +00005615 break;
5616 case 0x0f: /* fnstcw mem */
pbrooka7812ae2008-11-17 14:43:54 +00005617 gen_helper_fnstcw(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005618 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard19e6c4b2008-05-12 19:10:44 +00005619 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005620 break;
5621 case 0x1d: /* fldt mem */
bellard19e6c4b2008-05-12 19:10:44 +00005622 if (s->cc_op != CC_OP_DYNAMIC)
5623 gen_op_set_cc_op(s->cc_op);
5624 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005625 gen_helper_fldt_ST0(cpu_A0);
bellard2c0262a2003-09-30 20:34:21 +00005626 break;
5627 case 0x1f: /* fstpt mem */
bellard19e6c4b2008-05-12 19:10:44 +00005628 if (s->cc_op != CC_OP_DYNAMIC)
5629 gen_op_set_cc_op(s->cc_op);
5630 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005631 gen_helper_fstt_ST0(cpu_A0);
5632 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005633 break;
5634 case 0x2c: /* frstor mem */
bellard19e6c4b2008-05-12 19:10:44 +00005635 if (s->cc_op != CC_OP_DYNAMIC)
5636 gen_op_set_cc_op(s->cc_op);
5637 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005638 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
bellard2c0262a2003-09-30 20:34:21 +00005639 break;
5640 case 0x2e: /* fnsave mem */
bellard19e6c4b2008-05-12 19:10:44 +00005641 if (s->cc_op != CC_OP_DYNAMIC)
5642 gen_op_set_cc_op(s->cc_op);
5643 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005644 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
bellard2c0262a2003-09-30 20:34:21 +00005645 break;
5646 case 0x2f: /* fnstsw mem */
pbrooka7812ae2008-11-17 14:43:54 +00005647 gen_helper_fnstsw(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005648 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard19e6c4b2008-05-12 19:10:44 +00005649 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00005650 break;
5651 case 0x3c: /* fbld */
bellard19e6c4b2008-05-12 19:10:44 +00005652 if (s->cc_op != CC_OP_DYNAMIC)
5653 gen_op_set_cc_op(s->cc_op);
5654 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005655 gen_helper_fbld_ST0(cpu_A0);
bellard2c0262a2003-09-30 20:34:21 +00005656 break;
5657 case 0x3e: /* fbstp */
bellard19e6c4b2008-05-12 19:10:44 +00005658 if (s->cc_op != CC_OP_DYNAMIC)
5659 gen_op_set_cc_op(s->cc_op);
5660 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005661 gen_helper_fbst_ST0(cpu_A0);
5662 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005663 break;
5664 case 0x3d: /* fildll */
bellardb6abf972008-05-17 12:44:31 +00005665 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
bellard19e6c4b2008-05-12 19:10:44 +00005666 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00005667 gen_helper_fildll_ST0(cpu_tmp1_i64);
bellard2c0262a2003-09-30 20:34:21 +00005668 break;
5669 case 0x3f: /* fistpll */
pbrooka7812ae2008-11-17 14:43:54 +00005670 gen_helper_fistll_ST0(cpu_tmp1_i64);
bellardb6abf972008-05-17 12:44:31 +00005671 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
bellard19e6c4b2008-05-12 19:10:44 +00005672 (s->mem_index >> 2) - 1);
pbrooka7812ae2008-11-17 14:43:54 +00005673 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005674 break;
5675 default:
5676 goto illegal_op;
5677 }
5678 } else {
5679 /* register float ops */
5680 opreg = rm;
5681
5682 switch(op) {
5683 case 0x08: /* fld sti */
pbrooka7812ae2008-11-17 14:43:54 +00005684 gen_helper_fpush();
5685 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
bellard2c0262a2003-09-30 20:34:21 +00005686 break;
5687 case 0x09: /* fxchg sti */
bellardc169c902004-11-24 19:28:52 +00005688 case 0x29: /* fxchg4 sti, undocumented op */
5689 case 0x39: /* fxchg7 sti, undocumented op */
pbrooka7812ae2008-11-17 14:43:54 +00005690 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
bellard2c0262a2003-09-30 20:34:21 +00005691 break;
5692 case 0x0a: /* grp d9/2 */
5693 switch(rm) {
5694 case 0: /* fnop */
bellard023fe102004-05-29 11:08:52 +00005695 /* check exceptions (FreeBSD FPU probe) */
5696 if (s->cc_op != CC_OP_DYNAMIC)
5697 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00005698 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00005699 gen_helper_fwait();
bellard2c0262a2003-09-30 20:34:21 +00005700 break;
5701 default:
5702 goto illegal_op;
5703 }
5704 break;
5705 case 0x0c: /* grp d9/4 */
5706 switch(rm) {
5707 case 0: /* fchs */
pbrooka7812ae2008-11-17 14:43:54 +00005708 gen_helper_fchs_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005709 break;
5710 case 1: /* fabs */
pbrooka7812ae2008-11-17 14:43:54 +00005711 gen_helper_fabs_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005712 break;
5713 case 4: /* ftst */
pbrooka7812ae2008-11-17 14:43:54 +00005714 gen_helper_fldz_FT0();
5715 gen_helper_fcom_ST0_FT0();
bellard2c0262a2003-09-30 20:34:21 +00005716 break;
5717 case 5: /* fxam */
pbrooka7812ae2008-11-17 14:43:54 +00005718 gen_helper_fxam_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005719 break;
5720 default:
5721 goto illegal_op;
5722 }
5723 break;
5724 case 0x0d: /* grp d9/5 */
5725 {
5726 switch(rm) {
5727 case 0:
pbrooka7812ae2008-11-17 14:43:54 +00005728 gen_helper_fpush();
5729 gen_helper_fld1_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005730 break;
5731 case 1:
pbrooka7812ae2008-11-17 14:43:54 +00005732 gen_helper_fpush();
5733 gen_helper_fldl2t_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005734 break;
5735 case 2:
pbrooka7812ae2008-11-17 14:43:54 +00005736 gen_helper_fpush();
5737 gen_helper_fldl2e_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005738 break;
5739 case 3:
pbrooka7812ae2008-11-17 14:43:54 +00005740 gen_helper_fpush();
5741 gen_helper_fldpi_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005742 break;
5743 case 4:
pbrooka7812ae2008-11-17 14:43:54 +00005744 gen_helper_fpush();
5745 gen_helper_fldlg2_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005746 break;
5747 case 5:
pbrooka7812ae2008-11-17 14:43:54 +00005748 gen_helper_fpush();
5749 gen_helper_fldln2_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005750 break;
5751 case 6:
pbrooka7812ae2008-11-17 14:43:54 +00005752 gen_helper_fpush();
5753 gen_helper_fldz_ST0();
bellard2c0262a2003-09-30 20:34:21 +00005754 break;
5755 default:
5756 goto illegal_op;
5757 }
5758 }
5759 break;
5760 case 0x0e: /* grp d9/6 */
5761 switch(rm) {
5762 case 0: /* f2xm1 */
pbrooka7812ae2008-11-17 14:43:54 +00005763 gen_helper_f2xm1();
bellard2c0262a2003-09-30 20:34:21 +00005764 break;
5765 case 1: /* fyl2x */
pbrooka7812ae2008-11-17 14:43:54 +00005766 gen_helper_fyl2x();
bellard2c0262a2003-09-30 20:34:21 +00005767 break;
5768 case 2: /* fptan */
pbrooka7812ae2008-11-17 14:43:54 +00005769 gen_helper_fptan();
bellard2c0262a2003-09-30 20:34:21 +00005770 break;
5771 case 3: /* fpatan */
pbrooka7812ae2008-11-17 14:43:54 +00005772 gen_helper_fpatan();
bellard2c0262a2003-09-30 20:34:21 +00005773 break;
5774 case 4: /* fxtract */
pbrooka7812ae2008-11-17 14:43:54 +00005775 gen_helper_fxtract();
bellard2c0262a2003-09-30 20:34:21 +00005776 break;
5777 case 5: /* fprem1 */
pbrooka7812ae2008-11-17 14:43:54 +00005778 gen_helper_fprem1();
bellard2c0262a2003-09-30 20:34:21 +00005779 break;
5780 case 6: /* fdecstp */
pbrooka7812ae2008-11-17 14:43:54 +00005781 gen_helper_fdecstp();
bellard2c0262a2003-09-30 20:34:21 +00005782 break;
5783 default:
5784 case 7: /* fincstp */
pbrooka7812ae2008-11-17 14:43:54 +00005785 gen_helper_fincstp();
bellard2c0262a2003-09-30 20:34:21 +00005786 break;
5787 }
5788 break;
5789 case 0x0f: /* grp d9/7 */
5790 switch(rm) {
5791 case 0: /* fprem */
pbrooka7812ae2008-11-17 14:43:54 +00005792 gen_helper_fprem();
bellard2c0262a2003-09-30 20:34:21 +00005793 break;
5794 case 1: /* fyl2xp1 */
pbrooka7812ae2008-11-17 14:43:54 +00005795 gen_helper_fyl2xp1();
bellard2c0262a2003-09-30 20:34:21 +00005796 break;
5797 case 2: /* fsqrt */
pbrooka7812ae2008-11-17 14:43:54 +00005798 gen_helper_fsqrt();
bellard2c0262a2003-09-30 20:34:21 +00005799 break;
5800 case 3: /* fsincos */
pbrooka7812ae2008-11-17 14:43:54 +00005801 gen_helper_fsincos();
bellard2c0262a2003-09-30 20:34:21 +00005802 break;
5803 case 5: /* fscale */
pbrooka7812ae2008-11-17 14:43:54 +00005804 gen_helper_fscale();
bellard2c0262a2003-09-30 20:34:21 +00005805 break;
5806 case 4: /* frndint */
pbrooka7812ae2008-11-17 14:43:54 +00005807 gen_helper_frndint();
bellard2c0262a2003-09-30 20:34:21 +00005808 break;
5809 case 6: /* fsin */
pbrooka7812ae2008-11-17 14:43:54 +00005810 gen_helper_fsin();
bellard2c0262a2003-09-30 20:34:21 +00005811 break;
5812 default:
5813 case 7: /* fcos */
pbrooka7812ae2008-11-17 14:43:54 +00005814 gen_helper_fcos();
bellard2c0262a2003-09-30 20:34:21 +00005815 break;
5816 }
5817 break;
5818 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5819 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5820 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5821 {
5822 int op1;
ths3b46e622007-09-17 08:09:54 +00005823
bellard2c0262a2003-09-30 20:34:21 +00005824 op1 = op & 7;
5825 if (op >= 0x20) {
pbrooka7812ae2008-11-17 14:43:54 +00005826 gen_helper_fp_arith_STN_ST0(op1, opreg);
bellard2c0262a2003-09-30 20:34:21 +00005827 if (op >= 0x30)
pbrooka7812ae2008-11-17 14:43:54 +00005828 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005829 } else {
pbrooka7812ae2008-11-17 14:43:54 +00005830 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5831 gen_helper_fp_arith_ST0_FT0(op1);
bellard2c0262a2003-09-30 20:34:21 +00005832 }
5833 }
5834 break;
5835 case 0x02: /* fcom */
bellardc169c902004-11-24 19:28:52 +00005836 case 0x22: /* fcom2, undocumented op */
pbrooka7812ae2008-11-17 14:43:54 +00005837 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5838 gen_helper_fcom_ST0_FT0();
bellard2c0262a2003-09-30 20:34:21 +00005839 break;
5840 case 0x03: /* fcomp */
bellardc169c902004-11-24 19:28:52 +00005841 case 0x23: /* fcomp3, undocumented op */
5842 case 0x32: /* fcomp5, undocumented op */
pbrooka7812ae2008-11-17 14:43:54 +00005843 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5844 gen_helper_fcom_ST0_FT0();
5845 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005846 break;
5847 case 0x15: /* da/5 */
5848 switch(rm) {
5849 case 1: /* fucompp */
pbrooka7812ae2008-11-17 14:43:54 +00005850 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5851 gen_helper_fucom_ST0_FT0();
5852 gen_helper_fpop();
5853 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005854 break;
5855 default:
5856 goto illegal_op;
5857 }
5858 break;
5859 case 0x1c:
5860 switch(rm) {
5861 case 0: /* feni (287 only, just do nop here) */
5862 break;
5863 case 1: /* fdisi (287 only, just do nop here) */
5864 break;
5865 case 2: /* fclex */
pbrooka7812ae2008-11-17 14:43:54 +00005866 gen_helper_fclex();
bellard2c0262a2003-09-30 20:34:21 +00005867 break;
5868 case 3: /* fninit */
pbrooka7812ae2008-11-17 14:43:54 +00005869 gen_helper_fninit();
bellard2c0262a2003-09-30 20:34:21 +00005870 break;
5871 case 4: /* fsetpm (287 only, just do nop here) */
5872 break;
5873 default:
5874 goto illegal_op;
5875 }
5876 break;
5877 case 0x1d: /* fucomi */
5878 if (s->cc_op != CC_OP_DYNAMIC)
5879 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00005880 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5881 gen_helper_fucomi_ST0_FT0();
bellard2c0262a2003-09-30 20:34:21 +00005882 s->cc_op = CC_OP_EFLAGS;
5883 break;
5884 case 0x1e: /* fcomi */
5885 if (s->cc_op != CC_OP_DYNAMIC)
5886 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00005887 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5888 gen_helper_fcomi_ST0_FT0();
bellard2c0262a2003-09-30 20:34:21 +00005889 s->cc_op = CC_OP_EFLAGS;
5890 break;
bellard658c8bd2004-06-12 11:35:12 +00005891 case 0x28: /* ffree sti */
pbrooka7812ae2008-11-17 14:43:54 +00005892 gen_helper_ffree_STN(tcg_const_i32(opreg));
ths5fafdf22007-09-16 21:08:06 +00005893 break;
bellard2c0262a2003-09-30 20:34:21 +00005894 case 0x2a: /* fst sti */
pbrooka7812ae2008-11-17 14:43:54 +00005895 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
bellard2c0262a2003-09-30 20:34:21 +00005896 break;
5897 case 0x2b: /* fstp sti */
bellardc169c902004-11-24 19:28:52 +00005898 case 0x0b: /* fstp1 sti, undocumented op */
5899 case 0x3a: /* fstp8 sti, undocumented op */
5900 case 0x3b: /* fstp9 sti, undocumented op */
pbrooka7812ae2008-11-17 14:43:54 +00005901 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5902 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005903 break;
5904 case 0x2c: /* fucom st(i) */
pbrooka7812ae2008-11-17 14:43:54 +00005905 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5906 gen_helper_fucom_ST0_FT0();
bellard2c0262a2003-09-30 20:34:21 +00005907 break;
5908 case 0x2d: /* fucomp st(i) */
pbrooka7812ae2008-11-17 14:43:54 +00005909 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5910 gen_helper_fucom_ST0_FT0();
5911 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005912 break;
5913 case 0x33: /* de/3 */
5914 switch(rm) {
5915 case 1: /* fcompp */
pbrooka7812ae2008-11-17 14:43:54 +00005916 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5917 gen_helper_fcom_ST0_FT0();
5918 gen_helper_fpop();
5919 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005920 break;
5921 default:
5922 goto illegal_op;
5923 }
5924 break;
bellardc169c902004-11-24 19:28:52 +00005925 case 0x38: /* ffreep sti, undocumented op */
pbrooka7812ae2008-11-17 14:43:54 +00005926 gen_helper_ffree_STN(tcg_const_i32(opreg));
5927 gen_helper_fpop();
bellardc169c902004-11-24 19:28:52 +00005928 break;
bellard2c0262a2003-09-30 20:34:21 +00005929 case 0x3c: /* df/4 */
5930 switch(rm) {
5931 case 0:
pbrooka7812ae2008-11-17 14:43:54 +00005932 gen_helper_fnstsw(cpu_tmp2_i32);
bellardb6abf972008-05-17 12:44:31 +00005933 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
bellard19e6c4b2008-05-12 19:10:44 +00005934 gen_op_mov_reg_T0(OT_WORD, R_EAX);
bellard2c0262a2003-09-30 20:34:21 +00005935 break;
5936 default:
5937 goto illegal_op;
5938 }
5939 break;
5940 case 0x3d: /* fucomip */
5941 if (s->cc_op != CC_OP_DYNAMIC)
5942 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00005943 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5944 gen_helper_fucomi_ST0_FT0();
5945 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005946 s->cc_op = CC_OP_EFLAGS;
5947 break;
5948 case 0x3e: /* fcomip */
5949 if (s->cc_op != CC_OP_DYNAMIC)
5950 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00005951 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5952 gen_helper_fcomi_ST0_FT0();
5953 gen_helper_fpop();
bellard2c0262a2003-09-30 20:34:21 +00005954 s->cc_op = CC_OP_EFLAGS;
5955 break;
bellarda2cc3b22003-11-19 22:08:13 +00005956 case 0x10 ... 0x13: /* fcmovxx */
5957 case 0x18 ... 0x1b:
5958 {
bellard19e6c4b2008-05-12 19:10:44 +00005959 int op1, l1;
pbrookd70040b2008-07-05 17:03:54 +00005960 static const uint8_t fcmov_cc[8] = {
bellarda2cc3b22003-11-19 22:08:13 +00005961 (JCC_B << 1),
5962 (JCC_Z << 1),
5963 (JCC_BE << 1),
5964 (JCC_P << 1),
5965 };
bellard1e4840b2008-05-25 17:26:41 +00005966 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
bellard19e6c4b2008-05-12 19:10:44 +00005967 l1 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00005968 gen_jcc1(s, s->cc_op, op1, l1);
pbrooka7812ae2008-11-17 14:43:54 +00005969 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
bellard19e6c4b2008-05-12 19:10:44 +00005970 gen_set_label(l1);
bellarda2cc3b22003-11-19 22:08:13 +00005971 }
5972 break;
bellard2c0262a2003-09-30 20:34:21 +00005973 default:
5974 goto illegal_op;
5975 }
5976 }
5977 break;
5978 /************************/
5979 /* string ops */
5980
5981 case 0xa4: /* movsS */
5982 case 0xa5:
5983 if ((b & 1) == 0)
5984 ot = OT_BYTE;
5985 else
bellard14ce26e2005-01-03 23:50:08 +00005986 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00005987
5988 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5989 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5990 } else {
5991 gen_movs(s, ot);
5992 }
5993 break;
ths3b46e622007-09-17 08:09:54 +00005994
bellard2c0262a2003-09-30 20:34:21 +00005995 case 0xaa: /* stosS */
5996 case 0xab:
5997 if ((b & 1) == 0)
5998 ot = OT_BYTE;
5999 else
bellard14ce26e2005-01-03 23:50:08 +00006000 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00006001
6002 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6003 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6004 } else {
6005 gen_stos(s, ot);
6006 }
6007 break;
6008 case 0xac: /* lodsS */
6009 case 0xad:
6010 if ((b & 1) == 0)
6011 ot = OT_BYTE;
6012 else
bellard14ce26e2005-01-03 23:50:08 +00006013 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00006014 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6015 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6016 } else {
6017 gen_lods(s, ot);
6018 }
6019 break;
6020 case 0xae: /* scasS */
6021 case 0xaf:
6022 if ((b & 1) == 0)
6023 ot = OT_BYTE;
6024 else
bellard14ce26e2005-01-03 23:50:08 +00006025 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00006026 if (prefixes & PREFIX_REPNZ) {
6027 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6028 } else if (prefixes & PREFIX_REPZ) {
6029 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6030 } else {
6031 gen_scas(s, ot);
6032 s->cc_op = CC_OP_SUBB + ot;
6033 }
6034 break;
6035
6036 case 0xa6: /* cmpsS */
6037 case 0xa7:
6038 if ((b & 1) == 0)
6039 ot = OT_BYTE;
6040 else
bellard14ce26e2005-01-03 23:50:08 +00006041 ot = dflag + OT_WORD;
bellard2c0262a2003-09-30 20:34:21 +00006042 if (prefixes & PREFIX_REPNZ) {
6043 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6044 } else if (prefixes & PREFIX_REPZ) {
6045 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6046 } else {
6047 gen_cmps(s, ot);
6048 s->cc_op = CC_OP_SUBB + ot;
6049 }
6050 break;
6051 case 0x6c: /* insS */
6052 case 0x6d:
bellardf115e912003-11-13 01:43:28 +00006053 if ((b & 1) == 0)
6054 ot = OT_BYTE;
6055 else
6056 ot = dflag ? OT_LONG : OT_WORD;
bellard57fec1f2008-02-01 10:50:11 +00006057 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
ths0573fbf2007-09-23 15:28:04 +00006058 gen_op_andl_T0_ffff();
bellardb8b6a502008-05-15 16:46:30 +00006059 gen_check_io(s, ot, pc_start - s->cs_base,
6060 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
bellardf115e912003-11-13 01:43:28 +00006061 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6062 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00006063 } else {
bellardf115e912003-11-13 01:43:28 +00006064 gen_ins(s, ot);
pbrook2e70f6e2008-06-29 01:03:05 +00006065 if (use_icount) {
6066 gen_jmp(s, s->pc - s->cs_base);
6067 }
bellard2c0262a2003-09-30 20:34:21 +00006068 }
6069 break;
6070 case 0x6e: /* outsS */
6071 case 0x6f:
bellardf115e912003-11-13 01:43:28 +00006072 if ((b & 1) == 0)
6073 ot = OT_BYTE;
6074 else
6075 ot = dflag ? OT_LONG : OT_WORD;
bellard57fec1f2008-02-01 10:50:11 +00006076 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
ths0573fbf2007-09-23 15:28:04 +00006077 gen_op_andl_T0_ffff();
bellardb8b6a502008-05-15 16:46:30 +00006078 gen_check_io(s, ot, pc_start - s->cs_base,
6079 svm_is_rep(prefixes) | 4);
bellardf115e912003-11-13 01:43:28 +00006080 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6081 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00006082 } else {
bellardf115e912003-11-13 01:43:28 +00006083 gen_outs(s, ot);
pbrook2e70f6e2008-06-29 01:03:05 +00006084 if (use_icount) {
6085 gen_jmp(s, s->pc - s->cs_base);
6086 }
bellard2c0262a2003-09-30 20:34:21 +00006087 }
6088 break;
6089
6090 /************************/
6091 /* port I/O */
ths0573fbf2007-09-23 15:28:04 +00006092
bellard2c0262a2003-09-30 20:34:21 +00006093 case 0xe4:
6094 case 0xe5:
bellardf115e912003-11-13 01:43:28 +00006095 if ((b & 1) == 0)
6096 ot = OT_BYTE;
6097 else
6098 ot = dflag ? OT_LONG : OT_WORD;
6099 val = ldub_code(s->pc++);
6100 gen_op_movl_T0_im(val);
bellardb8b6a502008-05-15 16:46:30 +00006101 gen_check_io(s, ot, pc_start - s->cs_base,
6102 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
pbrook2e70f6e2008-06-29 01:03:05 +00006103 if (use_icount)
6104 gen_io_start();
bellardb6abf972008-05-17 12:44:31 +00006105 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00006106 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
bellard57fec1f2008-02-01 10:50:11 +00006107 gen_op_mov_reg_T1(ot, R_EAX);
pbrook2e70f6e2008-06-29 01:03:05 +00006108 if (use_icount) {
6109 gen_io_end();
6110 gen_jmp(s, s->pc - s->cs_base);
6111 }
bellard2c0262a2003-09-30 20:34:21 +00006112 break;
6113 case 0xe6:
6114 case 0xe7:
bellardf115e912003-11-13 01:43:28 +00006115 if ((b & 1) == 0)
6116 ot = OT_BYTE;
6117 else
6118 ot = dflag ? OT_LONG : OT_WORD;
6119 val = ldub_code(s->pc++);
6120 gen_op_movl_T0_im(val);
bellardb8b6a502008-05-15 16:46:30 +00006121 gen_check_io(s, ot, pc_start - s->cs_base,
6122 svm_is_rep(prefixes));
bellard57fec1f2008-02-01 10:50:11 +00006123 gen_op_mov_TN_reg(ot, 1, R_EAX);
bellardb8b6a502008-05-15 16:46:30 +00006124
pbrook2e70f6e2008-06-29 01:03:05 +00006125 if (use_icount)
6126 gen_io_start();
bellardb6abf972008-05-17 12:44:31 +00006127 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6128 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6129 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
pbrooka7812ae2008-11-17 14:43:54 +00006130 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
pbrook2e70f6e2008-06-29 01:03:05 +00006131 if (use_icount) {
6132 gen_io_end();
6133 gen_jmp(s, s->pc - s->cs_base);
6134 }
bellard2c0262a2003-09-30 20:34:21 +00006135 break;
6136 case 0xec:
6137 case 0xed:
bellardf115e912003-11-13 01:43:28 +00006138 if ((b & 1) == 0)
6139 ot = OT_BYTE;
6140 else
6141 ot = dflag ? OT_LONG : OT_WORD;
bellard57fec1f2008-02-01 10:50:11 +00006142 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
bellard4f319162004-01-04 17:35:00 +00006143 gen_op_andl_T0_ffff();
bellardb8b6a502008-05-15 16:46:30 +00006144 gen_check_io(s, ot, pc_start - s->cs_base,
6145 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
pbrook2e70f6e2008-06-29 01:03:05 +00006146 if (use_icount)
6147 gen_io_start();
bellardb6abf972008-05-17 12:44:31 +00006148 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00006149 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
bellard57fec1f2008-02-01 10:50:11 +00006150 gen_op_mov_reg_T1(ot, R_EAX);
pbrook2e70f6e2008-06-29 01:03:05 +00006151 if (use_icount) {
6152 gen_io_end();
6153 gen_jmp(s, s->pc - s->cs_base);
6154 }
bellard2c0262a2003-09-30 20:34:21 +00006155 break;
6156 case 0xee:
6157 case 0xef:
bellardf115e912003-11-13 01:43:28 +00006158 if ((b & 1) == 0)
6159 ot = OT_BYTE;
6160 else
6161 ot = dflag ? OT_LONG : OT_WORD;
bellard57fec1f2008-02-01 10:50:11 +00006162 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
bellard4f319162004-01-04 17:35:00 +00006163 gen_op_andl_T0_ffff();
bellardb8b6a502008-05-15 16:46:30 +00006164 gen_check_io(s, ot, pc_start - s->cs_base,
6165 svm_is_rep(prefixes));
bellard57fec1f2008-02-01 10:50:11 +00006166 gen_op_mov_TN_reg(ot, 1, R_EAX);
bellardb8b6a502008-05-15 16:46:30 +00006167
pbrook2e70f6e2008-06-29 01:03:05 +00006168 if (use_icount)
6169 gen_io_start();
bellardb6abf972008-05-17 12:44:31 +00006170 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6171 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6172 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
pbrooka7812ae2008-11-17 14:43:54 +00006173 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
pbrook2e70f6e2008-06-29 01:03:05 +00006174 if (use_icount) {
6175 gen_io_end();
6176 gen_jmp(s, s->pc - s->cs_base);
6177 }
bellard2c0262a2003-09-30 20:34:21 +00006178 break;
6179
6180 /************************/
6181 /* control */
6182 case 0xc2: /* ret im */
bellard61382a52003-10-27 21:22:23 +00006183 val = ldsw_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00006184 s->pc += 2;
6185 gen_pop_T0(s);
bellard8f091a52005-07-23 17:41:26 +00006186 if (CODE64(s) && s->dflag)
6187 s->dflag = 2;
bellard2c0262a2003-09-30 20:34:21 +00006188 gen_stack_update(s, val + (2 << s->dflag));
6189 if (s->dflag == 0)
6190 gen_op_andl_T0_ffff();
6191 gen_op_jmp_T0();
6192 gen_eob(s);
6193 break;
6194 case 0xc3: /* ret */
6195 gen_pop_T0(s);
6196 gen_pop_update(s);
6197 if (s->dflag == 0)
6198 gen_op_andl_T0_ffff();
6199 gen_op_jmp_T0();
6200 gen_eob(s);
6201 break;
6202 case 0xca: /* lret im */
bellard61382a52003-10-27 21:22:23 +00006203 val = ldsw_code(s->pc);
bellard2c0262a2003-09-30 20:34:21 +00006204 s->pc += 2;
6205 do_lret:
6206 if (s->pe && !s->vm86) {
6207 if (s->cc_op != CC_OP_DYNAMIC)
6208 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00006209 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006210 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6211 tcg_const_i32(val));
bellard2c0262a2003-09-30 20:34:21 +00006212 } else {
6213 gen_stack_A0(s);
6214 /* pop offset */
bellard57fec1f2008-02-01 10:50:11 +00006215 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00006216 if (s->dflag == 0)
6217 gen_op_andl_T0_ffff();
6218 /* NOTE: keeping EIP updated is not a problem in case of
6219 exception */
6220 gen_op_jmp_T0();
6221 /* pop selector */
6222 gen_op_addl_A0_im(2 << s->dflag);
bellard57fec1f2008-02-01 10:50:11 +00006223 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
bellard3bd7da92008-05-21 16:34:06 +00006224 gen_op_movl_seg_T0_vm(R_CS);
bellard2c0262a2003-09-30 20:34:21 +00006225 /* add stack offset */
6226 gen_stack_update(s, val + (4 << s->dflag));
6227 }
6228 gen_eob(s);
6229 break;
6230 case 0xcb: /* lret */
6231 val = 0;
6232 goto do_lret;
6233 case 0xcf: /* iret */
bellard872929a2008-05-28 16:16:54 +00006234 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
bellard2c0262a2003-09-30 20:34:21 +00006235 if (!s->pe) {
6236 /* real mode */
pbrooka7812ae2008-11-17 14:43:54 +00006237 gen_helper_iret_real(tcg_const_i32(s->dflag));
bellard2c0262a2003-09-30 20:34:21 +00006238 s->cc_op = CC_OP_EFLAGS;
bellardf115e912003-11-13 01:43:28 +00006239 } else if (s->vm86) {
6240 if (s->iopl != 3) {
6241 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6242 } else {
pbrooka7812ae2008-11-17 14:43:54 +00006243 gen_helper_iret_real(tcg_const_i32(s->dflag));
bellardf115e912003-11-13 01:43:28 +00006244 s->cc_op = CC_OP_EFLAGS;
6245 }
bellard2c0262a2003-09-30 20:34:21 +00006246 } else {
6247 if (s->cc_op != CC_OP_DYNAMIC)
6248 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00006249 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006250 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6251 tcg_const_i32(s->pc - s->cs_base));
bellard2c0262a2003-09-30 20:34:21 +00006252 s->cc_op = CC_OP_EFLAGS;
6253 }
6254 gen_eob(s);
6255 break;
6256 case 0xe8: /* call im */
6257 {
bellard14ce26e2005-01-03 23:50:08 +00006258 if (dflag)
6259 tval = (int32_t)insn_get(s, OT_LONG);
6260 else
6261 tval = (int16_t)insn_get(s, OT_WORD);
bellard2c0262a2003-09-30 20:34:21 +00006262 next_eip = s->pc - s->cs_base;
bellard14ce26e2005-01-03 23:50:08 +00006263 tval += next_eip;
bellard2c0262a2003-09-30 20:34:21 +00006264 if (s->dflag == 0)
bellard14ce26e2005-01-03 23:50:08 +00006265 tval &= 0xffff;
Aurelien Jarno99596382010-01-03 03:08:19 +01006266 else if(!CODE64(s))
6267 tval &= 0xffffffff;
bellard14ce26e2005-01-03 23:50:08 +00006268 gen_movtl_T0_im(next_eip);
bellard2c0262a2003-09-30 20:34:21 +00006269 gen_push_T0(s);
bellard14ce26e2005-01-03 23:50:08 +00006270 gen_jmp(s, tval);
bellard2c0262a2003-09-30 20:34:21 +00006271 }
6272 break;
6273 case 0x9a: /* lcall im */
6274 {
6275 unsigned int selector, offset;
ths3b46e622007-09-17 08:09:54 +00006276
bellard14ce26e2005-01-03 23:50:08 +00006277 if (CODE64(s))
6278 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006279 ot = dflag ? OT_LONG : OT_WORD;
6280 offset = insn_get(s, ot);
6281 selector = insn_get(s, OT_WORD);
ths3b46e622007-09-17 08:09:54 +00006282
bellard2c0262a2003-09-30 20:34:21 +00006283 gen_op_movl_T0_im(selector);
bellard14ce26e2005-01-03 23:50:08 +00006284 gen_op_movl_T1_imu(offset);
bellard2c0262a2003-09-30 20:34:21 +00006285 }
6286 goto do_lcall;
bellardecada8a2005-08-21 10:28:44 +00006287 case 0xe9: /* jmp im */
bellard14ce26e2005-01-03 23:50:08 +00006288 if (dflag)
6289 tval = (int32_t)insn_get(s, OT_LONG);
6290 else
6291 tval = (int16_t)insn_get(s, OT_WORD);
6292 tval += s->pc - s->cs_base;
bellard2c0262a2003-09-30 20:34:21 +00006293 if (s->dflag == 0)
bellard14ce26e2005-01-03 23:50:08 +00006294 tval &= 0xffff;
aurel3232938e12008-12-10 15:02:16 +00006295 else if(!CODE64(s))
6296 tval &= 0xffffffff;
bellard14ce26e2005-01-03 23:50:08 +00006297 gen_jmp(s, tval);
bellard2c0262a2003-09-30 20:34:21 +00006298 break;
6299 case 0xea: /* ljmp im */
6300 {
6301 unsigned int selector, offset;
6302
bellard14ce26e2005-01-03 23:50:08 +00006303 if (CODE64(s))
6304 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006305 ot = dflag ? OT_LONG : OT_WORD;
6306 offset = insn_get(s, ot);
6307 selector = insn_get(s, OT_WORD);
ths3b46e622007-09-17 08:09:54 +00006308
bellard2c0262a2003-09-30 20:34:21 +00006309 gen_op_movl_T0_im(selector);
bellard14ce26e2005-01-03 23:50:08 +00006310 gen_op_movl_T1_imu(offset);
bellard2c0262a2003-09-30 20:34:21 +00006311 }
6312 goto do_ljmp;
6313 case 0xeb: /* jmp Jb */
bellard14ce26e2005-01-03 23:50:08 +00006314 tval = (int8_t)insn_get(s, OT_BYTE);
6315 tval += s->pc - s->cs_base;
bellard2c0262a2003-09-30 20:34:21 +00006316 if (s->dflag == 0)
bellard14ce26e2005-01-03 23:50:08 +00006317 tval &= 0xffff;
6318 gen_jmp(s, tval);
bellard2c0262a2003-09-30 20:34:21 +00006319 break;
6320 case 0x70 ... 0x7f: /* jcc Jb */
bellard14ce26e2005-01-03 23:50:08 +00006321 tval = (int8_t)insn_get(s, OT_BYTE);
bellard2c0262a2003-09-30 20:34:21 +00006322 goto do_jcc;
6323 case 0x180 ... 0x18f: /* jcc Jv */
6324 if (dflag) {
bellard14ce26e2005-01-03 23:50:08 +00006325 tval = (int32_t)insn_get(s, OT_LONG);
bellard2c0262a2003-09-30 20:34:21 +00006326 } else {
ths5fafdf22007-09-16 21:08:06 +00006327 tval = (int16_t)insn_get(s, OT_WORD);
bellard2c0262a2003-09-30 20:34:21 +00006328 }
6329 do_jcc:
6330 next_eip = s->pc - s->cs_base;
bellard14ce26e2005-01-03 23:50:08 +00006331 tval += next_eip;
bellard2c0262a2003-09-30 20:34:21 +00006332 if (s->dflag == 0)
bellard14ce26e2005-01-03 23:50:08 +00006333 tval &= 0xffff;
6334 gen_jcc(s, b, tval, next_eip);
bellard2c0262a2003-09-30 20:34:21 +00006335 break;
6336
6337 case 0x190 ... 0x19f: /* setcc Gv */
bellard61382a52003-10-27 21:22:23 +00006338 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00006339 gen_setcc(s, b);
6340 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6341 break;
6342 case 0x140 ... 0x14f: /* cmov Gv, Ev */
bellard8e1c85e2008-05-21 19:16:45 +00006343 {
6344 int l1;
bellard1e4840b2008-05-25 17:26:41 +00006345 TCGv t0;
6346
bellard8e1c85e2008-05-21 19:16:45 +00006347 ot = dflag + OT_WORD;
6348 modrm = ldub_code(s->pc++);
6349 reg = ((modrm >> 3) & 7) | rex_r;
6350 mod = (modrm >> 6) & 3;
pbrooka7812ae2008-11-17 14:43:54 +00006351 t0 = tcg_temp_local_new();
bellard8e1c85e2008-05-21 19:16:45 +00006352 if (mod != 3) {
6353 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard1e4840b2008-05-25 17:26:41 +00006354 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
bellard8e1c85e2008-05-21 19:16:45 +00006355 } else {
6356 rm = (modrm & 7) | REX_B(s);
bellard1e4840b2008-05-25 17:26:41 +00006357 gen_op_mov_v_reg(ot, t0, rm);
bellard8e1c85e2008-05-21 19:16:45 +00006358 }
bellard8e1c85e2008-05-21 19:16:45 +00006359#ifdef TARGET_X86_64
6360 if (ot == OT_LONG) {
6361 /* XXX: specific Intel behaviour ? */
6362 l1 = gen_new_label();
6363 gen_jcc1(s, s->cc_op, b ^ 1, l1);
Laurent Desnoguescc739bb2009-09-29 11:58:04 +02006364 tcg_gen_mov_tl(cpu_regs[reg], t0);
bellard8e1c85e2008-05-21 19:16:45 +00006365 gen_set_label(l1);
Laurent Desnoguescc739bb2009-09-29 11:58:04 +02006366 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
bellard8e1c85e2008-05-21 19:16:45 +00006367 } else
6368#endif
6369 {
6370 l1 = gen_new_label();
6371 gen_jcc1(s, s->cc_op, b ^ 1, l1);
bellard1e4840b2008-05-25 17:26:41 +00006372 gen_op_mov_reg_v(ot, reg, t0);
bellard8e1c85e2008-05-21 19:16:45 +00006373 gen_set_label(l1);
6374 }
bellard1e4840b2008-05-25 17:26:41 +00006375 tcg_temp_free(t0);
bellard2c0262a2003-09-30 20:34:21 +00006376 }
bellard2c0262a2003-09-30 20:34:21 +00006377 break;
ths3b46e622007-09-17 08:09:54 +00006378
bellard2c0262a2003-09-30 20:34:21 +00006379 /************************/
6380 /* flags */
6381 case 0x9c: /* pushf */
bellard872929a2008-05-28 16:16:54 +00006382 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
bellard2c0262a2003-09-30 20:34:21 +00006383 if (s->vm86 && s->iopl != 3) {
6384 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6385 } else {
6386 if (s->cc_op != CC_OP_DYNAMIC)
6387 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00006388 gen_helper_read_eflags(cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00006389 gen_push_T0(s);
6390 }
6391 break;
6392 case 0x9d: /* popf */
bellard872929a2008-05-28 16:16:54 +00006393 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
bellard2c0262a2003-09-30 20:34:21 +00006394 if (s->vm86 && s->iopl != 3) {
6395 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6396 } else {
6397 gen_pop_T0(s);
6398 if (s->cpl == 0) {
6399 if (s->dflag) {
pbrooka7812ae2008-11-17 14:43:54 +00006400 gen_helper_write_eflags(cpu_T[0],
bellardbd7a7b32008-05-21 17:07:20 +00006401 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
bellard2c0262a2003-09-30 20:34:21 +00006402 } else {
pbrooka7812ae2008-11-17 14:43:54 +00006403 gen_helper_write_eflags(cpu_T[0],
bellardbd7a7b32008-05-21 17:07:20 +00006404 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
bellard2c0262a2003-09-30 20:34:21 +00006405 }
6406 } else {
bellard4136f332003-11-23 23:09:40 +00006407 if (s->cpl <= s->iopl) {
6408 if (s->dflag) {
pbrooka7812ae2008-11-17 14:43:54 +00006409 gen_helper_write_eflags(cpu_T[0],
bellardbd7a7b32008-05-21 17:07:20 +00006410 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
bellard4136f332003-11-23 23:09:40 +00006411 } else {
pbrooka7812ae2008-11-17 14:43:54 +00006412 gen_helper_write_eflags(cpu_T[0],
bellardbd7a7b32008-05-21 17:07:20 +00006413 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
bellard4136f332003-11-23 23:09:40 +00006414 }
bellard2c0262a2003-09-30 20:34:21 +00006415 } else {
bellard4136f332003-11-23 23:09:40 +00006416 if (s->dflag) {
pbrooka7812ae2008-11-17 14:43:54 +00006417 gen_helper_write_eflags(cpu_T[0],
bellardbd7a7b32008-05-21 17:07:20 +00006418 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
bellard4136f332003-11-23 23:09:40 +00006419 } else {
pbrooka7812ae2008-11-17 14:43:54 +00006420 gen_helper_write_eflags(cpu_T[0],
bellardbd7a7b32008-05-21 17:07:20 +00006421 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
bellard4136f332003-11-23 23:09:40 +00006422 }
bellard2c0262a2003-09-30 20:34:21 +00006423 }
6424 }
6425 gen_pop_update(s);
6426 s->cc_op = CC_OP_EFLAGS;
6427 /* abort translation because TF flag may change */
bellard14ce26e2005-01-03 23:50:08 +00006428 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00006429 gen_eob(s);
6430 }
6431 break;
6432 case 0x9e: /* sahf */
bellard12e26b72008-05-22 10:13:38 +00006433 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
bellard14ce26e2005-01-03 23:50:08 +00006434 goto illegal_op;
bellard57fec1f2008-02-01 10:50:11 +00006435 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
bellard2c0262a2003-09-30 20:34:21 +00006436 if (s->cc_op != CC_OP_DYNAMIC)
6437 gen_op_set_cc_op(s->cc_op);
bellardbd7a7b32008-05-21 17:07:20 +00006438 gen_compute_eflags(cpu_cc_src);
6439 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6440 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6441 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00006442 s->cc_op = CC_OP_EFLAGS;
6443 break;
6444 case 0x9f: /* lahf */
bellard12e26b72008-05-22 10:13:38 +00006445 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
bellard14ce26e2005-01-03 23:50:08 +00006446 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006447 if (s->cc_op != CC_OP_DYNAMIC)
6448 gen_op_set_cc_op(s->cc_op);
bellardbd7a7b32008-05-21 17:07:20 +00006449 gen_compute_eflags(cpu_T[0]);
6450 /* Note: gen_compute_eflags() only gives the condition codes */
6451 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
bellard57fec1f2008-02-01 10:50:11 +00006452 gen_op_mov_reg_T0(OT_BYTE, R_AH);
bellard2c0262a2003-09-30 20:34:21 +00006453 break;
6454 case 0xf5: /* cmc */
6455 if (s->cc_op != CC_OP_DYNAMIC)
6456 gen_op_set_cc_op(s->cc_op);
bellardbd7a7b32008-05-21 17:07:20 +00006457 gen_compute_eflags(cpu_cc_src);
6458 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
bellard2c0262a2003-09-30 20:34:21 +00006459 s->cc_op = CC_OP_EFLAGS;
6460 break;
6461 case 0xf8: /* clc */
6462 if (s->cc_op != CC_OP_DYNAMIC)
6463 gen_op_set_cc_op(s->cc_op);
bellardbd7a7b32008-05-21 17:07:20 +00006464 gen_compute_eflags(cpu_cc_src);
6465 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
bellard2c0262a2003-09-30 20:34:21 +00006466 s->cc_op = CC_OP_EFLAGS;
6467 break;
6468 case 0xf9: /* stc */
6469 if (s->cc_op != CC_OP_DYNAMIC)
6470 gen_op_set_cc_op(s->cc_op);
bellardbd7a7b32008-05-21 17:07:20 +00006471 gen_compute_eflags(cpu_cc_src);
6472 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
bellard2c0262a2003-09-30 20:34:21 +00006473 s->cc_op = CC_OP_EFLAGS;
6474 break;
6475 case 0xfc: /* cld */
bellardb6abf972008-05-17 12:44:31 +00006476 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6477 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
bellard2c0262a2003-09-30 20:34:21 +00006478 break;
6479 case 0xfd: /* std */
bellardb6abf972008-05-17 12:44:31 +00006480 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6481 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
bellard2c0262a2003-09-30 20:34:21 +00006482 break;
6483
6484 /************************/
6485 /* bit operations */
6486 case 0x1ba: /* bt/bts/btr/btc Gv, im */
bellard14ce26e2005-01-03 23:50:08 +00006487 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00006488 modrm = ldub_code(s->pc++);
bellard33698e52006-04-02 19:13:41 +00006489 op = (modrm >> 3) & 7;
bellard2c0262a2003-09-30 20:34:21 +00006490 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00006491 rm = (modrm & 7) | REX_B(s);
bellard2c0262a2003-09-30 20:34:21 +00006492 if (mod != 3) {
bellard14ce26e2005-01-03 23:50:08 +00006493 s->rip_offset = 1;
bellard2c0262a2003-09-30 20:34:21 +00006494 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00006495 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00006496 } else {
bellard57fec1f2008-02-01 10:50:11 +00006497 gen_op_mov_TN_reg(ot, 0, rm);
bellard2c0262a2003-09-30 20:34:21 +00006498 }
6499 /* load shift */
bellard61382a52003-10-27 21:22:23 +00006500 val = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00006501 gen_op_movl_T1_im(val);
6502 if (op < 4)
6503 goto illegal_op;
6504 op -= 4;
bellardf484d382008-05-17 16:10:38 +00006505 goto bt_op;
bellard2c0262a2003-09-30 20:34:21 +00006506 case 0x1a3: /* bt Gv, Ev */
6507 op = 0;
6508 goto do_btx;
6509 case 0x1ab: /* bts */
6510 op = 1;
6511 goto do_btx;
6512 case 0x1b3: /* btr */
6513 op = 2;
6514 goto do_btx;
6515 case 0x1bb: /* btc */
6516 op = 3;
6517 do_btx:
bellard14ce26e2005-01-03 23:50:08 +00006518 ot = dflag + OT_WORD;
bellard61382a52003-10-27 21:22:23 +00006519 modrm = ldub_code(s->pc++);
bellard14ce26e2005-01-03 23:50:08 +00006520 reg = ((modrm >> 3) & 7) | rex_r;
bellard2c0262a2003-09-30 20:34:21 +00006521 mod = (modrm >> 6) & 3;
bellard14ce26e2005-01-03 23:50:08 +00006522 rm = (modrm & 7) | REX_B(s);
bellard57fec1f2008-02-01 10:50:11 +00006523 gen_op_mov_TN_reg(OT_LONG, 1, reg);
bellard2c0262a2003-09-30 20:34:21 +00006524 if (mod != 3) {
6525 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6526 /* specific case: we need to add a displacement */
bellardf484d382008-05-17 16:10:38 +00006527 gen_exts(ot, cpu_T[1]);
6528 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6529 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6530 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
bellard57fec1f2008-02-01 10:50:11 +00006531 gen_op_ld_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00006532 } else {
bellard57fec1f2008-02-01 10:50:11 +00006533 gen_op_mov_TN_reg(ot, 0, rm);
bellard2c0262a2003-09-30 20:34:21 +00006534 }
bellardf484d382008-05-17 16:10:38 +00006535 bt_op:
6536 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6537 switch(op) {
6538 case 0:
6539 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6540 tcg_gen_movi_tl(cpu_cc_dst, 0);
6541 break;
6542 case 1:
6543 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6544 tcg_gen_movi_tl(cpu_tmp0, 1);
6545 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6546 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6547 break;
6548 case 2:
6549 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6550 tcg_gen_movi_tl(cpu_tmp0, 1);
6551 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6552 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6553 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6554 break;
6555 default:
6556 case 3:
6557 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6558 tcg_gen_movi_tl(cpu_tmp0, 1);
6559 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6560 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6561 break;
6562 }
bellard2c0262a2003-09-30 20:34:21 +00006563 s->cc_op = CC_OP_SARB + ot;
6564 if (op != 0) {
6565 if (mod != 3)
bellard57fec1f2008-02-01 10:50:11 +00006566 gen_op_st_T0_A0(ot + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00006567 else
bellard57fec1f2008-02-01 10:50:11 +00006568 gen_op_mov_reg_T0(ot, rm);
bellardf484d382008-05-17 16:10:38 +00006569 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6570 tcg_gen_movi_tl(cpu_cc_dst, 0);
bellard2c0262a2003-09-30 20:34:21 +00006571 }
6572 break;
6573 case 0x1bc: /* bsf */
6574 case 0x1bd: /* bsr */
bellard6191b052008-05-17 18:44:58 +00006575 {
6576 int label1;
bellard1e4840b2008-05-25 17:26:41 +00006577 TCGv t0;
6578
bellard6191b052008-05-17 18:44:58 +00006579 ot = dflag + OT_WORD;
6580 modrm = ldub_code(s->pc++);
6581 reg = ((modrm >> 3) & 7) | rex_r;
Andre Przywara31501a72009-10-23 13:44:31 +02006582 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
bellard6191b052008-05-17 18:44:58 +00006583 gen_extu(ot, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00006584 t0 = tcg_temp_local_new();
bellard1e4840b2008-05-25 17:26:41 +00006585 tcg_gen_mov_tl(t0, cpu_T[0]);
Andre Przywara31501a72009-10-23 13:44:31 +02006586 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6587 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6588 switch(ot) {
6589 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6590 tcg_const_i32(16)); break;
6591 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6592 tcg_const_i32(32)); break;
6593 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6594 tcg_const_i32(64)); break;
6595 }
6596 gen_op_mov_reg_T0(ot, reg);
bellard6191b052008-05-17 18:44:58 +00006597 } else {
Andre Przywara31501a72009-10-23 13:44:31 +02006598 label1 = gen_new_label();
6599 tcg_gen_movi_tl(cpu_cc_dst, 0);
6600 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6601 if (b & 1) {
6602 gen_helper_bsr(cpu_T[0], t0);
6603 } else {
6604 gen_helper_bsf(cpu_T[0], t0);
6605 }
6606 gen_op_mov_reg_T0(ot, reg);
6607 tcg_gen_movi_tl(cpu_cc_dst, 1);
6608 gen_set_label(label1);
6609 tcg_gen_discard_tl(cpu_cc_src);
6610 s->cc_op = CC_OP_LOGICB + ot;
bellard6191b052008-05-17 18:44:58 +00006611 }
bellard1e4840b2008-05-25 17:26:41 +00006612 tcg_temp_free(t0);
bellard6191b052008-05-17 18:44:58 +00006613 }
bellard2c0262a2003-09-30 20:34:21 +00006614 break;
6615 /************************/
6616 /* bcd */
6617 case 0x27: /* daa */
bellard14ce26e2005-01-03 23:50:08 +00006618 if (CODE64(s))
6619 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006620 if (s->cc_op != CC_OP_DYNAMIC)
6621 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00006622 gen_helper_daa();
bellard2c0262a2003-09-30 20:34:21 +00006623 s->cc_op = CC_OP_EFLAGS;
6624 break;
6625 case 0x2f: /* das */
bellard14ce26e2005-01-03 23:50:08 +00006626 if (CODE64(s))
6627 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006628 if (s->cc_op != CC_OP_DYNAMIC)
6629 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00006630 gen_helper_das();
bellard2c0262a2003-09-30 20:34:21 +00006631 s->cc_op = CC_OP_EFLAGS;
6632 break;
6633 case 0x37: /* aaa */
bellard14ce26e2005-01-03 23:50:08 +00006634 if (CODE64(s))
6635 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006636 if (s->cc_op != CC_OP_DYNAMIC)
6637 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00006638 gen_helper_aaa();
bellard2c0262a2003-09-30 20:34:21 +00006639 s->cc_op = CC_OP_EFLAGS;
6640 break;
6641 case 0x3f: /* aas */
bellard14ce26e2005-01-03 23:50:08 +00006642 if (CODE64(s))
6643 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006644 if (s->cc_op != CC_OP_DYNAMIC)
6645 gen_op_set_cc_op(s->cc_op);
pbrooka7812ae2008-11-17 14:43:54 +00006646 gen_helper_aas();
bellard2c0262a2003-09-30 20:34:21 +00006647 s->cc_op = CC_OP_EFLAGS;
6648 break;
6649 case 0xd4: /* aam */
bellard14ce26e2005-01-03 23:50:08 +00006650 if (CODE64(s))
6651 goto illegal_op;
bellard61382a52003-10-27 21:22:23 +00006652 val = ldub_code(s->pc++);
thsb6d7c3d2007-06-23 18:21:26 +00006653 if (val == 0) {
6654 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6655 } else {
pbrooka7812ae2008-11-17 14:43:54 +00006656 gen_helper_aam(tcg_const_i32(val));
thsb6d7c3d2007-06-23 18:21:26 +00006657 s->cc_op = CC_OP_LOGICB;
6658 }
bellard2c0262a2003-09-30 20:34:21 +00006659 break;
6660 case 0xd5: /* aad */
bellard14ce26e2005-01-03 23:50:08 +00006661 if (CODE64(s))
6662 goto illegal_op;
bellard61382a52003-10-27 21:22:23 +00006663 val = ldub_code(s->pc++);
pbrooka7812ae2008-11-17 14:43:54 +00006664 gen_helper_aad(tcg_const_i32(val));
bellard2c0262a2003-09-30 20:34:21 +00006665 s->cc_op = CC_OP_LOGICB;
6666 break;
6667 /************************/
6668 /* misc */
6669 case 0x90: /* nop */
bellardab1f1422004-01-19 20:31:37 +00006670 /* XXX: correct lock test for all insn */
Richard Henderson74180272010-07-01 09:42:21 -07006671 if (prefixes & PREFIX_LOCK) {
bellardab1f1422004-01-19 20:31:37 +00006672 goto illegal_op;
Richard Henderson74180272010-07-01 09:42:21 -07006673 }
6674 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6675 if (REX_B(s)) {
6676 goto do_xchg_reg_eax;
6677 }
ths0573fbf2007-09-23 15:28:04 +00006678 if (prefixes & PREFIX_REPZ) {
6679 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6680 }
bellard2c0262a2003-09-30 20:34:21 +00006681 break;
6682 case 0x9b: /* fwait */
ths5fafdf22007-09-16 21:08:06 +00006683 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
bellard7eee2a52004-02-25 23:17:58 +00006684 (HF_MP_MASK | HF_TS_MASK)) {
6685 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
bellard2ee73ac2004-05-08 21:08:41 +00006686 } else {
6687 if (s->cc_op != CC_OP_DYNAMIC)
6688 gen_op_set_cc_op(s->cc_op);
bellard14ce26e2005-01-03 23:50:08 +00006689 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006690 gen_helper_fwait();
bellard7eee2a52004-02-25 23:17:58 +00006691 }
bellard2c0262a2003-09-30 20:34:21 +00006692 break;
6693 case 0xcc: /* int3 */
6694 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6695 break;
6696 case 0xcd: /* int N */
bellard61382a52003-10-27 21:22:23 +00006697 val = ldub_code(s->pc++);
bellardf115e912003-11-13 01:43:28 +00006698 if (s->vm86 && s->iopl != 3) {
ths5fafdf22007-09-16 21:08:06 +00006699 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
bellardf115e912003-11-13 01:43:28 +00006700 } else {
6701 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6702 }
bellard2c0262a2003-09-30 20:34:21 +00006703 break;
6704 case 0xce: /* into */
bellard14ce26e2005-01-03 23:50:08 +00006705 if (CODE64(s))
6706 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006707 if (s->cc_op != CC_OP_DYNAMIC)
6708 gen_op_set_cc_op(s->cc_op);
bellarda8ede8b2005-01-06 20:46:58 +00006709 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006710 gen_helper_into(tcg_const_i32(s->pc - pc_start));
bellard2c0262a2003-09-30 20:34:21 +00006711 break;
aurel320b971342008-12-07 18:15:36 +00006712#ifdef WANT_ICEBP
bellard2c0262a2003-09-30 20:34:21 +00006713 case 0xf1: /* icebp (undocumented, exits to external debugger) */
bellard872929a2008-05-28 16:16:54 +00006714 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
bellardaba9d612005-04-23 17:53:12 +00006715#if 1
bellard2c0262a2003-09-30 20:34:21 +00006716 gen_debug(s, pc_start - s->cs_base);
bellardaba9d612005-04-23 17:53:12 +00006717#else
6718 /* start debug */
6719 tb_flush(cpu_single_env);
6720 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6721#endif
bellard2c0262a2003-09-30 20:34:21 +00006722 break;
aurel320b971342008-12-07 18:15:36 +00006723#endif
bellard2c0262a2003-09-30 20:34:21 +00006724 case 0xfa: /* cli */
6725 if (!s->vm86) {
6726 if (s->cpl <= s->iopl) {
pbrooka7812ae2008-11-17 14:43:54 +00006727 gen_helper_cli();
bellard2c0262a2003-09-30 20:34:21 +00006728 } else {
6729 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6730 }
6731 } else {
6732 if (s->iopl == 3) {
pbrooka7812ae2008-11-17 14:43:54 +00006733 gen_helper_cli();
bellard2c0262a2003-09-30 20:34:21 +00006734 } else {
6735 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6736 }
6737 }
6738 break;
6739 case 0xfb: /* sti */
6740 if (!s->vm86) {
6741 if (s->cpl <= s->iopl) {
6742 gen_sti:
pbrooka7812ae2008-11-17 14:43:54 +00006743 gen_helper_sti();
bellard2c0262a2003-09-30 20:34:21 +00006744 /* interruptions are enabled only the first insn after sti */
bellarda2cc3b22003-11-19 22:08:13 +00006745 /* If several instructions disable interrupts, only the
6746 _first_ does it */
6747 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
pbrooka7812ae2008-11-17 14:43:54 +00006748 gen_helper_set_inhibit_irq();
bellard2c0262a2003-09-30 20:34:21 +00006749 /* give a chance to handle pending irqs */
bellard14ce26e2005-01-03 23:50:08 +00006750 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00006751 gen_eob(s);
6752 } else {
6753 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6754 }
6755 } else {
6756 if (s->iopl == 3) {
6757 goto gen_sti;
6758 } else {
6759 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6760 }
6761 }
6762 break;
6763 case 0x62: /* bound */
bellard14ce26e2005-01-03 23:50:08 +00006764 if (CODE64(s))
6765 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006766 ot = dflag ? OT_LONG : OT_WORD;
bellard61382a52003-10-27 21:22:23 +00006767 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00006768 reg = (modrm >> 3) & 7;
6769 mod = (modrm >> 6) & 3;
6770 if (mod == 3)
6771 goto illegal_op;
bellard57fec1f2008-02-01 10:50:11 +00006772 gen_op_mov_TN_reg(ot, 0, reg);
bellard2c0262a2003-09-30 20:34:21 +00006773 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard14ce26e2005-01-03 23:50:08 +00006774 gen_jmp_im(pc_start - s->cs_base);
bellardb6abf972008-05-17 12:44:31 +00006775 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
bellard2c0262a2003-09-30 20:34:21 +00006776 if (ot == OT_WORD)
pbrooka7812ae2008-11-17 14:43:54 +00006777 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00006778 else
pbrooka7812ae2008-11-17 14:43:54 +00006779 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00006780 break;
6781 case 0x1c8 ... 0x1cf: /* bswap reg */
bellard14ce26e2005-01-03 23:50:08 +00006782 reg = (b & 7) | REX_B(s);
6783#ifdef TARGET_X86_64
6784 if (dflag == 2) {
bellard57fec1f2008-02-01 10:50:11 +00006785 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
aurel3266896cb2009-03-13 09:34:48 +00006786 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
bellard57fec1f2008-02-01 10:50:11 +00006787 gen_op_mov_reg_T0(OT_QUAD, reg);
ths5fafdf22007-09-16 21:08:06 +00006788 } else
bellard57fec1f2008-02-01 10:50:11 +00006789#endif
aurel3287776432009-03-13 09:35:41 +00006790 {
6791 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6792 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6793 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6794 gen_op_mov_reg_T0(OT_LONG, reg);
6795 }
bellard2c0262a2003-09-30 20:34:21 +00006796 break;
6797 case 0xd6: /* salc */
bellard14ce26e2005-01-03 23:50:08 +00006798 if (CODE64(s))
6799 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006800 if (s->cc_op != CC_OP_DYNAMIC)
6801 gen_op_set_cc_op(s->cc_op);
bellardbd7a7b32008-05-21 17:07:20 +00006802 gen_compute_eflags_c(cpu_T[0]);
6803 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6804 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
bellard2c0262a2003-09-30 20:34:21 +00006805 break;
6806 case 0xe0: /* loopnz */
6807 case 0xe1: /* loopz */
bellard2c0262a2003-09-30 20:34:21 +00006808 case 0xe2: /* loop */
6809 case 0xe3: /* jecxz */
bellard14ce26e2005-01-03 23:50:08 +00006810 {
bellard6e0d8672008-05-18 19:28:26 +00006811 int l1, l2, l3;
bellard14ce26e2005-01-03 23:50:08 +00006812
6813 tval = (int8_t)insn_get(s, OT_BYTE);
6814 next_eip = s->pc - s->cs_base;
6815 tval += next_eip;
6816 if (s->dflag == 0)
6817 tval &= 0xffff;
ths3b46e622007-09-17 08:09:54 +00006818
bellard14ce26e2005-01-03 23:50:08 +00006819 l1 = gen_new_label();
6820 l2 = gen_new_label();
bellard6e0d8672008-05-18 19:28:26 +00006821 l3 = gen_new_label();
bellard14ce26e2005-01-03 23:50:08 +00006822 b &= 3;
bellard6e0d8672008-05-18 19:28:26 +00006823 switch(b) {
6824 case 0: /* loopnz */
6825 case 1: /* loopz */
6826 if (s->cc_op != CC_OP_DYNAMIC)
6827 gen_op_set_cc_op(s->cc_op);
6828 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6829 gen_op_jz_ecx(s->aflag, l3);
6830 gen_compute_eflags(cpu_tmp0);
6831 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6832 if (b == 0) {
pbrookcb636692008-05-24 02:22:00 +00006833 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
bellard6e0d8672008-05-18 19:28:26 +00006834 } else {
pbrookcb636692008-05-24 02:22:00 +00006835 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
bellard6e0d8672008-05-18 19:28:26 +00006836 }
6837 break;
6838 case 2: /* loop */
6839 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6840 gen_op_jnz_ecx(s->aflag, l1);
6841 break;
6842 default:
6843 case 3: /* jcxz */
6844 gen_op_jz_ecx(s->aflag, l1);
6845 break;
bellard14ce26e2005-01-03 23:50:08 +00006846 }
6847
bellard6e0d8672008-05-18 19:28:26 +00006848 gen_set_label(l3);
bellard14ce26e2005-01-03 23:50:08 +00006849 gen_jmp_im(next_eip);
bellard8e1c85e2008-05-21 19:16:45 +00006850 tcg_gen_br(l2);
bellard6e0d8672008-05-18 19:28:26 +00006851
bellard14ce26e2005-01-03 23:50:08 +00006852 gen_set_label(l1);
6853 gen_jmp_im(tval);
6854 gen_set_label(l2);
6855 gen_eob(s);
6856 }
bellard2c0262a2003-09-30 20:34:21 +00006857 break;
6858 case 0x130: /* wrmsr */
6859 case 0x132: /* rdmsr */
6860 if (s->cpl != 0) {
6861 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6862 } else {
bellard872929a2008-05-28 16:16:54 +00006863 if (s->cc_op != CC_OP_DYNAMIC)
6864 gen_op_set_cc_op(s->cc_op);
6865 gen_jmp_im(pc_start - s->cs_base);
ths0573fbf2007-09-23 15:28:04 +00006866 if (b & 2) {
pbrooka7812ae2008-11-17 14:43:54 +00006867 gen_helper_rdmsr();
ths0573fbf2007-09-23 15:28:04 +00006868 } else {
pbrooka7812ae2008-11-17 14:43:54 +00006869 gen_helper_wrmsr();
ths0573fbf2007-09-23 15:28:04 +00006870 }
bellard2c0262a2003-09-30 20:34:21 +00006871 }
6872 break;
6873 case 0x131: /* rdtsc */
bellard872929a2008-05-28 16:16:54 +00006874 if (s->cc_op != CC_OP_DYNAMIC)
6875 gen_op_set_cc_op(s->cc_op);
bellardecada8a2005-08-21 10:28:44 +00006876 gen_jmp_im(pc_start - s->cs_base);
pbrookefade672008-06-30 17:51:26 +00006877 if (use_icount)
6878 gen_io_start();
pbrooka7812ae2008-11-17 14:43:54 +00006879 gen_helper_rdtsc();
pbrookefade672008-06-30 17:51:26 +00006880 if (use_icount) {
6881 gen_io_end();
6882 gen_jmp(s, s->pc - s->cs_base);
6883 }
bellard2c0262a2003-09-30 20:34:21 +00006884 break;
balrogdf01e0f2007-12-09 23:35:27 +00006885 case 0x133: /* rdpmc */
bellard872929a2008-05-28 16:16:54 +00006886 if (s->cc_op != CC_OP_DYNAMIC)
6887 gen_op_set_cc_op(s->cc_op);
balrogdf01e0f2007-12-09 23:35:27 +00006888 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006889 gen_helper_rdpmc();
balrogdf01e0f2007-12-09 23:35:27 +00006890 break;
bellard023fe102004-05-29 11:08:52 +00006891 case 0x134: /* sysenter */
balrog2436b612008-09-25 18:16:18 +00006892 /* For Intel SYSENTER is valid on 64-bit */
6893 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
bellard14ce26e2005-01-03 23:50:08 +00006894 goto illegal_op;
bellard023fe102004-05-29 11:08:52 +00006895 if (!s->pe) {
6896 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6897 } else {
Jun Koi728d8032010-07-25 12:30:03 +09006898 gen_update_cc_op(s);
bellard14ce26e2005-01-03 23:50:08 +00006899 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006900 gen_helper_sysenter();
bellard023fe102004-05-29 11:08:52 +00006901 gen_eob(s);
6902 }
6903 break;
6904 case 0x135: /* sysexit */
balrog2436b612008-09-25 18:16:18 +00006905 /* For Intel SYSEXIT is valid on 64-bit */
6906 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
bellard14ce26e2005-01-03 23:50:08 +00006907 goto illegal_op;
bellard023fe102004-05-29 11:08:52 +00006908 if (!s->pe) {
6909 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6910 } else {
Jun Koi728d8032010-07-25 12:30:03 +09006911 gen_update_cc_op(s);
bellard14ce26e2005-01-03 23:50:08 +00006912 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006913 gen_helper_sysexit(tcg_const_i32(dflag));
bellard023fe102004-05-29 11:08:52 +00006914 gen_eob(s);
6915 }
6916 break;
bellard14ce26e2005-01-03 23:50:08 +00006917#ifdef TARGET_X86_64
6918 case 0x105: /* syscall */
6919 /* XXX: is it usable in real mode ? */
Jun Koi728d8032010-07-25 12:30:03 +09006920 gen_update_cc_op(s);
bellard14ce26e2005-01-03 23:50:08 +00006921 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006922 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
bellard14ce26e2005-01-03 23:50:08 +00006923 gen_eob(s);
6924 break;
6925 case 0x107: /* sysret */
6926 if (!s->pe) {
6927 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6928 } else {
Jun Koi728d8032010-07-25 12:30:03 +09006929 gen_update_cc_op(s);
bellard14ce26e2005-01-03 23:50:08 +00006930 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006931 gen_helper_sysret(tcg_const_i32(s->dflag));
bellardaba9d612005-04-23 17:53:12 +00006932 /* condition codes are modified only in long mode */
6933 if (s->lma)
6934 s->cc_op = CC_OP_EFLAGS;
bellard14ce26e2005-01-03 23:50:08 +00006935 gen_eob(s);
6936 }
6937 break;
6938#endif
bellard2c0262a2003-09-30 20:34:21 +00006939 case 0x1a2: /* cpuid */
bellard9575cb92008-06-04 17:12:40 +00006940 if (s->cc_op != CC_OP_DYNAMIC)
6941 gen_op_set_cc_op(s->cc_op);
6942 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006943 gen_helper_cpuid();
bellard2c0262a2003-09-30 20:34:21 +00006944 break;
6945 case 0xf4: /* hlt */
6946 if (s->cpl != 0) {
6947 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6948 } else {
6949 if (s->cc_op != CC_OP_DYNAMIC)
6950 gen_op_set_cc_op(s->cc_op);
bellard94451172008-06-18 09:32:32 +00006951 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00006952 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
Jun Koi57794062010-07-24 00:17:00 +09006953 s->is_jmp = DISAS_TB_JUMP;
bellard2c0262a2003-09-30 20:34:21 +00006954 }
6955 break;
6956 case 0x100:
bellard61382a52003-10-27 21:22:23 +00006957 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00006958 mod = (modrm >> 6) & 3;
6959 op = (modrm >> 3) & 7;
6960 switch(op) {
6961 case 0: /* sldt */
bellardf115e912003-11-13 01:43:28 +00006962 if (!s->pe || s->vm86)
6963 goto illegal_op;
bellard872929a2008-05-28 16:16:54 +00006964 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
bellard651ba602008-05-21 17:16:11 +00006965 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
bellard2c0262a2003-09-30 20:34:21 +00006966 ot = OT_WORD;
6967 if (mod == 3)
6968 ot += s->dflag;
6969 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6970 break;
6971 case 2: /* lldt */
bellardf115e912003-11-13 01:43:28 +00006972 if (!s->pe || s->vm86)
6973 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006974 if (s->cpl != 0) {
6975 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6976 } else {
bellard872929a2008-05-28 16:16:54 +00006977 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
bellard2c0262a2003-09-30 20:34:21 +00006978 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
bellard14ce26e2005-01-03 23:50:08 +00006979 gen_jmp_im(pc_start - s->cs_base);
bellardb6abf972008-05-17 12:44:31 +00006980 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00006981 gen_helper_lldt(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00006982 }
6983 break;
6984 case 1: /* str */
bellardf115e912003-11-13 01:43:28 +00006985 if (!s->pe || s->vm86)
6986 goto illegal_op;
bellard872929a2008-05-28 16:16:54 +00006987 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
bellard651ba602008-05-21 17:16:11 +00006988 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
bellard2c0262a2003-09-30 20:34:21 +00006989 ot = OT_WORD;
6990 if (mod == 3)
6991 ot += s->dflag;
6992 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6993 break;
6994 case 3: /* ltr */
bellardf115e912003-11-13 01:43:28 +00006995 if (!s->pe || s->vm86)
6996 goto illegal_op;
bellard2c0262a2003-09-30 20:34:21 +00006997 if (s->cpl != 0) {
6998 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6999 } else {
bellard872929a2008-05-28 16:16:54 +00007000 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
bellard2c0262a2003-09-30 20:34:21 +00007001 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
bellard14ce26e2005-01-03 23:50:08 +00007002 gen_jmp_im(pc_start - s->cs_base);
bellardb6abf972008-05-17 12:44:31 +00007003 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
pbrooka7812ae2008-11-17 14:43:54 +00007004 gen_helper_ltr(cpu_tmp2_i32);
bellard2c0262a2003-09-30 20:34:21 +00007005 }
7006 break;
7007 case 4: /* verr */
7008 case 5: /* verw */
bellardf115e912003-11-13 01:43:28 +00007009 if (!s->pe || s->vm86)
7010 goto illegal_op;
7011 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7012 if (s->cc_op != CC_OP_DYNAMIC)
7013 gen_op_set_cc_op(s->cc_op);
7014 if (op == 4)
pbrooka7812ae2008-11-17 14:43:54 +00007015 gen_helper_verr(cpu_T[0]);
bellardf115e912003-11-13 01:43:28 +00007016 else
pbrooka7812ae2008-11-17 14:43:54 +00007017 gen_helper_verw(cpu_T[0]);
bellardf115e912003-11-13 01:43:28 +00007018 s->cc_op = CC_OP_EFLAGS;
7019 break;
bellard2c0262a2003-09-30 20:34:21 +00007020 default:
7021 goto illegal_op;
7022 }
7023 break;
7024 case 0x101:
bellard61382a52003-10-27 21:22:23 +00007025 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00007026 mod = (modrm >> 6) & 3;
7027 op = (modrm >> 3) & 7;
bellard3d7374c2006-07-10 19:53:04 +00007028 rm = modrm & 7;
bellard2c0262a2003-09-30 20:34:21 +00007029 switch(op) {
7030 case 0: /* sgdt */
bellard2c0262a2003-09-30 20:34:21 +00007031 if (mod == 3)
7032 goto illegal_op;
bellard872929a2008-05-28 16:16:54 +00007033 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
bellard2c0262a2003-09-30 20:34:21 +00007034 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard651ba602008-05-21 17:16:11 +00007035 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
bellard57fec1f2008-02-01 10:50:11 +00007036 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellardaba9d612005-04-23 17:53:12 +00007037 gen_add_A0_im(s, 2);
bellard651ba602008-05-21 17:16:11 +00007038 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
bellard2c0262a2003-09-30 20:34:21 +00007039 if (!s->dflag)
7040 gen_op_andl_T0_im(0xffffff);
bellard57fec1f2008-02-01 10:50:11 +00007041 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00007042 break;
bellard3d7374c2006-07-10 19:53:04 +00007043 case 1:
7044 if (mod == 3) {
7045 switch (rm) {
7046 case 0: /* monitor */
7047 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7048 s->cpl != 0)
7049 goto illegal_op;
bellard94451172008-06-18 09:32:32 +00007050 if (s->cc_op != CC_OP_DYNAMIC)
7051 gen_op_set_cc_op(s->cc_op);
bellard3d7374c2006-07-10 19:53:04 +00007052 gen_jmp_im(pc_start - s->cs_base);
7053#ifdef TARGET_X86_64
7054 if (s->aflag == 2) {
bellardbbf662e2008-05-17 19:05:28 +00007055 gen_op_movq_A0_reg(R_EAX);
ths5fafdf22007-09-16 21:08:06 +00007056 } else
bellard3d7374c2006-07-10 19:53:04 +00007057#endif
7058 {
bellardbbf662e2008-05-17 19:05:28 +00007059 gen_op_movl_A0_reg(R_EAX);
bellard3d7374c2006-07-10 19:53:04 +00007060 if (s->aflag == 0)
7061 gen_op_andl_A0_ffff();
7062 }
7063 gen_add_A0_ds_seg(s);
pbrooka7812ae2008-11-17 14:43:54 +00007064 gen_helper_monitor(cpu_A0);
bellard3d7374c2006-07-10 19:53:04 +00007065 break;
7066 case 1: /* mwait */
7067 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7068 s->cpl != 0)
7069 goto illegal_op;
Jun Koi728d8032010-07-25 12:30:03 +09007070 gen_update_cc_op(s);
bellard94451172008-06-18 09:32:32 +00007071 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00007072 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
bellard3d7374c2006-07-10 19:53:04 +00007073 gen_eob(s);
7074 break;
7075 default:
7076 goto illegal_op;
7077 }
7078 } else { /* sidt */
bellard872929a2008-05-28 16:16:54 +00007079 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
bellard3d7374c2006-07-10 19:53:04 +00007080 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard651ba602008-05-21 17:16:11 +00007081 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
bellard57fec1f2008-02-01 10:50:11 +00007082 gen_op_st_T0_A0(OT_WORD + s->mem_index);
bellard3d7374c2006-07-10 19:53:04 +00007083 gen_add_A0_im(s, 2);
bellard651ba602008-05-21 17:16:11 +00007084 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
bellard3d7374c2006-07-10 19:53:04 +00007085 if (!s->dflag)
7086 gen_op_andl_T0_im(0xffffff);
bellard57fec1f2008-02-01 10:50:11 +00007087 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
bellard3d7374c2006-07-10 19:53:04 +00007088 }
7089 break;
bellard2c0262a2003-09-30 20:34:21 +00007090 case 2: /* lgdt */
7091 case 3: /* lidt */
ths0573fbf2007-09-23 15:28:04 +00007092 if (mod == 3) {
bellard872929a2008-05-28 16:16:54 +00007093 if (s->cc_op != CC_OP_DYNAMIC)
7094 gen_op_set_cc_op(s->cc_op);
7095 gen_jmp_im(pc_start - s->cs_base);
ths0573fbf2007-09-23 15:28:04 +00007096 switch(rm) {
7097 case 0: /* VMRUN */
bellard872929a2008-05-28 16:16:54 +00007098 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7099 goto illegal_op;
7100 if (s->cpl != 0) {
7101 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
ths0573fbf2007-09-23 15:28:04 +00007102 break;
bellard872929a2008-05-28 16:16:54 +00007103 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007104 gen_helper_vmrun(tcg_const_i32(s->aflag),
7105 tcg_const_i32(s->pc - pc_start));
bellarddb620f42008-06-04 17:02:19 +00007106 tcg_gen_exit_tb(0);
Jun Koi57794062010-07-24 00:17:00 +09007107 s->is_jmp = DISAS_TB_JUMP;
bellard872929a2008-05-28 16:16:54 +00007108 }
ths0573fbf2007-09-23 15:28:04 +00007109 break;
7110 case 1: /* VMMCALL */
bellard872929a2008-05-28 16:16:54 +00007111 if (!(s->flags & HF_SVME_MASK))
7112 goto illegal_op;
pbrooka7812ae2008-11-17 14:43:54 +00007113 gen_helper_vmmcall();
ths0573fbf2007-09-23 15:28:04 +00007114 break;
7115 case 2: /* VMLOAD */
bellard872929a2008-05-28 16:16:54 +00007116 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7117 goto illegal_op;
7118 if (s->cpl != 0) {
7119 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7120 break;
7121 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007122 gen_helper_vmload(tcg_const_i32(s->aflag));
bellard872929a2008-05-28 16:16:54 +00007123 }
ths0573fbf2007-09-23 15:28:04 +00007124 break;
7125 case 3: /* VMSAVE */
bellard872929a2008-05-28 16:16:54 +00007126 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7127 goto illegal_op;
7128 if (s->cpl != 0) {
7129 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7130 break;
7131 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007132 gen_helper_vmsave(tcg_const_i32(s->aflag));
bellard872929a2008-05-28 16:16:54 +00007133 }
ths0573fbf2007-09-23 15:28:04 +00007134 break;
7135 case 4: /* STGI */
bellard872929a2008-05-28 16:16:54 +00007136 if ((!(s->flags & HF_SVME_MASK) &&
7137 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7138 !s->pe)
7139 goto illegal_op;
7140 if (s->cpl != 0) {
7141 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7142 break;
7143 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007144 gen_helper_stgi();
bellard872929a2008-05-28 16:16:54 +00007145 }
ths0573fbf2007-09-23 15:28:04 +00007146 break;
7147 case 5: /* CLGI */
bellard872929a2008-05-28 16:16:54 +00007148 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7149 goto illegal_op;
7150 if (s->cpl != 0) {
7151 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7152 break;
7153 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007154 gen_helper_clgi();
bellard872929a2008-05-28 16:16:54 +00007155 }
ths0573fbf2007-09-23 15:28:04 +00007156 break;
7157 case 6: /* SKINIT */
bellard872929a2008-05-28 16:16:54 +00007158 if ((!(s->flags & HF_SVME_MASK) &&
7159 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7160 !s->pe)
7161 goto illegal_op;
pbrooka7812ae2008-11-17 14:43:54 +00007162 gen_helper_skinit();
ths0573fbf2007-09-23 15:28:04 +00007163 break;
7164 case 7: /* INVLPGA */
bellard872929a2008-05-28 16:16:54 +00007165 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7166 goto illegal_op;
7167 if (s->cpl != 0) {
7168 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7169 break;
7170 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007171 gen_helper_invlpga(tcg_const_i32(s->aflag));
bellard872929a2008-05-28 16:16:54 +00007172 }
ths0573fbf2007-09-23 15:28:04 +00007173 break;
7174 default:
7175 goto illegal_op;
7176 }
7177 } else if (s->cpl != 0) {
bellard2c0262a2003-09-30 20:34:21 +00007178 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7179 } else {
bellard872929a2008-05-28 16:16:54 +00007180 gen_svm_check_intercept(s, pc_start,
7181 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
bellard2c0262a2003-09-30 20:34:21 +00007182 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard57fec1f2008-02-01 10:50:11 +00007183 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
bellardaba9d612005-04-23 17:53:12 +00007184 gen_add_A0_im(s, 2);
bellard57fec1f2008-02-01 10:50:11 +00007185 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
bellard2c0262a2003-09-30 20:34:21 +00007186 if (!s->dflag)
7187 gen_op_andl_T0_im(0xffffff);
7188 if (op == 2) {
bellard651ba602008-05-21 17:16:11 +00007189 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7190 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
bellard2c0262a2003-09-30 20:34:21 +00007191 } else {
bellard651ba602008-05-21 17:16:11 +00007192 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7193 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
bellard2c0262a2003-09-30 20:34:21 +00007194 }
7195 }
7196 break;
7197 case 4: /* smsw */
bellard872929a2008-05-28 16:16:54 +00007198 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
Juan Quintelae2542fe2009-07-27 16:13:06 +02007199#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
malcf60d2722008-12-13 15:51:14 +00007200 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7201#else
bellard651ba602008-05-21 17:16:11 +00007202 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
malcf60d2722008-12-13 15:51:14 +00007203#endif
bellard2c0262a2003-09-30 20:34:21 +00007204 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7205 break;
7206 case 6: /* lmsw */
7207 if (s->cpl != 0) {
7208 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7209 } else {
bellard872929a2008-05-28 16:16:54 +00007210 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
bellard2c0262a2003-09-30 20:34:21 +00007211 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
pbrooka7812ae2008-11-17 14:43:54 +00007212 gen_helper_lmsw(cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00007213 gen_jmp_im(s->pc - s->cs_base);
bellardd71b9a82003-11-13 02:48:18 +00007214 gen_eob(s);
bellard2c0262a2003-09-30 20:34:21 +00007215 }
7216 break;
Andre Przywara1b050072009-09-19 00:30:49 +02007217 case 7:
7218 if (mod != 3) { /* invlpg */
7219 if (s->cpl != 0) {
7220 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
bellard14ce26e2005-01-03 23:50:08 +00007221 } else {
bellard9575cb92008-06-04 17:12:40 +00007222 if (s->cc_op != CC_OP_DYNAMIC)
7223 gen_op_set_cc_op(s->cc_op);
7224 gen_jmp_im(pc_start - s->cs_base);
bellard14ce26e2005-01-03 23:50:08 +00007225 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
pbrooka7812ae2008-11-17 14:43:54 +00007226 gen_helper_invlpg(cpu_A0);
bellard14ce26e2005-01-03 23:50:08 +00007227 gen_jmp_im(s->pc - s->cs_base);
7228 gen_eob(s);
7229 }
Andre Przywara1b050072009-09-19 00:30:49 +02007230 } else {
7231 switch (rm) {
7232 case 0: /* swapgs */
7233#ifdef TARGET_X86_64
7234 if (CODE64(s)) {
7235 if (s->cpl != 0) {
7236 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7237 } else {
7238 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7239 offsetof(CPUX86State,segs[R_GS].base));
7240 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7241 offsetof(CPUX86State,kernelgsbase));
7242 tcg_gen_st_tl(cpu_T[1], cpu_env,
7243 offsetof(CPUX86State,segs[R_GS].base));
7244 tcg_gen_st_tl(cpu_T[0], cpu_env,
7245 offsetof(CPUX86State,kernelgsbase));
7246 }
7247 } else
7248#endif
7249 {
7250 goto illegal_op;
7251 }
7252 break;
7253 case 1: /* rdtscp */
7254 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7255 goto illegal_op;
7256 if (s->cc_op != CC_OP_DYNAMIC)
7257 gen_op_set_cc_op(s->cc_op);
7258 gen_jmp_im(pc_start - s->cs_base);
7259 if (use_icount)
7260 gen_io_start();
7261 gen_helper_rdtscp();
7262 if (use_icount) {
7263 gen_io_end();
7264 gen_jmp(s, s->pc - s->cs_base);
7265 }
7266 break;
7267 default:
7268 goto illegal_op;
7269 }
bellard2c0262a2003-09-30 20:34:21 +00007270 }
7271 break;
7272 default:
7273 goto illegal_op;
7274 }
7275 break;
bellard3415a4d2004-01-04 15:21:33 +00007276 case 0x108: /* invd */
7277 case 0x109: /* wbinvd */
7278 if (s->cpl != 0) {
7279 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7280 } else {
bellard872929a2008-05-28 16:16:54 +00007281 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
bellard3415a4d2004-01-04 15:21:33 +00007282 /* nothing to do */
7283 }
7284 break;
bellard14ce26e2005-01-03 23:50:08 +00007285 case 0x63: /* arpl or movslS (x86_64) */
7286#ifdef TARGET_X86_64
7287 if (CODE64(s)) {
7288 int d_ot;
7289 /* d_ot is the size of destination */
7290 d_ot = dflag + OT_WORD;
7291
7292 modrm = ldub_code(s->pc++);
7293 reg = ((modrm >> 3) & 7) | rex_r;
7294 mod = (modrm >> 6) & 3;
7295 rm = (modrm & 7) | REX_B(s);
ths3b46e622007-09-17 08:09:54 +00007296
bellard14ce26e2005-01-03 23:50:08 +00007297 if (mod == 3) {
bellard57fec1f2008-02-01 10:50:11 +00007298 gen_op_mov_TN_reg(OT_LONG, 0, rm);
bellard14ce26e2005-01-03 23:50:08 +00007299 /* sign extend */
7300 if (d_ot == OT_QUAD)
bellarde108dd02008-05-17 19:24:07 +00007301 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
bellard57fec1f2008-02-01 10:50:11 +00007302 gen_op_mov_reg_T0(d_ot, reg);
bellard14ce26e2005-01-03 23:50:08 +00007303 } else {
7304 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7305 if (d_ot == OT_QUAD) {
bellard57fec1f2008-02-01 10:50:11 +00007306 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
bellard14ce26e2005-01-03 23:50:08 +00007307 } else {
bellard57fec1f2008-02-01 10:50:11 +00007308 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellard14ce26e2005-01-03 23:50:08 +00007309 }
bellard57fec1f2008-02-01 10:50:11 +00007310 gen_op_mov_reg_T0(d_ot, reg);
bellard14ce26e2005-01-03 23:50:08 +00007311 }
ths5fafdf22007-09-16 21:08:06 +00007312 } else
bellard14ce26e2005-01-03 23:50:08 +00007313#endif
7314 {
bellard3bd7da92008-05-21 16:34:06 +00007315 int label1;
Laurent Desnogues49d9fdc2009-10-06 10:14:29 +02007316 TCGv t0, t1, t2, a0;
bellard1e4840b2008-05-25 17:26:41 +00007317
bellard14ce26e2005-01-03 23:50:08 +00007318 if (!s->pe || s->vm86)
7319 goto illegal_op;
pbrooka7812ae2008-11-17 14:43:54 +00007320 t0 = tcg_temp_local_new();
7321 t1 = tcg_temp_local_new();
7322 t2 = tcg_temp_local_new();
bellard3bd7da92008-05-21 16:34:06 +00007323 ot = OT_WORD;
bellard14ce26e2005-01-03 23:50:08 +00007324 modrm = ldub_code(s->pc++);
7325 reg = (modrm >> 3) & 7;
7326 mod = (modrm >> 6) & 3;
7327 rm = modrm & 7;
7328 if (mod != 3) {
7329 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard1e4840b2008-05-25 17:26:41 +00007330 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
Laurent Desnogues49d9fdc2009-10-06 10:14:29 +02007331 a0 = tcg_temp_local_new();
7332 tcg_gen_mov_tl(a0, cpu_A0);
bellard14ce26e2005-01-03 23:50:08 +00007333 } else {
bellard1e4840b2008-05-25 17:26:41 +00007334 gen_op_mov_v_reg(ot, t0, rm);
Laurent Desnogues49d9fdc2009-10-06 10:14:29 +02007335 TCGV_UNUSED(a0);
bellard14ce26e2005-01-03 23:50:08 +00007336 }
bellard1e4840b2008-05-25 17:26:41 +00007337 gen_op_mov_v_reg(ot, t1, reg);
7338 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7339 tcg_gen_andi_tl(t1, t1, 3);
7340 tcg_gen_movi_tl(t2, 0);
bellard3bd7da92008-05-21 16:34:06 +00007341 label1 = gen_new_label();
bellard1e4840b2008-05-25 17:26:41 +00007342 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7343 tcg_gen_andi_tl(t0, t0, ~3);
7344 tcg_gen_or_tl(t0, t0, t1);
7345 tcg_gen_movi_tl(t2, CC_Z);
bellard3bd7da92008-05-21 16:34:06 +00007346 gen_set_label(label1);
bellard14ce26e2005-01-03 23:50:08 +00007347 if (mod != 3) {
Laurent Desnogues49d9fdc2009-10-06 10:14:29 +02007348 gen_op_st_v(ot + s->mem_index, t0, a0);
7349 tcg_temp_free(a0);
7350 } else {
bellard1e4840b2008-05-25 17:26:41 +00007351 gen_op_mov_reg_v(ot, rm, t0);
bellard14ce26e2005-01-03 23:50:08 +00007352 }
bellard3bd7da92008-05-21 16:34:06 +00007353 if (s->cc_op != CC_OP_DYNAMIC)
7354 gen_op_set_cc_op(s->cc_op);
7355 gen_compute_eflags(cpu_cc_src);
7356 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
bellard1e4840b2008-05-25 17:26:41 +00007357 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
bellard3bd7da92008-05-21 16:34:06 +00007358 s->cc_op = CC_OP_EFLAGS;
bellard1e4840b2008-05-25 17:26:41 +00007359 tcg_temp_free(t0);
7360 tcg_temp_free(t1);
7361 tcg_temp_free(t2);
bellardf115e912003-11-13 01:43:28 +00007362 }
bellardf115e912003-11-13 01:43:28 +00007363 break;
bellard2c0262a2003-09-30 20:34:21 +00007364 case 0x102: /* lar */
7365 case 0x103: /* lsl */
bellardcec68432008-05-21 16:25:27 +00007366 {
7367 int label1;
bellard1e4840b2008-05-25 17:26:41 +00007368 TCGv t0;
bellardcec68432008-05-21 16:25:27 +00007369 if (!s->pe || s->vm86)
7370 goto illegal_op;
7371 ot = dflag ? OT_LONG : OT_WORD;
7372 modrm = ldub_code(s->pc++);
7373 reg = ((modrm >> 3) & 7) | rex_r;
7374 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
pbrooka7812ae2008-11-17 14:43:54 +00007375 t0 = tcg_temp_local_new();
bellardcec68432008-05-21 16:25:27 +00007376 if (s->cc_op != CC_OP_DYNAMIC)
7377 gen_op_set_cc_op(s->cc_op);
7378 if (b == 0x102)
pbrooka7812ae2008-11-17 14:43:54 +00007379 gen_helper_lar(t0, cpu_T[0]);
bellardcec68432008-05-21 16:25:27 +00007380 else
pbrooka7812ae2008-11-17 14:43:54 +00007381 gen_helper_lsl(t0, cpu_T[0]);
bellardcec68432008-05-21 16:25:27 +00007382 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7383 label1 = gen_new_label();
pbrookcb636692008-05-24 02:22:00 +00007384 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
bellard1e4840b2008-05-25 17:26:41 +00007385 gen_op_mov_reg_v(ot, reg, t0);
bellardcec68432008-05-21 16:25:27 +00007386 gen_set_label(label1);
7387 s->cc_op = CC_OP_EFLAGS;
bellard1e4840b2008-05-25 17:26:41 +00007388 tcg_temp_free(t0);
bellardcec68432008-05-21 16:25:27 +00007389 }
bellard2c0262a2003-09-30 20:34:21 +00007390 break;
7391 case 0x118:
bellard61382a52003-10-27 21:22:23 +00007392 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00007393 mod = (modrm >> 6) & 3;
7394 op = (modrm >> 3) & 7;
7395 switch(op) {
7396 case 0: /* prefetchnta */
7397 case 1: /* prefetchnt0 */
7398 case 2: /* prefetchnt0 */
7399 case 3: /* prefetchnt0 */
7400 if (mod == 3)
7401 goto illegal_op;
7402 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7403 /* nothing more to do */
7404 break;
bellarde17a36c2006-09-03 17:09:02 +00007405 default: /* nop (multi byte) */
7406 gen_nop_modrm(s, modrm);
7407 break;
bellard2c0262a2003-09-30 20:34:21 +00007408 }
7409 break;
bellarde17a36c2006-09-03 17:09:02 +00007410 case 0x119 ... 0x11f: /* nop (multi byte) */
7411 modrm = ldub_code(s->pc++);
7412 gen_nop_modrm(s, modrm);
7413 break;
bellard2c0262a2003-09-30 20:34:21 +00007414 case 0x120: /* mov reg, crN */
7415 case 0x122: /* mov crN, reg */
7416 if (s->cpl != 0) {
7417 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7418 } else {
bellard61382a52003-10-27 21:22:23 +00007419 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00007420 if ((modrm & 0xc0) != 0xc0)
7421 goto illegal_op;
bellard14ce26e2005-01-03 23:50:08 +00007422 rm = (modrm & 7) | REX_B(s);
7423 reg = ((modrm >> 3) & 7) | rex_r;
7424 if (CODE64(s))
7425 ot = OT_QUAD;
7426 else
7427 ot = OT_LONG;
Andre Przywaraccd59d02009-09-19 00:30:47 +02007428 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7429 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7430 reg = 8;
7431 }
bellard2c0262a2003-09-30 20:34:21 +00007432 switch(reg) {
7433 case 0:
7434 case 2:
7435 case 3:
7436 case 4:
bellard9230e662005-01-23 20:46:56 +00007437 case 8:
bellard872929a2008-05-28 16:16:54 +00007438 if (s->cc_op != CC_OP_DYNAMIC)
7439 gen_op_set_cc_op(s->cc_op);
7440 gen_jmp_im(pc_start - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00007441 if (b & 2) {
bellard57fec1f2008-02-01 10:50:11 +00007442 gen_op_mov_TN_reg(ot, 0, rm);
pbrooka7812ae2008-11-17 14:43:54 +00007443 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00007444 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00007445 gen_eob(s);
7446 } else {
pbrooka7812ae2008-11-17 14:43:54 +00007447 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
bellard57fec1f2008-02-01 10:50:11 +00007448 gen_op_mov_reg_T0(ot, rm);
bellard2c0262a2003-09-30 20:34:21 +00007449 }
7450 break;
7451 default:
7452 goto illegal_op;
7453 }
7454 }
7455 break;
7456 case 0x121: /* mov reg, drN */
7457 case 0x123: /* mov drN, reg */
7458 if (s->cpl != 0) {
7459 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7460 } else {
bellard61382a52003-10-27 21:22:23 +00007461 modrm = ldub_code(s->pc++);
bellard2c0262a2003-09-30 20:34:21 +00007462 if ((modrm & 0xc0) != 0xc0)
7463 goto illegal_op;
bellard14ce26e2005-01-03 23:50:08 +00007464 rm = (modrm & 7) | REX_B(s);
7465 reg = ((modrm >> 3) & 7) | rex_r;
7466 if (CODE64(s))
7467 ot = OT_QUAD;
7468 else
7469 ot = OT_LONG;
bellard2c0262a2003-09-30 20:34:21 +00007470 /* XXX: do it dynamically with CR4.DE bit */
bellard14ce26e2005-01-03 23:50:08 +00007471 if (reg == 4 || reg == 5 || reg >= 8)
bellard2c0262a2003-09-30 20:34:21 +00007472 goto illegal_op;
7473 if (b & 2) {
ths0573fbf2007-09-23 15:28:04 +00007474 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
bellard57fec1f2008-02-01 10:50:11 +00007475 gen_op_mov_TN_reg(ot, 0, rm);
pbrooka7812ae2008-11-17 14:43:54 +00007476 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
bellard14ce26e2005-01-03 23:50:08 +00007477 gen_jmp_im(s->pc - s->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00007478 gen_eob(s);
7479 } else {
ths0573fbf2007-09-23 15:28:04 +00007480 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
bellard651ba602008-05-21 17:16:11 +00007481 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
bellard57fec1f2008-02-01 10:50:11 +00007482 gen_op_mov_reg_T0(ot, rm);
bellard2c0262a2003-09-30 20:34:21 +00007483 }
7484 }
7485 break;
7486 case 0x106: /* clts */
7487 if (s->cpl != 0) {
7488 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7489 } else {
ths0573fbf2007-09-23 15:28:04 +00007490 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
pbrooka7812ae2008-11-17 14:43:54 +00007491 gen_helper_clts();
bellard7eee2a52004-02-25 23:17:58 +00007492 /* abort block because static cpu state changed */
bellard14ce26e2005-01-03 23:50:08 +00007493 gen_jmp_im(s->pc - s->cs_base);
bellard7eee2a52004-02-25 23:17:58 +00007494 gen_eob(s);
bellard2c0262a2003-09-30 20:34:21 +00007495 }
7496 break;
balrog222a3332008-10-04 03:27:44 +00007497 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
bellard664e0f12005-01-08 18:58:29 +00007498 case 0x1c3: /* MOVNTI reg, mem */
7499 if (!(s->cpuid_features & CPUID_SSE2))
7500 goto illegal_op;
7501 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7502 modrm = ldub_code(s->pc++);
7503 mod = (modrm >> 6) & 3;
7504 if (mod == 3)
7505 goto illegal_op;
7506 reg = ((modrm >> 3) & 7) | rex_r;
7507 /* generate a generic store */
7508 gen_ldst_modrm(s, modrm, ot, reg, 1);
7509 break;
7510 case 0x1ae:
7511 modrm = ldub_code(s->pc++);
7512 mod = (modrm >> 6) & 3;
7513 op = (modrm >> 3) & 7;
7514 switch(op) {
7515 case 0: /* fxsave */
ths5fafdf22007-09-16 21:08:06 +00007516 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
Kevin Wolf09d85fb2009-10-02 22:28:57 +02007517 (s->prefix & PREFIX_LOCK))
bellard14ce26e2005-01-03 23:50:08 +00007518 goto illegal_op;
Kevin Wolf09d85fb2009-10-02 22:28:57 +02007519 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
bellard0fd14b72006-02-04 17:40:20 +00007520 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7521 break;
7522 }
bellard664e0f12005-01-08 18:58:29 +00007523 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard19e6c4b2008-05-12 19:10:44 +00007524 if (s->cc_op != CC_OP_DYNAMIC)
7525 gen_op_set_cc_op(s->cc_op);
7526 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00007527 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
bellard664e0f12005-01-08 18:58:29 +00007528 break;
7529 case 1: /* fxrstor */
ths5fafdf22007-09-16 21:08:06 +00007530 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
Kevin Wolf09d85fb2009-10-02 22:28:57 +02007531 (s->prefix & PREFIX_LOCK))
bellard664e0f12005-01-08 18:58:29 +00007532 goto illegal_op;
Kevin Wolf09d85fb2009-10-02 22:28:57 +02007533 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
bellard0fd14b72006-02-04 17:40:20 +00007534 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7535 break;
7536 }
bellard664e0f12005-01-08 18:58:29 +00007537 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
bellard19e6c4b2008-05-12 19:10:44 +00007538 if (s->cc_op != CC_OP_DYNAMIC)
7539 gen_op_set_cc_op(s->cc_op);
7540 gen_jmp_im(pc_start - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00007541 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
bellard664e0f12005-01-08 18:58:29 +00007542 break;
7543 case 2: /* ldmxcsr */
7544 case 3: /* stmxcsr */
7545 if (s->flags & HF_TS_MASK) {
7546 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7547 break;
bellard14ce26e2005-01-03 23:50:08 +00007548 }
bellard664e0f12005-01-08 18:58:29 +00007549 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7550 mod == 3)
7551 goto illegal_op;
7552 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7553 if (op == 2) {
bellard57fec1f2008-02-01 10:50:11 +00007554 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
bellard651ba602008-05-21 17:16:11 +00007555 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
bellard664e0f12005-01-08 18:58:29 +00007556 } else {
bellard651ba602008-05-21 17:16:11 +00007557 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
bellard57fec1f2008-02-01 10:50:11 +00007558 gen_op_st_T0_A0(OT_LONG + s->mem_index);
bellard664e0f12005-01-08 18:58:29 +00007559 }
7560 break;
7561 case 5: /* lfence */
7562 case 6: /* mfence */
bellard664e0f12005-01-08 18:58:29 +00007563 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7564 goto illegal_op;
7565 break;
bellard8f091a52005-07-23 17:41:26 +00007566 case 7: /* sfence / clflush */
7567 if ((modrm & 0xc7) == 0xc0) {
7568 /* sfence */
aurel32a35f3ec2008-04-08 19:51:29 +00007569 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
bellard8f091a52005-07-23 17:41:26 +00007570 if (!(s->cpuid_features & CPUID_SSE))
7571 goto illegal_op;
7572 } else {
7573 /* clflush */
7574 if (!(s->cpuid_features & CPUID_CLFLUSH))
7575 goto illegal_op;
7576 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7577 }
7578 break;
bellard664e0f12005-01-08 18:58:29 +00007579 default:
bellard14ce26e2005-01-03 23:50:08 +00007580 goto illegal_op;
7581 }
7582 break;
aurel32a35f3ec2008-04-08 19:51:29 +00007583 case 0x10d: /* 3DNow! prefetch(w) */
bellard8f091a52005-07-23 17:41:26 +00007584 modrm = ldub_code(s->pc++);
aurel32a35f3ec2008-04-08 19:51:29 +00007585 mod = (modrm >> 6) & 3;
7586 if (mod == 3)
7587 goto illegal_op;
bellard8f091a52005-07-23 17:41:26 +00007588 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7589 /* ignore for now */
7590 break;
bellard3b21e032006-09-24 18:41:56 +00007591 case 0x1aa: /* rsm */
bellard872929a2008-05-28 16:16:54 +00007592 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
bellard3b21e032006-09-24 18:41:56 +00007593 if (!(s->flags & HF_SMM_MASK))
7594 goto illegal_op;
Jun Koi728d8032010-07-25 12:30:03 +09007595 gen_update_cc_op(s);
bellard3b21e032006-09-24 18:41:56 +00007596 gen_jmp_im(s->pc - s->cs_base);
pbrooka7812ae2008-11-17 14:43:54 +00007597 gen_helper_rsm();
bellard3b21e032006-09-24 18:41:56 +00007598 gen_eob(s);
7599 break;
balrog222a3332008-10-04 03:27:44 +00007600 case 0x1b8: /* SSE4.2 popcnt */
7601 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7602 PREFIX_REPZ)
7603 goto illegal_op;
7604 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7605 goto illegal_op;
7606
7607 modrm = ldub_code(s->pc++);
7608 reg = ((modrm >> 3) & 7);
7609
7610 if (s->prefix & PREFIX_DATA)
7611 ot = OT_WORD;
7612 else if (s->dflag != 2)
7613 ot = OT_LONG;
7614 else
7615 ot = OT_QUAD;
7616
7617 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
pbrooka7812ae2008-11-17 14:43:54 +00007618 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
balrog222a3332008-10-04 03:27:44 +00007619 gen_op_mov_reg_T0(ot, reg);
balrogfdb0d092008-10-04 03:32:00 +00007620
7621 s->cc_op = CC_OP_EFLAGS;
balrog222a3332008-10-04 03:27:44 +00007622 break;
aurel32a35f3ec2008-04-08 19:51:29 +00007623 case 0x10e ... 0x10f:
7624 /* 3DNow! instructions, ignore prefixes */
7625 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
bellard664e0f12005-01-08 18:58:29 +00007626 case 0x110 ... 0x117:
7627 case 0x128 ... 0x12f:
balrog4242b1b2008-09-25 18:01:46 +00007628 case 0x138 ... 0x13a:
Andre Przywarad9f4bb22009-09-19 00:30:48 +02007629 case 0x150 ... 0x179:
bellard664e0f12005-01-08 18:58:29 +00007630 case 0x17c ... 0x17f:
7631 case 0x1c2:
7632 case 0x1c4 ... 0x1c6:
7633 case 0x1d0 ... 0x1fe:
7634 gen_sse(s, b, pc_start, rex_r);
bellard14ce26e2005-01-03 23:50:08 +00007635 break;
bellard2c0262a2003-09-30 20:34:21 +00007636 default:
7637 goto illegal_op;
7638 }
7639 /* lock generation */
7640 if (s->prefix & PREFIX_LOCK)
pbrooka7812ae2008-11-17 14:43:54 +00007641 gen_helper_unlock();
bellard2c0262a2003-09-30 20:34:21 +00007642 return s->pc;
7643 illegal_op:
bellardab1f1422004-01-19 20:31:37 +00007644 if (s->prefix & PREFIX_LOCK)
pbrooka7812ae2008-11-17 14:43:54 +00007645 gen_helper_unlock();
bellard2c0262a2003-09-30 20:34:21 +00007646 /* XXX: ensure that no lock was generated */
7647 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7648 return s->pc;
7649}
7650
bellard2c0262a2003-09-30 20:34:21 +00007651void optimize_flags_init(void)
7652{
bellardb6abf972008-05-17 12:44:31 +00007653#if TCG_TARGET_REG_BITS == 32
7654 assert(sizeof(CCTable) == (1 << 3));
7655#else
7656 assert(sizeof(CCTable) == (1 << 4));
7657#endif
pbrooka7812ae2008-11-17 14:43:54 +00007658 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7659 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7660 offsetof(CPUState, cc_op), "cc_op");
7661 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7662 "cc_src");
7663 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7664 "cc_dst");
7665 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
7666 "cc_tmp");
bellard437a88a2008-05-22 16:11:04 +00007667
Laurent Desnoguescc739bb2009-09-29 11:58:04 +02007668#ifdef TARGET_X86_64
7669 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7670 offsetof(CPUState, regs[R_EAX]), "rax");
7671 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7672 offsetof(CPUState, regs[R_ECX]), "rcx");
7673 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7674 offsetof(CPUState, regs[R_EDX]), "rdx");
7675 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7676 offsetof(CPUState, regs[R_EBX]), "rbx");
7677 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7678 offsetof(CPUState, regs[R_ESP]), "rsp");
7679 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7680 offsetof(CPUState, regs[R_EBP]), "rbp");
7681 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7682 offsetof(CPUState, regs[R_ESI]), "rsi");
7683 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7684 offsetof(CPUState, regs[R_EDI]), "rdi");
7685 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7686 offsetof(CPUState, regs[8]), "r8");
7687 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7688 offsetof(CPUState, regs[9]), "r9");
7689 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7690 offsetof(CPUState, regs[10]), "r10");
7691 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7692 offsetof(CPUState, regs[11]), "r11");
7693 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7694 offsetof(CPUState, regs[12]), "r12");
7695 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7696 offsetof(CPUState, regs[13]), "r13");
7697 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7698 offsetof(CPUState, regs[14]), "r14");
7699 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7700 offsetof(CPUState, regs[15]), "r15");
7701#else
7702 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7703 offsetof(CPUState, regs[R_EAX]), "eax");
7704 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7705 offsetof(CPUState, regs[R_ECX]), "ecx");
7706 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7707 offsetof(CPUState, regs[R_EDX]), "edx");
7708 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7709 offsetof(CPUState, regs[R_EBX]), "ebx");
7710 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7711 offsetof(CPUState, regs[R_ESP]), "esp");
7712 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7713 offsetof(CPUState, regs[R_EBP]), "ebp");
7714 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7715 offsetof(CPUState, regs[R_ESI]), "esi");
7716 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7717 offsetof(CPUState, regs[R_EDI]), "edi");
7718#endif
7719
bellard437a88a2008-05-22 16:11:04 +00007720 /* register helpers */
pbrooka7812ae2008-11-17 14:43:54 +00007721#define GEN_HELPER 2
bellard437a88a2008-05-22 16:11:04 +00007722#include "helper.h"
bellard2c0262a2003-09-30 20:34:21 +00007723}
7724
7725/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7726 basic block 'tb'. If search_pc is TRUE, also generate PC
7727 information for each intermediate instruction. */
ths2cfc5f12008-07-18 18:01:29 +00007728static inline void gen_intermediate_code_internal(CPUState *env,
7729 TranslationBlock *tb,
7730 int search_pc)
bellard2c0262a2003-09-30 20:34:21 +00007731{
7732 DisasContext dc1, *dc = &dc1;
bellard14ce26e2005-01-03 23:50:08 +00007733 target_ulong pc_ptr;
bellard2c0262a2003-09-30 20:34:21 +00007734 uint16_t *gen_opc_end;
aliguoria1d1bb32008-11-18 20:07:32 +00007735 CPUBreakpoint *bp;
Blue Swirl7f5b7d32010-04-25 18:58:25 +00007736 int j, lj;
j_mayerc0686882007-09-20 22:47:42 +00007737 uint64_t flags;
bellard14ce26e2005-01-03 23:50:08 +00007738 target_ulong pc_start;
7739 target_ulong cs_base;
pbrook2e70f6e2008-06-29 01:03:05 +00007740 int num_insns;
7741 int max_insns;
ths3b46e622007-09-17 08:09:54 +00007742
bellard2c0262a2003-09-30 20:34:21 +00007743 /* generate intermediate code */
bellard14ce26e2005-01-03 23:50:08 +00007744 pc_start = tb->pc;
7745 cs_base = tb->cs_base;
bellard2c0262a2003-09-30 20:34:21 +00007746 flags = tb->flags;
bellard3a1d9b82004-02-16 22:10:33 +00007747
bellard4f319162004-01-04 17:35:00 +00007748 dc->pe = (flags >> HF_PE_SHIFT) & 1;
bellard2c0262a2003-09-30 20:34:21 +00007749 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7750 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7751 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7752 dc->f_st = 0;
7753 dc->vm86 = (flags >> VM_SHIFT) & 1;
7754 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7755 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7756 dc->tf = (flags >> TF_SHIFT) & 1;
bellard34865132003-10-05 14:28:56 +00007757 dc->singlestep_enabled = env->singlestep_enabled;
bellard2c0262a2003-09-30 20:34:21 +00007758 dc->cc_op = CC_OP_DYNAMIC;
7759 dc->cs_base = cs_base;
7760 dc->tb = tb;
7761 dc->popl_esp_hack = 0;
7762 /* select memory access functions */
7763 dc->mem_index = 0;
7764 if (flags & HF_SOFTMMU_MASK) {
7765 if (dc->cpl == 3)
bellard14ce26e2005-01-03 23:50:08 +00007766 dc->mem_index = 2 * 4;
bellard2c0262a2003-09-30 20:34:21 +00007767 else
bellard14ce26e2005-01-03 23:50:08 +00007768 dc->mem_index = 1 * 4;
bellard2c0262a2003-09-30 20:34:21 +00007769 }
bellard14ce26e2005-01-03 23:50:08 +00007770 dc->cpuid_features = env->cpuid_features;
bellard3d7374c2006-07-10 19:53:04 +00007771 dc->cpuid_ext_features = env->cpuid_ext_features;
aurel32e771eda2008-04-09 06:41:37 +00007772 dc->cpuid_ext2_features = env->cpuid_ext2_features;
bellard12e26b72008-05-22 10:13:38 +00007773 dc->cpuid_ext3_features = env->cpuid_ext3_features;
bellard14ce26e2005-01-03 23:50:08 +00007774#ifdef TARGET_X86_64
7775 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7776 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7777#endif
bellard7eee2a52004-02-25 23:17:58 +00007778 dc->flags = flags;
bellarda2cc3b22003-11-19 22:08:13 +00007779 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7780 (flags & HF_INHIBIT_IRQ_MASK)
bellard415fa2e2003-10-30 00:39:38 +00007781#ifndef CONFIG_SOFTMMU
bellard2c0262a2003-09-30 20:34:21 +00007782 || (flags & HF_SOFTMMU_MASK)
7783#endif
7784 );
bellard4f319162004-01-04 17:35:00 +00007785#if 0
7786 /* check addseg logic */
bellarddc196a52004-06-13 13:26:14 +00007787 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
bellard4f319162004-01-04 17:35:00 +00007788 printf("ERROR addseg\n");
7789#endif
7790
pbrooka7812ae2008-11-17 14:43:54 +00007791 cpu_T[0] = tcg_temp_new();
7792 cpu_T[1] = tcg_temp_new();
7793 cpu_A0 = tcg_temp_new();
7794 cpu_T3 = tcg_temp_new();
bellard1e4840b2008-05-25 17:26:41 +00007795
pbrooka7812ae2008-11-17 14:43:54 +00007796 cpu_tmp0 = tcg_temp_new();
7797 cpu_tmp1_i64 = tcg_temp_new_i64();
7798 cpu_tmp2_i32 = tcg_temp_new_i32();
7799 cpu_tmp3_i32 = tcg_temp_new_i32();
7800 cpu_tmp4 = tcg_temp_new();
7801 cpu_tmp5 = tcg_temp_new();
pbrooka7812ae2008-11-17 14:43:54 +00007802 cpu_ptr0 = tcg_temp_new_ptr();
7803 cpu_ptr1 = tcg_temp_new_ptr();
bellard57fec1f2008-02-01 10:50:11 +00007804
bellard2c0262a2003-09-30 20:34:21 +00007805 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
bellard2c0262a2003-09-30 20:34:21 +00007806
7807 dc->is_jmp = DISAS_NEXT;
7808 pc_ptr = pc_start;
7809 lj = -1;
pbrook2e70f6e2008-06-29 01:03:05 +00007810 num_insns = 0;
7811 max_insns = tb->cflags & CF_COUNT_MASK;
7812 if (max_insns == 0)
7813 max_insns = CF_COUNT_MASK;
bellard2c0262a2003-09-30 20:34:21 +00007814
pbrook2e70f6e2008-06-29 01:03:05 +00007815 gen_icount_start();
bellard2c0262a2003-09-30 20:34:21 +00007816 for(;;) {
Blue Swirl72cf2d42009-09-12 07:36:22 +00007817 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7818 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
Jan Kiszkaa2397802009-05-10 22:30:53 +02007819 if (bp->pc == pc_ptr &&
7820 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
bellard2c0262a2003-09-30 20:34:21 +00007821 gen_debug(dc, pc_ptr - dc->cs_base);
7822 break;
7823 }
7824 }
7825 }
7826 if (search_pc) {
7827 j = gen_opc_ptr - gen_opc_buf;
7828 if (lj < j) {
7829 lj++;
7830 while (lj < j)
7831 gen_opc_instr_start[lj++] = 0;
7832 }
bellard14ce26e2005-01-03 23:50:08 +00007833 gen_opc_pc[lj] = pc_ptr;
bellard2c0262a2003-09-30 20:34:21 +00007834 gen_opc_cc_op[lj] = dc->cc_op;
7835 gen_opc_instr_start[lj] = 1;
pbrook2e70f6e2008-06-29 01:03:05 +00007836 gen_opc_icount[lj] = num_insns;
bellard2c0262a2003-09-30 20:34:21 +00007837 }
pbrook2e70f6e2008-06-29 01:03:05 +00007838 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7839 gen_io_start();
7840
bellard2c0262a2003-09-30 20:34:21 +00007841 pc_ptr = disas_insn(dc, pc_ptr);
pbrook2e70f6e2008-06-29 01:03:05 +00007842 num_insns++;
bellard2c0262a2003-09-30 20:34:21 +00007843 /* stop translation if indicated */
7844 if (dc->is_jmp)
7845 break;
7846 /* if single step mode, we generate only one instruction and
7847 generate an exception */
bellarda2cc3b22003-11-19 22:08:13 +00007848 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7849 the flag and abort the translation to give the irqs a
7850 change to be happen */
ths5fafdf22007-09-16 21:08:06 +00007851 if (dc->tf || dc->singlestep_enabled ||
pbrook2e70f6e2008-06-29 01:03:05 +00007852 (flags & HF_INHIBIT_IRQ_MASK)) {
bellard14ce26e2005-01-03 23:50:08 +00007853 gen_jmp_im(pc_ptr - dc->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00007854 gen_eob(dc);
7855 break;
7856 }
7857 /* if too long translation, stop generation too */
7858 if (gen_opc_ptr >= gen_opc_end ||
pbrook2e70f6e2008-06-29 01:03:05 +00007859 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7860 num_insns >= max_insns) {
bellard14ce26e2005-01-03 23:50:08 +00007861 gen_jmp_im(pc_ptr - dc->cs_base);
bellard2c0262a2003-09-30 20:34:21 +00007862 gen_eob(dc);
7863 break;
7864 }
aurel321b530a62009-04-05 20:08:59 +00007865 if (singlestep) {
7866 gen_jmp_im(pc_ptr - dc->cs_base);
7867 gen_eob(dc);
7868 break;
7869 }
bellard2c0262a2003-09-30 20:34:21 +00007870 }
pbrook2e70f6e2008-06-29 01:03:05 +00007871 if (tb->cflags & CF_LAST_IO)
7872 gen_io_end();
7873 gen_icount_end(tb, num_insns);
bellard2c0262a2003-09-30 20:34:21 +00007874 *gen_opc_ptr = INDEX_op_end;
7875 /* we don't forget to fill the last values */
7876 if (search_pc) {
7877 j = gen_opc_ptr - gen_opc_buf;
7878 lj++;
7879 while (lj <= j)
7880 gen_opc_instr_start[lj++] = 0;
7881 }
ths3b46e622007-09-17 08:09:54 +00007882
bellard2c0262a2003-09-30 20:34:21 +00007883#ifdef DEBUG_DISAS
aliguori8fec2b82009-01-15 22:36:53 +00007884 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
bellard14ce26e2005-01-03 23:50:08 +00007885 int disas_flags;
aliguori93fcfe32009-01-15 22:34:14 +00007886 qemu_log("----------------\n");
7887 qemu_log("IN: %s\n", lookup_symbol(pc_start));
bellard14ce26e2005-01-03 23:50:08 +00007888#ifdef TARGET_X86_64
7889 if (dc->code64)
7890 disas_flags = 2;
7891 else
7892#endif
7893 disas_flags = !dc->code32;
aliguori93fcfe32009-01-15 22:34:14 +00007894 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7895 qemu_log("\n");
bellard2c0262a2003-09-30 20:34:21 +00007896 }
7897#endif
7898
pbrook2e70f6e2008-06-29 01:03:05 +00007899 if (!search_pc) {
bellard2c0262a2003-09-30 20:34:21 +00007900 tb->size = pc_ptr - pc_start;
pbrook2e70f6e2008-06-29 01:03:05 +00007901 tb->icount = num_insns;
7902 }
bellard2c0262a2003-09-30 20:34:21 +00007903}
7904
ths2cfc5f12008-07-18 18:01:29 +00007905void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
bellard2c0262a2003-09-30 20:34:21 +00007906{
ths2cfc5f12008-07-18 18:01:29 +00007907 gen_intermediate_code_internal(env, tb, 0);
bellard2c0262a2003-09-30 20:34:21 +00007908}
7909
ths2cfc5f12008-07-18 18:01:29 +00007910void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
bellard2c0262a2003-09-30 20:34:21 +00007911{
ths2cfc5f12008-07-18 18:01:29 +00007912 gen_intermediate_code_internal(env, tb, 1);
bellard2c0262a2003-09-30 20:34:21 +00007913}
7914
aurel32d2856f12008-04-28 00:32:32 +00007915void gen_pc_load(CPUState *env, TranslationBlock *tb,
7916 unsigned long searched_pc, int pc_pos, void *puc)
7917{
7918 int cc_op;
7919#ifdef DEBUG_DISAS
aliguori8fec2b82009-01-15 22:36:53 +00007920 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
aurel32d2856f12008-04-28 00:32:32 +00007921 int i;
aliguori93fcfe32009-01-15 22:34:14 +00007922 qemu_log("RESTORE:\n");
aurel32d2856f12008-04-28 00:32:32 +00007923 for(i = 0;i <= pc_pos; i++) {
7924 if (gen_opc_instr_start[i]) {
aliguori93fcfe32009-01-15 22:34:14 +00007925 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
aurel32d2856f12008-04-28 00:32:32 +00007926 }
7927 }
aliguori93fcfe32009-01-15 22:34:14 +00007928 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
aurel32d2856f12008-04-28 00:32:32 +00007929 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7930 (uint32_t)tb->cs_base);
7931 }
7932#endif
7933 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7934 cc_op = gen_opc_cc_op[pc_pos];
7935 if (cc_op != CC_OP_DYNAMIC)
7936 env->cc_op = cc_op;
7937}