commit 49d9fdcca673f94cd3cf8200fff978bd2032b42b
author Laurent Desnogues <laurent.desnogues@gmail.com> Tue Oct 06 10:14:29 2009 +0200
committer Aurelien Jarno <aurelien@aurel32.net> Tue Oct 06 22:01:00 2009 +0200
tree e849d25078236c52da87835bf6cb359b93edc89d
parent d9ace8b384744062ddd569a573bc95f38f420c7f

target-i386: fix ARPL

The arpl implementation in target-i386/translate.c uses cpu_A0
temporary across a brcond op.  This patch fixes that issue.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-i386/translate.c

diff --git a/target-i386/translate.c b/target-i386/translate.c
index e3cb49f..2511943 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7305,7 +7305,7 @@
 #endif
         {
             int label1;
-            TCGv t0, t1, t2;
+            TCGv t0, t1, t2, a0;
 
             if (!s->pe || s->vm86)
                 goto illegal_op;
@@ -7320,8 +7320,11 @@
             if (mod != 3) {
                 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
                 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
+                a0 = tcg_temp_local_new();
+                tcg_gen_mov_tl(a0, cpu_A0);
             } else {
                 gen_op_mov_v_reg(ot, t0, rm);
+                TCGV_UNUSED(a0);
             }
             gen_op_mov_v_reg(ot, t1, reg);
             tcg_gen_andi_tl(cpu_tmp0, t0, 3);
@@ -7334,8 +7337,9 @@
             tcg_gen_movi_tl(t2, CC_Z);
             gen_set_label(label1);
             if (mod != 3) {
-                gen_op_st_v(ot + s->mem_index, t0, cpu_A0);
-            } else {
+                gen_op_st_v(ot + s->mem_index, t0, a0);
+                tcg_temp_free(a0);
+           } else {
                 gen_op_mov_reg_v(ot, rm, t0);
             }
             if (s->cc_op != CC_OP_DYNAMIC)