blob: 3ab831a6a73d49dc2bee1cf6f7ff2d74cddfddf0 [file] [log] [blame]
bellarde80cfcf2004-12-19 23:18:01 +00001/*
blueswir1b4ed08e2009-01-12 17:38:28 +00002 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard8be1f5c2005-04-06 20:42:35 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellarde80cfcf2004-12-19 23:18:01 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirl6c319c82009-07-15 08:51:32 +000024
Peter Maydell04308912016-01-26 18:17:30 +000025#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010026#include "hw/hw.h"
27#include "hw/sysbus.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010028#include "hw/char/escc.h"
Marc-André Lureau4d43a602017-01-26 18:26:44 +040029#include "chardev/char-fe.h"
Marc-André Lureau7566c6e2017-01-26 17:33:39 +040030#include "chardev/char-serial.h"
Paolo Bonzini28ecbae2012-11-28 12:06:30 +010031#include "ui/console.h"
Gerd Hoffmann65e75452014-03-25 13:16:21 +010032#include "ui/input.h"
Blue Swirl30c2f232011-08-07 11:01:05 +000033#include "trace.h"
bellarde80cfcf2004-12-19 23:18:01 +000034
35/*
Blue Swirl09330e92009-10-24 16:09:01 +000036 * Chipset docs:
37 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
38 * http://www.zilog.com/docs/serial/scc_escc_um.pdf
39 *
blueswir1b4ed08e2009-01-12 17:38:28 +000040 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
bellarde80cfcf2004-12-19 23:18:01 +000041 * (Slave I/O), also produced as NCR89C105. See
42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
ths5fafdf22007-09-16 21:08:06 +000043 *
bellarde80cfcf2004-12-19 23:18:01 +000044 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
45 * mouse and keyboard ports don't implement all functions and they are
46 * only asynchronous. There is no DMA.
47 *
blueswir1b4ed08e2009-01-12 17:38:28 +000048 * Z85C30 is also used on PowerMacs. There are some small differences
49 * between Sparc version (sunzilog) and PowerMac (pmac):
50 * Offset between control and data registers
51 * There is some kind of lockup bug, but we can ignore it
52 * CTS is inverted
53 * DMA on pmac using DBDMA chip
54 * pmac can do IRDA and faster rates, sunzilog can only do 38400
55 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
bellarde80cfcf2004-12-19 23:18:01 +000056 */
57
bellard715748f2006-09-09 11:35:47 +000058/*
59 * Modifications:
60 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
61 * serial mouse queue.
62 * Implemented serial mouse protocol.
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +020063 *
64 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
bellard715748f2006-09-09 11:35:47 +000065 */
66
bellard8be1f5c2005-04-06 20:42:35 +000067typedef enum {
68 chn_a, chn_b,
Blue Swirl8e39a032010-02-07 08:05:47 +000069} ChnID;
bellard8be1f5c2005-04-06 20:42:35 +000070
bellard35db0992006-09-09 12:17:15 +000071#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
72
bellard8be1f5c2005-04-06 20:42:35 +000073typedef enum {
74 ser, kbd, mouse,
Blue Swirl8e39a032010-02-07 08:05:47 +000075} ChnType;
bellard8be1f5c2005-04-06 20:42:35 +000076
bellard715748f2006-09-09 11:35:47 +000077#define SERIO_QUEUE_SIZE 256
bellard8be1f5c2005-04-06 20:42:35 +000078
79typedef struct {
bellard715748f2006-09-09 11:35:47 +000080 uint8_t data[SERIO_QUEUE_SIZE];
bellard8be1f5c2005-04-06 20:42:35 +000081 int rptr, wptr, count;
bellard715748f2006-09-09 11:35:47 +000082} SERIOQueue;
bellard8be1f5c2005-04-06 20:42:35 +000083
blueswir112abac82007-12-10 20:05:09 +000084#define SERIAL_REGS 16
bellarde80cfcf2004-12-19 23:18:01 +000085typedef struct ChannelState {
pbrookd537cf62007-04-07 18:14:41 +000086 qemu_irq irq;
blueswir122548762008-05-10 10:12:00 +000087 uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
bellard8be1f5c2005-04-06 20:42:35 +000088 struct ChannelState *otherchn;
Blue Swirld7b95532011-08-07 19:55:23 +000089 uint32_t reg;
90 uint8_t wregs[SERIAL_REGS], rregs[SERIAL_REGS];
bellard715748f2006-09-09 11:35:47 +000091 SERIOQueue queue;
Marc-André Lureaubecdfa02016-10-22 12:52:51 +030092 CharBackend chr;
blueswir1bbbb2f02007-09-23 11:48:47 +000093 int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
blueswir1577390f2007-12-04 20:58:31 +000094 int disabled;
blueswir1b4ed08e2009-01-12 17:38:28 +000095 int clock;
Blue Swirlbdb78ca2009-10-24 16:07:10 +000096 uint32_t vmstate_dummy;
Blue Swirld7b95532011-08-07 19:55:23 +000097 ChnID chn; // this channel, A (base+4) or B (base+0)
98 ChnType type;
99 uint8_t rx, tx;
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100100 QemuInputHandlerState *hs;
bellarde80cfcf2004-12-19 23:18:01 +0000101} ChannelState;
102
Andreas Färber81069b22013-07-24 21:30:40 +0200103#define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC)
104
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +0200105typedef struct ESCCState {
Andreas Färber81069b22013-07-24 21:30:40 +0200106 SysBusDevice parent_obj;
107
bellarde80cfcf2004-12-19 23:18:01 +0000108 struct ChannelState chn[2];
Gerd Hoffmannec02f7d2009-08-03 17:35:23 +0200109 uint32_t it_shift;
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300110 MemoryRegion mmio;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200111 uint32_t disabled;
112 uint32_t frequency;
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +0200113} ESCCState;
bellarde80cfcf2004-12-19 23:18:01 +0000114
blueswir112abac82007-12-10 20:05:09 +0000115#define SERIAL_CTRL 0
116#define SERIAL_DATA 1
117
118#define W_CMD 0
119#define CMD_PTR_MASK 0x07
120#define CMD_CMD_MASK 0x38
121#define CMD_HI 0x08
122#define CMD_CLR_TXINT 0x28
123#define CMD_CLR_IUS 0x38
124#define W_INTR 1
125#define INTR_INTALL 0x01
126#define INTR_TXINT 0x02
127#define INTR_RXMODEMSK 0x18
128#define INTR_RXINT1ST 0x08
129#define INTR_RXINTALL 0x10
130#define W_IVEC 2
131#define W_RXCTRL 3
132#define RXCTRL_RXEN 0x01
133#define W_TXCTRL1 4
134#define TXCTRL1_PAREN 0x01
135#define TXCTRL1_PAREV 0x02
136#define TXCTRL1_1STOP 0x04
137#define TXCTRL1_1HSTOP 0x08
138#define TXCTRL1_2STOP 0x0c
139#define TXCTRL1_STPMSK 0x0c
140#define TXCTRL1_CLK1X 0x00
141#define TXCTRL1_CLK16X 0x40
142#define TXCTRL1_CLK32X 0x80
143#define TXCTRL1_CLK64X 0xc0
144#define TXCTRL1_CLKMSK 0xc0
145#define W_TXCTRL2 5
146#define TXCTRL2_TXEN 0x08
147#define TXCTRL2_BITMSK 0x60
148#define TXCTRL2_5BITS 0x00
149#define TXCTRL2_7BITS 0x20
150#define TXCTRL2_6BITS 0x40
151#define TXCTRL2_8BITS 0x60
152#define W_SYNC1 6
153#define W_SYNC2 7
154#define W_TXBUF 8
155#define W_MINTR 9
156#define MINTR_STATUSHI 0x10
157#define MINTR_RST_MASK 0xc0
158#define MINTR_RST_B 0x40
159#define MINTR_RST_A 0x80
160#define MINTR_RST_ALL 0xc0
161#define W_MISC1 10
162#define W_CLOCK 11
163#define CLOCK_TRXC 0x08
164#define W_BRGLO 12
165#define W_BRGHI 13
166#define W_MISC2 14
167#define MISC2_PLLDIS 0x30
168#define W_EXTINT 15
169#define EXTINT_DCD 0x08
170#define EXTINT_SYNCINT 0x10
171#define EXTINT_CTSINT 0x20
172#define EXTINT_TXUNDRN 0x40
173#define EXTINT_BRKINT 0x80
174
175#define R_STATUS 0
176#define STATUS_RXAV 0x01
177#define STATUS_ZERO 0x02
178#define STATUS_TXEMPTY 0x04
179#define STATUS_DCD 0x08
180#define STATUS_SYNC 0x10
181#define STATUS_CTS 0x20
182#define STATUS_TXUNDRN 0x40
183#define STATUS_BRK 0x80
184#define R_SPEC 1
185#define SPEC_ALLSENT 0x01
186#define SPEC_BITS8 0x06
187#define R_IVEC 2
188#define IVEC_TXINTB 0x00
189#define IVEC_LONOINT 0x06
190#define IVEC_LORXINTA 0x0c
191#define IVEC_LORXINTB 0x04
192#define IVEC_LOTXINTA 0x08
193#define IVEC_HINOINT 0x60
194#define IVEC_HIRXINTA 0x30
195#define IVEC_HIRXINTB 0x20
196#define IVEC_HITXINTA 0x10
197#define R_INTR 3
198#define INTR_EXTINTB 0x01
199#define INTR_TXINTB 0x02
200#define INTR_RXINTB 0x04
201#define INTR_EXTINTA 0x08
202#define INTR_TXINTA 0x10
203#define INTR_RXINTA 0x20
204#define R_IPEN 4
205#define R_TXCTRL1 5
206#define R_TXCTRL2 6
207#define R_BC 7
208#define R_RXBUF 8
209#define R_RXCTRL 9
210#define R_MISC 10
211#define R_MISC1 11
212#define R_BRGLO 12
213#define R_BRGHI 13
214#define R_MISC1I 14
215#define R_EXTINT 15
bellarde80cfcf2004-12-19 23:18:01 +0000216
bellard8be1f5c2005-04-06 20:42:35 +0000217static void handle_kbd_command(ChannelState *s, int val);
218static int serial_can_receive(void *opaque);
219static void serial_receive_byte(ChannelState *s, int ch);
220
blueswir167deb562007-04-18 19:21:38 +0000221static void clear_queue(void *opaque)
222{
223 ChannelState *s = opaque;
224 SERIOQueue *q = &s->queue;
225 q->rptr = q->wptr = q->count = 0;
226}
227
bellard8be1f5c2005-04-06 20:42:35 +0000228static void put_queue(void *opaque, int b)
229{
230 ChannelState *s = opaque;
bellard715748f2006-09-09 11:35:47 +0000231 SERIOQueue *q = &s->queue;
bellard8be1f5c2005-04-06 20:42:35 +0000232
Blue Swirl30c2f232011-08-07 11:01:05 +0000233 trace_escc_put_queue(CHN_C(s), b);
bellard715748f2006-09-09 11:35:47 +0000234 if (q->count >= SERIO_QUEUE_SIZE)
bellard8be1f5c2005-04-06 20:42:35 +0000235 return;
236 q->data[q->wptr] = b;
bellard715748f2006-09-09 11:35:47 +0000237 if (++q->wptr == SERIO_QUEUE_SIZE)
bellard8be1f5c2005-04-06 20:42:35 +0000238 q->wptr = 0;
239 q->count++;
240 serial_receive_byte(s, 0);
241}
242
243static uint32_t get_queue(void *opaque)
244{
245 ChannelState *s = opaque;
bellard715748f2006-09-09 11:35:47 +0000246 SERIOQueue *q = &s->queue;
bellard8be1f5c2005-04-06 20:42:35 +0000247 int val;
ths3b46e622007-09-17 08:09:54 +0000248
bellard8be1f5c2005-04-06 20:42:35 +0000249 if (q->count == 0) {
blueswir1f930d072007-10-06 11:28:21 +0000250 return 0;
bellard8be1f5c2005-04-06 20:42:35 +0000251 } else {
252 val = q->data[q->rptr];
bellard715748f2006-09-09 11:35:47 +0000253 if (++q->rptr == SERIO_QUEUE_SIZE)
bellard8be1f5c2005-04-06 20:42:35 +0000254 q->rptr = 0;
255 q->count--;
256 }
Blue Swirl30c2f232011-08-07 11:01:05 +0000257 trace_escc_get_queue(CHN_C(s), val);
bellard8be1f5c2005-04-06 20:42:35 +0000258 if (q->count > 0)
blueswir1f930d072007-10-06 11:28:21 +0000259 serial_receive_byte(s, 0);
bellard8be1f5c2005-04-06 20:42:35 +0000260 return val;
261}
262
blueswir1b4ed08e2009-01-12 17:38:28 +0000263static int escc_update_irq_chn(ChannelState *s)
bellarde80cfcf2004-12-19 23:18:01 +0000264{
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200265 if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) ||
blueswir112abac82007-12-10 20:05:09 +0000266 // tx ints enabled, pending
267 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) ||
268 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) &&
blueswir1f930d072007-10-06 11:28:21 +0000269 s->rxint == 1) || // rx ints enabled, pending
blueswir112abac82007-12-10 20:05:09 +0000270 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) &&
271 (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p
bellarde4a89052006-09-09 11:38:11 +0000272 return 1;
bellarde80cfcf2004-12-19 23:18:01 +0000273 }
bellarde4a89052006-09-09 11:38:11 +0000274 return 0;
275}
276
blueswir1b4ed08e2009-01-12 17:38:28 +0000277static void escc_update_irq(ChannelState *s)
bellarde4a89052006-09-09 11:38:11 +0000278{
279 int irq;
280
blueswir1b4ed08e2009-01-12 17:38:28 +0000281 irq = escc_update_irq_chn(s);
282 irq |= escc_update_irq_chn(s->otherchn);
bellarde4a89052006-09-09 11:38:11 +0000283
Blue Swirl30c2f232011-08-07 11:01:05 +0000284 trace_escc_update_irq(irq);
pbrookd537cf62007-04-07 18:14:41 +0000285 qemu_set_irq(s->irq, irq);
bellarde80cfcf2004-12-19 23:18:01 +0000286}
287
blueswir1b4ed08e2009-01-12 17:38:28 +0000288static void escc_reset_chn(ChannelState *s)
bellarde80cfcf2004-12-19 23:18:01 +0000289{
290 int i;
291
292 s->reg = 0;
blueswir18f180a42009-01-12 17:31:29 +0000293 for (i = 0; i < SERIAL_REGS; i++) {
blueswir1f930d072007-10-06 11:28:21 +0000294 s->rregs[i] = 0;
295 s->wregs[i] = 0;
bellarde80cfcf2004-12-19 23:18:01 +0000296 }
blueswir112abac82007-12-10 20:05:09 +0000297 s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity
298 s->wregs[W_MINTR] = MINTR_RST_ALL;
299 s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC
300 s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled
301 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
302 EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts
blueswir1577390f2007-12-04 20:58:31 +0000303 if (s->disabled)
blueswir112abac82007-12-10 20:05:09 +0000304 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
305 STATUS_CTS | STATUS_TXUNDRN;
blueswir1577390f2007-12-04 20:58:31 +0000306 else
blueswir112abac82007-12-10 20:05:09 +0000307 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
blueswir1f48c5372007-12-27 20:24:15 +0000308 s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
bellarde80cfcf2004-12-19 23:18:01 +0000309
310 s->rx = s->tx = 0;
311 s->rxint = s->txint = 0;
bellarde4a89052006-09-09 11:38:11 +0000312 s->rxint_under_svc = s->txint_under_svc = 0;
blueswir1bbbb2f02007-09-23 11:48:47 +0000313 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
blueswir167deb562007-04-18 19:21:38 +0000314 clear_queue(s);
bellarde80cfcf2004-12-19 23:18:01 +0000315}
316
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000317static void escc_reset(DeviceState *d)
bellarde80cfcf2004-12-19 23:18:01 +0000318{
Andreas Färber81069b22013-07-24 21:30:40 +0200319 ESCCState *s = ESCC(d);
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000320
blueswir1b4ed08e2009-01-12 17:38:28 +0000321 escc_reset_chn(&s->chn[0]);
322 escc_reset_chn(&s->chn[1]);
bellarde80cfcf2004-12-19 23:18:01 +0000323}
324
bellardba3c64f2005-12-05 20:31:52 +0000325static inline void set_rxint(ChannelState *s)
326{
327 s->rxint = 1;
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200328 /* XXX: missing daisy chainnig: chn_b rx should have a lower priority
329 than chn_a rx/tx/special_condition service*/
330 s->rxint_under_svc = 1;
331 if (s->chn == chn_a) {
blueswir112abac82007-12-10 20:05:09 +0000332 s->rregs[R_INTR] |= INTR_RXINTA;
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200333 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
334 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA;
335 else
336 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA;
337 } else {
blueswir112abac82007-12-10 20:05:09 +0000338 s->otherchn->rregs[R_INTR] |= INTR_RXINTB;
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200339 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
340 s->rregs[R_IVEC] = IVEC_HIRXINTB;
341 else
342 s->rregs[R_IVEC] = IVEC_LORXINTB;
343 }
blueswir1b4ed08e2009-01-12 17:38:28 +0000344 escc_update_irq(s);
bellardba3c64f2005-12-05 20:31:52 +0000345}
346
blueswir180637a62008-01-17 21:07:04 +0000347static inline void set_txint(ChannelState *s)
348{
349 s->txint = 1;
350 if (!s->rxint_under_svc) {
351 s->txint_under_svc = 1;
352 if (s->chn == chn_a) {
Aurelien Jarnof53671c2011-01-27 08:21:35 +0100353 if (s->wregs[W_INTR] & INTR_TXINT) {
354 s->rregs[R_INTR] |= INTR_TXINTA;
355 }
blueswir180637a62008-01-17 21:07:04 +0000356 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
357 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA;
358 else
359 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA;
360 } else {
361 s->rregs[R_IVEC] = IVEC_TXINTB;
Aurelien Jarnof53671c2011-01-27 08:21:35 +0100362 if (s->wregs[W_INTR] & INTR_TXINT) {
363 s->otherchn->rregs[R_INTR] |= INTR_TXINTB;
364 }
blueswir180637a62008-01-17 21:07:04 +0000365 }
blueswir1b4ed08e2009-01-12 17:38:28 +0000366 escc_update_irq(s);
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200367 }
blueswir180637a62008-01-17 21:07:04 +0000368}
369
370static inline void clr_rxint(ChannelState *s)
371{
372 s->rxint = 0;
373 s->rxint_under_svc = 0;
374 if (s->chn == chn_a) {
375 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
376 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
377 else
378 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
379 s->rregs[R_INTR] &= ~INTR_RXINTA;
380 } else {
381 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
382 s->rregs[R_IVEC] = IVEC_HINOINT;
383 else
384 s->rregs[R_IVEC] = IVEC_LONOINT;
385 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB;
386 }
387 if (s->txint)
388 set_txint(s);
blueswir1b4ed08e2009-01-12 17:38:28 +0000389 escc_update_irq(s);
blueswir180637a62008-01-17 21:07:04 +0000390}
391
bellardba3c64f2005-12-05 20:31:52 +0000392static inline void clr_txint(ChannelState *s)
393{
394 s->txint = 0;
bellarde4a89052006-09-09 11:38:11 +0000395 s->txint_under_svc = 0;
blueswir1b9652ca2007-04-20 19:35:25 +0000396 if (s->chn == chn_a) {
blueswir112abac82007-12-10 20:05:09 +0000397 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
398 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
blueswir1b9652ca2007-04-20 19:35:25 +0000399 else
blueswir112abac82007-12-10 20:05:09 +0000400 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
401 s->rregs[R_INTR] &= ~INTR_TXINTA;
blueswir1b9652ca2007-04-20 19:35:25 +0000402 } else {
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200403 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
blueswir112abac82007-12-10 20:05:09 +0000404 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
405 s->rregs[R_IVEC] = IVEC_HINOINT;
blueswir1b9652ca2007-04-20 19:35:25 +0000406 else
blueswir112abac82007-12-10 20:05:09 +0000407 s->rregs[R_IVEC] = IVEC_LONOINT;
408 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
blueswir1b9652ca2007-04-20 19:35:25 +0000409 }
bellarde4a89052006-09-09 11:38:11 +0000410 if (s->rxint)
411 set_rxint(s);
blueswir1b4ed08e2009-01-12 17:38:28 +0000412 escc_update_irq(s);
bellardba3c64f2005-12-05 20:31:52 +0000413}
414
blueswir1b4ed08e2009-01-12 17:38:28 +0000415static void escc_update_parameters(ChannelState *s)
bellard35db0992006-09-09 12:17:15 +0000416{
417 int speed, parity, data_bits, stop_bits;
418 QEMUSerialSetParams ssp;
419
Anton Nefedov30650702017-07-06 15:08:52 +0300420 if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != ser)
bellard35db0992006-09-09 12:17:15 +0000421 return;
422
blueswir112abac82007-12-10 20:05:09 +0000423 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
424 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV)
bellard35db0992006-09-09 12:17:15 +0000425 parity = 'E';
426 else
427 parity = 'O';
428 } else {
429 parity = 'N';
430 }
blueswir112abac82007-12-10 20:05:09 +0000431 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP)
bellard35db0992006-09-09 12:17:15 +0000432 stop_bits = 2;
433 else
434 stop_bits = 1;
blueswir112abac82007-12-10 20:05:09 +0000435 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {
436 case TXCTRL2_5BITS:
bellard35db0992006-09-09 12:17:15 +0000437 data_bits = 5;
438 break;
blueswir112abac82007-12-10 20:05:09 +0000439 case TXCTRL2_7BITS:
bellard35db0992006-09-09 12:17:15 +0000440 data_bits = 7;
441 break;
blueswir112abac82007-12-10 20:05:09 +0000442 case TXCTRL2_6BITS:
bellard35db0992006-09-09 12:17:15 +0000443 data_bits = 6;
444 break;
445 default:
blueswir112abac82007-12-10 20:05:09 +0000446 case TXCTRL2_8BITS:
bellard35db0992006-09-09 12:17:15 +0000447 data_bits = 8;
448 break;
449 }
blueswir1b4ed08e2009-01-12 17:38:28 +0000450 speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2);
blueswir112abac82007-12-10 20:05:09 +0000451 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {
452 case TXCTRL1_CLK1X:
bellard35db0992006-09-09 12:17:15 +0000453 break;
blueswir112abac82007-12-10 20:05:09 +0000454 case TXCTRL1_CLK16X:
bellard35db0992006-09-09 12:17:15 +0000455 speed /= 16;
456 break;
blueswir112abac82007-12-10 20:05:09 +0000457 case TXCTRL1_CLK32X:
bellard35db0992006-09-09 12:17:15 +0000458 speed /= 32;
459 break;
460 default:
blueswir112abac82007-12-10 20:05:09 +0000461 case TXCTRL1_CLK64X:
bellard35db0992006-09-09 12:17:15 +0000462 speed /= 64;
463 break;
464 }
465 ssp.speed = speed;
466 ssp.parity = parity;
467 ssp.data_bits = data_bits;
468 ssp.stop_bits = stop_bits;
Blue Swirl30c2f232011-08-07 11:01:05 +0000469 trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300470 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
bellard35db0992006-09-09 12:17:15 +0000471}
472
Avi Kivitya8170e52012-10-23 12:30:10 +0200473static void escc_mem_write(void *opaque, hwaddr addr,
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300474 uint64_t val, unsigned size)
bellarde80cfcf2004-12-19 23:18:01 +0000475{
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +0200476 ESCCState *serial = opaque;
bellarde80cfcf2004-12-19 23:18:01 +0000477 ChannelState *s;
478 uint32_t saddr;
479 int newreg, channel;
480
481 val &= 0xff;
blueswir1b4ed08e2009-01-12 17:38:28 +0000482 saddr = (addr >> serial->it_shift) & 1;
483 channel = (addr >> (serial->it_shift + 1)) & 1;
blueswir1b3ceef22007-06-25 19:56:13 +0000484 s = &serial->chn[channel];
bellarde80cfcf2004-12-19 23:18:01 +0000485 switch (saddr) {
blueswir112abac82007-12-10 20:05:09 +0000486 case SERIAL_CTRL:
Blue Swirl30c2f232011-08-07 11:01:05 +0000487 trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff);
blueswir1f930d072007-10-06 11:28:21 +0000488 newreg = 0;
489 switch (s->reg) {
blueswir112abac82007-12-10 20:05:09 +0000490 case W_CMD:
491 newreg = val & CMD_PTR_MASK;
492 val &= CMD_CMD_MASK;
blueswir1f930d072007-10-06 11:28:21 +0000493 switch (val) {
blueswir112abac82007-12-10 20:05:09 +0000494 case CMD_HI:
495 newreg |= CMD_HI;
blueswir1f930d072007-10-06 11:28:21 +0000496 break;
blueswir112abac82007-12-10 20:05:09 +0000497 case CMD_CLR_TXINT:
bellardba3c64f2005-12-05 20:31:52 +0000498 clr_txint(s);
blueswir1f930d072007-10-06 11:28:21 +0000499 break;
blueswir112abac82007-12-10 20:05:09 +0000500 case CMD_CLR_IUS:
Artyom Tarasenko9fc391f2010-08-15 16:04:41 +0200501 if (s->rxint_under_svc) {
502 s->rxint_under_svc = 0;
503 if (s->txint) {
504 set_txint(s);
505 }
506 } else if (s->txint_under_svc) {
507 s->txint_under_svc = 0;
508 }
509 escc_update_irq(s);
blueswir1f930d072007-10-06 11:28:21 +0000510 break;
511 default:
512 break;
513 }
514 break;
blueswir112abac82007-12-10 20:05:09 +0000515 case W_INTR ... W_RXCTRL:
516 case W_SYNC1 ... W_TXBUF:
517 case W_MISC1 ... W_CLOCK:
518 case W_MISC2 ... W_EXTINT:
blueswir1f930d072007-10-06 11:28:21 +0000519 s->wregs[s->reg] = val;
520 break;
blueswir112abac82007-12-10 20:05:09 +0000521 case W_TXCTRL1:
522 case W_TXCTRL2:
blueswir1796d8282008-04-12 08:47:27 +0000523 s->wregs[s->reg] = val;
blueswir1b4ed08e2009-01-12 17:38:28 +0000524 escc_update_parameters(s);
blueswir1796d8282008-04-12 08:47:27 +0000525 break;
blueswir112abac82007-12-10 20:05:09 +0000526 case W_BRGLO:
527 case W_BRGHI:
blueswir1f930d072007-10-06 11:28:21 +0000528 s->wregs[s->reg] = val;
blueswir1796d8282008-04-12 08:47:27 +0000529 s->rregs[s->reg] = val;
blueswir1b4ed08e2009-01-12 17:38:28 +0000530 escc_update_parameters(s);
blueswir1f930d072007-10-06 11:28:21 +0000531 break;
blueswir112abac82007-12-10 20:05:09 +0000532 case W_MINTR:
533 switch (val & MINTR_RST_MASK) {
blueswir1f930d072007-10-06 11:28:21 +0000534 case 0:
535 default:
536 break;
blueswir112abac82007-12-10 20:05:09 +0000537 case MINTR_RST_B:
blueswir1b4ed08e2009-01-12 17:38:28 +0000538 escc_reset_chn(&serial->chn[0]);
blueswir1f930d072007-10-06 11:28:21 +0000539 return;
blueswir112abac82007-12-10 20:05:09 +0000540 case MINTR_RST_A:
blueswir1b4ed08e2009-01-12 17:38:28 +0000541 escc_reset_chn(&serial->chn[1]);
blueswir1f930d072007-10-06 11:28:21 +0000542 return;
blueswir112abac82007-12-10 20:05:09 +0000543 case MINTR_RST_ALL:
Andreas Färber81069b22013-07-24 21:30:40 +0200544 escc_reset(DEVICE(serial));
blueswir1f930d072007-10-06 11:28:21 +0000545 return;
546 }
547 break;
548 default:
549 break;
550 }
551 if (s->reg == 0)
552 s->reg = newreg;
553 else
554 s->reg = 0;
555 break;
blueswir112abac82007-12-10 20:05:09 +0000556 case SERIAL_DATA:
Blue Swirl30c2f232011-08-07 11:01:05 +0000557 trace_escc_mem_writeb_data(CHN_C(s), val);
blueswir196c4f562007-08-11 07:54:26 +0000558 s->tx = val;
blueswir112abac82007-12-10 20:05:09 +0000559 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
Anton Nefedov30650702017-07-06 15:08:52 +0300560 if (qemu_chr_fe_backend_connected(&s->chr)) {
Daniel P. Berrange6ab3fc32016-09-06 14:56:04 +0100561 /* XXX this blocks entire thread. Rewrite to use
562 * qemu_chr_fe_write and background I/O callbacks */
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300563 qemu_chr_fe_write_all(&s->chr, &s->tx, 1);
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300564 } else if (s->type == kbd && !s->disabled) {
blueswir1f930d072007-10-06 11:28:21 +0000565 handle_kbd_command(s, val);
566 }
567 }
blueswir112abac82007-12-10 20:05:09 +0000568 s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty
569 s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent
blueswir196c4f562007-08-11 07:54:26 +0000570 set_txint(s);
blueswir1f930d072007-10-06 11:28:21 +0000571 break;
bellarde80cfcf2004-12-19 23:18:01 +0000572 default:
blueswir1f930d072007-10-06 11:28:21 +0000573 break;
bellarde80cfcf2004-12-19 23:18:01 +0000574 }
575}
576
Avi Kivitya8170e52012-10-23 12:30:10 +0200577static uint64_t escc_mem_read(void *opaque, hwaddr addr,
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300578 unsigned size)
bellarde80cfcf2004-12-19 23:18:01 +0000579{
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +0200580 ESCCState *serial = opaque;
bellarde80cfcf2004-12-19 23:18:01 +0000581 ChannelState *s;
582 uint32_t saddr;
583 uint32_t ret;
584 int channel;
585
blueswir1b4ed08e2009-01-12 17:38:28 +0000586 saddr = (addr >> serial->it_shift) & 1;
587 channel = (addr >> (serial->it_shift + 1)) & 1;
blueswir1b3ceef22007-06-25 19:56:13 +0000588 s = &serial->chn[channel];
bellarde80cfcf2004-12-19 23:18:01 +0000589 switch (saddr) {
blueswir112abac82007-12-10 20:05:09 +0000590 case SERIAL_CTRL:
Blue Swirl30c2f232011-08-07 11:01:05 +0000591 trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]);
blueswir1f930d072007-10-06 11:28:21 +0000592 ret = s->rregs[s->reg];
593 s->reg = 0;
594 return ret;
blueswir112abac82007-12-10 20:05:09 +0000595 case SERIAL_DATA:
596 s->rregs[R_STATUS] &= ~STATUS_RXAV;
bellardba3c64f2005-12-05 20:31:52 +0000597 clr_rxint(s);
blueswir1f930d072007-10-06 11:28:21 +0000598 if (s->type == kbd || s->type == mouse)
599 ret = get_queue(s);
600 else
601 ret = s->rx;
Blue Swirl30c2f232011-08-07 11:01:05 +0000602 trace_escc_mem_readb_data(CHN_C(s), ret);
Marc-André Lureaufa394ed2016-10-22 12:52:59 +0300603 qemu_chr_fe_accept_input(&s->chr);
blueswir1f930d072007-10-06 11:28:21 +0000604 return ret;
bellarde80cfcf2004-12-19 23:18:01 +0000605 default:
blueswir1f930d072007-10-06 11:28:21 +0000606 break;
bellarde80cfcf2004-12-19 23:18:01 +0000607 }
608 return 0;
609}
610
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300611static const MemoryRegionOps escc_mem_ops = {
612 .read = escc_mem_read,
613 .write = escc_mem_write,
614 .endianness = DEVICE_NATIVE_ENDIAN,
615 .valid = {
616 .min_access_size = 1,
617 .max_access_size = 1,
618 },
619};
620
bellarde80cfcf2004-12-19 23:18:01 +0000621static int serial_can_receive(void *opaque)
622{
623 ChannelState *s = opaque;
bellarde4a89052006-09-09 11:38:11 +0000624 int ret;
625
blueswir112abac82007-12-10 20:05:09 +0000626 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled
627 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV))
628 // char already available
blueswir1f930d072007-10-06 11:28:21 +0000629 ret = 0;
bellarde80cfcf2004-12-19 23:18:01 +0000630 else
blueswir1f930d072007-10-06 11:28:21 +0000631 ret = 1;
bellarde4a89052006-09-09 11:38:11 +0000632 return ret;
bellarde80cfcf2004-12-19 23:18:01 +0000633}
634
635static void serial_receive_byte(ChannelState *s, int ch)
636{
Blue Swirl30c2f232011-08-07 11:01:05 +0000637 trace_escc_serial_receive_byte(CHN_C(s), ch);
blueswir112abac82007-12-10 20:05:09 +0000638 s->rregs[R_STATUS] |= STATUS_RXAV;
bellarde80cfcf2004-12-19 23:18:01 +0000639 s->rx = ch;
bellardba3c64f2005-12-05 20:31:52 +0000640 set_rxint(s);
bellarde80cfcf2004-12-19 23:18:01 +0000641}
642
643static void serial_receive_break(ChannelState *s)
644{
blueswir112abac82007-12-10 20:05:09 +0000645 s->rregs[R_STATUS] |= STATUS_BRK;
blueswir1b4ed08e2009-01-12 17:38:28 +0000646 escc_update_irq(s);
bellarde80cfcf2004-12-19 23:18:01 +0000647}
648
649static void serial_receive1(void *opaque, const uint8_t *buf, int size)
650{
651 ChannelState *s = opaque;
652 serial_receive_byte(s, buf[0]);
653}
654
655static void serial_event(void *opaque, int event)
656{
657 ChannelState *s = opaque;
658 if (event == CHR_EVENT_BREAK)
659 serial_receive_break(s);
660}
661
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000662static const VMStateDescription vmstate_escc_chn = {
663 .name ="escc_chn",
664 .version_id = 2,
665 .minimum_version_id = 1,
Juan Quintela3aff6c22014-04-16 15:24:04 +0200666 .fields = (VMStateField[]) {
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000667 VMSTATE_UINT32(vmstate_dummy, ChannelState),
668 VMSTATE_UINT32(reg, ChannelState),
669 VMSTATE_UINT32(rxint, ChannelState),
670 VMSTATE_UINT32(txint, ChannelState),
671 VMSTATE_UINT32(rxint_under_svc, ChannelState),
672 VMSTATE_UINT32(txint_under_svc, ChannelState),
673 VMSTATE_UINT8(rx, ChannelState),
674 VMSTATE_UINT8(tx, ChannelState),
675 VMSTATE_BUFFER(wregs, ChannelState),
676 VMSTATE_BUFFER(rregs, ChannelState),
677 VMSTATE_END_OF_LIST()
bellarde4a89052006-09-09 11:38:11 +0000678 }
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000679};
bellarde80cfcf2004-12-19 23:18:01 +0000680
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000681static const VMStateDescription vmstate_escc = {
682 .name ="escc",
683 .version_id = 2,
684 .minimum_version_id = 1,
Juan Quintela3aff6c22014-04-16 15:24:04 +0200685 .fields = (VMStateField[]) {
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +0200686 VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn,
Blue Swirlbdb78ca2009-10-24 16:07:10 +0000687 ChannelState),
688 VMSTATE_END_OF_LIST()
689 }
690};
bellarde80cfcf2004-12-19 23:18:01 +0000691
Avi Kivitya8170e52012-10-23 12:30:10 +0200692MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
Marc-André Lureau0ec7b3e2016-12-07 16:20:22 +0300693 Chardev *chrA, Chardev *chrB,
aurel32aeeb69c2009-01-14 14:47:56 +0000694 int clock, int it_shift)
bellarde80cfcf2004-12-19 23:18:01 +0000695{
Blue Swirl6c319c82009-07-15 08:51:32 +0000696 DeviceState *dev;
697 SysBusDevice *s;
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +0200698 ESCCState *d;
bellarde80cfcf2004-12-19 23:18:01 +0000699
Andreas Färber81069b22013-07-24 21:30:40 +0200700 dev = qdev_create(NULL, TYPE_ESCC);
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200701 qdev_prop_set_uint32(dev, "disabled", 0);
702 qdev_prop_set_uint32(dev, "frequency", clock);
703 qdev_prop_set_uint32(dev, "it_shift", it_shift);
Blue Swirlbc19fca2009-08-13 16:26:52 +0000704 qdev_prop_set_chr(dev, "chrB", chrB);
705 qdev_prop_set_chr(dev, "chrA", chrA);
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200706 qdev_prop_set_uint32(dev, "chnBtype", ser);
707 qdev_prop_set_uint32(dev, "chnAtype", ser);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200708 qdev_init_nofail(dev);
Andreas Färber1356b982013-01-20 02:47:33 +0100709 s = SYS_BUS_DEVICE(dev);
Aurelien Jarnoe1a0e472009-09-16 00:13:15 +0200710 sysbus_connect_irq(s, 0, irqB);
711 sysbus_connect_irq(s, 1, irqA);
Blue Swirl6c319c82009-07-15 08:51:32 +0000712 if (base) {
713 sysbus_mmio_map(s, 0, base);
bellarde80cfcf2004-12-19 23:18:01 +0000714 }
Blue Swirl6c319c82009-07-15 08:51:32 +0000715
Andreas Färber81069b22013-07-24 21:30:40 +0200716 d = ESCC(s);
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300717 return &d->mmio;
bellarde80cfcf2004-12-19 23:18:01 +0000718}
719
Eric Blake7fb1cf12015-11-18 01:52:57 -0700720static const uint8_t qcode_to_keycode[Q_KEY_CODE__MAX] = {
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100721 [Q_KEY_CODE_SHIFT] = 99,
722 [Q_KEY_CODE_SHIFT_R] = 110,
723 [Q_KEY_CODE_ALT] = 19,
724 [Q_KEY_CODE_ALT_R] = 13,
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100725 [Q_KEY_CODE_CTRL] = 76,
726 [Q_KEY_CODE_CTRL_R] = 76,
727 [Q_KEY_CODE_ESC] = 29,
728 [Q_KEY_CODE_1] = 30,
729 [Q_KEY_CODE_2] = 31,
730 [Q_KEY_CODE_3] = 32,
731 [Q_KEY_CODE_4] = 33,
732 [Q_KEY_CODE_5] = 34,
733 [Q_KEY_CODE_6] = 35,
734 [Q_KEY_CODE_7] = 36,
735 [Q_KEY_CODE_8] = 37,
736 [Q_KEY_CODE_9] = 38,
737 [Q_KEY_CODE_0] = 39,
738 [Q_KEY_CODE_MINUS] = 40,
739 [Q_KEY_CODE_EQUAL] = 41,
740 [Q_KEY_CODE_BACKSPACE] = 43,
741 [Q_KEY_CODE_TAB] = 53,
742 [Q_KEY_CODE_Q] = 54,
743 [Q_KEY_CODE_W] = 55,
744 [Q_KEY_CODE_E] = 56,
745 [Q_KEY_CODE_R] = 57,
746 [Q_KEY_CODE_T] = 58,
747 [Q_KEY_CODE_Y] = 59,
748 [Q_KEY_CODE_U] = 60,
749 [Q_KEY_CODE_I] = 61,
750 [Q_KEY_CODE_O] = 62,
751 [Q_KEY_CODE_P] = 63,
752 [Q_KEY_CODE_BRACKET_LEFT] = 64,
753 [Q_KEY_CODE_BRACKET_RIGHT] = 65,
754 [Q_KEY_CODE_RET] = 89,
755 [Q_KEY_CODE_A] = 77,
756 [Q_KEY_CODE_S] = 78,
757 [Q_KEY_CODE_D] = 79,
758 [Q_KEY_CODE_F] = 80,
759 [Q_KEY_CODE_G] = 81,
760 [Q_KEY_CODE_H] = 82,
761 [Q_KEY_CODE_J] = 83,
762 [Q_KEY_CODE_K] = 84,
763 [Q_KEY_CODE_L] = 85,
764 [Q_KEY_CODE_SEMICOLON] = 86,
765 [Q_KEY_CODE_APOSTROPHE] = 87,
766 [Q_KEY_CODE_GRAVE_ACCENT] = 42,
767 [Q_KEY_CODE_BACKSLASH] = 88,
768 [Q_KEY_CODE_Z] = 100,
769 [Q_KEY_CODE_X] = 101,
770 [Q_KEY_CODE_C] = 102,
771 [Q_KEY_CODE_V] = 103,
772 [Q_KEY_CODE_B] = 104,
773 [Q_KEY_CODE_N] = 105,
774 [Q_KEY_CODE_M] = 106,
775 [Q_KEY_CODE_COMMA] = 107,
776 [Q_KEY_CODE_DOT] = 108,
777 [Q_KEY_CODE_SLASH] = 109,
778 [Q_KEY_CODE_ASTERISK] = 47,
779 [Q_KEY_CODE_SPC] = 121,
780 [Q_KEY_CODE_CAPS_LOCK] = 119,
781 [Q_KEY_CODE_F1] = 5,
782 [Q_KEY_CODE_F2] = 6,
783 [Q_KEY_CODE_F3] = 8,
784 [Q_KEY_CODE_F4] = 10,
785 [Q_KEY_CODE_F5] = 12,
786 [Q_KEY_CODE_F6] = 14,
787 [Q_KEY_CODE_F7] = 16,
788 [Q_KEY_CODE_F8] = 17,
789 [Q_KEY_CODE_F9] = 18,
790 [Q_KEY_CODE_F10] = 7,
791 [Q_KEY_CODE_NUM_LOCK] = 98,
792 [Q_KEY_CODE_SCROLL_LOCK] = 23,
Gerd Hoffmann97256072014-04-29 13:19:32 +0200793 [Q_KEY_CODE_KP_DIVIDE] = 46,
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100794 [Q_KEY_CODE_KP_MULTIPLY] = 47,
795 [Q_KEY_CODE_KP_SUBTRACT] = 71,
796 [Q_KEY_CODE_KP_ADD] = 125,
797 [Q_KEY_CODE_KP_ENTER] = 90,
798 [Q_KEY_CODE_KP_DECIMAL] = 50,
799 [Q_KEY_CODE_KP_0] = 94,
800 [Q_KEY_CODE_KP_1] = 112,
801 [Q_KEY_CODE_KP_2] = 113,
802 [Q_KEY_CODE_KP_3] = 114,
803 [Q_KEY_CODE_KP_4] = 91,
804 [Q_KEY_CODE_KP_5] = 92,
805 [Q_KEY_CODE_KP_6] = 93,
806 [Q_KEY_CODE_KP_7] = 68,
807 [Q_KEY_CODE_KP_8] = 69,
808 [Q_KEY_CODE_KP_9] = 70,
809 [Q_KEY_CODE_LESS] = 124,
810 [Q_KEY_CODE_F11] = 9,
811 [Q_KEY_CODE_F12] = 11,
Gerd Hoffmann97256072014-04-29 13:19:32 +0200812 [Q_KEY_CODE_HOME] = 52,
813 [Q_KEY_CODE_PGUP] = 96,
814 [Q_KEY_CODE_PGDN] = 123,
815 [Q_KEY_CODE_END] = 74,
816 [Q_KEY_CODE_LEFT] = 24,
817 [Q_KEY_CODE_UP] = 20,
818 [Q_KEY_CODE_DOWN] = 27,
819 [Q_KEY_CODE_RIGHT] = 28,
820 [Q_KEY_CODE_INSERT] = 44,
821 [Q_KEY_CODE_DELETE] = 66,
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100822 [Q_KEY_CODE_STOP] = 1,
823 [Q_KEY_CODE_AGAIN] = 3,
824 [Q_KEY_CODE_PROPS] = 25,
825 [Q_KEY_CODE_UNDO] = 26,
826 [Q_KEY_CODE_FRONT] = 49,
Gerd Hoffmann97256072014-04-29 13:19:32 +0200827 [Q_KEY_CODE_COPY] = 51,
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100828 [Q_KEY_CODE_OPEN] = 72,
829 [Q_KEY_CODE_PASTE] = 73,
Gerd Hoffmann97256072014-04-29 13:19:32 +0200830 [Q_KEY_CODE_FIND] = 95,
831 [Q_KEY_CODE_CUT] = 97,
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100832 [Q_KEY_CODE_LF] = 111,
833 [Q_KEY_CODE_HELP] = 118,
834 [Q_KEY_CODE_META_L] = 120,
835 [Q_KEY_CODE_META_R] = 122,
836 [Q_KEY_CODE_COMPOSE] = 67,
Gerd Hoffmann97256072014-04-29 13:19:32 +0200837 [Q_KEY_CODE_PRINT] = 22,
838 [Q_KEY_CODE_SYSRQ] = 21,
bellard8be1f5c2005-04-06 20:42:35 +0000839};
840
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100841static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src,
842 InputEvent *evt)
bellarde80cfcf2004-12-19 23:18:01 +0000843{
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100844 ChannelState *s = (ChannelState *)dev;
845 int qcode, keycode;
Eric Blakeb5a1b442016-03-03 09:16:49 -0700846 InputKeyEvent *key;
bellard8be1f5c2005-04-06 20:42:35 +0000847
Eric Blake568c73a2015-10-26 16:34:58 -0600848 assert(evt->type == INPUT_EVENT_KIND_KEY);
Eric Blake32bafa82016-03-17 16:48:37 -0600849 key = evt->u.key.data;
Eric Blakeb5a1b442016-03-03 09:16:49 -0700850 qcode = qemu_input_key_value_to_qcode(key->key);
Markus Armbruster977c7362017-08-24 10:46:08 +0200851 trace_escc_sunkbd_event_in(qcode, QKeyCode_str(qcode),
Eric Blakeb5a1b442016-03-03 09:16:49 -0700852 key->down);
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100853
854 if (qcode == Q_KEY_CODE_CAPS_LOCK) {
Eric Blakeb5a1b442016-03-03 09:16:49 -0700855 if (key->down) {
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100856 s->caps_lock_mode ^= 1;
857 if (s->caps_lock_mode == 2) {
858 return; /* Drop second press */
859 }
860 } else {
861 s->caps_lock_mode ^= 2;
862 if (s->caps_lock_mode == 3) {
863 return; /* Drop first release */
864 }
865 }
blueswir143febf42007-09-21 19:09:35 +0000866 }
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100867
868 if (qcode == Q_KEY_CODE_NUM_LOCK) {
Eric Blakeb5a1b442016-03-03 09:16:49 -0700869 if (key->down) {
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100870 s->num_lock_mode ^= 1;
871 if (s->num_lock_mode == 2) {
872 return; /* Drop second press */
873 }
874 } else {
875 s->num_lock_mode ^= 2;
876 if (s->num_lock_mode == 3) {
877 return; /* Drop first release */
878 }
879 }
blueswir143febf42007-09-21 19:09:35 +0000880 }
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100881
882 keycode = qcode_to_keycode[qcode];
Eric Blakeb5a1b442016-03-03 09:16:49 -0700883 if (!key->down) {
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100884 keycode |= 0x80;
885 }
886 trace_escc_sunkbd_event_out(keycode);
887 put_queue(s, keycode);
bellard8be1f5c2005-04-06 20:42:35 +0000888}
889
Gerd Hoffmann65e75452014-03-25 13:16:21 +0100890static QemuInputHandler sunkbd_handler = {
891 .name = "sun keyboard",
892 .mask = INPUT_EVENT_MASK_KEY,
893 .event = sunkbd_handle_event,
894};
895
bellard8be1f5c2005-04-06 20:42:35 +0000896static void handle_kbd_command(ChannelState *s, int val)
897{
Blue Swirl30c2f232011-08-07 11:01:05 +0000898 trace_escc_kbd_command(val);
blueswir143febf42007-09-21 19:09:35 +0000899 if (s->led_mode) { // Ignore led byte
900 s->led_mode = 0;
901 return;
902 }
bellard8be1f5c2005-04-06 20:42:35 +0000903 switch (val) {
904 case 1: // Reset, return type code
blueswir167deb562007-04-18 19:21:38 +0000905 clear_queue(s);
blueswir1f930d072007-10-06 11:28:21 +0000906 put_queue(s, 0xff);
907 put_queue(s, 4); // Type 4
908 put_queue(s, 0x7f);
909 break;
blueswir143febf42007-09-21 19:09:35 +0000910 case 0xe: // Set leds
911 s->led_mode = 1;
912 break;
bellard8be1f5c2005-04-06 20:42:35 +0000913 case 7: // Query layout
blueswir167deb562007-04-18 19:21:38 +0000914 case 0xf:
915 clear_queue(s);
blueswir1f930d072007-10-06 11:28:21 +0000916 put_queue(s, 0xfe);
Gerd Hoffmann59e7a132014-05-06 14:11:16 +0200917 put_queue(s, 0x21); /* en-us layout */
blueswir1f930d072007-10-06 11:28:21 +0000918 break;
bellard8be1f5c2005-04-06 20:42:35 +0000919 default:
blueswir1f930d072007-10-06 11:28:21 +0000920 break;
bellard8be1f5c2005-04-06 20:42:35 +0000921 }
bellarde80cfcf2004-12-19 23:18:01 +0000922}
923
ths5fafdf22007-09-16 21:08:06 +0000924static void sunmouse_event(void *opaque,
bellarde80cfcf2004-12-19 23:18:01 +0000925 int dx, int dy, int dz, int buttons_state)
926{
927 ChannelState *s = opaque;
928 int ch;
929
Blue Swirl30c2f232011-08-07 11:01:05 +0000930 trace_escc_sunmouse_event(dx, dy, buttons_state);
bellard715748f2006-09-09 11:35:47 +0000931 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
932
933 if (buttons_state & MOUSE_EVENT_LBUTTON)
934 ch ^= 0x4;
935 if (buttons_state & MOUSE_EVENT_MBUTTON)
936 ch ^= 0x2;
937 if (buttons_state & MOUSE_EVENT_RBUTTON)
938 ch ^= 0x1;
939
940 put_queue(s, ch);
941
942 ch = dx;
943
944 if (ch > 127)
Michael S. Tsirkina0d98a72009-09-30 19:43:55 +0200945 ch = 127;
bellard715748f2006-09-09 11:35:47 +0000946 else if (ch < -127)
Michael S. Tsirkina0d98a72009-09-30 19:43:55 +0200947 ch = -127;
bellard715748f2006-09-09 11:35:47 +0000948
949 put_queue(s, ch & 0xff);
950
951 ch = -dy;
952
953 if (ch > 127)
Michael S. Tsirkin084bd072009-09-30 18:56:44 +0000954 ch = 127;
bellard715748f2006-09-09 11:35:47 +0000955 else if (ch < -127)
Michael S. Tsirkin084bd072009-09-30 18:56:44 +0000956 ch = -127;
bellard715748f2006-09-09 11:35:47 +0000957
958 put_queue(s, ch & 0xff);
959
960 // MSC protocol specify two extra motion bytes
961
962 put_queue(s, 0);
963 put_queue(s, 0);
bellarde80cfcf2004-12-19 23:18:01 +0000964}
965
Avi Kivitya8170e52012-10-23 12:30:10 +0200966void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
blueswir1b4ed08e2009-01-12 17:38:28 +0000967 int disabled, int clock, int it_shift)
bellarde80cfcf2004-12-19 23:18:01 +0000968{
Blue Swirl6c319c82009-07-15 08:51:32 +0000969 DeviceState *dev;
970 SysBusDevice *s;
bellarde80cfcf2004-12-19 23:18:01 +0000971
Andreas Färber81069b22013-07-24 21:30:40 +0200972 dev = qdev_create(NULL, TYPE_ESCC);
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200973 qdev_prop_set_uint32(dev, "disabled", disabled);
974 qdev_prop_set_uint32(dev, "frequency", clock);
975 qdev_prop_set_uint32(dev, "it_shift", it_shift);
Blue Swirlbc19fca2009-08-13 16:26:52 +0000976 qdev_prop_set_chr(dev, "chrB", NULL);
977 qdev_prop_set_chr(dev, "chrA", NULL);
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200978 qdev_prop_set_uint32(dev, "chnBtype", mouse);
979 qdev_prop_set_uint32(dev, "chnAtype", kbd);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200980 qdev_init_nofail(dev);
Andreas Färber1356b982013-01-20 02:47:33 +0100981 s = SYS_BUS_DEVICE(dev);
Blue Swirl6c319c82009-07-15 08:51:32 +0000982 sysbus_connect_irq(s, 0, irq);
983 sysbus_connect_irq(s, 1, irq);
984 sysbus_mmio_map(s, 0, base);
985}
blueswir1b4ed08e2009-01-12 17:38:28 +0000986
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +0800987static void escc_init1(Object *obj)
Blue Swirl6c319c82009-07-15 08:51:32 +0000988{
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +0800989 ESCCState *s = ESCC(obj);
990 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
Blue Swirl6c319c82009-07-15 08:51:32 +0000991 unsigned int i;
Blue Swirl6c319c82009-07-15 08:51:32 +0000992
bellard8be1f5c2005-04-06 20:42:35 +0000993 for (i = 0; i < 2; i++) {
Blue Swirl6c319c82009-07-15 08:51:32 +0000994 sysbus_init_irq(dev, &s->chn[i].irq);
blueswir1f930d072007-10-06 11:28:21 +0000995 s->chn[i].chn = 1 - i;
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +0800996 }
997 s->chn[0].otherchn = &s->chn[1];
998 s->chn[1].otherchn = &s->chn[0];
999
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +08001000 sysbus_init_mmio(dev, &s->mmio);
1001}
1002
1003static void escc_realize(DeviceState *dev, Error **errp)
1004{
1005 ESCCState *s = ESCC(dev);
1006 unsigned int i;
1007
xiaoqiang zhao4b3eec92016-06-01 15:58:18 +08001008 s->chn[0].disabled = s->disabled;
1009 s->chn[1].disabled = s->disabled;
1010
1011 memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc",
1012 ESCC_SIZE << s->it_shift);
1013
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +08001014 for (i = 0; i < 2; i++) {
Anton Nefedov30650702017-07-06 15:08:52 +03001015 if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) {
xiaoqiang zhao4b3eec92016-06-01 15:58:18 +08001016 s->chn[i].clock = s->frequency / 2;
Marc-André Lureau5345fdb2016-10-22 12:52:55 +03001017 qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive,
Anton Nefedov81517ba2017-07-06 15:08:49 +03001018 serial_receive1, serial_event, NULL,
Marc-André Lureau39ab61c2016-10-22 12:53:03 +03001019 &s->chn[i], NULL, true);
Blue Swirl6c319c82009-07-15 08:51:32 +00001020 }
bellard8be1f5c2005-04-06 20:42:35 +00001021 }
bellarde80cfcf2004-12-19 23:18:01 +00001022
Blue Swirl6c319c82009-07-15 08:51:32 +00001023 if (s->chn[0].type == mouse) {
1024 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
1025 "QEMU Sun Mouse");
1026 }
1027 if (s->chn[1].type == kbd) {
Gerd Hoffmann65e75452014-03-25 13:16:21 +01001028 s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]),
1029 &sunkbd_handler);
Blue Swirl6c319c82009-07-15 08:51:32 +00001030 }
bellarde80cfcf2004-12-19 23:18:01 +00001031}
Blue Swirl6c319c82009-07-15 08:51:32 +00001032
Anthony Liguori999e12b2012-01-24 13:12:29 -06001033static Property escc_properties[] = {
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +02001034 DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0),
1035 DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0),
1036 DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0),
1037 DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0),
1038 DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0),
1039 DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr),
1040 DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr),
Anthony Liguori999e12b2012-01-24 13:12:29 -06001041 DEFINE_PROP_END_OF_LIST(),
1042};
1043
1044static void escc_class_init(ObjectClass *klass, void *data)
1045{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001046 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -06001047
Anthony Liguori39bffca2011-12-07 21:34:16 -06001048 dc->reset = escc_reset;
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +08001049 dc->realize = escc_realize;
Anthony Liguori39bffca2011-12-07 21:34:16 -06001050 dc->vmsd = &vmstate_escc;
1051 dc->props = escc_properties;
Laurent Vivierf8d4c072015-09-26 18:22:05 +02001052 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
Anthony Liguori999e12b2012-01-24 13:12:29 -06001053}
1054
Andreas Färber8c43a6f2013-01-10 16:19:07 +01001055static const TypeInfo escc_info = {
Andreas Färber81069b22013-07-24 21:30:40 +02001056 .name = TYPE_ESCC,
Anthony Liguori39bffca2011-12-07 21:34:16 -06001057 .parent = TYPE_SYS_BUS_DEVICE,
Paolo Bonzini3cf63ff2013-06-25 15:02:38 +02001058 .instance_size = sizeof(ESCCState),
xiaoqiang zhaoe7c913692016-05-25 14:39:00 +08001059 .instance_init = escc_init1,
Anthony Liguori39bffca2011-12-07 21:34:16 -06001060 .class_init = escc_class_init,
Blue Swirl6c319c82009-07-15 08:51:32 +00001061};
1062
Andreas Färber83f7d432012-02-09 15:20:55 +01001063static void escc_register_types(void)
Blue Swirl6c319c82009-07-15 08:51:32 +00001064{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001065 type_register_static(&escc_info);
Blue Swirl6c319c82009-07-15 08:51:32 +00001066}
1067
Andreas Färber83f7d432012-02-09 15:20:55 +01001068type_init(escc_register_types)