blob: 638dc806a5feff268d629535c132a2c6b334f324 [file] [log] [blame]
Philippe Mathieu-Daudéf184f382024-04-24 18:04:09 +02001/*
2 * CPU interfaces that are target independent.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * SPDX-License-Identifier: LGPL-2.1+
7 */
Paul Brook1ad21342009-05-19 16:17:58 +01008#ifndef CPU_COMMON_H
Markus Armbruster175de522016-06-29 15:29:06 +02009#define CPU_COMMON_H
Paul Brook1ad21342009-05-19 16:17:58 +010010
Anton Johanssonc4b3f462024-01-19 15:39:56 +010011#include "exec/vaddr.h"
Andreas Färberce927ed2013-05-28 14:02:38 +020012#ifndef CONFIG_USER_ONLY
Paolo Bonzini022c62c2012-12-17 18:19:49 +010013#include "exec/hwaddr.h"
Andreas Färberce927ed2013-05-28 14:02:38 +020014#endif
Anton Johanssona7f6f4f2024-01-19 15:40:06 +010015#include "hw/core/cpu.h"
Richard Hendersona120d322024-01-29 11:37:54 +100016#include "tcg/debug-assert.h"
Philippe Mathieu-Daudé74781c02023-12-06 20:27:32 +010017#include "exec/page-protection.h"
Paolo Bonzini37b76cf2010-04-01 19:57:10 +020018
Philippe Mathieu-Daudé65b074d2023-09-14 20:57:07 +020019#define EXCP_INTERRUPT 0x10000 /* async interruption */
20#define EXCP_HLT 0x10001 /* hlt instruction reached */
21#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
22#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
23#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
24#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
25
Marc-André Lureau1f269c12022-03-23 19:57:33 +040026void cpu_exec_init_all(void);
27void cpu_exec_step_atomic(CPUState *cpu);
28
Marc-André Lureau8e3b0cb2022-03-23 19:57:22 +040029#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
Philippe Mathieu-Daudéb269a702022-01-20 01:08:36 +010030
Emilio G. Cota0ac20312017-08-04 23:46:31 -040031/* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
Jamie Iles370ed602023-04-27 03:09:24 +010032extern QemuMutex qemu_cpu_list_lock;
Paolo Bonzini267f6852016-08-28 03:45:14 +020033void qemu_init_cpu_list(void);
34void cpu_list_lock(void);
35void cpu_list_unlock(void);
Hyman Huang(黄勇)ab1a1612022-06-26 01:38:31 +080036unsigned int cpu_list_generation_id_get(void);
Paolo Bonzini267f6852016-08-28 03:45:14 +020037
Harsh Prateek Bora18530e72024-06-18 13:53:53 +053038int cpu_get_free_index(void);
39
Paolo Bonzinid9f24bf2020-10-06 09:05:29 +020040void tcg_iommu_init_notifier_list(CPUState *cpu);
41void tcg_iommu_free_notifier_list(CPUState *cpu);
42
Paul Brookb3755a92010-03-12 16:54:58 +000043#if !defined(CONFIG_USER_ONLY)
44
Alexander Grafdd310532010-12-08 12:05:36 +010045enum device_endian {
46 DEVICE_NATIVE_ENDIAN,
47 DEVICE_BIG_ENDIAN,
48 DEVICE_LITTLE_ENDIAN,
49};
50
Marc-André Lureaue03b5682022-03-23 19:57:17 +040051#if HOST_BIG_ENDIAN
Yongji Xiec99a29e2017-02-27 12:52:44 +080052#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
53#else
54#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
55#endif
56
Paul Brook1ad21342009-05-19 16:17:58 +010057/* address in the RAM (different from a physical address) */
Avi Kivity4be403c2012-10-04 12:36:04 +020058#if defined(CONFIG_XEN_BACKEND)
Anthony PERARDf15fbc42011-07-20 08:17:42 +000059typedef uint64_t ram_addr_t;
60# define RAM_ADDR_MAX UINT64_MAX
61# define RAM_ADDR_FMT "%" PRIx64
62#else
Stefan Weil53576992012-03-02 23:30:02 +010063typedef uintptr_t ram_addr_t;
64# define RAM_ADDR_MAX UINTPTR_MAX
65# define RAM_ADDR_FMT "%" PRIxPTR
Anthony PERARDf15fbc42011-07-20 08:17:42 +000066#endif
Paul Brook1ad21342009-05-19 16:17:58 +010067
68/* memory API */
69
Huang Yingcd19cfa2011-03-02 08:56:19 +010070void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
Paul Brook1ad21342009-05-19 16:17:58 +010071/* This should not be used by devices. */
Paolo Bonzini07bdaa42016-03-25 12:55:08 +010072ram_addr_t qemu_ram_addr_from_host(void *ptr);
Richard Henderson97e03462022-08-10 12:04:15 -070073ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
Dr. David Alan Gilberte3dd7492015-11-05 18:10:33 +000074RAMBlock *qemu_ram_block_by_name(const char *name);
David Hildenbrand022f0332023-09-26 20:57:23 +020075
76/*
77 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock.
78 *
79 * @ptr: The host pointer to translate.
80 * @round_offset: Whether to round the result offset down to a target page
81 * @offset: Will be set to the offset within the returned RAMBlock.
82 *
83 * Returns: RAMBlock (or NULL if not found)
84 *
85 * By the time this function returns, the returned pointer is not protected
86 * by RCU anymore. If the caller is not within an RCU critical section and
Stefan Hajnoczia4a411f2024-01-02 10:35:28 -050087 * does not hold the BQL, it must have other means of protecting the
David Hildenbrand022f0332023-09-26 20:57:23 +020088 * pointer, such as a reference to the memory region that owns the RAMBlock.
89 */
Dr. David Alan Gilbert422148d2015-11-05 18:10:32 +000090RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
Paolo Bonzinif615f392016-05-26 10:07:50 +020091 ram_addr_t *offset);
Dr. David Alan Gilbertf90bb712018-03-12 17:20:57 +000092ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
Gongleifa53a0e2016-05-10 10:04:59 +080093void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
94void qemu_ram_unset_idstr(RAMBlock *block);
Dr. David Alan Gilbert422148d2015-11-05 18:10:32 +000095const char *qemu_ram_get_idstr(RAMBlock *rb);
Yury Kotov754cb9c2019-02-15 20:45:44 +030096void *qemu_ram_get_host_addr(RAMBlock *rb);
97ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
98ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
David Hildenbrand082851a2021-04-29 13:26:59 +020099ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
Dr. David Alan Gilbert463a4ac2017-03-07 18:36:36 +0000100bool qemu_ram_is_shared(RAMBlock *rb);
David Hildenbrand8dbe22c2021-05-10 13:43:21 +0200101bool qemu_ram_is_noreserve(RAMBlock *rb);
Dr. David Alan Gilbert2ce16642018-03-12 17:20:58 +0000102bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
103void qemu_ram_set_uf_zeroable(RAMBlock *rb);
Cédric Le Goaterb895de52018-05-14 08:57:00 +0200104bool qemu_ram_is_migratable(RAMBlock *rb);
105void qemu_ram_set_migratable(RAMBlock *rb);
106void qemu_ram_unset_migratable(RAMBlock *rb);
Steve Sistareb0182e52023-06-07 08:18:36 -0700107bool qemu_ram_is_named_file(RAMBlock *rb);
Stefan Hajnoczi6d998f32022-10-13 14:59:05 -0400108int qemu_ram_get_fd(RAMBlock *rb);
Dr. David Alan Gilbert2ce16642018-03-12 17:20:58 +0000109
Dr. David Alan Gilbert863e9622016-09-29 20:09:37 +0100110size_t qemu_ram_pagesize(RAMBlock *block);
Dr. David Alan Gilbert67f11b52017-02-24 18:28:34 +0000111size_t qemu_ram_pagesize_largest(void);
Paul Brook1ad21342009-05-19 16:17:58 +0100112
Philippe Mathieu-Daudé1f649fe2021-05-16 19:01:31 +0200113/**
114 * cpu_address_space_init:
115 * @cpu: CPU to add this address space to
116 * @asidx: integer index of this address space
117 * @prefix: prefix to be used as name of address space
118 * @mr: the root memory region of address space
119 *
120 * Add the specified address space to the CPU's cpu_ases list.
121 * The address space added with @asidx 0 is the one used for the
122 * convenience pointer cpu->as.
123 * The target-specific code which registers ASes is responsible
124 * for defining what semantics address space 0, 1, 2, etc have.
125 *
126 * Before the first call to this function, the caller must set
127 * cpu->num_ases to the total number of address spaces it needs
128 * to support.
129 *
130 * Note that with KVM only one address space is supported.
131 */
132void cpu_address_space_init(CPUState *cpu, int asidx,
133 const char *prefix, MemoryRegion *mr);
Salil Mehta24bec422024-07-16 12:15:01 +0100134/**
135 * cpu_address_space_destroy:
136 * @cpu: CPU for which address space needs to be destroyed
137 * @asidx: integer index of this address space
138 *
139 * Note that with KVM only one address space is supported.
140 */
141void cpu_address_space_destroy(CPUState *cpu, int asidx);
Philippe Mathieu-Daudé1f649fe2021-05-16 19:01:31 +0200142
Philippe Mathieu-Daudéd7ef71e2020-02-19 20:02:11 +0100143void cpu_physical_memory_rw(hwaddr addr, void *buf,
Philippe Mathieu-Daudé28c80bf2020-02-19 20:32:30 +0100144 hwaddr len, bool is_write);
Avi Kivitya8170e52012-10-23 12:30:10 +0200145static inline void cpu_physical_memory_read(hwaddr addr,
Li Zhijian0c249ff2019-01-17 20:49:01 +0800146 void *buf, hwaddr len)
Paul Brook1ad21342009-05-19 16:17:58 +0100147{
Philippe Mathieu-Daudé85eb7c12020-02-19 20:20:42 +0100148 cpu_physical_memory_rw(addr, buf, len, false);
Paul Brook1ad21342009-05-19 16:17:58 +0100149}
Avi Kivitya8170e52012-10-23 12:30:10 +0200150static inline void cpu_physical_memory_write(hwaddr addr,
Li Zhijian0c249ff2019-01-17 20:49:01 +0800151 const void *buf, hwaddr len)
Paul Brook1ad21342009-05-19 16:17:58 +0100152{
Philippe Mathieu-Daudé85eb7c12020-02-19 20:20:42 +0100153 cpu_physical_memory_rw(addr, (void *)buf, len, true);
Paul Brook1ad21342009-05-19 16:17:58 +0100154}
Avi Kivitya8170e52012-10-23 12:30:10 +0200155void *cpu_physical_memory_map(hwaddr addr,
156 hwaddr *plen,
Philippe Mathieu-Daudé28c80bf2020-02-19 20:32:30 +0100157 bool is_write);
Avi Kivitya8170e52012-10-23 12:30:10 +0200158void cpu_physical_memory_unmap(void *buffer, hwaddr len,
Philippe Mathieu-Daudé28c80bf2020-02-19 20:32:30 +0100159 bool is_write, hwaddr access_len);
Paul Brook1ad21342009-05-19 16:17:58 +0100160
Avi Kivitya8170e52012-10-23 12:30:10 +0200161bool cpu_physical_memory_is_io(hwaddr phys_addr);
Wen Congyang76f35532012-05-07 12:04:18 +0800162
Blue Swirl6842a082010-03-21 19:47:13 +0000163/* Coalesced MMIO regions are areas where write operations can be reordered.
164 * This usually implies that write operations are side-effect free. This allows
165 * batching which can make a major impact on performance when using
166 * virtualization.
167 */
Blue Swirl6842a082010-03-21 19:47:13 +0000168void qemu_flush_coalesced_mmio_buffer(void);
169
Li Zhijian0c249ff2019-01-17 20:49:01 +0800170void cpu_flush_icache_range(hwaddr start, hwaddr len);
Paul Brook1ad21342009-05-19 16:17:58 +0100171
Yury Kotov754cb9c2019-02-15 20:45:44 +0300172typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
Michael R. Hinesbd2fa512013-06-25 21:35:34 -0400173
Dr. David Alan Gilberte3807052015-05-21 13:24:13 +0100174int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
Dr. David Alan Gilbertd3a50382017-02-24 18:28:32 +0000175int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
Xiaoyao Lib2e94262024-03-20 03:39:07 -0500176int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start,
177 size_t length);
Michael R. Hinesbd2fa512013-06-25 21:35:34 -0400178
Paul Brookb3755a92010-03-12 16:54:58 +0000179#endif
180
Philippe Mathieu-Daudé73842ef2022-02-03 02:13:28 +0100181/* Returns: 0 on success, -1 on error */
182int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
183 void *ptr, size_t len, bool is_write);
184
Paolo Bonzinic5e3c912020-10-28 08:04:08 -0400185/* vl.c */
Thomas Huthc138c3b2023-04-19 14:48:31 +0200186void list_cpus(void);
Philippe Mathieu-Daudé377bf6f2022-03-14 15:01:08 +0100187
Philippe Mathieu-Daudé35491182023-09-14 20:57:08 +0200188#ifdef CONFIG_TCG
Philippe Mathieu-Daudéb254c342024-01-10 18:09:56 +0100189
190bool tcg_cflags_has(CPUState *cpu, uint32_t flags);
191void tcg_cflags_set(CPUState *cpu, uint32_t flags);
192
193/* current cflags for hashing/comparison */
194uint32_t curr_cflags(CPUState *cpu);
195
Philippe Mathieu-Daudé35491182023-09-14 20:57:08 +0200196/**
197 * cpu_unwind_state_data:
198 * @cpu: the cpu context
199 * @host_pc: the host pc within the translation
200 * @data: output data
201 *
202 * Attempt to load the the unwind state for a host pc occurring in
203 * translated code. If @host_pc is not in translated code, the
204 * function returns false; otherwise @data is loaded.
205 * This is the same unwind info as given to restore_state_to_opc.
206 */
207bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
208
209/**
210 * cpu_restore_state:
211 * @cpu: the cpu context
212 * @host_pc: the host pc within the translation
213 * @return: true if state was restored, false otherwise
214 *
215 * Attempt to restore the state for a fault occurring in translated
216 * code. If @host_pc is not in translated code no state is
217 * restored and the function returns false.
218 */
219bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc);
220
221G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
222G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
223#endif /* CONFIG_TCG */
224G_NORETURN void cpu_loop_exit(CPUState *cpu);
225G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
226
Anton Johanssona7f6f4f2024-01-19 15:40:06 +0100227/* accel/tcg/cpu-exec.c */
228int cpu_exec(CPUState *cpu);
229
230/**
231 * env_archcpu(env)
232 * @env: The architecture environment
233 *
234 * Return the ArchCPU associated with the environment.
235 */
236static inline ArchCPU *env_archcpu(CPUArchState *env)
237{
238 return (void *)env - sizeof(CPUState);
239}
240
241/**
Ilya Leoshkevichf781af32024-09-12 11:28:20 +0200242 * env_cpu_const(env)
243 * @env: The architecture environment
244 *
245 * Return the CPUState associated with the environment.
246 */
247static inline const CPUState *env_cpu_const(const CPUArchState *env)
248{
249 return (void *)env - sizeof(CPUState);
250}
251
252/**
Anton Johanssona7f6f4f2024-01-19 15:40:06 +0100253 * env_cpu(env)
254 * @env: The architecture environment
255 *
256 * Return the CPUState associated with the environment.
257 */
258static inline CPUState *env_cpu(CPUArchState *env)
259{
Ilya Leoshkevichf781af32024-09-12 11:28:20 +0200260 return (CPUState *)env_cpu_const(env);
Anton Johanssona7f6f4f2024-01-19 15:40:06 +0100261}
262
Richard Hendersona120d322024-01-29 11:37:54 +1000263#ifndef CONFIG_USER_ONLY
264/**
265 * cpu_mmu_index:
266 * @env: The cpu environment
267 * @ifetch: True for code access, false for data access.
268 *
269 * Return the core mmu index for the current translation regime.
270 * This function is used by generic TCG code paths.
271 *
272 * The user-only version of this function is inline in cpu-all.h,
273 * where it always returns MMU_USER_IDX.
274 */
Richard Henderson3b916142024-01-29 20:35:06 +1000275static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
Richard Hendersona120d322024-01-29 11:37:54 +1000276{
Richard Hendersona120d322024-01-29 11:37:54 +1000277 int ret = cs->cc->mmu_index(cs, ifetch);
278 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
279 return ret;
280}
281#endif /* !CONFIG_USER_ONLY */
282
Markus Armbruster175de522016-06-29 15:29:06 +0200283#endif /* CPU_COMMON_H */