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Paul Brook1ad21342009-05-19 16:17:58 +01001#ifndef CPU_COMMON_H
Markus Armbruster175de522016-06-29 15:29:06 +02002#define CPU_COMMON_H
Paul Brook1ad21342009-05-19 16:17:58 +01003
Dong Xu Wang07f35072011-11-22 18:06:26 +08004/* CPU interfaces that are target independent. */
Paul Brook1ad21342009-05-19 16:17:58 +01005
Anton Johanssonc4b3f462024-01-19 15:39:56 +01006#include "exec/vaddr.h"
Andreas Färberce927ed2013-05-28 14:02:38 +02007#ifndef CONFIG_USER_ONLY
Paolo Bonzini022c62c2012-12-17 18:19:49 +01008#include "exec/hwaddr.h"
Andreas Färberce927ed2013-05-28 14:02:38 +02009#endif
Anton Johanssona7f6f4f2024-01-19 15:40:06 +010010#include "hw/core/cpu.h"
Richard Hendersona120d322024-01-29 11:37:54 +100011#include "tcg/debug-assert.h"
Paolo Bonzini37b76cf2010-04-01 19:57:10 +020012
Philippe Mathieu-Daudé65b074d2023-09-14 20:57:07 +020013#define EXCP_INTERRUPT 0x10000 /* async interruption */
14#define EXCP_HLT 0x10001 /* hlt instruction reached */
15#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
16#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
17#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
18#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
19
Marc-André Lureau1f269c12022-03-23 19:57:33 +040020void cpu_exec_init_all(void);
21void cpu_exec_step_atomic(CPUState *cpu);
22
Philippe Mathieu-Daudéb269a702022-01-20 01:08:36 +010023/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
24 * when intptr_t is 32-bit and we are aligning a long long.
25 */
26extern uintptr_t qemu_host_page_size;
27extern intptr_t qemu_host_page_mask;
28
29#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
Marc-André Lureau8e3b0cb2022-03-23 19:57:22 +040030#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
Philippe Mathieu-Daudéb269a702022-01-20 01:08:36 +010031
Emilio G. Cota0ac20312017-08-04 23:46:31 -040032/* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
Jamie Iles370ed602023-04-27 03:09:24 +010033extern QemuMutex qemu_cpu_list_lock;
Paolo Bonzini267f6852016-08-28 03:45:14 +020034void qemu_init_cpu_list(void);
35void cpu_list_lock(void);
36void cpu_list_unlock(void);
Hyman Huang(黄勇)ab1a1612022-06-26 01:38:31 +080037unsigned int cpu_list_generation_id_get(void);
Paolo Bonzini267f6852016-08-28 03:45:14 +020038
Paolo Bonzinid9f24bf2020-10-06 09:05:29 +020039void tcg_iommu_init_notifier_list(CPUState *cpu);
40void tcg_iommu_free_notifier_list(CPUState *cpu);
41
Paul Brookb3755a92010-03-12 16:54:58 +000042#if !defined(CONFIG_USER_ONLY)
43
Alexander Grafdd310532010-12-08 12:05:36 +010044enum device_endian {
45 DEVICE_NATIVE_ENDIAN,
46 DEVICE_BIG_ENDIAN,
47 DEVICE_LITTLE_ENDIAN,
48};
49
Marc-André Lureaue03b5682022-03-23 19:57:17 +040050#if HOST_BIG_ENDIAN
Yongji Xiec99a29e2017-02-27 12:52:44 +080051#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
52#else
53#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
54#endif
55
Paul Brook1ad21342009-05-19 16:17:58 +010056/* address in the RAM (different from a physical address) */
Avi Kivity4be403c2012-10-04 12:36:04 +020057#if defined(CONFIG_XEN_BACKEND)
Anthony PERARDf15fbc42011-07-20 08:17:42 +000058typedef uint64_t ram_addr_t;
59# define RAM_ADDR_MAX UINT64_MAX
60# define RAM_ADDR_FMT "%" PRIx64
61#else
Stefan Weil53576992012-03-02 23:30:02 +010062typedef uintptr_t ram_addr_t;
63# define RAM_ADDR_MAX UINTPTR_MAX
64# define RAM_ADDR_FMT "%" PRIxPTR
Anthony PERARDf15fbc42011-07-20 08:17:42 +000065#endif
Paul Brook1ad21342009-05-19 16:17:58 +010066
67/* memory API */
68
Huang Yingcd19cfa2011-03-02 08:56:19 +010069void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
Paul Brook1ad21342009-05-19 16:17:58 +010070/* This should not be used by devices. */
Paolo Bonzini07bdaa42016-03-25 12:55:08 +010071ram_addr_t qemu_ram_addr_from_host(void *ptr);
Richard Henderson97e03462022-08-10 12:04:15 -070072ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
Dr. David Alan Gilberte3dd7492015-11-05 18:10:33 +000073RAMBlock *qemu_ram_block_by_name(const char *name);
David Hildenbrand022f0332023-09-26 20:57:23 +020074
75/*
76 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock.
77 *
78 * @ptr: The host pointer to translate.
79 * @round_offset: Whether to round the result offset down to a target page
80 * @offset: Will be set to the offset within the returned RAMBlock.
81 *
82 * Returns: RAMBlock (or NULL if not found)
83 *
84 * By the time this function returns, the returned pointer is not protected
85 * by RCU anymore. If the caller is not within an RCU critical section and
Stefan Hajnoczia4a411f2024-01-02 10:35:28 -050086 * does not hold the BQL, it must have other means of protecting the
David Hildenbrand022f0332023-09-26 20:57:23 +020087 * pointer, such as a reference to the memory region that owns the RAMBlock.
88 */
Dr. David Alan Gilbert422148d2015-11-05 18:10:32 +000089RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
Paolo Bonzinif615f392016-05-26 10:07:50 +020090 ram_addr_t *offset);
Dr. David Alan Gilbertf90bb712018-03-12 17:20:57 +000091ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
Gongleifa53a0e2016-05-10 10:04:59 +080092void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
93void qemu_ram_unset_idstr(RAMBlock *block);
Dr. David Alan Gilbert422148d2015-11-05 18:10:32 +000094const char *qemu_ram_get_idstr(RAMBlock *rb);
Yury Kotov754cb9c2019-02-15 20:45:44 +030095void *qemu_ram_get_host_addr(RAMBlock *rb);
96ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
97ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
David Hildenbrand082851a2021-04-29 13:26:59 +020098ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
Dr. David Alan Gilbert463a4ac2017-03-07 18:36:36 +000099bool qemu_ram_is_shared(RAMBlock *rb);
David Hildenbrand8dbe22c2021-05-10 13:43:21 +0200100bool qemu_ram_is_noreserve(RAMBlock *rb);
Dr. David Alan Gilbert2ce16642018-03-12 17:20:58 +0000101bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
102void qemu_ram_set_uf_zeroable(RAMBlock *rb);
Cédric Le Goaterb895de52018-05-14 08:57:00 +0200103bool qemu_ram_is_migratable(RAMBlock *rb);
104void qemu_ram_set_migratable(RAMBlock *rb);
105void qemu_ram_unset_migratable(RAMBlock *rb);
Steve Sistareb0182e52023-06-07 08:18:36 -0700106bool qemu_ram_is_named_file(RAMBlock *rb);
Stefan Hajnoczi6d998f32022-10-13 14:59:05 -0400107int qemu_ram_get_fd(RAMBlock *rb);
Dr. David Alan Gilbert2ce16642018-03-12 17:20:58 +0000108
Dr. David Alan Gilbert863e9622016-09-29 20:09:37 +0100109size_t qemu_ram_pagesize(RAMBlock *block);
Dr. David Alan Gilbert67f11b52017-02-24 18:28:34 +0000110size_t qemu_ram_pagesize_largest(void);
Paul Brook1ad21342009-05-19 16:17:58 +0100111
Philippe Mathieu-Daudé1f649fe2021-05-16 19:01:31 +0200112/**
113 * cpu_address_space_init:
114 * @cpu: CPU to add this address space to
115 * @asidx: integer index of this address space
116 * @prefix: prefix to be used as name of address space
117 * @mr: the root memory region of address space
118 *
119 * Add the specified address space to the CPU's cpu_ases list.
120 * The address space added with @asidx 0 is the one used for the
121 * convenience pointer cpu->as.
122 * The target-specific code which registers ASes is responsible
123 * for defining what semantics address space 0, 1, 2, etc have.
124 *
125 * Before the first call to this function, the caller must set
126 * cpu->num_ases to the total number of address spaces it needs
127 * to support.
128 *
129 * Note that with KVM only one address space is supported.
130 */
131void cpu_address_space_init(CPUState *cpu, int asidx,
132 const char *prefix, MemoryRegion *mr);
133
Philippe Mathieu-Daudéd7ef71e2020-02-19 20:02:11 +0100134void cpu_physical_memory_rw(hwaddr addr, void *buf,
Philippe Mathieu-Daudé28c80bf2020-02-19 20:32:30 +0100135 hwaddr len, bool is_write);
Avi Kivitya8170e52012-10-23 12:30:10 +0200136static inline void cpu_physical_memory_read(hwaddr addr,
Li Zhijian0c249ff2019-01-17 20:49:01 +0800137 void *buf, hwaddr len)
Paul Brook1ad21342009-05-19 16:17:58 +0100138{
Philippe Mathieu-Daudé85eb7c12020-02-19 20:20:42 +0100139 cpu_physical_memory_rw(addr, buf, len, false);
Paul Brook1ad21342009-05-19 16:17:58 +0100140}
Avi Kivitya8170e52012-10-23 12:30:10 +0200141static inline void cpu_physical_memory_write(hwaddr addr,
Li Zhijian0c249ff2019-01-17 20:49:01 +0800142 const void *buf, hwaddr len)
Paul Brook1ad21342009-05-19 16:17:58 +0100143{
Philippe Mathieu-Daudé85eb7c12020-02-19 20:20:42 +0100144 cpu_physical_memory_rw(addr, (void *)buf, len, true);
Paul Brook1ad21342009-05-19 16:17:58 +0100145}
Avi Kivitya8170e52012-10-23 12:30:10 +0200146void *cpu_physical_memory_map(hwaddr addr,
147 hwaddr *plen,
Philippe Mathieu-Daudé28c80bf2020-02-19 20:32:30 +0100148 bool is_write);
Avi Kivitya8170e52012-10-23 12:30:10 +0200149void cpu_physical_memory_unmap(void *buffer, hwaddr len,
Philippe Mathieu-Daudé28c80bf2020-02-19 20:32:30 +0100150 bool is_write, hwaddr access_len);
Fam Zhenge95205e2015-03-16 17:03:37 +0800151void cpu_register_map_client(QEMUBH *bh);
152void cpu_unregister_map_client(QEMUBH *bh);
Paul Brook1ad21342009-05-19 16:17:58 +0100153
Avi Kivitya8170e52012-10-23 12:30:10 +0200154bool cpu_physical_memory_is_io(hwaddr phys_addr);
Wen Congyang76f35532012-05-07 12:04:18 +0800155
Blue Swirl6842a082010-03-21 19:47:13 +0000156/* Coalesced MMIO regions are areas where write operations can be reordered.
157 * This usually implies that write operations are side-effect free. This allows
158 * batching which can make a major impact on performance when using
159 * virtualization.
160 */
Blue Swirl6842a082010-03-21 19:47:13 +0000161void qemu_flush_coalesced_mmio_buffer(void);
162
Li Zhijian0c249ff2019-01-17 20:49:01 +0800163void cpu_flush_icache_range(hwaddr start, hwaddr len);
Paul Brook1ad21342009-05-19 16:17:58 +0100164
Yury Kotov754cb9c2019-02-15 20:45:44 +0300165typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
Michael R. Hinesbd2fa512013-06-25 21:35:34 -0400166
Dr. David Alan Gilberte3807052015-05-21 13:24:13 +0100167int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
Dr. David Alan Gilbertd3a50382017-02-24 18:28:32 +0000168int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
Michael R. Hinesbd2fa512013-06-25 21:35:34 -0400169
Paul Brookb3755a92010-03-12 16:54:58 +0000170#endif
171
Philippe Mathieu-Daudé73842ef2022-02-03 02:13:28 +0100172/* Returns: 0 on success, -1 on error */
173int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
174 void *ptr, size_t len, bool is_write);
175
Paolo Bonzinic5e3c912020-10-28 08:04:08 -0400176/* vl.c */
Thomas Huthc138c3b2023-04-19 14:48:31 +0200177void list_cpus(void);
Philippe Mathieu-Daudé377bf6f2022-03-14 15:01:08 +0100178
Philippe Mathieu-Daudé35491182023-09-14 20:57:08 +0200179#ifdef CONFIG_TCG
180/**
181 * cpu_unwind_state_data:
182 * @cpu: the cpu context
183 * @host_pc: the host pc within the translation
184 * @data: output data
185 *
186 * Attempt to load the the unwind state for a host pc occurring in
187 * translated code. If @host_pc is not in translated code, the
188 * function returns false; otherwise @data is loaded.
189 * This is the same unwind info as given to restore_state_to_opc.
190 */
191bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
192
193/**
194 * cpu_restore_state:
195 * @cpu: the cpu context
196 * @host_pc: the host pc within the translation
197 * @return: true if state was restored, false otherwise
198 *
199 * Attempt to restore the state for a fault occurring in translated
200 * code. If @host_pc is not in translated code no state is
201 * restored and the function returns false.
202 */
203bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc);
204
205G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
206G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
207#endif /* CONFIG_TCG */
208G_NORETURN void cpu_loop_exit(CPUState *cpu);
209G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
210
Anton Johansson58771922024-01-19 15:40:04 +0100211/* same as PROT_xxx */
212#define PAGE_READ 0x0001
213#define PAGE_WRITE 0x0002
214#define PAGE_EXEC 0x0004
215#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
216#define PAGE_VALID 0x0008
217/*
218 * Original state of the write flag (used when tracking self-modifying code)
219 */
220#define PAGE_WRITE_ORG 0x0010
221/*
222 * Invalidate the TLB entry immediately, helpful for s390x
223 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
224 */
225#define PAGE_WRITE_INV 0x0020
226/* For use with page_set_flags: page is being replaced; target_data cleared. */
227#define PAGE_RESET 0x0040
228/* For linux-user, indicates that the page is MAP_ANON. */
229#define PAGE_ANON 0x0080
230
231/* Target-specific bits that will be used via page_get_flags(). */
232#define PAGE_TARGET_1 0x0200
233#define PAGE_TARGET_2 0x0400
234
235/*
236 * For linux-user, indicates that the page is mapped with the same semantics
237 * in both guest and host.
238 */
239#define PAGE_PASSTHROUGH 0x0800
240
Anton Johanssona7f6f4f2024-01-19 15:40:06 +0100241/* accel/tcg/cpu-exec.c */
242int cpu_exec(CPUState *cpu);
243
244/**
245 * env_archcpu(env)
246 * @env: The architecture environment
247 *
248 * Return the ArchCPU associated with the environment.
249 */
250static inline ArchCPU *env_archcpu(CPUArchState *env)
251{
252 return (void *)env - sizeof(CPUState);
253}
254
255/**
256 * env_cpu(env)
257 * @env: The architecture environment
258 *
259 * Return the CPUState associated with the environment.
260 */
261static inline CPUState *env_cpu(CPUArchState *env)
262{
263 return (void *)env - sizeof(CPUState);
264}
265
Richard Hendersona120d322024-01-29 11:37:54 +1000266#ifndef CONFIG_USER_ONLY
267/**
268 * cpu_mmu_index:
269 * @env: The cpu environment
270 * @ifetch: True for code access, false for data access.
271 *
272 * Return the core mmu index for the current translation regime.
273 * This function is used by generic TCG code paths.
274 *
275 * The user-only version of this function is inline in cpu-all.h,
276 * where it always returns MMU_USER_IDX.
277 */
278static inline int cpu_mmu_index(CPUArchState *env, bool ifetch)
279{
280 CPUState *cs = env_cpu(env);
281 int ret = cs->cc->mmu_index(cs, ifetch);
282 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
283 return ret;
284}
285#endif /* !CONFIG_USER_ONLY */
286
Markus Armbruster175de522016-06-29 15:29:06 +0200287#endif /* CPU_COMMON_H */