blob: 1f9ad319438dc0a2d6d04f0973aa321cca4da20c [file] [log] [blame]
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
Peter Maydell47df5152016-01-26 18:17:13 +000021#include "qemu/osdep.h"
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -030022#include "qemu/units.h"
Alon Levya639ab02012-09-12 16:13:28 +030023#include <zlib.h>
24
Markus Armbrustere688df62018-02-01 12:18:31 +010025#include "qapi/error.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010026#include "qemu/timer.h"
27#include "qemu/queue.h"
Paolo Bonzini5444e762013-05-13 13:29:47 +020028#include "qemu/atomic.h"
Markus Armbrusterdb725812019-08-12 07:23:50 +020029#include "qemu/main-loop.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020030#include "qemu/module.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020031#include "hw/qdev-properties.h"
Markus Armbruster54d31232019-08-12 07:23:59 +020032#include "sysemu/runstate.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020033#include "migration/vmstate.h"
Alon Levyc480bb72012-03-18 13:46:14 +010034#include "trace.h"
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020035
Paolo Bonzini47b43a12013-03-18 17:36:02 +010036#include "qxl.h"
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020037
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020038#undef SPICE_RING_CONS_ITEM
Alon Levy0b81c472012-04-25 12:13:21 +030039#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020040 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
Markus Armbrusterbc5f92e2013-01-10 14:24:49 +010041 if (cons >= ARRAY_SIZE((r)->items)) { \
Alon Levy0a530542012-05-24 12:38:12 +030042 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
Markus Armbrusterbc5f92e2013-01-10 14:24:49 +010043 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
Alon Levy0b81c472012-04-25 12:13:21 +030044 ret = NULL; \
45 } else { \
Markus Armbrusterbc5f92e2013-01-10 14:24:49 +010046 ret = &(r)->items[cons].el; \
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020047 } \
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020048 }
49
50#undef ALIGN
51#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
52
53#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
54
55#define QXL_MODE(_x, _y, _b, _o) \
56 { .x_res = _x, \
57 .y_res = _y, \
58 .bits = _b, \
59 .stride = (_x) * (_b) / 8, \
60 .x_mili = PIXEL_SIZE * (_x), \
61 .y_mili = PIXEL_SIZE * (_y), \
62 .orientation = _o, \
63 }
64
65#define QXL_MODE_16_32(x_res, y_res, orientation) \
66 QXL_MODE(x_res, y_res, 16, orientation), \
67 QXL_MODE(x_res, y_res, 32, orientation)
68
69#define QXL_MODE_EX(x_res, y_res) \
70 QXL_MODE_16_32(x_res, y_res, 0), \
Alon Levy038c1872013-01-21 14:48:07 +020071 QXL_MODE_16_32(x_res, y_res, 1)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020072
73static QXLMode qxl_modes[] = {
74 QXL_MODE_EX(640, 480),
75 QXL_MODE_EX(800, 480),
76 QXL_MODE_EX(800, 600),
77 QXL_MODE_EX(832, 624),
78 QXL_MODE_EX(960, 640),
79 QXL_MODE_EX(1024, 600),
80 QXL_MODE_EX(1024, 768),
81 QXL_MODE_EX(1152, 864),
82 QXL_MODE_EX(1152, 870),
83 QXL_MODE_EX(1280, 720),
84 QXL_MODE_EX(1280, 760),
85 QXL_MODE_EX(1280, 768),
86 QXL_MODE_EX(1280, 800),
87 QXL_MODE_EX(1280, 960),
88 QXL_MODE_EX(1280, 1024),
89 QXL_MODE_EX(1360, 768),
90 QXL_MODE_EX(1366, 768),
91 QXL_MODE_EX(1400, 1050),
92 QXL_MODE_EX(1440, 900),
93 QXL_MODE_EX(1600, 900),
94 QXL_MODE_EX(1600, 1200),
95 QXL_MODE_EX(1680, 1050),
96 QXL_MODE_EX(1920, 1080),
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +020097 /* these modes need more than 8 MB video memory */
98 QXL_MODE_EX(1920, 1200),
99 QXL_MODE_EX(1920, 1440),
Gerd Hoffmann5c74fb22013-04-04 10:15:34 +0200100 QXL_MODE_EX(2000, 2000),
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200101 QXL_MODE_EX(2048, 1536),
Gerd Hoffmann5c74fb22013-04-04 10:15:34 +0200102 QXL_MODE_EX(2048, 2048),
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200103 QXL_MODE_EX(2560, 1440),
104 QXL_MODE_EX(2560, 1600),
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200105 /* these modes need more than 16 MB video memory */
106 QXL_MODE_EX(2560, 2048),
107 QXL_MODE_EX(2800, 2100),
108 QXL_MODE_EX(3200, 2400),
Radim Krčmář03d98252015-02-17 17:30:50 +0100109 /* these modes need more than 32 MB video memory */
Gerd Hoffmannd4bcb192013-03-15 11:53:47 +0100110 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
111 QXL_MODE_EX(4096, 2160), /* 4k */
Radim Krčmář03d98252015-02-17 17:30:50 +0100112 /* these modes need more than 64 MB video memory */
Gerd Hoffmannd4bcb192013-03-15 11:53:47 +0100113 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
Radim Krčmář03d98252015-02-17 17:30:50 +0100114 /* these modes need more than 128 MB video memory */
Gerd Hoffmannd4bcb192013-03-15 11:53:47 +0100115 QXL_MODE_EX(8192, 4320), /* 8k */
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200116};
117
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200118static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
Alon Levy5ff4e362011-07-20 12:20:58 +0300119static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200120static void qxl_reset_memslots(PCIQXLDevice *d);
121static void qxl_reset_surfaces(PCIQXLDevice *d);
122static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
123
Gerd Hoffmann15162332014-09-24 17:05:45 +0200124static void qxl_hw_update(void *opaque);
125
Alon Levy0a530542012-05-24 12:38:12 +0300126void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
Gerd Hoffmann2bce0402011-07-20 12:20:55 +0300127{
Alon Levy917ae082012-09-12 16:13:26 +0300128 trace_qxl_set_guest_bug(qxl->id);
Gerd Hoffmann2bce0402011-07-20 12:20:55 +0300129 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
Alon Levy087e6a42012-05-24 19:18:54 +0300130 qxl->guest_bug = 1;
Gerd Hoffmann2bce0402011-07-20 12:20:55 +0300131 if (qxl->guestdebug) {
Alon Levy76353922011-07-20 12:20:56 +0300132 va_list ap;
133 va_start(ap, msg);
134 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
135 vfprintf(stderr, msg, ap);
136 fprintf(stderr, "\n");
137 va_end(ap);
Gerd Hoffmann2bce0402011-07-20 12:20:55 +0300138 }
139}
140
Alon Levy087e6a42012-05-24 19:18:54 +0300141static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
142{
143 qxl->guest_bug = 0;
144}
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300145
146void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
147 struct QXLRect *area, struct QXLRect *dirty_rects,
148 uint32_t num_dirty_rects,
Alon Levy5ff4e362011-07-20 12:20:58 +0300149 uint32_t clear_dirty_region,
Alon Levy2e1a98c2012-02-24 23:19:30 +0200150 qxl_async_io async, struct QXLCookie *cookie)
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300151{
Alon Levyc480bb72012-03-18 13:46:14 +0100152 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
153 area->top, area->bottom);
154 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
155 clear_dirty_region);
Alon Levy5ff4e362011-07-20 12:20:58 +0300156 if (async == QXL_SYNC) {
Marc-André Lureau26defe82013-10-04 13:10:46 +0200157 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
Alon Levy5ff4e362011-07-20 12:20:58 +0300158 dirty_rects, num_dirty_rects, clear_dirty_region);
159 } else {
Alon Levy2e1a98c2012-02-24 23:19:30 +0200160 assert(cookie != NULL);
Alon Levy5ff4e362011-07-20 12:20:58 +0300161 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
Peter Maydell5dba0d42012-03-16 13:50:04 +0000162 clear_dirty_region, (uintptr_t)cookie);
Alon Levy5ff4e362011-07-20 12:20:58 +0300163 }
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300164}
165
Alon Levy5ff4e362011-07-20 12:20:58 +0300166static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
167 uint32_t id)
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300168{
Alon Levyc480bb72012-03-18 13:46:14 +0100169 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
Gerd Hoffmann14898cf2011-07-20 12:20:53 +0300170 qemu_mutex_lock(&qxl->track_lock);
Gerd Hoffmann14898cf2011-07-20 12:20:53 +0300171 qxl->guest_surfaces.cmds[id] = 0;
172 qxl->guest_surfaces.count--;
173 qemu_mutex_unlock(&qxl->track_lock);
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300174}
175
Alon Levy5ff4e362011-07-20 12:20:58 +0300176static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
177 qxl_async_io async)
178{
Alon Levy2e1a98c2012-02-24 23:19:30 +0200179 QXLCookie *cookie;
180
Alon Levyc480bb72012-03-18 13:46:14 +0100181 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
Alon Levy5ff4e362011-07-20 12:20:58 +0300182 if (async) {
Alon Levy2e1a98c2012-02-24 23:19:30 +0200183 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
184 QXL_IO_DESTROY_SURFACE_ASYNC);
185 cookie->u.surface_id = id;
Peter Maydell5dba0d42012-03-16 13:50:04 +0000186 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
Alon Levy5ff4e362011-07-20 12:20:58 +0300187 } else {
Marc-André Lureau26defe82013-10-04 13:10:46 +0200188 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
Uri Lublin753b8b02012-09-11 10:09:58 +0300189 qxl_spice_destroy_surface_wait_complete(qxl, id);
Alon Levy5ff4e362011-07-20 12:20:58 +0300190 }
191}
192
Alon Levy3e16b9c2011-07-20 12:20:59 +0300193static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
194{
Alon Levyc480bb72012-03-18 13:46:14 +0100195 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
196 qxl->num_free_res);
Alon Levy2e1a98c2012-02-24 23:19:30 +0200197 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
Peter Maydell5dba0d42012-03-16 13:50:04 +0000198 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
199 QXL_IO_FLUSH_SURFACES_ASYNC));
Alon Levy3e16b9c2011-07-20 12:20:59 +0300200}
Alon Levy3e16b9c2011-07-20 12:20:59 +0300201
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300202void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
203 uint32_t count)
204{
Alon Levyc480bb72012-03-18 13:46:14 +0100205 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
Marc-André Lureau26defe82013-10-04 13:10:46 +0200206 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300207}
208
209void qxl_spice_oom(PCIQXLDevice *qxl)
210{
Alon Levyc480bb72012-03-18 13:46:14 +0100211 trace_qxl_spice_oom(qxl->id);
Marc-André Lureau26defe82013-10-04 13:10:46 +0200212 spice_qxl_oom(&qxl->ssd.qxl);
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300213}
214
215void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
216{
Alon Levyc480bb72012-03-18 13:46:14 +0100217 trace_qxl_spice_reset_memslots(qxl->id);
Marc-André Lureau26defe82013-10-04 13:10:46 +0200218 spice_qxl_reset_memslots(&qxl->ssd.qxl);
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300219}
220
Alon Levy5ff4e362011-07-20 12:20:58 +0300221static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300222{
Alon Levyc480bb72012-03-18 13:46:14 +0100223 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
Gerd Hoffmann14898cf2011-07-20 12:20:53 +0300224 qemu_mutex_lock(&qxl->track_lock);
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +0200225 memset(qxl->guest_surfaces.cmds, 0,
Alon Levy8bb9f512013-03-13 17:58:35 +0200226 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
Gerd Hoffmann14898cf2011-07-20 12:20:53 +0300227 qxl->guest_surfaces.count = 0;
228 qemu_mutex_unlock(&qxl->track_lock);
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300229}
230
Alon Levy5ff4e362011-07-20 12:20:58 +0300231static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
232{
Alon Levyc480bb72012-03-18 13:46:14 +0100233 trace_qxl_spice_destroy_surfaces(qxl->id, async);
Alon Levy5ff4e362011-07-20 12:20:58 +0300234 if (async) {
Alon Levy2e1a98c2012-02-24 23:19:30 +0200235 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
Peter Maydell5dba0d42012-03-16 13:50:04 +0000236 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
237 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
Alon Levy5ff4e362011-07-20 12:20:58 +0300238 } else {
Marc-André Lureau26defe82013-10-04 13:10:46 +0200239 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
Alon Levy5ff4e362011-07-20 12:20:58 +0300240 qxl_spice_destroy_surfaces_complete(qxl);
241 }
242}
243
Alon Levy020af1c2012-08-22 11:16:25 +0300244static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
245{
Gerd Hoffmann979f7ef2018-09-19 12:30:57 +0200246 QXLMonitorsConfig *cfg;
247
Alon Levy020af1c2012-08-22 11:16:25 +0300248 trace_qxl_spice_monitors_config(qxl->id);
Alon Levy020af1c2012-08-22 11:16:25 +0300249 if (replay) {
250 /*
251 * don't use QXL_COOKIE_TYPE_IO:
252 * - we are not running yet (post_load), we will assert
253 * in send_events
254 * - this is not a guest io, but a reply, so async_io isn't set.
255 */
256 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
257 qxl->guest_monitors_config,
258 MEMSLOT_GROUP_GUEST,
259 (uintptr_t)qxl_cookie_new(
260 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
261 0));
262 } else {
Lukáš Hrázkýbe812c02019-02-15 16:09:19 +0100263/* >= release 0.12.6, < release 0.14.2 */
264#if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
Frediano Ziglio567161f2015-07-06 07:56:38 +0100265 if (qxl->max_outputs) {
Frediano Ziglioa52b2cb2015-07-20 09:43:23 +0100266 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
Frediano Ziglio567161f2015-07-06 07:56:38 +0100267 }
268#endif
Alon Levy020af1c2012-08-22 11:16:25 +0300269 qxl->guest_monitors_config = qxl->ram->monitors_config;
270 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
271 qxl->ram->monitors_config,
272 MEMSLOT_GROUP_GUEST,
273 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
274 QXL_IO_MONITORS_CONFIG_ASYNC));
275 }
Gerd Hoffmann979f7ef2018-09-19 12:30:57 +0200276
277 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
Gerd Hoffmann2f99f802018-10-05 15:46:08 +0200278 if (cfg != NULL && cfg->count == 1) {
Gerd Hoffmann979f7ef2018-09-19 12:30:57 +0200279 qxl->guest_primary.resized = 1;
280 qxl->guest_head0_width = cfg->heads[0].width;
281 qxl->guest_head0_height = cfg->heads[0].height;
282 } else {
283 qxl->guest_head0_width = 0;
284 qxl->guest_head0_height = 0;
285 }
Alon Levy020af1c2012-08-22 11:16:25 +0300286}
287
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300288void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
289{
Alon Levyc480bb72012-03-18 13:46:14 +0100290 trace_qxl_spice_reset_image_cache(qxl->id);
Marc-André Lureau26defe82013-10-04 13:10:46 +0200291 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300292}
293
294void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
295{
Alon Levyc480bb72012-03-18 13:46:14 +0100296 trace_qxl_spice_reset_cursor(qxl->id);
Marc-André Lureau26defe82013-10-04 13:10:46 +0200297 spice_qxl_reset_cursor(&qxl->ssd.qxl);
Yonit Halperin30f6da62011-10-18 18:58:54 +0200298 qemu_mutex_lock(&qxl->track_lock);
299 qxl->guest_cursor = 0;
300 qemu_mutex_unlock(&qxl->track_lock);
Gerd Hoffmann958c2bc2012-09-14 22:17:44 +0200301 if (qxl->ssd.cursor) {
302 cursor_put(qxl->ssd.cursor);
303 }
304 qxl->ssd.cursor = cursor_builtin_hidden();
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +0300305}
306
Gerd Hoffmann6f663d72017-04-21 11:22:34 +0200307static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
308{
309 /*
310 * zlib xors the seed with 0xffffffff, and xors the result
311 * again with 0xffffffff; Both are not done with linux's crc32,
312 * which we want to be compatible with, so undo that.
313 */
314 return crc32(0xffffffff, p, len) ^ 0xffffffff;
315}
316
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200317static ram_addr_t qxl_rom_size(void)
318{
Michael S. Tsirkindf458922017-01-25 23:48:51 +0200319#define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
320#define QXL_ROM_SZ 8192
Alon Levy13d1fd42012-06-10 18:05:06 +0300321
Michael S. Tsirkindf458922017-01-25 23:48:51 +0200322 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
maobiboce7015d2021-05-18 20:20:48 +0800323 return QEMU_ALIGN_UP(QXL_REQUIRED_SZ, qemu_real_host_page_size);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200324}
325
326static void init_qxl_rom(PCIQXLDevice *d)
327{
Avi Kivityb1950432011-08-08 16:08:57 +0300328 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200329 QXLModes *modes = (QXLModes *)(rom + 1);
330 uint32_t ram_header_size;
331 uint32_t surface0_area_size;
332 uint32_t num_pages;
Alon Levy13d1fd42012-06-10 18:05:06 +0300333 uint32_t fb;
334 int i, n;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200335
336 memset(rom, 0, d->rom_size);
337
338 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
339 rom->id = cpu_to_le32(d->id);
340 rom->log_level = cpu_to_le32(d->guestdebug);
341 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
342
343 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
344 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
345 rom->slots_start = 1;
346 rom->slots_end = NUM_MEMSLOTS - 1;
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +0200347 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200348
Alon Levy13d1fd42012-06-10 18:05:06 +0300349 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200350 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
Alon Levy13d1fd42012-06-10 18:05:06 +0300351 if (fb > d->vgamem_size) {
352 continue;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200353 }
Alon Levy13d1fd42012-06-10 18:05:06 +0300354 modes->modes[n].id = cpu_to_le32(i);
355 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
356 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
357 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
358 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
359 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
360 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
361 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
362 n++;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200363 }
Alon Levy13d1fd42012-06-10 18:05:06 +0300364 modes->n_modes = cpu_to_le32(n);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200365
366 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
Alon Levy13d1fd42012-06-10 18:05:06 +0300367 surface0_area_size = ALIGN(d->vgamem_size, 4096);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200368 num_pages = d->vga.vram_size;
369 num_pages -= ram_header_size;
370 num_pages -= surface0_area_size;
Gerd Hoffmann9efc2d82013-09-11 13:14:25 +0200371 num_pages = num_pages / QXL_PAGE_SIZE;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200372
Radim Krčmář876d5162015-02-17 17:30:51 +0100373 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
374
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200375 rom->draw_area_offset = cpu_to_le32(0);
376 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
377 rom->pages_offset = cpu_to_le32(surface0_area_size);
378 rom->num_pages = cpu_to_le32(num_pages);
379 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
380
Gerd Hoffmann6f663d72017-04-21 11:22:34 +0200381 if (d->xres && d->yres) {
382 /* needs linux kernel 4.12+ to work */
383 rom->client_monitors_config.count = 1;
384 rom->client_monitors_config.heads[0].left = 0;
385 rom->client_monitors_config.heads[0].top = 0;
386 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
387 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
388 rom->client_monitors_config_crc = qxl_crc32(
389 (const uint8_t *)&rom->client_monitors_config,
390 sizeof(rom->client_monitors_config));
391 }
392
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200393 d->shadow_rom = *rom;
394 d->rom = rom;
395 d->modes = modes;
396}
397
398static void init_qxl_ram(PCIQXLDevice *d)
399{
400 uint8_t *buf;
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100401 uint32_t prod;
402 QXLReleaseRing *ring;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200403
404 buf = d->vga.vram_ptr;
405 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
406 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
407 d->ram->int_pending = cpu_to_le32(0);
408 d->ram->int_mask = cpu_to_le32(0);
Alon Levy9f0f3522011-10-23 17:03:52 +0200409 d->ram->update_surface = 0;
Anthony PERARD329f97f2013-06-17 17:38:26 +0100410 d->ram->monitors_config = 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200411 SPICE_RING_INIT(&d->ram->cmd_ring);
412 SPICE_RING_INIT(&d->ram->cursor_ring);
413 SPICE_RING_INIT(&d->ram->release_ring);
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100414
415 ring = &d->ram->release_ring;
416 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
417 assert(prod < ARRAY_SIZE(ring->items));
418 ring->items[prod].el = 0;
419
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200420 qxl_ring_set_dirty(d);
421}
422
423/* can be called from spice server thread context */
Avi Kivityb1950432011-08-08 16:08:57 +0300424static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200425{
Blue Swirlfd4aa972011-10-16 16:04:59 +0000426 memory_region_set_dirty(mr, addr, end - addr);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200427}
428
429static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
430{
Avi Kivityb1950432011-08-08 16:08:57 +0300431 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200432}
433
434/* called from spice server thread context only */
435static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
436{
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200437 void *base = qxl->vga.vram_ptr;
438 intptr_t offset;
439
440 offset = ptr - base;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200441 assert(offset < qxl->vga.vram_size);
Gerd Hoffmannb0297b42013-09-11 13:15:48 +0200442 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200443}
444
445/* can be called from spice server thread context */
446static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
447{
Avi Kivityb1950432011-08-08 16:08:57 +0300448 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
449 ram_addr_t end = qxl->vga.vram_size;
450 qxl_set_dirty(&qxl->vga.vram, addr, end);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200451}
452
453/*
454 * keep track of some command state, for savevm/loadvm.
455 * called from spice server thread context only
456 */
Alon Levyfae2afb2012-04-25 12:13:18 +0300457static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200458{
459 switch (le32_to_cpu(ext->cmd.type)) {
460 case QXL_CMD_SURFACE:
461 {
462 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
Alon Levyfae2afb2012-04-25 12:13:18 +0300463
464 if (!cmd) {
465 return 1;
466 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200467 uint32_t id = le32_to_cpu(cmd->surface_id);
Alon Levy47eddfb2012-04-25 12:13:19 +0300468
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +0200469 if (id >= qxl->ssd.num_surfaces) {
Alon Levy0a530542012-05-24 12:38:12 +0300470 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +0200471 qxl->ssd.num_surfaces);
Alon Levy47eddfb2012-04-25 12:13:19 +0300472 return 1;
473 }
Alon Levy48f4ba62012-10-15 14:54:03 +0200474 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
475 (cmd->u.surface_create.stride & 0x03) != 0) {
476 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
477 cmd->u.surface_create.stride);
478 return 1;
479 }
Daniel Brodsky6e8a3552020-04-03 21:21:08 -0700480 WITH_QEMU_LOCK_GUARD(&qxl->track_lock) {
481 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
482 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
483 qxl->guest_surfaces.count++;
484 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) {
485 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
486 }
487 }
488 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
489 qxl->guest_surfaces.cmds[id] = 0;
490 qxl->guest_surfaces.count--;
491 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200492 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200493 break;
494 }
495 case QXL_CMD_CURSOR:
496 {
497 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
Alon Levyfae2afb2012-04-25 12:13:18 +0300498
499 if (!cmd) {
500 return 1;
501 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200502 if (cmd->type == QXL_CURSOR_SET) {
Yonit Halperin30f6da62011-10-18 18:58:54 +0200503 qemu_mutex_lock(&qxl->track_lock);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200504 qxl->guest_cursor = ext->cmd.data;
Yonit Halperin30f6da62011-10-18 18:58:54 +0200505 qemu_mutex_unlock(&qxl->track_lock);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200506 }
Gerd Hoffmanndbb5fb82017-03-06 09:31:51 +0100507 if (cmd->type == QXL_CURSOR_HIDE) {
508 qemu_mutex_lock(&qxl->track_lock);
509 qxl->guest_cursor = 0;
510 qemu_mutex_unlock(&qxl->track_lock);
511 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200512 break;
513 }
514 }
Alon Levyfae2afb2012-04-25 12:13:18 +0300515 return 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200516}
517
518/* spice display interface callbacks */
519
John Snow9dcafa42022-01-05 13:49:37 +0000520static void interface_attached_worker(QXLInstance *sin)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200521{
522 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
523
Alon Levyc480bb72012-03-18 13:46:14 +0100524 trace_qxl_interface_attach_worker(qxl->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200525}
526
John Snow9dcafa42022-01-05 13:49:37 +0000527#if !(SPICE_HAS_ATTACHED_WORKER)
528static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
529{
530 interface_attached_worker(sin);
531}
532#endif
533
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200534static void interface_set_compression_level(QXLInstance *sin, int level)
535{
536 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
537
Alon Levyc480bb72012-03-18 13:46:14 +0100538 trace_qxl_interface_set_compression_level(qxl->id, level);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200539 qxl->shadow_rom.compression_level = cpu_to_le32(level);
540 qxl->rom->compression_level = cpu_to_le32(level);
541 qxl_rom_set_dirty(qxl);
542}
543
John Snow015e02f2016-06-29 18:41:35 -0400544#if SPICE_NEEDS_SET_MM_TIME
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200545static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
546{
547 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
548
Gerd Hoffmann641381c2015-05-12 11:54:34 +0200549 if (!qemu_spice_display_is_running(&qxl->ssd)) {
550 return;
551 }
552
Alon Levyc480bb72012-03-18 13:46:14 +0100553 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200554 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
555 qxl->rom->mm_clock = cpu_to_le32(mm_time);
556 qxl_rom_set_dirty(qxl);
557}
John Snow015e02f2016-06-29 18:41:35 -0400558#endif
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200559
560static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
561{
562 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
563
Alon Levyc480bb72012-03-18 13:46:14 +0100564 trace_qxl_interface_get_init_info(qxl->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200565 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
566 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
567 info->num_memslots = NUM_MEMSLOTS;
568 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
569 info->internal_groupslot_id = 0;
Gerd Hoffmann9efc2d82013-09-11 13:14:25 +0200570 info->qxl_ram_size =
571 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +0200572 info->n_surfaces = qxl->ssd.num_surfaces;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200573}
574
Alon Levy5b778702011-06-24 15:02:47 +0200575static const char *qxl_mode_to_string(int mode)
576{
577 switch (mode) {
578 case QXL_MODE_COMPAT:
579 return "compat";
580 case QXL_MODE_NATIVE:
581 return "native";
582 case QXL_MODE_UNDEFINED:
583 return "undefined";
584 case QXL_MODE_VGA:
585 return "vga";
586 }
587 return "INVALID";
588}
589
Alon Levy8b92e292011-07-20 12:20:54 +0300590static const char *io_port_to_string(uint32_t io_port)
591{
592 if (io_port >= QXL_IO_RANGE_SIZE) {
593 return "out of range";
594 }
595 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
596 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
597 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
598 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
599 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
600 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
601 [QXL_IO_RESET] = "QXL_IO_RESET",
602 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
603 [QXL_IO_LOG] = "QXL_IO_LOG",
604 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
605 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
606 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
607 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
608 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
609 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
610 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
611 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
Alon Levy8b92e292011-07-20 12:20:54 +0300612 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
613 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
614 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
615 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
616 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
617 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
618 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
619 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
620 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
Alon Levy020af1c2012-08-22 11:16:25 +0300621 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
Alon Levy8b92e292011-07-20 12:20:54 +0300622 };
623 return io_port_to_string[io_port];
624}
625
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200626/* called from spice server thread context only */
627static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
628{
629 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
630 SimpleSpiceUpdate *update;
631 QXLCommandRing *ring;
632 QXLCommand *cmd;
Gerd Hoffmanne0c64d02011-04-27 15:21:51 +0200633 int notify, ret;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200634
Alon Levyc480bb72012-03-18 13:46:14 +0100635 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
636
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200637 switch (qxl->mode) {
638 case QXL_MODE_VGA:
Gerd Hoffmanne0c64d02011-04-27 15:21:51 +0200639 ret = false;
640 qemu_mutex_lock(&qxl->ssd.lock);
Gerd Hoffmannb1af98b2012-09-05 08:25:08 +0200641 update = QTAILQ_FIRST(&qxl->ssd.updates);
642 if (update != NULL) {
643 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
Gerd Hoffmanne0c64d02011-04-27 15:21:51 +0200644 *ext = update->ext;
645 ret = true;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200646 }
Gerd Hoffmanne0c64d02011-04-27 15:21:51 +0200647 qemu_mutex_unlock(&qxl->ssd.lock);
Alon Levy212496c2011-05-18 17:34:36 +0300648 if (ret) {
Alon Levyc480bb72012-03-18 13:46:14 +0100649 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
Alon Levy212496c2011-05-18 17:34:36 +0300650 qxl_log_command(qxl, "vga", ext);
651 }
Gerd Hoffmanne0c64d02011-04-27 15:21:51 +0200652 return ret;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200653 case QXL_MODE_COMPAT:
654 case QXL_MODE_NATIVE:
655 case QXL_MODE_UNDEFINED:
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200656 ring = &qxl->ram->cmd_ring;
Alon Levy087e6a42012-05-24 19:18:54 +0300657 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200658 return false;
659 }
Alon Levy0b81c472012-04-25 12:13:21 +0300660 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
661 if (!cmd) {
662 return false;
663 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200664 ext->cmd = *cmd;
665 ext->group_id = MEMSLOT_GROUP_GUEST;
666 ext->flags = qxl->cmdflags;
667 SPICE_RING_POP(ring, notify);
668 qxl_ring_set_dirty(qxl);
669 if (notify) {
670 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
671 }
672 qxl->guest_primary.commands++;
673 qxl_track_command(qxl, ext);
674 qxl_log_command(qxl, "cmd", ext);
Alon Levy0b81c472012-04-25 12:13:21 +0300675 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200676 return true;
677 default:
678 return false;
679 }
680}
681
682/* called from spice server thread context only */
683static int interface_req_cmd_notification(QXLInstance *sin)
684{
685 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
686 int wait = 1;
687
Alon Levyc480bb72012-03-18 13:46:14 +0100688 trace_qxl_ring_command_req_notification(qxl->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200689 switch (qxl->mode) {
690 case QXL_MODE_COMPAT:
691 case QXL_MODE_NATIVE:
692 case QXL_MODE_UNDEFINED:
693 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
694 qxl_ring_set_dirty(qxl);
695 break;
696 default:
697 /* nothing */
698 break;
699 }
700 return wait;
701}
702
703/* called from spice server thread context only */
704static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
705{
706 QXLReleaseRing *ring = &d->ram->release_ring;
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100707 uint32_t prod;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200708 int notify;
709
710#define QXL_FREE_BUNCH_SIZE 32
711
712 if (ring->prod - ring->cons + 1 == ring->num_items) {
713 /* ring full -- can't push */
714 return;
715 }
716 if (!flush && d->oom_running) {
717 /* collect everything from oom handler before pushing */
718 return;
719 }
720 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
721 /* collect a bit more before pushing */
722 return;
723 }
724
725 SPICE_RING_PUSH(ring, notify);
Alon Levyc480bb72012-03-18 13:46:14 +0100726 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
727 d->guest_surfaces.count, d->num_free_res,
728 d->last_release, notify ? "yes" : "no");
729 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
730 ring->num_items, ring->prod, ring->cons);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200731 if (notify) {
732 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
733 }
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100734
735 ring = &d->ram->release_ring;
736 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
737 if (prod >= ARRAY_SIZE(ring->items)) {
738 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
739 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
Alon Levy0b81c472012-04-25 12:13:21 +0300740 return;
741 }
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100742 ring->items[prod].el = 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200743 d->num_free_res = 0;
744 d->last_release = NULL;
745 qxl_ring_set_dirty(d);
746}
747
748/* called from spice server thread context only */
749static void interface_release_resource(QXLInstance *sin,
Chih-Min Chaoc9f88ce2015-04-09 02:04:14 +0800750 QXLReleaseInfoExt ext)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200751{
752 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
753 QXLReleaseRing *ring;
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100754 uint32_t prod;
755 uint64_t id;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200756
Prasad J Panditd52680f2019-04-25 12:05:34 +0530757 if (!ext.info) {
758 return;
759 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200760 if (ext.group_id == MEMSLOT_GROUP_HOST) {
761 /* host group -> vga mode update request */
Gerd Hoffmanne8e23b72014-06-20 08:12:44 +0200762 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
Gerd Hoffmann5643fc02014-06-07 13:03:10 +0200763 SimpleSpiceUpdate *update;
764 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
765 update = container_of(cmdext, SimpleSpiceUpdate, ext);
766 qemu_spice_destroy_update(&qxl->ssd, update);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200767 return;
768 }
769
770 /*
771 * ext->info points into guest-visible memory
772 * pci bar 0, $command.release_info
773 */
774 ring = &qxl->ram->release_ring;
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100775 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
776 if (prod >= ARRAY_SIZE(ring->items)) {
777 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
778 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
Alon Levy0b81c472012-04-25 12:13:21 +0300779 return;
780 }
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100781 if (ring->items[prod].el == 0) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200782 /* stick head into the ring */
783 id = ext.info->id;
784 ext.info->next = 0;
785 qxl_ram_set_dirty(qxl, &ext.info->next);
Daniel P. Berrangé94932c92019-04-12 13:16:26 +0100786 ring->items[prod].el = id;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200787 qxl_ring_set_dirty(qxl);
788 } else {
789 /* append item to the list */
790 qxl->last_release->next = ext.info->id;
791 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
792 ext.info->next = 0;
793 qxl_ram_set_dirty(qxl, &ext.info->next);
794 }
795 qxl->last_release = ext.info;
796 qxl->num_free_res++;
Alon Levyc480bb72012-03-18 13:46:14 +0100797 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200798 qxl_push_free_res(qxl, 0);
799}
800
801/* called from spice server thread context only */
802static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
803{
804 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
805 QXLCursorRing *ring;
806 QXLCommand *cmd;
807 int notify;
808
Alon Levyc480bb72012-03-18 13:46:14 +0100809 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
810
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200811 switch (qxl->mode) {
812 case QXL_MODE_COMPAT:
813 case QXL_MODE_NATIVE:
814 case QXL_MODE_UNDEFINED:
815 ring = &qxl->ram->cursor_ring;
816 if (SPICE_RING_IS_EMPTY(ring)) {
817 return false;
818 }
Alon Levy0b81c472012-04-25 12:13:21 +0300819 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
820 if (!cmd) {
821 return false;
822 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200823 ext->cmd = *cmd;
824 ext->group_id = MEMSLOT_GROUP_GUEST;
825 ext->flags = qxl->cmdflags;
826 SPICE_RING_POP(ring, notify);
827 qxl_ring_set_dirty(qxl);
828 if (notify) {
829 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
830 }
831 qxl->guest_primary.commands++;
832 qxl_track_command(qxl, ext);
833 qxl_log_command(qxl, "csr", ext);
Gerd Hoffmann60e94e42018-10-12 13:45:40 +0200834 if (qxl->have_vga) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200835 qxl_render_cursor(qxl, ext);
836 }
Alon Levyc480bb72012-03-18 13:46:14 +0100837 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200838 return true;
839 default:
840 return false;
841 }
842}
843
844/* called from spice server thread context only */
845static int interface_req_cursor_notification(QXLInstance *sin)
846{
847 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
848 int wait = 1;
849
Alon Levyc480bb72012-03-18 13:46:14 +0100850 trace_qxl_ring_cursor_req_notification(qxl->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200851 switch (qxl->mode) {
852 case QXL_MODE_COMPAT:
853 case QXL_MODE_NATIVE:
854 case QXL_MODE_UNDEFINED:
855 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
856 qxl_ring_set_dirty(qxl);
857 break;
858 default:
859 /* nothing */
860 break;
861 }
862 return wait;
863}
864
865/* called from spice server thread context */
866static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
867{
Alon Levybaeae402012-04-25 12:13:23 +0300868 /*
869 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
870 * use by xf86-video-qxl and is defined out in the qxl windows driver.
871 * Probably was at some earlier version that is prior to git start (2009),
872 * and is still guest trigerrable.
873 */
874 fprintf(stderr, "%s: deprecated\n", __func__);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200875}
876
877/* called from spice server thread context only */
878static int interface_flush_resources(QXLInstance *sin)
879{
880 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
881 int ret;
882
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +0200883 ret = qxl->num_free_res;
884 if (ret) {
885 qxl_push_free_res(qxl, 1);
886 }
887 return ret;
888}
889
Alon Levy5ff4e362011-07-20 12:20:58 +0300890static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
891
Alon Levy5ff4e362011-07-20 12:20:58 +0300892/* called from spice server thread context only */
Alon Levy2e1a98c2012-02-24 23:19:30 +0200893static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
Alon Levy5ff4e362011-07-20 12:20:58 +0300894{
Alon Levy5ff4e362011-07-20 12:20:58 +0300895 uint32_t current_async;
896
897 qemu_mutex_lock(&qxl->async_lock);
898 current_async = qxl->current_async;
899 qxl->current_async = QXL_UNDEFINED_IO;
900 qemu_mutex_unlock(&qxl->async_lock);
901
Alon Levyc480bb72012-03-18 13:46:14 +0100902 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
Alon Levy2e1a98c2012-02-24 23:19:30 +0200903 if (!cookie) {
904 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
905 return;
906 }
907 if (cookie && current_async != cookie->io) {
908 fprintf(stderr,
Alon Levy2fce7ed2012-04-25 12:13:20 +0300909 "qxl: %s: error: current_async = %d != %"
910 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
Alon Levy2e1a98c2012-02-24 23:19:30 +0200911 }
Alon Levy5ff4e362011-07-20 12:20:58 +0300912 switch (current_async) {
Alon Levy81fb6f12012-02-24 23:19:31 +0200913 case QXL_IO_MEMSLOT_ADD_ASYNC:
914 case QXL_IO_DESTROY_PRIMARY_ASYNC:
915 case QXL_IO_UPDATE_AREA_ASYNC:
916 case QXL_IO_FLUSH_SURFACES_ASYNC:
Alon Levy020af1c2012-08-22 11:16:25 +0300917 case QXL_IO_MONITORS_CONFIG_ASYNC:
Alon Levy81fb6f12012-02-24 23:19:31 +0200918 break;
Alon Levy5ff4e362011-07-20 12:20:58 +0300919 case QXL_IO_CREATE_PRIMARY_ASYNC:
920 qxl_create_guest_primary_complete(qxl);
921 break;
922 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
923 qxl_spice_destroy_surfaces_complete(qxl);
924 break;
925 case QXL_IO_DESTROY_SURFACE_ASYNC:
Alon Levy2e1a98c2012-02-24 23:19:30 +0200926 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
Alon Levy5ff4e362011-07-20 12:20:58 +0300927 break;
Alon Levy81fb6f12012-02-24 23:19:31 +0200928 default:
Alex Chenada6f6f2020-11-19 02:58:51 +0000929 fprintf(stderr, "qxl: %s: unexpected current_async %u\n", __func__,
Alon Levy81fb6f12012-02-24 23:19:31 +0200930 current_async);
Alon Levy5ff4e362011-07-20 12:20:58 +0300931 }
932 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
933}
934
Alon Levy2e1a98c2012-02-24 23:19:30 +0200935/* called from spice server thread context only */
Alon Levy81fb6f12012-02-24 23:19:31 +0200936static void interface_update_area_complete(QXLInstance *sin,
937 uint32_t surface_id,
938 QXLRect *dirty, uint32_t num_updated_rects)
939{
940 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
941 int i;
942 int qxl_i;
943
Daniel Brodsky6e8a3552020-04-03 21:21:08 -0700944 QEMU_LOCK_GUARD(&qxl->ssd.lock);
Gerd Hoffmann2f5ae772016-06-08 16:11:41 +0200945 if (surface_id != 0 || !num_updated_rects ||
946 !qxl->render_update_cookie_num) {
Alon Levy81fb6f12012-02-24 23:19:31 +0200947 return;
948 }
Alon Levyc480bb72012-03-18 13:46:14 +0100949 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
950 dirty->right, dirty->top, dirty->bottom);
951 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
Alon Levy81fb6f12012-02-24 23:19:31 +0200952 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
953 /*
954 * overflow - treat this as a full update. Not expected to be common.
955 */
Alon Levyc480bb72012-03-18 13:46:14 +0100956 trace_qxl_interface_update_area_complete_overflow(qxl->id,
957 QXL_NUM_DIRTY_RECTS);
Alon Levy81fb6f12012-02-24 23:19:31 +0200958 qxl->guest_primary.resized = 1;
959 }
960 if (qxl->guest_primary.resized) {
961 /*
962 * Don't bother copying or scheduling the bh since we will flip
963 * the whole area anyway on completion of the update_area async call
964 */
Alon Levy81fb6f12012-02-24 23:19:31 +0200965 return;
966 }
967 qxl_i = qxl->num_dirty_rects;
968 for (i = 0; i < num_updated_rects; i++) {
969 qxl->dirty[qxl_i++] = dirty[i];
970 }
971 qxl->num_dirty_rects += num_updated_rects;
Alon Levyc480bb72012-03-18 13:46:14 +0100972 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
973 qxl->num_dirty_rects);
Alon Levy81fb6f12012-02-24 23:19:31 +0200974 qemu_bh_schedule(qxl->update_area_bh);
Alon Levy81fb6f12012-02-24 23:19:31 +0200975}
976
977/* called from spice server thread context only */
Alon Levy2e1a98c2012-02-24 23:19:30 +0200978static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
979{
980 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
Peter Maydell5dba0d42012-03-16 13:50:04 +0000981 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
Alon Levy2e1a98c2012-02-24 23:19:30 +0200982
983 switch (cookie->type) {
984 case QXL_COOKIE_TYPE_IO:
985 interface_async_complete_io(qxl, cookie);
Alon Levy81fb6f12012-02-24 23:19:31 +0200986 g_free(cookie);
987 break;
988 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
989 qxl_render_update_area_done(qxl, cookie);
Alon Levy2e1a98c2012-02-24 23:19:30 +0200990 break;
Alon Levy020af1c2012-08-22 11:16:25 +0300991 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
992 break;
Alon Levy2e1a98c2012-02-24 23:19:30 +0200993 default:
994 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
995 __func__, cookie->type);
Alon Levy81fb6f12012-02-24 23:19:31 +0200996 g_free(cookie);
Alon Levy2e1a98c2012-02-24 23:19:30 +0200997 }
Alon Levy2e1a98c2012-02-24 23:19:30 +0200998}
999
Søren Sandmann Pedersenc10018d2012-09-04 10:14:48 -04001000/* called from spice server thread context only */
1001static void interface_set_client_capabilities(QXLInstance *sin,
1002 uint8_t client_present,
1003 uint8_t caps[58])
1004{
1005 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1006
Alon Levye0ac6092013-01-21 14:48:06 +02001007 if (qxl->revision < 4) {
1008 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1009 qxl->revision);
1010 return;
1011 }
1012
Hans de Goedeab902982012-09-07 21:48:22 +02001013 if (runstate_check(RUN_STATE_INMIGRATE) ||
1014 runstate_check(RUN_STATE_POSTMIGRATE)) {
1015 return;
1016 }
1017
Søren Sandmann Pedersenc10018d2012-09-04 10:14:48 -04001018 qxl->shadow_rom.client_present = client_present;
Markus Armbruster08688af2013-01-10 14:24:50 +01001019 memcpy(qxl->shadow_rom.client_capabilities, caps,
1020 sizeof(qxl->shadow_rom.client_capabilities));
Søren Sandmann Pedersenc10018d2012-09-04 10:14:48 -04001021 qxl->rom->client_present = client_present;
Markus Armbruster08688af2013-01-10 14:24:50 +01001022 memcpy(qxl->rom->client_capabilities, caps,
1023 sizeof(qxl->rom->client_capabilities));
Søren Sandmann Pedersenc10018d2012-09-04 10:14:48 -04001024 qxl_rom_set_dirty(qxl);
1025
1026 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1027}
1028
Christophe Fergeau6c756502016-10-28 16:48:40 +02001029static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1030 VDAgentMonitorsConfig *monitors_config,
1031 unsigned int max_outputs)
1032{
1033 int i;
1034 unsigned int monitors_count;
1035
1036 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1037
1038 if (rom->client_monitors_config.count != monitors_count) {
1039 return true;
1040 }
1041
1042 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1043 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1044 QXLURect *rect = &rom->client_monitors_config.heads[i];
1045 /* monitor->depth ignored */
1046 if ((rect->left != monitor->x) ||
1047 (rect->top != monitor->y) ||
1048 (rect->right != monitor->x + monitor->width) ||
1049 (rect->bottom != monitor->y + monitor->height)) {
1050 return true;
1051 }
1052 }
1053
1054 return false;
1055}
1056
Alon Levya639ab02012-09-12 16:13:28 +03001057/* called from main context only */
1058static int interface_client_monitors_config(QXLInstance *sin,
1059 VDAgentMonitorsConfig *monitors_config)
1060{
1061 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1062 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1063 int i;
Frediano Ziglio567161f2015-07-06 07:56:38 +01001064 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
Christophe Fergeau6c756502016-10-28 16:48:40 +02001065 bool config_changed = false;
Alon Levya639ab02012-09-12 16:13:28 +03001066
Alon Levye0ac6092013-01-21 14:48:06 +02001067 if (qxl->revision < 4) {
1068 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1069 qxl->revision);
1070 return 0;
1071 }
Alon Levya639ab02012-09-12 16:13:28 +03001072 /*
1073 * Older windows drivers set int_mask to 0 when their ISR is called,
1074 * then later set it to ~0. So it doesn't relate to the actual interrupts
1075 * handled. However, they are old, so clearly they don't support this
1076 * interrupt
1077 */
1078 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1079 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1080 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1081 qxl->ram->int_mask,
1082 monitors_config);
1083 return 0;
1084 }
1085 if (!monitors_config) {
1086 return 1;
1087 }
Frediano Ziglio567161f2015-07-06 07:56:38 +01001088
1089#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1090 /* limit number of outputs based on setting limit */
1091 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1092 max_outputs = qxl->max_outputs;
1093 }
1094#endif
1095
Christophe Fergeau6c756502016-10-28 16:48:40 +02001096 config_changed = qxl_rom_monitors_config_changed(rom,
1097 monitors_config,
1098 max_outputs);
1099
Alon Levya639ab02012-09-12 16:13:28 +03001100 memset(&rom->client_monitors_config, 0,
1101 sizeof(rom->client_monitors_config));
1102 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1103 /* monitors_config->flags ignored */
Frediano Ziglio567161f2015-07-06 07:56:38 +01001104 if (rom->client_monitors_config.count >= max_outputs) {
Alon Levya639ab02012-09-12 16:13:28 +03001105 trace_qxl_client_monitors_config_capped(qxl->id,
1106 monitors_config->num_of_monitors,
Frediano Ziglio567161f2015-07-06 07:56:38 +01001107 max_outputs);
1108 rom->client_monitors_config.count = max_outputs;
Alon Levya639ab02012-09-12 16:13:28 +03001109 }
1110 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1111 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1112 QXLURect *rect = &rom->client_monitors_config.heads[i];
1113 /* monitor->depth ignored */
1114 rect->left = monitor->x;
1115 rect->top = monitor->y;
1116 rect->right = monitor->x + monitor->width;
1117 rect->bottom = monitor->y + monitor->height;
1118 }
1119 rom->client_monitors_config_crc = qxl_crc32(
1120 (const uint8_t *)&rom->client_monitors_config,
1121 sizeof(rom->client_monitors_config));
1122 trace_qxl_client_monitors_config_crc(qxl->id,
1123 sizeof(rom->client_monitors_config),
1124 rom->client_monitors_config_crc);
1125
1126 trace_qxl_interrupt_client_monitors_config(qxl->id,
1127 rom->client_monitors_config.count,
1128 rom->client_monitors_config.heads);
Christophe Fergeau6c756502016-10-28 16:48:40 +02001129 if (config_changed) {
1130 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1131 }
Alon Levya639ab02012-09-12 16:13:28 +03001132 return 1;
1133}
Alon Levya639ab02012-09-12 16:13:28 +03001134
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001135static const QXLInterface qxl_interface = {
1136 .base.type = SPICE_INTERFACE_QXL,
1137 .base.description = "qxl gpu",
1138 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1139 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1140
John Snow9dcafa42022-01-05 13:49:37 +00001141#if SPICE_HAS_ATTACHED_WORKER
1142 .attached_worker = interface_attached_worker,
1143#else
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001144 .attache_worker = interface_attach_worker,
John Snow9dcafa42022-01-05 13:49:37 +00001145#endif
1146
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001147 .set_compression_level = interface_set_compression_level,
John Snow015e02f2016-06-29 18:41:35 -04001148#if SPICE_NEEDS_SET_MM_TIME
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001149 .set_mm_time = interface_set_mm_time,
John Snow015e02f2016-06-29 18:41:35 -04001150#endif
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001151 .get_init_info = interface_get_init_info,
1152
1153 /* the callbacks below are called from spice server thread context */
1154 .get_command = interface_get_command,
1155 .req_cmd_notification = interface_req_cmd_notification,
1156 .release_resource = interface_release_resource,
1157 .get_cursor_command = interface_get_cursor_command,
1158 .req_cursor_notification = interface_req_cursor_notification,
1159 .notify_update = interface_notify_update,
1160 .flush_resources = interface_flush_resources,
Alon Levy5ff4e362011-07-20 12:20:58 +03001161 .async_complete = interface_async_complete,
Alon Levy81fb6f12012-02-24 23:19:31 +02001162 .update_area_complete = interface_update_area_complete,
Søren Sandmann Pedersenc10018d2012-09-04 10:14:48 -04001163 .set_client_capabilities = interface_set_client_capabilities,
Alon Levya639ab02012-09-12 16:13:28 +03001164 .client_monitors_config = interface_client_monitors_config,
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001165};
1166
Gerd Hoffmann15162332014-09-24 17:05:45 +02001167static const GraphicHwOps qxl_ops = {
1168 .gfx_update = qxl_hw_update,
Marc-André Lureau4d631622015-08-24 13:20:49 +02001169 .gfx_update_async = true,
Gerd Hoffmann15162332014-09-24 17:05:45 +02001170};
1171
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001172static void qxl_enter_vga_mode(PCIQXLDevice *d)
1173{
1174 if (d->mode == QXL_MODE_VGA) {
1175 return;
1176 }
Alon Levyc480bb72012-03-18 13:46:14 +01001177 trace_qxl_enter_vga_mode(d->id);
Hans de Goede0a2b5e32013-04-23 10:18:16 +02001178 spice_qxl_driver_unload(&d->ssd.qxl);
Gerd Hoffmann15162332014-09-24 17:05:45 +02001179 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
Gerd Hoffmann3dcadce2014-11-04 14:16:12 +01001180 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001181 qemu_spice_create_host_primary(&d->ssd);
1182 d->mode = QXL_MODE_VGA;
Marc-André Lureaua703d3a2017-04-06 14:05:13 +02001183 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
Alon Levy0f7bfd82012-05-24 19:18:53 +03001184 vga_dirty_log_start(&d->vga);
Gerd Hoffmann1dbfa002013-03-12 13:44:38 +01001185 graphic_hw_update(d->vga.con);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001186}
1187
1188static void qxl_exit_vga_mode(PCIQXLDevice *d)
1189{
1190 if (d->mode != QXL_MODE_VGA) {
1191 return;
1192 }
Alon Levyc480bb72012-03-18 13:46:14 +01001193 trace_qxl_exit_vga_mode(d->id);
Gerd Hoffmann15162332014-09-24 17:05:45 +02001194 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
Gerd Hoffmann3dcadce2014-11-04 14:16:12 +01001195 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
Alon Levy0f7bfd82012-05-24 19:18:53 +03001196 vga_dirty_log_stop(&d->vga);
Alon Levy5ff4e362011-07-20 12:20:58 +03001197 qxl_destroy_primary(d, QXL_SYNC);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001198}
1199
Yonit Halperin40010ae2011-09-05 08:45:59 +03001200static void qxl_update_irq(PCIQXLDevice *d)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001201{
1202 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1203 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1204 int level = !!(pending & mask);
Marcel Apfelbaum9e64f8a2013-10-07 10:36:39 +03001205 pci_set_irq(&d->pci, level);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001206 qxl_ring_set_dirty(d);
1207}
1208
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001209static void qxl_check_state(PCIQXLDevice *d)
1210{
1211 QXLRam *ram = d->ram;
Yonit Halperin71d388d2012-08-21 11:51:56 +03001212 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001213
Yonit Halperin71d388d2012-08-21 11:51:56 +03001214 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1215 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001216}
1217
1218static void qxl_reset_state(PCIQXLDevice *d)
1219{
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001220 QXLRom *rom = d->rom;
1221
Yonit Halperinbe48e992011-08-09 16:12:40 +03001222 qxl_check_state(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001223 d->shadow_rom.update_id = cpu_to_le32(0);
1224 *rom = d->shadow_rom;
1225 qxl_rom_set_dirty(d);
1226 init_qxl_ram(d);
1227 d->num_free_res = 0;
1228 d->last_release = NULL;
1229 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
Alon Levyf06b8522014-01-20 12:44:19 +02001230 qxl_update_irq(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001231}
1232
1233static void qxl_soft_reset(PCIQXLDevice *d)
1234{
Alon Levyc480bb72012-03-18 13:46:14 +01001235 trace_qxl_soft_reset(d->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001236 qxl_check_state(d);
Alon Levy087e6a42012-05-24 19:18:54 +03001237 qxl_clear_guest_bug(d);
Gerd Hoffmann05fa1c72015-10-20 09:57:30 +02001238 qemu_mutex_lock(&d->async_lock);
Alon Levya5f68c22012-06-11 09:24:01 +03001239 d->current_async = QXL_UNDEFINED_IO;
Gerd Hoffmann05fa1c72015-10-20 09:57:30 +02001240 qemu_mutex_unlock(&d->async_lock);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001241
Gerd Hoffmann60e94e42018-10-12 13:45:40 +02001242 if (d->have_vga) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001243 qxl_enter_vga_mode(d);
1244 } else {
1245 d->mode = QXL_MODE_UNDEFINED;
1246 }
1247}
1248
1249static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1250{
Gerd Hoffmann75c70e32013-12-09 16:03:49 +01001251 bool startstop = qemu_spice_display_is_running(&d->ssd);
1252
Alon Levyc480bb72012-03-18 13:46:14 +01001253 trace_qxl_hard_reset(d->id, loadvm);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001254
Gerd Hoffmann75c70e32013-12-09 16:03:49 +01001255 if (startstop) {
1256 qemu_spice_display_stop();
1257 }
1258
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +03001259 qxl_spice_reset_cursor(d);
1260 qxl_spice_reset_image_cache(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001261 qxl_reset_surfaces(d);
1262 qxl_reset_memslots(d);
1263
1264 /* pre loadvm reset must not touch QXLRam. This lives in
1265 * device memory, is migrated together with RAM and thus
1266 * already loaded at this point */
1267 if (!loadvm) {
1268 qxl_reset_state(d);
1269 }
1270 qemu_spice_create_host_memslot(&d->ssd);
1271 qxl_soft_reset(d);
Gerd Hoffmann75c70e32013-12-09 16:03:49 +01001272
1273 if (startstop) {
1274 qemu_spice_display_start();
1275 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001276}
1277
1278static void qxl_reset_handler(DeviceState *dev)
1279{
Gongleic69f6c72015-05-12 17:27:10 +08001280 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
Alon Levyc480bb72012-03-18 13:46:14 +01001281
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001282 qxl_hard_reset(d, 0);
1283}
1284
1285static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1286{
1287 VGACommonState *vga = opaque;
1288 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1289
Alon Levyc480bb72012-03-18 13:46:14 +01001290 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
Gerd Hoffmanned71c092020-02-06 08:43:58 +01001291 if (qxl->mode != QXL_MODE_VGA &&
1292 qxl->revision <= QXL_REVISION_STABLE_V12) {
Alon Levy5ff4e362011-07-20 12:20:58 +03001293 qxl_destroy_primary(qxl, QXL_SYNC);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001294 qxl_soft_reset(qxl);
1295 }
1296 vga_ioport_write(opaque, addr, val);
1297}
1298
Gerd Hoffmannf67ab772011-11-03 18:21:54 +01001299static const MemoryRegionPortio qxl_vga_portio_list[] = {
1300 { 0x04, 2, 1, .read = vga_ioport_read,
1301 .write = qxl_vga_ioport_write }, /* 3b4 */
1302 { 0x0a, 1, 1, .read = vga_ioport_read,
1303 .write = qxl_vga_ioport_write }, /* 3ba */
1304 { 0x10, 16, 1, .read = vga_ioport_read,
1305 .write = qxl_vga_ioport_write }, /* 3c0 */
1306 { 0x24, 2, 1, .read = vga_ioport_read,
1307 .write = qxl_vga_ioport_write }, /* 3d4 */
1308 { 0x2a, 1, 1, .read = vga_ioport_read,
1309 .write = qxl_vga_ioport_write }, /* 3da */
1310 PORTIO_END_OF_LIST(),
1311};
1312
Alon Levye954ea22012-04-25 12:13:24 +03001313static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1314 qxl_async_io async)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001315{
1316 static const int regions[] = {
1317 QXL_RAM_RANGE_INDEX,
1318 QXL_VRAM_RANGE_INDEX,
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02001319 QXL_VRAM64_RANGE_INDEX,
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001320 };
1321 uint64_t guest_start;
1322 uint64_t guest_end;
1323 int pci_region;
1324 pcibus_t pci_start;
1325 pcibus_t pci_end;
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001326 MemoryRegion *mr;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001327 intptr_t virt_start;
1328 QXLDevMemSlot memslot;
1329 int i;
1330
1331 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1332 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1333
Alon Levyc480bb72012-03-18 13:46:14 +01001334 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001335
Alon Levye954ea22012-04-25 12:13:24 +03001336 if (slot_id >= NUM_MEMSLOTS) {
Alon Levy0a530542012-05-24 12:38:12 +03001337 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
Alon Levye954ea22012-04-25 12:13:24 +03001338 slot_id, NUM_MEMSLOTS);
1339 return 1;
1340 }
1341 if (guest_start > guest_end) {
Alon Levy0a530542012-05-24 12:38:12 +03001342 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
Alon Levye954ea22012-04-25 12:13:24 +03001343 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1344 return 1;
1345 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001346
1347 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1348 pci_region = regions[i];
1349 pci_start = d->pci.io_regions[pci_region].addr;
1350 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1351 /* mapped? */
1352 if (pci_start == -1) {
1353 continue;
1354 }
1355 /* start address in range ? */
1356 if (guest_start < pci_start || guest_start > pci_end) {
1357 continue;
1358 }
1359 /* end address in range ? */
1360 if (guest_end > pci_end) {
1361 continue;
1362 }
1363 /* passed */
1364 break;
1365 }
Alon Levye954ea22012-04-25 12:13:24 +03001366 if (i == ARRAY_SIZE(regions)) {
Alon Levy0a530542012-05-24 12:38:12 +03001367 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
Alon Levye954ea22012-04-25 12:13:24 +03001368 return 1;
1369 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001370
1371 switch (pci_region) {
1372 case QXL_RAM_RANGE_INDEX:
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001373 mr = &d->vga.vram;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001374 break;
1375 case QXL_VRAM_RANGE_INDEX:
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02001376 case 4 /* vram 64bit */:
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001377 mr = &d->vram_bar;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001378 break;
1379 default:
1380 /* should not happen */
Alon Levy0a530542012-05-24 12:38:12 +03001381 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
Alon Levye954ea22012-04-25 12:13:24 +03001382 return 1;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001383 }
1384
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001385 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001386 memslot.slot_id = slot_id;
1387 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1388 memslot.virt_start = virt_start + (guest_start - pci_start);
1389 memslot.virt_end = virt_start + (guest_end - pci_start);
1390 memslot.addr_delta = memslot.virt_start - delta;
1391 memslot.generation = d->rom->slot_generation = 0;
1392 qxl_rom_set_dirty(d);
1393
Alon Levy5ff4e362011-07-20 12:20:58 +03001394 qemu_spice_add_memslot(&d->ssd, &memslot, async);
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001395 d->guest_slots[slot_id].mr = mr;
1396 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001397 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1398 d->guest_slots[slot_id].delta = delta;
1399 d->guest_slots[slot_id].active = 1;
Alon Levye954ea22012-04-25 12:13:24 +03001400 return 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001401}
1402
1403static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1404{
Gerd Hoffmann5c59d112011-07-20 12:20:50 +03001405 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001406 d->guest_slots[slot_id].active = 0;
1407}
1408
1409static void qxl_reset_memslots(PCIQXLDevice *d)
1410{
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +03001411 qxl_spice_reset_memslots(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001412 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1413}
1414
1415static void qxl_reset_surfaces(PCIQXLDevice *d)
1416{
Alon Levyc480bb72012-03-18 13:46:14 +01001417 trace_qxl_reset_surfaces(d->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001418 d->mode = QXL_MODE_UNDEFINED;
Alon Levy5ff4e362011-07-20 12:20:58 +03001419 qxl_spice_destroy_surfaces(d, QXL_SYNC);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001420}
1421
Yonit Halperine25139b2012-02-15 11:22:15 +02001422/* can be also called from spice server thread context */
Gerd Hoffmann726bdf62016-06-22 14:07:22 +02001423static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1424 uint32_t *s, uint64_t *o)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001425{
1426 uint64_t phys = le64_to_cpu(pqxl);
1427 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1428 uint64_t offset = phys & 0xffffffffffff;
1429
Gerd Hoffmann726bdf62016-06-22 14:07:22 +02001430 if (slot >= NUM_MEMSLOTS) {
1431 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1432 NUM_MEMSLOTS);
1433 return false;
1434 }
1435 if (!qxl->guest_slots[slot].active) {
1436 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1437 return false;
1438 }
1439 if (offset < qxl->guest_slots[slot].delta) {
1440 qxl_set_guest_bug(qxl,
Alon Levy0a530542012-05-24 12:38:12 +03001441 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
Alon Levy4b635c52012-04-25 12:13:17 +03001442 slot, offset, qxl->guest_slots[slot].delta);
Gerd Hoffmann726bdf62016-06-22 14:07:22 +02001443 return false;
1444 }
1445 offset -= qxl->guest_slots[slot].delta;
1446 if (offset > qxl->guest_slots[slot].size) {
1447 qxl_set_guest_bug(qxl,
Alon Levy0a530542012-05-24 12:38:12 +03001448 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
Alon Levy4b635c52012-04-25 12:13:17 +03001449 slot, offset, qxl->guest_slots[slot].size);
Gerd Hoffmann726bdf62016-06-22 14:07:22 +02001450 return false;
1451 }
1452
1453 *s = slot;
1454 *o = offset;
1455 return true;
1456}
1457
1458/* can be also called from spice server thread context */
1459void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1460{
1461 uint64_t offset;
1462 uint32_t slot;
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001463 void *ptr;
Gerd Hoffmann726bdf62016-06-22 14:07:22 +02001464
1465 switch (group_id) {
1466 case MEMSLOT_GROUP_HOST:
1467 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1468 return (void *)(intptr_t)offset;
1469 case MEMSLOT_GROUP_GUEST:
1470 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
Alon Levy4b635c52012-04-25 12:13:17 +03001471 return NULL;
1472 }
Gerd Hoffmann3cb51582016-06-22 14:07:23 +02001473 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1474 ptr += qxl->guest_slots[slot].offset;
1475 ptr += offset;
1476 return ptr;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001477 }
Alon Levy4b635c52012-04-25 12:13:17 +03001478 return NULL;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001479}
1480
Alon Levy5ff4e362011-07-20 12:20:58 +03001481static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1482{
1483 /* for local rendering */
1484 qxl_render_resize(qxl);
1485}
1486
1487static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1488 qxl_async_io async)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001489{
1490 QXLDevSurfaceCreate surface;
1491 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
Alon Levy3761abb2014-01-20 18:57:12 +02001492 uint32_t requested_height = le32_to_cpu(sc->height);
Alon Levy13d1fd42012-06-10 18:05:06 +03001493 int requested_stride = le32_to_cpu(sc->stride);
1494
Alon Levy3761abb2014-01-20 18:57:12 +02001495 if (requested_stride == INT32_MIN ||
1496 abs(requested_stride) * (uint64_t)requested_height
1497 > qxl->vgamem_size) {
1498 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1499 " stride %d x height %" PRIu32 " > %" PRIu32,
1500 __func__, requested_stride, requested_height,
1501 qxl->vgamem_size);
Alon Levy13d1fd42012-06-10 18:05:06 +03001502 return;
1503 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001504
Alon Levyddf9f4b2012-04-25 12:43:31 +03001505 if (qxl->mode == QXL_MODE_NATIVE) {
Alon Levy0a530542012-05-24 12:38:12 +03001506 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
Alon Levyddf9f4b2012-04-25 12:43:31 +03001507 __func__);
1508 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001509 qxl_exit_vga_mode(qxl);
1510
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001511 surface.format = le32_to_cpu(sc->format);
1512 surface.height = le32_to_cpu(sc->height);
1513 surface.mem = le64_to_cpu(sc->mem);
1514 surface.position = le32_to_cpu(sc->position);
1515 surface.stride = le32_to_cpu(sc->stride);
1516 surface.width = le32_to_cpu(sc->width);
1517 surface.type = le32_to_cpu(sc->type);
1518 surface.flags = le32_to_cpu(sc->flags);
Alon Levyc480bb72012-03-18 13:46:14 +01001519 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1520 sc->format, sc->position);
1521 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1522 sc->flags);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001523
Alon Levy48f4ba62012-10-15 14:54:03 +02001524 if ((surface.stride & 0x3) != 0) {
1525 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1526 surface.stride);
1527 return;
1528 }
1529
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001530 surface.mouse_mode = true;
1531 surface.group_id = MEMSLOT_GROUP_GUEST;
1532 if (loadvm) {
1533 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1534 }
1535
1536 qxl->mode = QXL_MODE_NATIVE;
1537 qxl->cmdflags = 0;
Alon Levy5ff4e362011-07-20 12:20:58 +03001538 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001539
Alon Levy5ff4e362011-07-20 12:20:58 +03001540 if (async == QXL_SYNC) {
1541 qxl_create_guest_primary_complete(qxl);
1542 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001543}
1544
Alon Levy5ff4e362011-07-20 12:20:58 +03001545/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1546 * done (in QXL_SYNC case), 0 otherwise. */
1547static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001548{
1549 if (d->mode == QXL_MODE_UNDEFINED) {
Alon Levy5ff4e362011-07-20 12:20:58 +03001550 return 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001551 }
Alon Levyc480bb72012-03-18 13:46:14 +01001552 trace_qxl_destroy_primary(d->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001553 d->mode = QXL_MODE_UNDEFINED;
Alon Levy5ff4e362011-07-20 12:20:58 +03001554 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
Yonit Halperin30f6da62011-10-18 18:58:54 +02001555 qxl_spice_reset_cursor(d);
Alon Levy5ff4e362011-07-20 12:20:58 +03001556 return 1;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001557}
1558
Gerd Hoffmann9c704342014-02-19 11:40:17 +01001559static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001560{
1561 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1562 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1563 QXLMode *mode = d->modes->modes + modenr;
1564 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1565 QXLMemSlot slot = {
1566 .mem_start = start,
1567 .mem_end = end
1568 };
Gerd Hoffmann9c704342014-02-19 11:40:17 +01001569
1570 if (modenr >= d->modes->n_modes) {
1571 qxl_set_guest_bug(d, "mode number out of range");
1572 return;
1573 }
1574
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001575 QXLSurfaceCreate surface = {
1576 .width = mode->x_res,
1577 .height = mode->y_res,
1578 .stride = -mode->x_res * 4,
1579 .format = SPICE_SURFACE_FMT_32_xRGB,
1580 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1581 .mouse_mode = true,
1582 .mem = devmem + d->shadow_rom.draw_area_offset,
1583 };
1584
Alon Levyc480bb72012-03-18 13:46:14 +01001585 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1586 devmem);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001587 if (!loadvm) {
1588 qxl_hard_reset(d, 0);
1589 }
1590
1591 d->guest_slots[0].slot = slot;
Alon Levye954ea22012-04-25 12:13:24 +03001592 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001593
1594 d->guest_primary.surface = surface;
Alon Levy5ff4e362011-07-20 12:20:58 +03001595 qxl_create_guest_primary(d, 0, QXL_SYNC);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001596
1597 d->mode = QXL_MODE_COMPAT;
1598 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001599 if (mode->bits == 16) {
1600 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1601 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001602 d->shadow_rom.mode = cpu_to_le32(modenr);
1603 d->rom->mode = cpu_to_le32(modenr);
1604 qxl_rom_set_dirty(d);
1605}
1606
Avi Kivitya8170e52012-10-23 12:30:10 +02001607static void ioport_write(void *opaque, hwaddr addr,
Avi Kivityb1950432011-08-08 16:08:57 +03001608 uint64_t val, unsigned size)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001609{
1610 PCIQXLDevice *d = opaque;
Avi Kivityb1950432011-08-08 16:08:57 +03001611 uint32_t io_port = addr;
Alon Levy5ff4e362011-07-20 12:20:58 +03001612 qxl_async_io async = QXL_SYNC;
Philippe Mathieu-Daudé380e6d82020-02-15 17:15:56 +01001613 uint32_t orig_io_port;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001614
Alon Levyd96aafc2012-10-02 11:39:14 +02001615 if (d->guest_bug && io_port != QXL_IO_RESET) {
Alon Levy087e6a42012-05-24 19:18:54 +03001616 return;
1617 }
1618
Alon Levy020af1c2012-08-22 11:16:25 +03001619 if (d->revision <= QXL_REVISION_STABLE_V10 &&
Gerd Hoffmannffe01e52012-09-25 13:56:40 +02001620 io_port > QXL_IO_FLUSH_RELEASE) {
Alon Levy020af1c2012-08-22 11:16:25 +03001621 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1622 io_port, d->revision);
1623 return;
1624 }
1625
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001626 switch (io_port) {
1627 case QXL_IO_RESET:
1628 case QXL_IO_SET_MODE:
1629 case QXL_IO_MEMSLOT_ADD:
1630 case QXL_IO_MEMSLOT_DEL:
1631 case QXL_IO_CREATE_PRIMARY:
Gerd Hoffmann81144d12011-06-24 12:23:44 +02001632 case QXL_IO_UPDATE_IRQ:
Alon Levya3d14052011-06-29 13:57:11 +02001633 case QXL_IO_LOG:
Alon Levy5ff4e362011-07-20 12:20:58 +03001634 case QXL_IO_MEMSLOT_ADD_ASYNC:
1635 case QXL_IO_CREATE_PRIMARY_ASYNC:
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001636 break;
1637 default:
Alon Levye21a2982011-07-20 12:20:57 +03001638 if (d->mode != QXL_MODE_VGA) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001639 break;
Alon Levye21a2982011-07-20 12:20:57 +03001640 }
Alon Levyc480bb72012-03-18 13:46:14 +01001641 trace_qxl_io_unexpected_vga_mode(d->id,
Alon Levy917ae082012-09-12 16:13:26 +03001642 addr, val, io_port_to_string(io_port));
Alon Levy5ff4e362011-07-20 12:20:58 +03001643 /* be nice to buggy guest drivers */
1644 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
Alon Levy020af1c2012-08-22 11:16:25 +03001645 io_port < QXL_IO_RANGE_SIZE) {
Alon Levy5ff4e362011-07-20 12:20:58 +03001646 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1647 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001648 return;
1649 }
1650
Alon Levy5ff4e362011-07-20 12:20:58 +03001651 /* we change the io_port to avoid ifdeffery in the main switch */
1652 orig_io_port = io_port;
1653 switch (io_port) {
1654 case QXL_IO_UPDATE_AREA_ASYNC:
1655 io_port = QXL_IO_UPDATE_AREA;
1656 goto async_common;
1657 case QXL_IO_MEMSLOT_ADD_ASYNC:
1658 io_port = QXL_IO_MEMSLOT_ADD;
1659 goto async_common;
1660 case QXL_IO_CREATE_PRIMARY_ASYNC:
1661 io_port = QXL_IO_CREATE_PRIMARY;
1662 goto async_common;
1663 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1664 io_port = QXL_IO_DESTROY_PRIMARY;
1665 goto async_common;
1666 case QXL_IO_DESTROY_SURFACE_ASYNC:
1667 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1668 goto async_common;
1669 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1670 io_port = QXL_IO_DESTROY_ALL_SURFACES;
Alon Levy3e16b9c2011-07-20 12:20:59 +03001671 goto async_common;
1672 case QXL_IO_FLUSH_SURFACES_ASYNC:
Alon Levy020af1c2012-08-22 11:16:25 +03001673 case QXL_IO_MONITORS_CONFIG_ASYNC:
Alon Levy5ff4e362011-07-20 12:20:58 +03001674async_common:
1675 async = QXL_ASYNC;
Daniel Brodsky6e8a3552020-04-03 21:21:08 -07001676 WITH_QEMU_LOCK_GUARD(&d->async_lock) {
1677 if (d->current_async != QXL_UNDEFINED_IO) {
1678 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1679 io_port, d->current_async);
1680 return;
1681 }
1682 d->current_async = orig_io_port;
Alon Levy5ff4e362011-07-20 12:20:58 +03001683 }
Alon Levy5ff4e362011-07-20 12:20:58 +03001684 break;
1685 default:
1686 break;
1687 }
Gerd Hoffmann18b20382013-09-05 17:30:05 +02001688 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1689 addr, io_port_to_string(addr),
1690 val, size, async);
Alon Levy5ff4e362011-07-20 12:20:58 +03001691
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001692 switch (io_port) {
1693 case QXL_IO_UPDATE_AREA:
1694 {
Alon Levy81fb6f12012-02-24 23:19:31 +02001695 QXLCookie *cookie = NULL;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001696 QXLRect update = d->ram->update_area;
Alon Levy81fb6f12012-02-24 23:19:31 +02001697
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02001698 if (d->ram->update_surface > d->ssd.num_surfaces) {
Alon Levy511b13e2012-08-21 13:51:31 +03001699 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1700 d->ram->update_surface);
Michael Tokarev36a03e02012-09-19 17:41:26 +04001701 break;
Alon Levy511b13e2012-08-21 13:51:31 +03001702 }
Michael Tokarev36a03e02012-09-19 17:41:26 +04001703 if (update.left >= update.right || update.top >= update.bottom ||
1704 update.left < 0 || update.top < 0) {
Alon Levy511b13e2012-08-21 13:51:31 +03001705 qxl_set_guest_bug(d,
1706 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1707 update.left, update.top, update.right, update.bottom);
Marc-André Lureau9e5a25f2014-10-10 19:05:11 +02001708 if (update.left == update.right || update.top == update.bottom) {
1709 /* old drivers may provide empty area, keep going */
1710 qxl_clear_guest_bug(d);
1711 goto cancel_async;
1712 }
Dunrong Huangccc29602012-08-31 00:44:44 +08001713 break;
1714 }
Alon Levy81fb6f12012-02-24 23:19:31 +02001715 if (async == QXL_ASYNC) {
1716 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1717 QXL_IO_UPDATE_AREA_ASYNC);
1718 cookie->u.area = update;
1719 }
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +03001720 qxl_spice_update_area(d, d->ram->update_surface,
Alon Levy81fb6f12012-02-24 23:19:31 +02001721 cookie ? &cookie->u.area : &update,
1722 NULL, 0, 0, async, cookie);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001723 break;
1724 }
1725 case QXL_IO_NOTIFY_CMD:
Gerd Hoffmann5c59d112011-07-20 12:20:50 +03001726 qemu_spice_wakeup(&d->ssd);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001727 break;
1728 case QXL_IO_NOTIFY_CURSOR:
Gerd Hoffmann5c59d112011-07-20 12:20:50 +03001729 qemu_spice_wakeup(&d->ssd);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001730 break;
1731 case QXL_IO_UPDATE_IRQ:
Yonit Halperin40010ae2011-09-05 08:45:59 +03001732 qxl_update_irq(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001733 break;
1734 case QXL_IO_NOTIFY_OOM:
1735 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1736 break;
1737 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001738 d->oom_running = 1;
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +03001739 qxl_spice_oom(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001740 d->oom_running = 0;
1741 break;
1742 case QXL_IO_SET_MODE:
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001743 qxl_set_mode(d, val, 0);
1744 break;
1745 case QXL_IO_LOG:
Gerd Hoffmannd97df4b2020-07-20 12:03:50 +02001746#ifdef CONFIG_MODULES
1747 /*
1748 * FIXME
1749 * trace_event_get_state_backends() does not work for modules,
1750 * it leads to "undefined symbol: qemu_qxl_io_log_semaphore"
1751 */
1752 if (true) {
1753#else
Peter Maydelld4aceb22020-01-20 15:11:42 +00001754 if (trace_event_get_state_backends(TRACE_QXL_IO_LOG) || d->guestdebug) {
Gerd Hoffmannd97df4b2020-07-20 12:03:50 +02001755#endif
Daniel P. Berrangé00f42692019-01-23 12:00:13 +00001756 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1757 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1758 sizeof(d->ram->log_buf));
1759 trace_qxl_io_log(d->id, log_buf);
1760 if (d->guestdebug) {
1761 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1762 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1763 }
1764 g_free(log_buf);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001765 }
1766 break;
1767 case QXL_IO_RESET:
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001768 qxl_hard_reset(d, 0);
1769 break;
1770 case QXL_IO_MEMSLOT_ADD:
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001771 if (val >= NUM_MEMSLOTS) {
Alon Levy0a530542012-05-24 12:38:12 +03001772 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001773 break;
1774 }
1775 if (d->guest_slots[val].active) {
Alon Levy0a530542012-05-24 12:38:12 +03001776 qxl_set_guest_bug(d,
1777 "QXL_IO_MEMSLOT_ADD: memory slot already active");
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001778 break;
1779 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001780 d->guest_slots[val].slot = d->ram->mem_slot;
Alon Levy5ff4e362011-07-20 12:20:58 +03001781 qxl_add_memslot(d, val, 0, async);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001782 break;
1783 case QXL_IO_MEMSLOT_DEL:
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001784 if (val >= NUM_MEMSLOTS) {
Alon Levy0a530542012-05-24 12:38:12 +03001785 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001786 break;
1787 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001788 qxl_del_memslot(d, val);
1789 break;
1790 case QXL_IO_CREATE_PRIMARY:
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001791 if (val != 0) {
Alon Levy0a530542012-05-24 12:38:12 +03001792 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
Alon Levy5ff4e362011-07-20 12:20:58 +03001793 async);
1794 goto cancel_async;
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001795 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001796 d->guest_primary.surface = d->ram->create_surface;
Alon Levy5ff4e362011-07-20 12:20:58 +03001797 qxl_create_guest_primary(d, 0, async);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001798 break;
1799 case QXL_IO_DESTROY_PRIMARY:
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001800 if (val != 0) {
Alon Levy0a530542012-05-24 12:38:12 +03001801 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
Alon Levy5ff4e362011-07-20 12:20:58 +03001802 async);
1803 goto cancel_async;
Gerd Hoffmann2bce0402011-07-20 12:20:55 +03001804 }
Alon Levy5ff4e362011-07-20 12:20:58 +03001805 if (!qxl_destroy_primary(d, async)) {
Alon Levyc480bb72012-03-18 13:46:14 +01001806 trace_qxl_io_destroy_primary_ignored(d->id,
1807 qxl_mode_to_string(d->mode));
Alon Levy5ff4e362011-07-20 12:20:58 +03001808 goto cancel_async;
1809 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001810 break;
1811 case QXL_IO_DESTROY_SURFACE_WAIT:
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02001812 if (val >= d->ssd.num_surfaces) {
Alon Levy0a530542012-05-24 12:38:12 +03001813 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
Stefan Weil5f8daf22012-04-01 22:07:30 +02001814 "%" PRIu64 " >= NUM_SURFACES", async, val);
Alon Levy5ff4e362011-07-20 12:20:58 +03001815 goto cancel_async;
1816 }
1817 qxl_spice_destroy_surface_wait(d, val, async);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001818 break;
Alon Levy3e16b9c2011-07-20 12:20:59 +03001819 case QXL_IO_FLUSH_RELEASE: {
1820 QXLReleaseRing *ring = &d->ram->release_ring;
1821 if (ring->prod - ring->cons + 1 == ring->num_items) {
1822 fprintf(stderr,
1823 "ERROR: no flush, full release ring [p%d,%dc]\n",
1824 ring->prod, ring->cons);
1825 }
1826 qxl_push_free_res(d, 1 /* flush */);
Alon Levy3e16b9c2011-07-20 12:20:59 +03001827 break;
1828 }
1829 case QXL_IO_FLUSH_SURFACES_ASYNC:
Alon Levy3e16b9c2011-07-20 12:20:59 +03001830 qxl_spice_flush_surfaces_async(d);
1831 break;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001832 case QXL_IO_DESTROY_ALL_SURFACES:
Alon Levy5ff4e362011-07-20 12:20:58 +03001833 d->mode = QXL_MODE_UNDEFINED;
1834 qxl_spice_destroy_surfaces(d, async);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001835 break;
Alon Levy020af1c2012-08-22 11:16:25 +03001836 case QXL_IO_MONITORS_CONFIG_ASYNC:
1837 qxl_spice_monitors_config_async(d, 0);
1838 break;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001839 default:
Alon Levy0a530542012-05-24 12:38:12 +03001840 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001841 }
Alon Levy5ff4e362011-07-20 12:20:58 +03001842 return;
1843cancel_async:
Alon Levy5ff4e362011-07-20 12:20:58 +03001844 if (async) {
1845 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1846 qemu_mutex_lock(&d->async_lock);
1847 d->current_async = QXL_UNDEFINED_IO;
1848 qemu_mutex_unlock(&d->async_lock);
1849 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001850}
1851
Avi Kivitya8170e52012-10-23 12:30:10 +02001852static uint64_t ioport_read(void *opaque, hwaddr addr,
Avi Kivityb1950432011-08-08 16:08:57 +03001853 unsigned size)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001854{
Alon Levy917ae082012-09-12 16:13:26 +03001855 PCIQXLDevice *qxl = opaque;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001856
Alon Levy917ae082012-09-12 16:13:26 +03001857 trace_qxl_io_read_unexpected(qxl->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001858 return 0xff;
1859}
1860
Avi Kivityb1950432011-08-08 16:08:57 +03001861static const MemoryRegionOps qxl_io_ops = {
1862 .read = ioport_read,
1863 .write = ioport_write,
1864 .valid = {
1865 .min_access_size = 1,
1866 .max_access_size = 1,
1867 },
1868};
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001869
Gerd Hoffmann4a46c992013-10-29 13:29:43 +01001870static void qxl_update_irq_bh(void *opaque)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001871{
1872 PCIQXLDevice *d = opaque;
Yonit Halperin40010ae2011-09-05 08:45:59 +03001873 qxl_update_irq(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001874}
1875
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001876static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1877{
1878 uint32_t old_pending;
1879 uint32_t le_events = cpu_to_le32(events);
1880
Alon Levy917ae082012-09-12 16:13:26 +03001881 trace_qxl_send_events(d->id, events);
Alon Levy511aefb2012-11-01 14:56:00 +02001882 if (!qemu_spice_display_is_running(&d->ssd)) {
1883 /* spice-server tracks guest running state and should not do this */
1884 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1885 __func__);
1886 trace_qxl_send_events_vm_stopped(d->id, events);
1887 return;
1888 }
Peter Maydell5a358b32018-09-27 16:55:38 +01001889 /*
1890 * Older versions of Spice forgot to define the QXLRam struct
1891 * with the '__aligned__(4)' attribute. clang 7 and newer will
Stefan Hajnoczid73415a2020-09-23 11:56:46 +01001892 * thus warn that qatomic_fetch_or(&d->ram->int_pending, ...)
Peter Maydell5a358b32018-09-27 16:55:38 +01001893 * might be a misaligned atomic access, and will generate an
1894 * out-of-line call for it, which results in a link error since
1895 * we don't currently link against libatomic.
1896 *
1897 * In fact we set up d->ram in init_qxl_ram() so it always starts
1898 * at a 4K boundary, so we know that &d->ram->int_pending is
1899 * naturally aligned for a uint32_t. Newer Spice versions
1900 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1901 * will fix the bug directly. To deal with older versions,
1902 * we tell the compiler to assume the address really is aligned.
1903 * Any compiler which cares about the misalignment will have
1904 * __builtin_assume_aligned.
1905 */
1906#ifdef HAS_ASSUME_ALIGNED
1907#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1908#else
1909#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1910#endif
1911
Stefan Hajnoczid73415a2020-09-23 11:56:46 +01001912 old_pending = qatomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
Peter Maydell5a358b32018-09-27 16:55:38 +01001913 le_events);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001914 if ((old_pending & le_events) == le_events) {
1915 return;
1916 }
Gerd Hoffmann4a46c992013-10-29 13:29:43 +01001917 qemu_bh_schedule(d->update_irq);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001918}
1919
1920/* graphics console */
1921
1922static void qxl_hw_update(void *opaque)
1923{
1924 PCIQXLDevice *qxl = opaque;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001925
Gerd Hoffmann15162332014-09-24 17:05:45 +02001926 qxl_render_update(qxl);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001927}
1928
Gerd Hoffmann1331eab2016-06-22 14:07:24 +02001929static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1930 uint32_t height, int32_t stride)
1931{
Gerd Hoffmanne0127d22016-07-13 14:33:06 +02001932 uint64_t offset, size;
1933 uint32_t slot;
Gerd Hoffmann1331eab2016-06-22 14:07:24 +02001934 bool rc;
1935
1936 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1937 assert(rc == true);
Gerd Hoffmanne0127d22016-07-13 14:33:06 +02001938 size = (uint64_t)height * abs(stride);
1939 trace_qxl_surfaces_dirty(qxl->id, offset, size);
Gerd Hoffmann1331eab2016-06-22 14:07:24 +02001940 qxl_set_dirty(qxl->guest_slots[slot].mr,
Gerd Hoffmanne0127d22016-07-13 14:33:06 +02001941 qxl->guest_slots[slot].offset + offset,
1942 qxl->guest_slots[slot].offset + offset + size);
Gerd Hoffmann1331eab2016-06-22 14:07:24 +02001943}
1944
Yonit Halperine25139b2012-02-15 11:22:15 +02001945static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1946{
Yonit Halperine25139b2012-02-15 11:22:15 +02001947 int i;
1948
Yonit Halperin2aa9e852012-02-15 11:22:16 +02001949 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
Yonit Halperine25139b2012-02-15 11:22:15 +02001950 return;
1951 }
1952
1953 /* dirty the primary surface */
Gerd Hoffmann1331eab2016-06-22 14:07:24 +02001954 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1955 qxl->guest_primary.surface.height,
1956 qxl->guest_primary.surface.stride);
Yonit Halperine25139b2012-02-15 11:22:15 +02001957
1958 /* dirty the off-screen surfaces */
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02001959 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
Yonit Halperine25139b2012-02-15 11:22:15 +02001960 QXLSurfaceCmd *cmd;
Yonit Halperine25139b2012-02-15 11:22:15 +02001961
1962 if (qxl->guest_surfaces.cmds[i] == 0) {
1963 continue;
1964 }
1965
1966 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1967 MEMSLOT_GROUP_GUEST);
Alon Levyfae2afb2012-04-25 12:13:18 +03001968 assert(cmd);
Yonit Halperine25139b2012-02-15 11:22:15 +02001969 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
Gerd Hoffmann1331eab2016-06-22 14:07:24 +02001970 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1971 cmd->u.surface_create.height,
1972 cmd->u.surface_create.stride);
Yonit Halperine25139b2012-02-15 11:22:15 +02001973 }
1974}
1975
Philippe Mathieu-Daudé538f0492021-01-11 16:20:20 +01001976static void qxl_vm_change_state_handler(void *opaque, bool running,
Luiz Capitulino1dfb4dd2011-07-29 14:26:33 -03001977 RunState state)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001978{
1979 PCIQXLDevice *qxl = opaque;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001980
Yonit Halperinefbf2952011-09-05 08:45:58 +03001981 if (running) {
1982 /*
1983 * if qxl_send_events was called from spice server context before
Yonit Halperin40010ae2011-09-05 08:45:59 +03001984 * migration ended, qxl_update_irq for these events might not have been
Yonit Halperinefbf2952011-09-05 08:45:58 +03001985 * called
1986 */
Yonit Halperin40010ae2011-09-05 08:45:59 +03001987 qxl_update_irq(qxl);
Yonit Halperine25139b2012-02-15 11:22:15 +02001988 } else {
1989 /* make sure surfaces are saved before migration */
1990 qxl_dirty_surfaces(qxl);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001991 }
1992}
1993
1994/* display change listener */
1995
Gerd Hoffmann7c20b4a2012-11-13 14:51:41 +01001996static void display_update(DisplayChangeListener *dcl,
Gerd Hoffmann7c20b4a2012-11-13 14:51:41 +01001997 int x, int y, int w, int h)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02001998{
Gerd Hoffmannc6c06852013-02-28 12:15:00 +01001999 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2000
2001 if (qxl->mode == QXL_MODE_VGA) {
2002 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002003 }
2004}
2005
Gerd Hoffmannc12aeb82013-02-28 15:03:04 +01002006static void display_switch(DisplayChangeListener *dcl,
Gerd Hoffmannc12aeb82013-02-28 15:03:04 +01002007 struct DisplaySurface *surface)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002008{
Gerd Hoffmannc6c06852013-02-28 12:15:00 +01002009 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2010
Gerd Hoffmann71874c12013-02-28 16:42:28 +01002011 qxl->ssd.ds = surface;
Gerd Hoffmannc6c06852013-02-28 12:15:00 +01002012 if (qxl->mode == QXL_MODE_VGA) {
Gerd Hoffmannc12aeb82013-02-28 15:03:04 +01002013 qemu_spice_display_switch(&qxl->ssd, surface);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002014 }
2015}
2016
Gerd Hoffmannbc2ed972013-03-01 13:03:04 +01002017static void display_refresh(DisplayChangeListener *dcl)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002018{
Gerd Hoffmannc6c06852013-02-28 12:15:00 +01002019 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2020
2021 if (qxl->mode == QXL_MODE_VGA) {
2022 qemu_spice_display_refresh(&qxl->ssd);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002023 }
2024}
2025
Gerd Hoffmann7c20b4a2012-11-13 14:51:41 +01002026static DisplayChangeListenerOps display_listener_ops = {
2027 .dpy_name = "spice/qxl",
Gerd Hoffmanna93a4a22012-09-28 15:02:08 +02002028 .dpy_gfx_update = display_update,
Gerd Hoffmannc12aeb82013-02-28 15:03:04 +01002029 .dpy_gfx_switch = display_switch,
Gerd Hoffmann7c20b4a2012-11-13 14:51:41 +01002030 .dpy_refresh = display_refresh,
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002031};
2032
Alon Levy13d1fd42012-06-10 18:05:06 +03002033static void qxl_init_ramsize(PCIQXLDevice *qxl)
Gerd Hoffmanna9741922012-02-17 15:02:40 +01002034{
Alon Levy13d1fd42012-06-10 18:05:06 +03002035 /* vga mode framebuffer / primary surface (bar 0, first part) */
2036 if (qxl->vgamem_size_mb < 8) {
2037 qxl->vgamem_size_mb = 8;
2038 }
Radim Krčmář876d5162015-02-17 17:30:51 +01002039 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2040 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2041 */
2042 if (qxl->vgamem_size_mb > 256) {
2043 qxl->vgamem_size_mb = 256;
2044 }
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002045 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
Alon Levy13d1fd42012-06-10 18:05:06 +03002046
2047 /* vga ram (bar 0, total) */
Gerd Hoffmann017438e2012-02-17 15:03:24 +01002048 if (qxl->ram_size_mb != -1) {
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002049 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
Gerd Hoffmann017438e2012-02-17 15:03:24 +01002050 }
Alon Levy13d1fd42012-06-10 18:05:06 +03002051 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2052 qxl->vga.vram_size = qxl->vgamem_size * 2;
Gerd Hoffmanna9741922012-02-17 15:02:40 +01002053 }
2054
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02002055 /* vram32 (surfaces, 32bit, bar 1) */
2056 if (qxl->vram32_size_mb != -1) {
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002057 qxl->vram32_size = qxl->vram32_size_mb * MiB;
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02002058 }
2059 if (qxl->vram32_size < 4096) {
2060 qxl->vram32_size = 4096;
2061 }
2062
2063 /* vram (surfaces, 64bit, bar 4+5) */
Gerd Hoffmann017438e2012-02-17 15:03:24 +01002064 if (qxl->vram_size_mb != -1) {
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002065 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
Gerd Hoffmann017438e2012-02-17 15:03:24 +01002066 }
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02002067 if (qxl->vram_size < qxl->vram32_size) {
2068 qxl->vram_size = qxl->vram32_size;
Gerd Hoffmanna9741922012-02-17 15:02:40 +01002069 }
2070
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02002071 if (qxl->revision == 1) {
2072 qxl->vram32_size = 4096;
2073 qxl->vram_size = 4096;
2074 }
Radim Krčmářbb7443f2015-02-17 17:30:52 +01002075 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2076 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2077 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2078 qxl->vram_size = pow2ceil(qxl->vram_size);
Gerd Hoffmanna9741922012-02-17 15:02:40 +01002079}
2080
Markus Armbruster042a24d2015-01-19 15:52:36 +01002081static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002082{
2083 uint8_t* config = qxl->pci.config;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002084 uint32_t pci_device_rev;
2085 uint32_t io_size;
2086
Paolo Bonzini47025a02017-08-15 01:15:52 +02002087 qemu_spice_display_init_common(&qxl->ssd);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002088 qxl->mode = QXL_MODE_UNDEFINED;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002089 qxl->num_memslots = NUM_MEMSLOTS;
Gerd Hoffmann14898cf2011-07-20 12:20:53 +03002090 qemu_mutex_init(&qxl->track_lock);
Alon Levy5ff4e362011-07-20 12:20:58 +03002091 qemu_mutex_init(&qxl->async_lock);
2092 qxl->current_async = QXL_UNDEFINED_IO;
Alon Levy087e6a42012-05-24 19:18:54 +03002093 qxl->guest_bug = 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002094
2095 switch (qxl->revision) {
2096 case 1: /* spice 0.4 -- qxl-1 */
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002097 pci_device_rev = QXL_REVISION_STABLE_V04;
Uri Lublin3f6297b2012-05-10 16:24:53 +03002098 io_size = 8;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002099 break;
2100 case 2: /* spice 0.6 -- qxl-2 */
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002101 pci_device_rev = QXL_REVISION_STABLE_V06;
Uri Lublin3f6297b2012-05-10 16:24:53 +03002102 io_size = 16;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002103 break;
Gerd Hoffmann9197a7c2011-07-20 12:21:00 +03002104 case 3: /* qxl-3 */
Alon Levy020af1c2012-08-22 11:16:25 +03002105 pci_device_rev = QXL_REVISION_STABLE_V10;
2106 io_size = 32; /* PCI region size must be pow2 */
2107 break;
Alon Levy020af1c2012-08-22 11:16:25 +03002108 case 4: /* qxl-4 */
2109 pci_device_rev = QXL_REVISION_STABLE_V12;
Radim Krčmářbb7443f2015-02-17 17:30:52 +01002110 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
Gerd Hoffmann9197a7c2011-07-20 12:21:00 +03002111 break;
Gerd Hoffmanned71c092020-02-06 08:43:58 +01002112 case 5: /* qxl-5 */
2113 pci_device_rev = QXL_REVISION_STABLE_V12 + 1;
2114 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2115 break;
Alon Levy36839d32012-08-21 13:51:32 +03002116 default:
Markus Armbruster042a24d2015-01-19 15:52:36 +01002117 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2118 qxl->revision, QXL_DEFAULT_REVISION);
2119 return;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002120 }
2121
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002122 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2123 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2124
2125 qxl->rom_size = qxl_rom_size();
Gerd Hoffmann44b5c1e2020-02-25 06:59:19 +01002126 memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +02002127 qxl->rom_size, &error_fatal);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002128 init_qxl_rom(qxl);
2129 init_qxl_ram(qxl);
2130
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02002131 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
Peter Maydellce66d772017-07-07 15:42:56 +01002132 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +02002133 qxl->vram_size, &error_fatal);
Paolo Bonzini3eadad52013-06-06 21:25:08 -04002134 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2135 &qxl->vram_bar, 0, qxl->vram32_size);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002136
Paolo Bonzini3eadad52013-06-06 21:25:08 -04002137 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
Avi Kivityb1950432011-08-08 16:08:57 +03002138 "qxl-ioports", io_size);
Gerd Hoffmann60e94e42018-10-12 13:45:40 +02002139 if (qxl->have_vga) {
Avi Kivityb1950432011-08-08 16:08:57 +03002140 vga_dirty_log_start(&qxl->vga);
2141 }
Jan Kiszkabd8f2f52012-08-23 13:02:33 +02002142 memory_region_set_flush_coalesced(&qxl->io_bar);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002143
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002144
Avi Kivitye824b2c2011-08-08 16:09:31 +03002145 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2146 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002147
Avi Kivitye824b2c2011-08-08 16:09:31 +03002148 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2149 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
Avi Kivityb1950432011-08-08 16:08:57 +03002150
Avi Kivitye824b2c2011-08-08 16:09:31 +03002151 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2152 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
Avi Kivityb1950432011-08-08 16:08:57 +03002153
Avi Kivitye824b2c2011-08-08 16:09:31 +03002154 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02002155 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2156
2157 if (qxl->vram32_size < qxl->vram_size) {
2158 /*
2159 * Make the 64bit vram bar show up only in case it is
2160 * configured to be larger than the 32bit vram bar.
2161 */
2162 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2163 PCI_BASE_ADDRESS_SPACE_MEMORY |
2164 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2165 PCI_BASE_ADDRESS_MEM_PREFETCH,
2166 &qxl->vram_bar);
2167 }
2168
2169 /* print pci bar details */
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002170 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
Gerd Hoffmann60e94e42018-10-12 13:45:40 +02002171 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002172 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2173 qxl->vram32_size / MiB);
2174 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2175 qxl->vram_size / MiB,
Gerd Hoffmann6f2b1752011-10-14 18:05:48 +02002176 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002177
2178 qxl->ssd.qxl.base.sif = &qxl_interface.base;
Gerd Hoffmann9fa03282013-10-11 22:39:59 +02002179 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
Markus Armbruster042a24d2015-01-19 15:52:36 +01002180 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2181 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2182 return;
Alon Levye25a0652012-10-03 20:13:58 +02002183 }
Lukáš Hrázkýbe812c02019-02-15 16:09:19 +01002184
2185#if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
Marc-André Lureauf6ef71b2021-02-15 15:10:36 +04002186 Error *err = NULL;
Lukáš Hrázkýbe812c02019-02-15 16:09:19 +01002187 char device_address[256] = "";
Marc-André Lureauf6ef71b2021-02-15 15:10:36 +04002188 if (qemu_console_fill_device_address(qxl->vga.con,
2189 device_address, sizeof(device_address),
2190 &err)) {
Lukáš Hrázkýbe812c02019-02-15 16:09:19 +01002191 spice_qxl_set_device_info(&qxl->ssd.qxl,
2192 device_address,
2193 0,
2194 qxl->max_outputs);
Marc-André Lureauf6ef71b2021-02-15 15:10:36 +04002195 } else {
2196 error_report_err(err);
Lukáš Hrázkýbe812c02019-02-15 16:09:19 +01002197 }
2198#endif
2199
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002200 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2201
Gerd Hoffmann4a46c992013-10-29 13:29:43 +01002202 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002203 qxl_reset_state(qxl);
2204
Alon Levy81fb6f12012-02-24 23:19:31 +02002205 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
Gerd Hoffmann0b2824e2014-11-04 13:59:59 +01002206 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002207}
2208
Markus Armbruster042a24d2015-01-19 15:52:36 +01002209static void qxl_realize_primary(PCIDevice *dev, Error **errp)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002210{
Gongleic69f6c72015-05-12 17:27:10 +08002211 PCIQXLDevice *qxl = PCI_QXL(dev);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002212 VGACommonState *vga = &qxl->vga;
Markus Armbruster042a24d2015-01-19 15:52:36 +01002213 Error *local_err = NULL;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002214
Alon Levy13d1fd42012-06-10 18:05:06 +03002215 qxl_init_ramsize(qxl);
Gerd Hoffmann54a85d42014-08-26 14:16:30 +02002216 vga->vbe_size = qxl->vgamem_size;
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002217 vga->vram_size_mb = qxl->vga.vram_size / MiB;
Gerd Hoffmann1fcfdc42018-07-02 18:33:44 +02002218 vga_common_init(vga, OBJECT(dev));
Paolo Bonzini712f0cc2013-06-06 21:21:13 -04002219 vga_init(vga, OBJECT(dev),
2220 pci_address_space(dev), pci_address_space_io(dev), false);
Kirill Batuzov848696b2014-04-29 17:38:39 +04002221 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
Paolo Bonzinidb10ca92013-06-06 21:19:53 -04002222 vga, "vga");
Kirill Batuzov848696b2014-04-29 17:38:39 +04002223 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2224 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
Gerd Hoffmann60e94e42018-10-12 13:45:40 +02002225 qxl->have_vga = true;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002226
Gerd Hoffmann56437062014-01-24 15:35:21 +01002227 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
Gerd Hoffmann60e94e42018-10-12 13:45:40 +02002228 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2229 if (qxl->id != 0) {
2230 error_setg(errp, "primary qxl-vga device must be console 0 "
2231 "(first display device on the command line)");
2232 return;
2233 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002234
Markus Armbruster042a24d2015-01-19 15:52:36 +01002235 qxl_realize_common(qxl, &local_err);
2236 if (local_err) {
2237 error_propagate(errp, local_err);
2238 return;
Gerd Hoffmannbdd4df32012-11-02 09:37:27 +01002239 }
2240
Gerd Hoffmann7c20b4a2012-11-13 14:51:41 +01002241 qxl->ssd.dcl.ops = &display_listener_ops;
Gerd Hoffmann284d1c62013-03-15 15:45:54 +01002242 qxl->ssd.dcl.con = vga->con;
Gerd Hoffmann52090892013-04-23 15:44:31 +02002243 register_displaychangelistener(&qxl->ssd.dcl);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002244}
2245
Markus Armbruster042a24d2015-01-19 15:52:36 +01002246static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002247{
Gongleic69f6c72015-05-12 17:27:10 +08002248 PCIQXLDevice *qxl = PCI_QXL(dev);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002249
Alon Levy13d1fd42012-06-10 18:05:06 +03002250 qxl_init_ramsize(qxl);
Peter Maydellce66d772017-07-07 15:42:56 +01002251 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +02002252 qxl->vga.vram_size, &error_fatal);
Avi Kivityb1950432011-08-08 16:08:57 +03002253 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
Gerd Hoffmann56437062014-01-24 15:35:21 +01002254 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
Marc-André Lureauc5027582021-02-02 00:14:21 +04002255 qxl->ssd.dcl.con = qxl->vga.con;
Gerd Hoffmann60e94e42018-10-12 13:45:40 +02002256 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002257
Markus Armbruster042a24d2015-01-19 15:52:36 +01002258 qxl_realize_common(qxl, errp);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002259}
2260
Dr. David Alan Gilbert44b1ff32017-09-25 12:29:12 +01002261static int qxl_pre_save(void *opaque)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002262{
2263 PCIQXLDevice* d = opaque;
2264 uint8_t *ram_start = d->vga.vram_ptr;
2265
Alon Levyc480bb72012-03-18 13:46:14 +01002266 trace_qxl_pre_save(d->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002267 if (d->last_release == NULL) {
2268 d->last_release_offset = 0;
2269 } else {
2270 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2271 }
Gerd Hoffmanneb948462021-09-10 11:42:03 +02002272 if (d->last_release_offset >= d->vga.vram_size) {
Gerd Hoffmann39b8a182021-07-21 11:33:46 +02002273 return 1;
2274 }
Dr. David Alan Gilbert44b1ff32017-09-25 12:29:12 +01002275
2276 return 0;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002277}
2278
2279static int qxl_pre_load(void *opaque)
2280{
2281 PCIQXLDevice* d = opaque;
2282
Alon Levyc480bb72012-03-18 13:46:14 +01002283 trace_qxl_pre_load(d->id);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002284 qxl_hard_reset(d, 1);
2285 qxl_exit_vga_mode(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002286 return 0;
2287}
2288
Alon Levy54825d22011-10-25 15:39:50 +02002289static void qxl_create_memslots(PCIQXLDevice *d)
2290{
2291 int i;
2292
2293 for (i = 0; i < NUM_MEMSLOTS; i++) {
2294 if (!d->guest_slots[i].active) {
2295 continue;
2296 }
Alon Levy54825d22011-10-25 15:39:50 +02002297 qxl_add_memslot(d, i, 0, QXL_SYNC);
2298 }
2299}
2300
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002301static int qxl_post_load(void *opaque, int version)
2302{
2303 PCIQXLDevice* d = opaque;
2304 uint8_t *ram_start = d->vga.vram_ptr;
2305 QXLCommandExt *cmds;
Alon Levy54825d22011-10-25 15:39:50 +02002306 int in, out, newmode;
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002307
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002308 assert(d->last_release_offset < d->vga.vram_size);
2309 if (d->last_release_offset == 0) {
2310 d->last_release = NULL;
2311 } else {
2312 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2313 }
2314
2315 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2316
Alon Levyc480bb72012-03-18 13:46:14 +01002317 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002318 newmode = d->mode;
2319 d->mode = QXL_MODE_UNDEFINED;
Alon Levy54825d22011-10-25 15:39:50 +02002320
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002321 switch (newmode) {
2322 case QXL_MODE_UNDEFINED:
Yonit Halperinfa98efe2012-11-28 10:08:22 -05002323 qxl_create_memslots(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002324 break;
2325 case QXL_MODE_VGA:
Alon Levy54825d22011-10-25 15:39:50 +02002326 qxl_create_memslots(d);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002327 qxl_enter_vga_mode(d);
2328 break;
2329 case QXL_MODE_NATIVE:
Alon Levy54825d22011-10-25 15:39:50 +02002330 qxl_create_memslots(d);
Alon Levy5ff4e362011-07-20 12:20:58 +03002331 qxl_create_guest_primary(d, 1, QXL_SYNC);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002332
2333 /* replay surface-create and cursor-set commands */
Markus Armbruster9de68632015-10-29 16:55:21 +01002334 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02002335 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002336 if (d->guest_surfaces.cmds[in] == 0) {
2337 continue;
2338 }
2339 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2340 cmds[out].cmd.type = QXL_CMD_SURFACE;
2341 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2342 out++;
2343 }
Yonit Halperin30f6da62011-10-18 18:58:54 +02002344 if (d->guest_cursor) {
2345 cmds[out].cmd.data = d->guest_cursor;
2346 cmds[out].cmd.type = QXL_CMD_CURSOR;
2347 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2348 out++;
2349 }
Gerd Hoffmannaee32bf2011-07-20 12:20:52 +03002350 qxl_spice_loadvm_commands(d, cmds, out);
Anthony Liguori7267c092011-08-20 22:09:37 -05002351 g_free(cmds);
Alon Levy020af1c2012-08-22 11:16:25 +03002352 if (d->guest_monitors_config) {
2353 qxl_spice_monitors_config_async(d, 1);
2354 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002355 break;
2356 case QXL_MODE_COMPAT:
Alon Levy54825d22011-10-25 15:39:50 +02002357 /* note: no need to call qxl_create_memslots, qxl_set_mode
2358 * creates the mem slot. */
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002359 qxl_set_mode(d, d->shadow_rom.mode, 1);
2360 break;
2361 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002362 return 0;
2363}
2364
Gerd Hoffmannb67737a2011-01-05 18:05:52 +01002365#define QXL_SAVE_VERSION 21
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002366
Alon Levy020af1c2012-08-22 11:16:25 +03002367static bool qxl_monitors_config_needed(void *opaque)
2368{
2369 PCIQXLDevice *qxl = opaque;
2370
2371 return qxl->guest_monitors_config != 0;
2372}
2373
2374
Philippe Mathieu-Daudé54cbf292021-03-13 18:11:49 +01002375static const VMStateDescription qxl_memslot = {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002376 .name = "qxl-memslot",
2377 .version_id = QXL_SAVE_VERSION,
2378 .minimum_version_id = QXL_SAVE_VERSION,
2379 .fields = (VMStateField[]) {
2380 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2381 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2382 VMSTATE_UINT32(active, struct guest_slots),
2383 VMSTATE_END_OF_LIST()
2384 }
2385};
2386
Philippe Mathieu-Daudé54cbf292021-03-13 18:11:49 +01002387static const VMStateDescription qxl_surface = {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002388 .name = "qxl-surface",
2389 .version_id = QXL_SAVE_VERSION,
2390 .minimum_version_id = QXL_SAVE_VERSION,
2391 .fields = (VMStateField[]) {
2392 VMSTATE_UINT32(width, QXLSurfaceCreate),
2393 VMSTATE_UINT32(height, QXLSurfaceCreate),
2394 VMSTATE_INT32(stride, QXLSurfaceCreate),
2395 VMSTATE_UINT32(format, QXLSurfaceCreate),
2396 VMSTATE_UINT32(position, QXLSurfaceCreate),
2397 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2398 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2399 VMSTATE_UINT32(type, QXLSurfaceCreate),
2400 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2401 VMSTATE_END_OF_LIST()
2402 }
2403};
2404
Philippe Mathieu-Daudé54cbf292021-03-13 18:11:49 +01002405static const VMStateDescription qxl_vmstate_monitors_config = {
Alon Levy020af1c2012-08-22 11:16:25 +03002406 .name = "qxl/monitors-config",
2407 .version_id = 1,
2408 .minimum_version_id = 1,
Juan Quintela5cd8cad2014-09-23 14:09:54 +02002409 .needed = qxl_monitors_config_needed,
Alon Levy020af1c2012-08-22 11:16:25 +03002410 .fields = (VMStateField[]) {
2411 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2412 VMSTATE_END_OF_LIST()
2413 },
2414};
2415
Philippe Mathieu-Daudé54cbf292021-03-13 18:11:49 +01002416static const VMStateDescription qxl_vmstate = {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002417 .name = "qxl",
2418 .version_id = QXL_SAVE_VERSION,
2419 .minimum_version_id = QXL_SAVE_VERSION,
2420 .pre_save = qxl_pre_save,
2421 .pre_load = qxl_pre_load,
2422 .post_load = qxl_post_load,
Alon Levy020af1c2012-08-22 11:16:25 +03002423 .fields = (VMStateField[]) {
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002424 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2425 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2426 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2427 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2428 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2429 VMSTATE_UINT32(mode, PCIQXLDevice),
2430 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
Halil Pasicd2164ad2017-06-23 16:48:23 +02002431 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
Gerd Hoffmannb67737a2011-01-05 18:05:52 +01002432 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2433 qxl_memslot, struct guest_slots),
2434 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2435 qxl_surface, QXLSurfaceCreate),
Halil Pasicd2164ad2017-06-23 16:48:23 +02002436 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02002437 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2438 ssd.num_surfaces, 0,
2439 vmstate_info_uint64, uint64_t),
Gerd Hoffmannb67737a2011-01-05 18:05:52 +01002440 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002441 VMSTATE_END_OF_LIST()
2442 },
Juan Quintela5cd8cad2014-09-23 14:09:54 +02002443 .subsections = (const VMStateDescription*[]) {
2444 &qxl_vmstate_monitors_config,
2445 NULL
Alon Levy020af1c2012-08-22 11:16:25 +03002446 }
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002447};
2448
Gerd Hoffmann78e60ba2011-10-17 14:11:16 +02002449static Property qxl_properties[] = {
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -03002450 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2451 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
Gerd Hoffmann78e60ba2011-10-17 14:11:16 +02002452 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2453 QXL_DEFAULT_REVISION),
2454 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2455 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2456 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
Gerd Hoffmann017438e2012-02-17 15:03:24 +01002457 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
Alon Levy79ce3562012-03-29 22:24:38 +02002458 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2459 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
Gerd Hoffmann9e56edc2012-06-11 10:42:53 +02002460 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
Gerd Hoffmannddd8fdc2012-09-04 11:39:41 +02002461 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
Frediano Ziglio567161f2015-07-06 07:56:38 +01002462#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2463 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2464#endif
Gerd Hoffmann6f663d72017-04-21 11:22:34 +02002465 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2466 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
Gerd Hoffmann1fcfdc42018-07-02 18:33:44 +02002467 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
Gerd Hoffmann78e60ba2011-10-17 14:11:16 +02002468 DEFINE_PROP_END_OF_LIST(),
2469};
2470
Gongleic69f6c72015-05-12 17:27:10 +08002471static void qxl_pci_class_init(ObjectClass *klass, void *data)
2472{
2473 DeviceClass *dc = DEVICE_CLASS(klass);
2474 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2475
2476 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2477 k->device_id = QXL_DEVICE_ID_STABLE;
2478 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2479 dc->reset = qxl_reset_handler;
2480 dc->vmsd = &qxl_vmstate;
Marc-André Lureau4f67d302020-01-10 19:30:32 +04002481 device_class_set_props(dc, qxl_properties);
Gongleic69f6c72015-05-12 17:27:10 +08002482}
2483
2484static const TypeInfo qxl_pci_type_info = {
2485 .name = TYPE_PCI_QXL,
2486 .parent = TYPE_PCI_DEVICE,
2487 .instance_size = sizeof(PCIQXLDevice),
2488 .abstract = true,
2489 .class_init = qxl_pci_class_init,
Eduardo Habkostfd3b02c2017-09-27 16:56:34 -03002490 .interfaces = (InterfaceInfo[]) {
2491 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2492 { },
2493 },
Gongleic69f6c72015-05-12 17:27:10 +08002494};
2495
Anthony Liguori40021f02011-12-04 12:22:06 -06002496static void qxl_primary_class_init(ObjectClass *klass, void *data)
2497{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002498 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06002499 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2500
Markus Armbruster042a24d2015-01-19 15:52:36 +01002501 k->realize = qxl_realize_primary;
Anthony Liguori40021f02011-12-04 12:22:06 -06002502 k->romfile = "vgabios-qxl.bin";
Anthony Liguori40021f02011-12-04 12:22:06 -06002503 k->class_id = PCI_CLASS_DISPLAY_VGA;
Anthony Liguori39bffca2011-12-07 21:34:16 -06002504 dc->desc = "Spice QXL GPU (primary, vga compatible)";
Igor Mammedov2897ae02014-02-05 16:36:48 +01002505 dc->hotpluggable = false;
Anthony Liguori40021f02011-12-04 12:22:06 -06002506}
2507
Andreas Färber8c43a6f2013-01-10 16:19:07 +01002508static const TypeInfo qxl_primary_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -06002509 .name = "qxl-vga",
Gongleic69f6c72015-05-12 17:27:10 +08002510 .parent = TYPE_PCI_QXL,
Anthony Liguori39bffca2011-12-07 21:34:16 -06002511 .class_init = qxl_primary_class_init,
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002512};
Gerd Hoffmannec604e02021-06-24 12:38:07 +02002513module_obj("qxl-vga");
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002514
Anthony Liguori40021f02011-12-04 12:22:06 -06002515static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2516{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002517 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06002518 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2519
Markus Armbruster042a24d2015-01-19 15:52:36 +01002520 k->realize = qxl_realize_secondary;
Anthony Liguori40021f02011-12-04 12:22:06 -06002521 k->class_id = PCI_CLASS_DISPLAY_OTHER;
Anthony Liguori39bffca2011-12-07 21:34:16 -06002522 dc->desc = "Spice QXL GPU (secondary)";
Anthony Liguori40021f02011-12-04 12:22:06 -06002523}
2524
Andreas Färber8c43a6f2013-01-10 16:19:07 +01002525static const TypeInfo qxl_secondary_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -06002526 .name = "qxl",
Gongleic69f6c72015-05-12 17:27:10 +08002527 .parent = TYPE_PCI_QXL,
Anthony Liguori39bffca2011-12-07 21:34:16 -06002528 .class_init = qxl_secondary_class_init,
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002529};
Gerd Hoffmannec604e02021-06-24 12:38:07 +02002530module_obj("qxl");
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002531
Andreas Färber83f7d432012-02-09 15:20:55 +01002532static void qxl_register_types(void)
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002533{
Gongleic69f6c72015-05-12 17:27:10 +08002534 type_register_static(&qxl_pci_type_info);
Anthony Liguori39bffca2011-12-07 21:34:16 -06002535 type_register_static(&qxl_primary_info);
2536 type_register_static(&qxl_secondary_info);
Gerd Hoffmanna19cbfb2010-04-27 11:50:11 +02002537}
2538
Andreas Färber83f7d432012-02-09 15:20:55 +01002539type_init(qxl_register_types)
Gerd Hoffmannec604e02021-06-24 12:38:07 +02002540
2541module_dep("ui-spice-core");