ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * MIPS emulation for qemu: CPU initialisation routines. |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
| 5 | * Copyright (c) 2007 Herve Poussineau |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 21 | /* CPU / CPU family specific config register values. */ |
| 22 | |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 23 | /* Have config1, uncached coherency */ |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 24 | #define MIPS_CONFIG0 \ |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 25 | ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 26 | |
ths | ae5d805 | 2007-07-29 22:11:46 +0000 | [diff] [blame] | 27 | /* Have config2, no coprocessor2 attached, no MDMX support attached, |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 28 | no performance counters, watch registers present, |
| 29 | no code compression, EJTAG present, no FPU */ |
| 30 | #define MIPS_CONFIG1 \ |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 31 | ((1U << CP0C1_M) | \ |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 32 | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
| 33 | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
| 34 | (0 << CP0C1_FP)) |
| 35 | |
| 36 | /* Have config3, no tertiary/secondary caches implemented */ |
| 37 | #define MIPS_CONFIG2 \ |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 38 | ((1U << CP0C2_M)) |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 39 | |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 40 | /* No config4, no DSP ASE, no large physaddr (PABITS), |
Stefan Weil | ff2712b | 2011-04-28 17:20:35 +0200 | [diff] [blame] | 41 | no external interrupt controller, no vectored interrupts, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 42 | no 1kb pages, no SmartMIPS ASE, no trace logic */ |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 43 | #define MIPS_CONFIG3 \ |
| 44 | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
| 45 | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 46 | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 47 | |
Petar Jovanovic | b4160af | 2014-01-24 13:45:05 +0100 | [diff] [blame] | 48 | #define MIPS_CONFIG4 \ |
| 49 | ((0 << CP0C4_M)) |
| 50 | |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 51 | #define MIPS_CONFIG5 \ |
| 52 | ((0 << CP0C5_M)) |
| 53 | |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 54 | /* MMU types, the first four entries have the same layout as the |
| 55 | CP0C0_MT field. */ |
| 56 | enum mips_mmu_types { |
| 57 | MMU_TYPE_NONE, |
| 58 | MMU_TYPE_R4000, |
| 59 | MMU_TYPE_RESERVED, |
| 60 | MMU_TYPE_FMT, |
| 61 | MMU_TYPE_R3000, |
| 62 | MMU_TYPE_R6000, |
| 63 | MMU_TYPE_R8000 |
| 64 | }; |
| 65 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 66 | struct mips_def_t { |
ths | 50366fe | 2008-07-20 19:13:19 +0000 | [diff] [blame] | 67 | const char *name; |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 68 | int32_t CP0_PRid; |
| 69 | int32_t CP0_Config0; |
| 70 | int32_t CP0_Config1; |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 71 | int32_t CP0_Config2; |
| 72 | int32_t CP0_Config3; |
Petar Jovanovic | b4160af | 2014-01-24 13:45:05 +0100 | [diff] [blame] | 73 | int32_t CP0_Config4; |
| 74 | int32_t CP0_Config4_rw_bitmask; |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 75 | int32_t CP0_Config5; |
| 76 | int32_t CP0_Config5_rw_bitmask; |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 77 | int32_t CP0_Config6; |
| 78 | int32_t CP0_Config7; |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 79 | target_ulong CP0_LLAddr_rw_bitmask; |
| 80 | int CP0_LLAddr_shift; |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 81 | int32_t SYNCI_Step; |
| 82 | int32_t CCRes; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 83 | int32_t CP0_Status_rw_bitmask; |
| 84 | int32_t CP0_TCStatus_rw_bitmask; |
| 85 | int32_t CP0_SRSCtl; |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 86 | int32_t CP1_fcr0; |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 87 | int32_t SEGBITS; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 88 | int32_t PABITS; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 89 | int32_t CP0_SRSConf0_rw_bitmask; |
| 90 | int32_t CP0_SRSConf0; |
| 91 | int32_t CP0_SRSConf1_rw_bitmask; |
| 92 | int32_t CP0_SRSConf1; |
| 93 | int32_t CP0_SRSConf2_rw_bitmask; |
| 94 | int32_t CP0_SRSConf2; |
| 95 | int32_t CP0_SRSConf3_rw_bitmask; |
| 96 | int32_t CP0_SRSConf3; |
| 97 | int32_t CP0_SRSConf4_rw_bitmask; |
| 98 | int32_t CP0_SRSConf4; |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 99 | int insn_flags; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 100 | enum mips_mmu_types mmu_type; |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 101 | }; |
| 102 | |
| 103 | /*****************************************************************************/ |
| 104 | /* MIPS CPU definitions */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 105 | static const mips_def_t mips_defs[] = |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 106 | { |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 107 | { |
| 108 | .name = "4Kc", |
| 109 | .CP0_PRid = 0x00018000, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 110 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | ae5d805 | 2007-07-29 22:11:46 +0000 | [diff] [blame] | 111 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 112 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 113 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
Stefan Weil | ab3aee2 | 2009-12-15 14:03:03 +0100 | [diff] [blame] | 114 | (0 << CP0C1_CA), |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 115 | .CP0_Config2 = MIPS_CONFIG2, |
| 116 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 117 | .CP0_LLAddr_rw_bitmask = 0, |
| 118 | .CP0_LLAddr_shift = 4, |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 119 | .SYNCI_Step = 32, |
| 120 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 121 | .CP0_Status_rw_bitmask = 0x1278FF17, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 122 | .SEGBITS = 32, |
| 123 | .PABITS = 32, |
Stefan Weil | 73642f5 | 2009-12-15 14:43:40 +0100 | [diff] [blame] | 124 | .insn_flags = CPU_MIPS32, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 125 | .mmu_type = MMU_TYPE_R4000, |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 126 | }, |
| 127 | { |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 128 | .name = "4Km", |
| 129 | .CP0_PRid = 0x00018300, |
| 130 | /* Config1 implemented, fixed mapping MMU, |
| 131 | no virtual icache, uncached coherency. */ |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 132 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 133 | .CP0_Config1 = MIPS_CONFIG1 | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 134 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 135 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 136 | (1 << CP0C1_CA), |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 137 | .CP0_Config2 = MIPS_CONFIG2, |
| 138 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 139 | .CP0_LLAddr_rw_bitmask = 0, |
| 140 | .CP0_LLAddr_shift = 4, |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 141 | .SYNCI_Step = 32, |
| 142 | .CCRes = 2, |
| 143 | .CP0_Status_rw_bitmask = 0x1258FF17, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 144 | .SEGBITS = 32, |
| 145 | .PABITS = 32, |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 146 | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 147 | .mmu_type = MMU_TYPE_FMT, |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 148 | }, |
| 149 | { |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 150 | .name = "4KEcR1", |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 151 | .CP0_PRid = 0x00018400, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 152 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | ae5d805 | 2007-07-29 22:11:46 +0000 | [diff] [blame] | 153 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 154 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 155 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
Stefan Weil | ab3aee2 | 2009-12-15 14:03:03 +0100 | [diff] [blame] | 156 | (0 << CP0C1_CA), |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 157 | .CP0_Config2 = MIPS_CONFIG2, |
| 158 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 159 | .CP0_LLAddr_rw_bitmask = 0, |
| 160 | .CP0_LLAddr_shift = 4, |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 161 | .SYNCI_Step = 32, |
| 162 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 163 | .CP0_Status_rw_bitmask = 0x1278FF17, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 164 | .SEGBITS = 32, |
| 165 | .PABITS = 32, |
Stefan Weil | 73642f5 | 2009-12-15 14:43:40 +0100 | [diff] [blame] | 166 | .insn_flags = CPU_MIPS32, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 167 | .mmu_type = MMU_TYPE_R4000, |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 168 | }, |
| 169 | { |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 170 | .name = "4KEmR1", |
| 171 | .CP0_PRid = 0x00018500, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 172 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 173 | .CP0_Config1 = MIPS_CONFIG1 | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 174 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 175 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 176 | (1 << CP0C1_CA), |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 177 | .CP0_Config2 = MIPS_CONFIG2, |
| 178 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 179 | .CP0_LLAddr_rw_bitmask = 0, |
| 180 | .CP0_LLAddr_shift = 4, |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 181 | .SYNCI_Step = 32, |
| 182 | .CCRes = 2, |
| 183 | .CP0_Status_rw_bitmask = 0x1258FF17, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 184 | .SEGBITS = 32, |
| 185 | .PABITS = 32, |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 186 | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 187 | .mmu_type = MMU_TYPE_FMT, |
ths | 8d162c2 | 2007-11-19 16:10:33 +0000 | [diff] [blame] | 188 | }, |
| 189 | { |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 190 | .name = "4KEc", |
| 191 | .CP0_PRid = 0x00019000, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 192 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 193 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | ae5d805 | 2007-07-29 22:11:46 +0000 | [diff] [blame] | 194 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 195 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 196 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
Stefan Weil | ab3aee2 | 2009-12-15 14:03:03 +0100 | [diff] [blame] | 197 | (0 << CP0C1_CA), |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 198 | .CP0_Config2 = MIPS_CONFIG2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 199 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 200 | .CP0_LLAddr_rw_bitmask = 0, |
| 201 | .CP0_LLAddr_shift = 4, |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 202 | .SYNCI_Step = 32, |
| 203 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 204 | .CP0_Status_rw_bitmask = 0x1278FF17, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 205 | .SEGBITS = 32, |
| 206 | .PABITS = 32, |
Stefan Weil | 73642f5 | 2009-12-15 14:43:40 +0100 | [diff] [blame] | 207 | .insn_flags = CPU_MIPS32R2, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 208 | .mmu_type = MMU_TYPE_R4000, |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 209 | }, |
| 210 | { |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 211 | .name = "4KEm", |
| 212 | .CP0_PRid = 0x00019100, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 213 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 214 | (MMU_TYPE_FMT << CP0C0_MT), |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 215 | .CP0_Config1 = MIPS_CONFIG1 | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 216 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 217 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 218 | (1 << CP0C1_CA), |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 219 | .CP0_Config2 = MIPS_CONFIG2, |
| 220 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 221 | .CP0_LLAddr_rw_bitmask = 0, |
| 222 | .CP0_LLAddr_shift = 4, |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 223 | .SYNCI_Step = 32, |
| 224 | .CCRes = 2, |
| 225 | .CP0_Status_rw_bitmask = 0x1258FF17, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 226 | .SEGBITS = 32, |
| 227 | .PABITS = 32, |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 228 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 229 | .mmu_type = MMU_TYPE_FMT, |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 230 | }, |
| 231 | { |
ths | 34ee2ed | 2007-03-24 23:36:18 +0000 | [diff] [blame] | 232 | .name = "24Kc", |
| 233 | .CP0_PRid = 0x00019300, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 234 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 235 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | ae5d805 | 2007-07-29 22:11:46 +0000 | [diff] [blame] | 236 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 237 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 238 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 239 | (1 << CP0C1_CA), |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 240 | .CP0_Config2 = MIPS_CONFIG2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 241 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 242 | .CP0_LLAddr_rw_bitmask = 0, |
| 243 | .CP0_LLAddr_shift = 4, |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 244 | .SYNCI_Step = 32, |
| 245 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 246 | /* No DSP implemented. */ |
ths | 671880e | 2007-09-29 19:21:36 +0000 | [diff] [blame] | 247 | .CP0_Status_rw_bitmask = 0x1278FF1F, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 248 | .SEGBITS = 32, |
| 249 | .PABITS = 32, |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 250 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 251 | .mmu_type = MMU_TYPE_R4000, |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 252 | }, |
| 253 | { |
| 254 | .name = "24Kf", |
| 255 | .CP0_PRid = 0x00019300, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 256 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 257 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | ae5d805 | 2007-07-29 22:11:46 +0000 | [diff] [blame] | 258 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 259 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 260 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 261 | (1 << CP0C1_CA), |
ths | 3953d78 | 2007-03-21 11:04:42 +0000 | [diff] [blame] | 262 | .CP0_Config2 = MIPS_CONFIG2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 263 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 264 | .CP0_LLAddr_rw_bitmask = 0, |
| 265 | .CP0_LLAddr_shift = 4, |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 266 | .SYNCI_Step = 32, |
| 267 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 268 | /* No DSP implemented. */ |
ths | 671880e | 2007-09-29 19:21:36 +0000 | [diff] [blame] | 269 | .CP0_Status_rw_bitmask = 0x3678FF1F, |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 270 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 271 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 272 | .SEGBITS = 32, |
| 273 | .PABITS = 32, |
ths | 3e4587d | 2007-11-14 03:11:17 +0000 | [diff] [blame] | 274 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 275 | .mmu_type = MMU_TYPE_R4000, |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 276 | }, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 277 | { |
| 278 | .name = "34Kf", |
| 279 | .CP0_PRid = 0x00019500, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 280 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 281 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 282 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 283 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
Nathan Froyd | d19954f | 2009-12-08 08:06:32 -0800 | [diff] [blame] | 284 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 285 | (1 << CP0C1_CA), |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 286 | .CP0_Config2 = MIPS_CONFIG2, |
Yongbok Kim | b9ac5d9 | 2013-08-02 10:33:43 +0100 | [diff] [blame] | 287 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | |
| 288 | (1 << CP0C3_DSPP), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 289 | .CP0_LLAddr_rw_bitmask = 0, |
| 290 | .CP0_LLAddr_shift = 0, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 291 | .SYNCI_Step = 32, |
| 292 | .CCRes = 2, |
Yongbok Kim | b9ac5d9 | 2013-08-02 10:33:43 +0100 | [diff] [blame] | 293 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 294 | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
| 295 | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
| 296 | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
| 297 | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
| 298 | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
| 299 | (0xff << CP0TCSt_TASID), |
| 300 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 301 | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
| 302 | .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), |
| 303 | .CP0_SRSConf0_rw_bitmask = 0x3fffffff, |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 304 | .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 305 | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
| 306 | .CP0_SRSConf1_rw_bitmask = 0x3fffffff, |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 307 | .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 308 | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
| 309 | .CP0_SRSConf2_rw_bitmask = 0x3fffffff, |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 310 | .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 311 | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
| 312 | .CP0_SRSConf3_rw_bitmask = 0x3fffffff, |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 313 | .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 314 | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
| 315 | .CP0_SRSConf4_rw_bitmask = 0x3fffffff, |
| 316 | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | |
| 317 | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 318 | .SEGBITS = 32, |
| 319 | .PABITS = 32, |
ths | 7385ac0 | 2007-10-23 17:04:27 +0000 | [diff] [blame] | 320 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 321 | .mmu_type = MMU_TYPE_R4000, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 322 | }, |
Jia Liu | af13ae0 | 2012-10-24 22:17:12 +0800 | [diff] [blame] | 323 | { |
| 324 | .name = "74Kf", |
| 325 | .CP0_PRid = 0x00019700, |
| 326 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 327 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 328 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 329 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 330 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 331 | (1 << CP0C1_CA), |
| 332 | .CP0_Config2 = MIPS_CONFIG2, |
| 333 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), |
| 334 | .CP0_LLAddr_rw_bitmask = 0, |
| 335 | .CP0_LLAddr_shift = 4, |
| 336 | .SYNCI_Step = 32, |
| 337 | .CCRes = 2, |
| 338 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
| 339 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 340 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
| 341 | .SEGBITS = 32, |
| 342 | .PABITS = 32, |
| 343 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, |
| 344 | .mmu_type = MMU_TYPE_R4000, |
| 345 | }, |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 346 | { |
| 347 | /* A generic CPU providing MIPS32 Release 5 features. |
| 348 | FIXME: Eventually this should be replaced by a real CPU model. */ |
| 349 | .name = "mips32r5-generic", |
| 350 | .CP0_PRid = 0x00019700, |
| 351 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 352 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 353 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 354 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 355 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 356 | (1 << CP0C1_CA), |
| 357 | .CP0_Config2 = MIPS_CONFIG2, |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 358 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), |
| 359 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), |
Petar Jovanovic | b4160af | 2014-01-24 13:45:05 +0100 | [diff] [blame] | 360 | .CP0_Config4_rw_bitmask = 0, |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 361 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 362 | .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | |
| 363 | (1 << CP0C5_CV) | (0 << CP0C5_EVA) | |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 364 | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) | |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 365 | (0 << CP0C5_NFExists), |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 366 | .CP0_LLAddr_rw_bitmask = 0, |
| 367 | .CP0_LLAddr_shift = 4, |
| 368 | .SYNCI_Step = 32, |
| 369 | .CCRes = 2, |
| 370 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 371 | .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | |
| 372 | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | |
| 373 | (0x93 << FCR0_PRID), |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 374 | .SEGBITS = 32, |
| 375 | .PABITS = 32, |
| 376 | .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, |
| 377 | .mmu_type = MMU_TYPE_R4000, |
| 378 | }, |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 379 | #if defined(TARGET_MIPS64) |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 380 | { |
| 381 | .name = "R4000", |
| 382 | .CP0_PRid = 0x00000400, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 383 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
| 384 | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 385 | /* Note: Config1 is only used internally, the R4000 has only Config0. */ |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 386 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 387 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, |
| 388 | .CP0_LLAddr_shift = 4, |
ths | 2f64454 | 2007-04-11 20:34:23 +0000 | [diff] [blame] | 389 | .SYNCI_Step = 16, |
| 390 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 391 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 392 | /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 393 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 394 | .SEGBITS = 40, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 395 | .PABITS = 36, |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 396 | .insn_flags = CPU_MIPS3, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 397 | .mmu_type = MMU_TYPE_R4000, |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 398 | }, |
| 399 | { |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 400 | .name = "VR5432", |
| 401 | .CP0_PRid = 0x00005400, |
| 402 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
| 403 | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
| 404 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 405 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, |
| 406 | .CP0_LLAddr_shift = 4, |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 407 | .SYNCI_Step = 16, |
| 408 | .CCRes = 2, |
| 409 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
| 410 | /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
| 411 | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 412 | .SEGBITS = 40, |
| 413 | .PABITS = 32, |
| 414 | .insn_flags = CPU_VR54XX, |
| 415 | .mmu_type = MMU_TYPE_R4000, |
| 416 | }, |
| 417 | { |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 418 | .name = "5Kc", |
| 419 | .CP0_PRid = 0x00018100, |
ths | 29fe0e3 | 2007-12-25 17:32:46 +0000 | [diff] [blame] | 420 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 421 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 422 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 423 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 424 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 425 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 426 | .CP0_Config2 = MIPS_CONFIG2, |
| 427 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 428 | .CP0_LLAddr_rw_bitmask = 0, |
| 429 | .CP0_LLAddr_shift = 4, |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 430 | .SYNCI_Step = 32, |
| 431 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 432 | .CP0_Status_rw_bitmask = 0x32F8FFFF, |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 433 | .SEGBITS = 42, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 434 | .PABITS = 36, |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 435 | .insn_flags = CPU_MIPS64, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 436 | .mmu_type = MMU_TYPE_R4000, |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 437 | }, |
| 438 | { |
| 439 | .name = "5Kf", |
| 440 | .CP0_PRid = 0x00018100, |
ths | 29fe0e3 | 2007-12-25 17:32:46 +0000 | [diff] [blame] | 441 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 442 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 443 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 444 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 445 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 446 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 447 | .CP0_Config2 = MIPS_CONFIG2, |
| 448 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 449 | .CP0_LLAddr_rw_bitmask = 0, |
| 450 | .CP0_LLAddr_shift = 4, |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 451 | .SYNCI_Step = 32, |
| 452 | .CCRes = 2, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 453 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 454 | /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 455 | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
| 456 | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 457 | .SEGBITS = 42, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 458 | .PABITS = 36, |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 459 | .insn_flags = CPU_MIPS64, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 460 | .mmu_type = MMU_TYPE_R4000, |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 461 | }, |
| 462 | { |
| 463 | .name = "20Kc", |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 464 | /* We emulate a later version of the 20Kc, earlier ones had a broken |
ths | bd04c6f | 2007-06-12 12:43:47 +0000 | [diff] [blame] | 465 | WAIT instruction. */ |
| 466 | .CP0_PRid = 0x000182a0, |
ths | 29fe0e3 | 2007-12-25 17:32:46 +0000 | [diff] [blame] | 467 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 468 | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 469 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 470 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 471 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 472 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 473 | .CP0_Config2 = MIPS_CONFIG2, |
| 474 | .CP0_Config3 = MIPS_CONFIG3, |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 475 | .CP0_LLAddr_rw_bitmask = 0, |
| 476 | .CP0_LLAddr_shift = 0, |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 477 | .SYNCI_Step = 32, |
ths | a1daafd | 2007-12-24 14:33:57 +0000 | [diff] [blame] | 478 | .CCRes = 1, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 479 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 480 | /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 481 | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 482 | (1 << FCR0_D) | (1 << FCR0_S) | |
ths | c9c1a06 | 2007-06-01 14:58:56 +0000 | [diff] [blame] | 483 | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 484 | .SEGBITS = 40, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 485 | .PABITS = 36, |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 486 | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 487 | .mmu_type = MMU_TYPE_R4000, |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 488 | }, |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 489 | { |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 490 | /* A generic CPU providing MIPS64 Release 2 features. |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 491 | FIXME: Eventually this should be replaced by a real CPU model. */ |
| 492 | .name = "MIPS64R2-generic", |
ths | 8c89395 | 2007-11-18 03:19:58 +0000 | [diff] [blame] | 493 | .CP0_PRid = 0x00010000, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 494 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 495 | (MMU_TYPE_R4000 << CP0C0_MT), |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 496 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 497 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 498 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 499 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 500 | .CP0_Config2 = MIPS_CONFIG2, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 501 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 502 | .CP0_LLAddr_rw_bitmask = 0, |
| 503 | .CP0_LLAddr_shift = 0, |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 504 | .SYNCI_Step = 32, |
| 505 | .CCRes = 2, |
| 506 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
ths | ea4b07f | 2007-12-28 12:35:05 +0000 | [diff] [blame] | 507 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 508 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 509 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 510 | .SEGBITS = 42, |
| 511 | /* The architectural limit is 59, but we have hardcoded 36 bit |
| 512 | in some places... |
| 513 | .PABITS = 59, */ /* the architectural limit */ |
| 514 | .PABITS = 36, |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 515 | .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 516 | .mmu_type = MMU_TYPE_R4000, |
ths | d2123ea | 2007-10-29 09:38:43 +0000 | [diff] [blame] | 517 | }, |
Huacai Chen | 5bc6fba | 2010-06-29 10:50:27 +0800 | [diff] [blame] | 518 | { |
| 519 | .name = "Loongson-2E", |
| 520 | .CP0_PRid = 0x6302, |
| 521 | /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ |
| 522 | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | |
| 523 | (0x1<<4) | (0x1<<1), |
| 524 | /* Note: Config1 is only used internally, Loongson-2E has only Config0. */ |
| 525 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 526 | .SYNCI_Step = 16, |
| 527 | .CCRes = 2, |
| 528 | .CP0_Status_rw_bitmask = 0x35D0FFFF, |
| 529 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
| 530 | .SEGBITS = 40, |
| 531 | .PABITS = 40, |
| 532 | .insn_flags = CPU_LOONGSON2E, |
| 533 | .mmu_type = MMU_TYPE_R4000, |
| 534 | }, |
| 535 | { |
| 536 | .name = "Loongson-2F", |
| 537 | .CP0_PRid = 0x6303, |
| 538 | /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ |
| 539 | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | |
| 540 | (0x1<<4) | (0x1<<1), |
| 541 | /* Note: Config1 is only used internally, Loongson-2F has only Config0. */ |
| 542 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 543 | .SYNCI_Step = 16, |
| 544 | .CCRes = 2, |
Stefan Weil | ebabb67 | 2011-04-26 10:29:36 +0200 | [diff] [blame] | 545 | .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/ |
Huacai Chen | 5bc6fba | 2010-06-29 10:50:27 +0800 | [diff] [blame] | 546 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
| 547 | .SEGBITS = 40, |
| 548 | .PABITS = 40, |
| 549 | .insn_flags = CPU_LOONGSON2F, |
| 550 | .mmu_type = MMU_TYPE_R4000, |
| 551 | }, |
Jia Liu | af13ae0 | 2012-10-24 22:17:12 +0800 | [diff] [blame] | 552 | { |
| 553 | /* A generic CPU providing MIPS64 ASE DSP 2 features. |
| 554 | FIXME: Eventually this should be replaced by a real CPU model. */ |
| 555 | .name = "mips64dspr2", |
| 556 | .CP0_PRid = 0x00010000, |
| 557 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 558 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 559 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 560 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 561 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 562 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 563 | .CP0_Config2 = MIPS_CONFIG2, |
| 564 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
| 565 | .CP0_LLAddr_rw_bitmask = 0, |
| 566 | .CP0_LLAddr_shift = 0, |
| 567 | .SYNCI_Step = 32, |
| 568 | .CCRes = 2, |
| 569 | .CP0_Status_rw_bitmask = 0x37FBFFFF, |
| 570 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 571 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 572 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 573 | .SEGBITS = 42, |
| 574 | /* The architectural limit is 59, but we have hardcoded 36 bit |
| 575 | in some places... |
| 576 | .PABITS = 59, */ /* the architectural limit */ |
| 577 | .PABITS = 36, |
| 578 | .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, |
| 579 | .mmu_type = MMU_TYPE_R4000, |
| 580 | }, |
Huacai Chen | 5bc6fba | 2010-06-29 10:50:27 +0800 | [diff] [blame] | 581 | |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 582 | #endif |
| 583 | }; |
| 584 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 585 | static const mips_def_t *cpu_mips_find_by_name (const char *name) |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 586 | { |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 587 | int i; |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 588 | |
malc | b1503cd | 2008-12-22 20:33:55 +0000 | [diff] [blame] | 589 | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 590 | if (strcasecmp(name, mips_defs[i].name) == 0) { |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 591 | return &mips_defs[i]; |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 592 | } |
| 593 | } |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 594 | return NULL; |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 595 | } |
| 596 | |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 597 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf) |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 598 | { |
| 599 | int i; |
| 600 | |
malc | b1503cd | 2008-12-22 20:33:55 +0000 | [diff] [blame] | 601 | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 602 | (*cpu_fprintf)(f, "MIPS '%s'\n", |
| 603 | mips_defs[i].name); |
| 604 | } |
| 605 | } |
| 606 | |
ths | f8a6ec5 | 2008-09-02 17:39:45 +0000 | [diff] [blame] | 607 | #ifndef CONFIG_USER_ONLY |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 608 | static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 609 | { |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 610 | env->tlb->nb_tlb = 1; |
| 611 | env->tlb->map_address = &no_mmu_map_address; |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 612 | } |
| 613 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 614 | static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 615 | { |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 616 | env->tlb->nb_tlb = 1; |
| 617 | env->tlb->map_address = &fixed_mmu_map_address; |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 618 | } |
| 619 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 620 | static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 621 | { |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 622 | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
| 623 | env->tlb->map_address = &r4k_map_address; |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 624 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
| 625 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
| 626 | env->tlb->helper_tlbp = r4k_helper_tlbp; |
| 627 | env->tlb->helper_tlbr = r4k_helper_tlbr; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 628 | } |
| 629 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 630 | static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 631 | { |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 632 | MIPSCPU *cpu = mips_env_get_cpu(env); |
| 633 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 634 | env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 635 | |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 636 | switch (def->mmu_type) { |
| 637 | case MMU_TYPE_NONE: |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 638 | no_mmu_init(env, def); |
| 639 | break; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 640 | case MMU_TYPE_R4000: |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 641 | r4k_mmu_init(env, def); |
| 642 | break; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 643 | case MMU_TYPE_FMT: |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 644 | fixed_mmu_init(env, def); |
| 645 | break; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 646 | case MMU_TYPE_R3000: |
| 647 | case MMU_TYPE_R6000: |
| 648 | case MMU_TYPE_R8000: |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 649 | default: |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 650 | cpu_abort(CPU(cpu), "MMU type not supported\n"); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 651 | } |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 652 | } |
ths | f8a6ec5 | 2008-09-02 17:39:45 +0000 | [diff] [blame] | 653 | #endif /* CONFIG_USER_ONLY */ |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 654 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 655 | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 656 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 657 | int i; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 658 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 659 | for (i = 0; i < MIPS_FPU_MAX; i++) |
| 660 | env->fpus[i].fcr0 = def->CP1_fcr0; |
| 661 | |
| 662 | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 663 | } |
| 664 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 665 | static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 666 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 667 | env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 668 | |
| 669 | /* MVPConf1 implemented, TLB sharable, no gating storage support, |
| 670 | programmable cache partitioning implemented, number of allocatable |
| 671 | and sharable TLB entries, MVP has allocatable TCs, 2 VPEs |
| 672 | implemented, 5 TCs implemented. */ |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 673 | env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 674 | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 675 | // TODO: actually do 2 VPEs. |
| 676 | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | |
| 677 | // (0x04 << CP0MVPC0_PTC); |
| 678 | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
Edgar E. Iglesias | 1dab005 | 2011-08-29 23:07:38 +0200 | [diff] [blame] | 679 | (0x00 << CP0MVPC0_PTC); |
aurel32 | 932e71c | 2009-01-12 21:33:13 +0000 | [diff] [blame] | 680 | #if !defined(CONFIG_USER_ONLY) |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 681 | /* Usermode has no TLB support */ |
aurel32 | 932e71c | 2009-01-12 21:33:13 +0000 | [diff] [blame] | 682 | env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
| 683 | #endif |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 684 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 685 | /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
| 686 | no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 687 | env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 688 | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
| 689 | (0x1 << CP0MVPC1_PCP1); |
| 690 | } |