blob: 29dc2ef73851c10efdad03ec69b470e1887a0140 [file] [log] [blame]
ths33d68b52007-03-18 00:30:29 +00001/*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths33d68b52007-03-18 00:30:29 +000019 */
20
ths3953d782007-03-21 11:04:42 +000021/* CPU / CPU family specific config register values. */
22
ths6d355242007-12-25 03:13:56 +000023/* Have config1, uncached coherency */
ths3953d782007-03-21 11:04:42 +000024#define MIPS_CONFIG0 \
Peter Maydellf45cb2f2014-03-17 16:00:34 +000025 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
ths3953d782007-03-21 11:04:42 +000026
thsae5d8052007-07-29 22:11:46 +000027/* Have config2, no coprocessor2 attached, no MDMX support attached,
ths3953d782007-03-21 11:04:42 +000028 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30#define MIPS_CONFIG1 \
Peter Maydellf45cb2f2014-03-17 16:00:34 +000031((1U << CP0C1_M) | \
ths3953d782007-03-21 11:04:42 +000032 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36/* Have config3, no tertiary/secondary caches implemented */
37#define MIPS_CONFIG2 \
Peter Maydellf45cb2f2014-03-17 16:00:34 +000038((1U << CP0C2_M))
ths3953d782007-03-21 11:04:42 +000039
ths6d355242007-12-25 03:13:56 +000040/* No config4, no DSP ASE, no large physaddr (PABITS),
Stefan Weilff2712b2011-04-28 17:20:35 +020041 no external interrupt controller, no vectored interrupts,
thsead93602007-09-06 00:18:15 +000042 no 1kb pages, no SmartMIPS ASE, no trace logic */
ths3953d782007-03-21 11:04:42 +000043#define MIPS_CONFIG3 \
44((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
thsead93602007-09-06 00:18:15 +000046 (0 << CP0C3_SM) | (0 << CP0C3_TL))
ths3953d782007-03-21 11:04:42 +000047
Petar Jovanovicb4160af2014-01-24 13:45:05 +010048#define MIPS_CONFIG4 \
49((0 << CP0C4_M))
50
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +010051#define MIPS_CONFIG5 \
52((0 << CP0C5_M))
53
ths6d355242007-12-25 03:13:56 +000054/* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64};
65
Anthony Liguoric227f092009-10-01 16:12:16 -050066struct mips_def_t {
ths50366fe2008-07-20 19:13:19 +000067 const char *name;
ths33d68b52007-03-18 00:30:29 +000068 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
ths3953d782007-03-21 11:04:42 +000071 int32_t CP0_Config2;
72 int32_t CP0_Config3;
Petar Jovanovicb4160af2014-01-24 13:45:05 +010073 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +010075 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
ths34ee2ed2007-03-24 23:36:18 +000077 int32_t CP0_Config6;
78 int32_t CP0_Config7;
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +010079 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
ths2f644542007-04-11 20:34:23 +000081 int32_t SYNCI_Step;
82 int32_t CCRes;
thsead93602007-09-06 00:18:15 +000083 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
ths3953d782007-03-21 11:04:42 +000086 int32_t CP1_fcr0;
thse034e2c2007-06-23 18:04:12 +000087 int32_t SEGBITS;
ths6d355242007-12-25 03:13:56 +000088 int32_t PABITS;
thsead93602007-09-06 00:18:15 +000089 int32_t CP0_SRSConf0_rw_bitmask;
90 int32_t CP0_SRSConf0;
91 int32_t CP0_SRSConf1_rw_bitmask;
92 int32_t CP0_SRSConf1;
93 int32_t CP0_SRSConf2_rw_bitmask;
94 int32_t CP0_SRSConf2;
95 int32_t CP0_SRSConf3_rw_bitmask;
96 int32_t CP0_SRSConf3;
97 int32_t CP0_SRSConf4_rw_bitmask;
98 int32_t CP0_SRSConf4;
thse189e742007-09-24 12:48:00 +000099 int insn_flags;
ths6d355242007-12-25 03:13:56 +0000100 enum mips_mmu_types mmu_type;
ths33d68b52007-03-18 00:30:29 +0000101};
102
103/*****************************************************************************/
104/* MIPS CPU definitions */
Anthony Liguoric227f092009-10-01 16:12:16 -0500105static const mips_def_t mips_defs[] =
ths33d68b52007-03-18 00:30:29 +0000106{
ths33d68b52007-03-18 00:30:29 +0000107 {
108 .name = "4Kc",
109 .CP0_PRid = 0x00018000,
ths6d355242007-12-25 03:13:56 +0000110 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000111 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000112 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800113 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100114 (0 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000115 .CP0_Config2 = MIPS_CONFIG2,
116 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100117 .CP0_LLAddr_rw_bitmask = 0,
118 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000119 .SYNCI_Step = 32,
120 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000121 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000122 .SEGBITS = 32,
123 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100124 .insn_flags = CPU_MIPS32,
ths6d355242007-12-25 03:13:56 +0000125 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000126 },
127 {
ths8d162c22007-11-19 16:10:33 +0000128 .name = "4Km",
129 .CP0_PRid = 0x00018300,
130 /* Config1 implemented, fixed mapping MMU,
131 no virtual icache, uncached coherency. */
ths6d355242007-12-25 03:13:56 +0000132 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
ths8d162c22007-11-19 16:10:33 +0000133 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000134 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800135 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
136 (1 << CP0C1_CA),
ths8d162c22007-11-19 16:10:33 +0000137 .CP0_Config2 = MIPS_CONFIG2,
138 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100139 .CP0_LLAddr_rw_bitmask = 0,
140 .CP0_LLAddr_shift = 4,
ths8d162c22007-11-19 16:10:33 +0000141 .SYNCI_Step = 32,
142 .CCRes = 2,
143 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000144 .SEGBITS = 32,
145 .PABITS = 32,
ths8d162c22007-11-19 16:10:33 +0000146 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000147 .mmu_type = MMU_TYPE_FMT,
ths8d162c22007-11-19 16:10:33 +0000148 },
149 {
ths34ee2ed2007-03-24 23:36:18 +0000150 .name = "4KEcR1",
ths33d68b52007-03-18 00:30:29 +0000151 .CP0_PRid = 0x00018400,
ths6d355242007-12-25 03:13:56 +0000152 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000153 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000154 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800155 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100156 (0 << CP0C1_CA),
ths34ee2ed2007-03-24 23:36:18 +0000157 .CP0_Config2 = MIPS_CONFIG2,
158 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100159 .CP0_LLAddr_rw_bitmask = 0,
160 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000161 .SYNCI_Step = 32,
162 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000163 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000164 .SEGBITS = 32,
165 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100166 .insn_flags = CPU_MIPS32,
ths6d355242007-12-25 03:13:56 +0000167 .mmu_type = MMU_TYPE_R4000,
ths34ee2ed2007-03-24 23:36:18 +0000168 },
169 {
ths8d162c22007-11-19 16:10:33 +0000170 .name = "4KEmR1",
171 .CP0_PRid = 0x00018500,
ths6d355242007-12-25 03:13:56 +0000172 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
ths8d162c22007-11-19 16:10:33 +0000173 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000174 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800175 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
176 (1 << CP0C1_CA),
ths8d162c22007-11-19 16:10:33 +0000177 .CP0_Config2 = MIPS_CONFIG2,
178 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100179 .CP0_LLAddr_rw_bitmask = 0,
180 .CP0_LLAddr_shift = 4,
ths8d162c22007-11-19 16:10:33 +0000181 .SYNCI_Step = 32,
182 .CCRes = 2,
183 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000184 .SEGBITS = 32,
185 .PABITS = 32,
ths8d162c22007-11-19 16:10:33 +0000186 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000187 .mmu_type = MMU_TYPE_FMT,
ths8d162c22007-11-19 16:10:33 +0000188 },
189 {
ths34ee2ed2007-03-24 23:36:18 +0000190 .name = "4KEc",
191 .CP0_PRid = 0x00019000,
ths6d355242007-12-25 03:13:56 +0000192 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
193 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000194 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000195 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800196 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100197 (0 << CP0C1_CA),
ths34ee2ed2007-03-24 23:36:18 +0000198 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000199 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100200 .CP0_LLAddr_rw_bitmask = 0,
201 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000202 .SYNCI_Step = 32,
203 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000204 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000205 .SEGBITS = 32,
206 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100207 .insn_flags = CPU_MIPS32R2,
ths6d355242007-12-25 03:13:56 +0000208 .mmu_type = MMU_TYPE_R4000,
ths34ee2ed2007-03-24 23:36:18 +0000209 },
210 {
ths3e4587d2007-11-14 03:11:17 +0000211 .name = "4KEm",
212 .CP0_PRid = 0x00019100,
ths6d355242007-12-25 03:13:56 +0000213 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000214 (MMU_TYPE_FMT << CP0C0_MT),
ths3e4587d2007-11-14 03:11:17 +0000215 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000216 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800217 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
218 (1 << CP0C1_CA),
ths3e4587d2007-11-14 03:11:17 +0000219 .CP0_Config2 = MIPS_CONFIG2,
220 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100221 .CP0_LLAddr_rw_bitmask = 0,
222 .CP0_LLAddr_shift = 4,
ths3e4587d2007-11-14 03:11:17 +0000223 .SYNCI_Step = 32,
224 .CCRes = 2,
225 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000226 .SEGBITS = 32,
227 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000228 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000229 .mmu_type = MMU_TYPE_FMT,
ths3e4587d2007-11-14 03:11:17 +0000230 },
231 {
ths34ee2ed2007-03-24 23:36:18 +0000232 .name = "24Kc",
233 .CP0_PRid = 0x00019300,
ths6d355242007-12-25 03:13:56 +0000234 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000235 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000236 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000237 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800238 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
239 (1 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000240 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000241 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100242 .CP0_LLAddr_rw_bitmask = 0,
243 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000244 .SYNCI_Step = 32,
245 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000246 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000247 .CP0_Status_rw_bitmask = 0x1278FF1F,
ths6d355242007-12-25 03:13:56 +0000248 .SEGBITS = 32,
249 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000250 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000251 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000252 },
253 {
254 .name = "24Kf",
255 .CP0_PRid = 0x00019300,
ths6d355242007-12-25 03:13:56 +0000256 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
257 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000258 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000259 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800260 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
261 (1 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000262 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000263 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100264 .CP0_LLAddr_rw_bitmask = 0,
265 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000266 .SYNCI_Step = 32,
267 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000268 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000269 .CP0_Status_rw_bitmask = 0x3678FF1F,
ths5a5012e2007-05-07 13:55:33 +0000270 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
271 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
ths6d355242007-12-25 03:13:56 +0000272 .SEGBITS = 32,
273 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000274 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000275 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000276 },
thsead93602007-09-06 00:18:15 +0000277 {
278 .name = "34Kf",
279 .CP0_PRid = 0x00019500,
ths6d355242007-12-25 03:13:56 +0000280 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000281 (MMU_TYPE_R4000 << CP0C0_MT),
thsead93602007-09-06 00:18:15 +0000282 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000283 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800284 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
285 (1 << CP0C1_CA),
thsead93602007-09-06 00:18:15 +0000286 .CP0_Config2 = MIPS_CONFIG2,
Yongbok Kimb9ac5d92013-08-02 10:33:43 +0100287 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
288 (1 << CP0C3_DSPP),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100289 .CP0_LLAddr_rw_bitmask = 0,
290 .CP0_LLAddr_shift = 0,
thsead93602007-09-06 00:18:15 +0000291 .SYNCI_Step = 32,
292 .CCRes = 2,
Yongbok Kimb9ac5d92013-08-02 10:33:43 +0100293 .CP0_Status_rw_bitmask = 0x3778FF1F,
thsead93602007-09-06 00:18:15 +0000294 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
295 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
296 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
297 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
298 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
299 (0xff << CP0TCSt_TASID),
300 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
301 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
302 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
303 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000304 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
thsead93602007-09-06 00:18:15 +0000305 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
306 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000307 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
thsead93602007-09-06 00:18:15 +0000308 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
309 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000310 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
thsead93602007-09-06 00:18:15 +0000311 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
312 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000313 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
thsead93602007-09-06 00:18:15 +0000314 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
315 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
317 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
ths6d355242007-12-25 03:13:56 +0000318 .SEGBITS = 32,
319 .PABITS = 32,
ths7385ac02007-10-23 17:04:27 +0000320 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
ths6d355242007-12-25 03:13:56 +0000321 .mmu_type = MMU_TYPE_R4000,
thsead93602007-09-06 00:18:15 +0000322 },
Jia Liuaf13ae02012-10-24 22:17:12 +0800323 {
324 .name = "74Kf",
325 .CP0_PRid = 0x00019700,
326 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
327 (MMU_TYPE_R4000 << CP0C0_MT),
328 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
329 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
330 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
331 (1 << CP0C1_CA),
332 .CP0_Config2 = MIPS_CONFIG2,
333 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
334 .CP0_LLAddr_rw_bitmask = 0,
335 .CP0_LLAddr_shift = 4,
336 .SYNCI_Step = 32,
337 .CCRes = 2,
338 .CP0_Status_rw_bitmask = 0x3778FF1F,
339 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
340 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
341 .SEGBITS = 32,
342 .PABITS = 32,
343 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
344 .mmu_type = MMU_TYPE_R4000,
345 },
Petar Jovanovice5275262014-01-15 17:01:46 +0100346 {
347 /* A generic CPU providing MIPS32 Release 5 features.
348 FIXME: Eventually this should be replaced by a real CPU model. */
349 .name = "mips32r5-generic",
350 .CP0_PRid = 0x00019700,
351 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
352 (MMU_TYPE_R4000 << CP0C0_MT),
353 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
354 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
355 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
356 (1 << CP0C1_CA),
357 .CP0_Config2 = MIPS_CONFIG2,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000358 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
359 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
Petar Jovanovicb4160af2014-01-24 13:45:05 +0100360 .CP0_Config4_rw_bitmask = 0,
Petar Jovanovic736d1202014-01-22 18:35:32 +0100361 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +0100362 .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
363 (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
Petar Jovanovic736d1202014-01-22 18:35:32 +0100364 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +0100365 (0 << CP0C5_NFExists),
Petar Jovanovice5275262014-01-15 17:01:46 +0100366 .CP0_LLAddr_rw_bitmask = 0,
367 .CP0_LLAddr_shift = 4,
368 .SYNCI_Step = 32,
369 .CCRes = 2,
370 .CP0_Status_rw_bitmask = 0x3778FF1F,
Petar Jovanovic736d1202014-01-22 18:35:32 +0100371 .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
372 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
373 (0x93 << FCR0_PRID),
Petar Jovanovice5275262014-01-15 17:01:46 +0100374 .SEGBITS = 32,
375 .PABITS = 32,
376 .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
377 .mmu_type = MMU_TYPE_R4000,
378 },
thsd26bc212007-11-08 18:05:37 +0000379#if defined(TARGET_MIPS64)
ths33d68b52007-03-18 00:30:29 +0000380 {
381 .name = "R4000",
382 .CP0_PRid = 0x00000400,
ths6d355242007-12-25 03:13:56 +0000383 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
384 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
aurel3269585492009-01-14 19:40:36 +0000385 /* Note: Config1 is only used internally, the R4000 has only Config0. */
ths6d355242007-12-25 03:13:56 +0000386 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100387 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
388 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000389 .SYNCI_Step = 16,
390 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000391 .CP0_Status_rw_bitmask = 0x3678FFFF,
aurel3269585492009-01-14 19:40:36 +0000392 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000393 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
thse034e2c2007-06-23 18:04:12 +0000394 .SEGBITS = 40,
ths6d355242007-12-25 03:13:56 +0000395 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000396 .insn_flags = CPU_MIPS3,
ths6d355242007-12-25 03:13:56 +0000397 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000398 },
399 {
thse9c71dd2007-12-25 20:46:56 +0000400 .name = "VR5432",
401 .CP0_PRid = 0x00005400,
402 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
403 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
404 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100405 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
406 .CP0_LLAddr_shift = 4,
thse9c71dd2007-12-25 20:46:56 +0000407 .SYNCI_Step = 16,
408 .CCRes = 2,
409 .CP0_Status_rw_bitmask = 0x3678FFFF,
410 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
411 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
412 .SEGBITS = 40,
413 .PABITS = 32,
414 .insn_flags = CPU_VR54XX,
415 .mmu_type = MMU_TYPE_R4000,
416 },
417 {
thsc9c1a062007-06-01 14:58:56 +0000418 .name = "5Kc",
419 .CP0_PRid = 0x00018100,
ths29fe0e32007-12-25 17:32:46 +0000420 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000421 (MMU_TYPE_R4000 << CP0C0_MT),
thsc9c1a062007-06-01 14:58:56 +0000422 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000423 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
424 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
425 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000426 .CP0_Config2 = MIPS_CONFIG2,
427 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100428 .CP0_LLAddr_rw_bitmask = 0,
429 .CP0_LLAddr_shift = 4,
thsc9c1a062007-06-01 14:58:56 +0000430 .SYNCI_Step = 32,
431 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000432 .CP0_Status_rw_bitmask = 0x32F8FFFF,
thse034e2c2007-06-23 18:04:12 +0000433 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000434 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000435 .insn_flags = CPU_MIPS64,
ths6d355242007-12-25 03:13:56 +0000436 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000437 },
438 {
439 .name = "5Kf",
440 .CP0_PRid = 0x00018100,
ths29fe0e32007-12-25 17:32:46 +0000441 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000442 (MMU_TYPE_R4000 << CP0C0_MT),
thsc9c1a062007-06-01 14:58:56 +0000443 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000444 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
445 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
446 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000447 .CP0_Config2 = MIPS_CONFIG2,
448 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100449 .CP0_LLAddr_rw_bitmask = 0,
450 .CP0_LLAddr_shift = 4,
thsc9c1a062007-06-01 14:58:56 +0000451 .SYNCI_Step = 32,
452 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000453 .CP0_Status_rw_bitmask = 0x36F8FFFF,
aurel3269585492009-01-14 19:40:36 +0000454 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000455 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
456 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
thse034e2c2007-06-23 18:04:12 +0000457 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000458 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000459 .insn_flags = CPU_MIPS64,
ths6d355242007-12-25 03:13:56 +0000460 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000461 },
462 {
463 .name = "20Kc",
aurel3269585492009-01-14 19:40:36 +0000464 /* We emulate a later version of the 20Kc, earlier ones had a broken
thsbd04c6f2007-06-12 12:43:47 +0000465 WAIT instruction. */
466 .CP0_PRid = 0x000182a0,
ths29fe0e32007-12-25 17:32:46 +0000467 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
ths6d355242007-12-25 03:13:56 +0000468 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
thsc9c1a062007-06-01 14:58:56 +0000469 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000470 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
471 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
472 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000473 .CP0_Config2 = MIPS_CONFIG2,
474 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100475 .CP0_LLAddr_rw_bitmask = 0,
476 .CP0_LLAddr_shift = 0,
thsc9c1a062007-06-01 14:58:56 +0000477 .SYNCI_Step = 32,
thsa1daafd2007-12-24 14:33:57 +0000478 .CCRes = 1,
thsead93602007-09-06 00:18:15 +0000479 .CP0_Status_rw_bitmask = 0x36FBFFFF,
aurel3269585492009-01-14 19:40:36 +0000480 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000481 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
ths5a5012e2007-05-07 13:55:33 +0000482 (1 << FCR0_D) | (1 << FCR0_S) |
thsc9c1a062007-06-01 14:58:56 +0000483 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
thse034e2c2007-06-23 18:04:12 +0000484 .SEGBITS = 40,
ths6d355242007-12-25 03:13:56 +0000485 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000486 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
ths6d355242007-12-25 03:13:56 +0000487 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000488 },
thsd2123ea2007-10-29 09:38:43 +0000489 {
aurel3269585492009-01-14 19:40:36 +0000490 /* A generic CPU providing MIPS64 Release 2 features.
thsd2123ea2007-10-29 09:38:43 +0000491 FIXME: Eventually this should be replaced by a real CPU model. */
492 .name = "MIPS64R2-generic",
ths8c893952007-11-18 03:19:58 +0000493 .CP0_PRid = 0x00010000,
ths6d355242007-12-25 03:13:56 +0000494 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000495 (MMU_TYPE_R4000 << CP0C0_MT),
thsd2123ea2007-10-29 09:38:43 +0000496 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000497 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
498 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
499 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsd2123ea2007-10-29 09:38:43 +0000500 .CP0_Config2 = MIPS_CONFIG2,
ths6d355242007-12-25 03:13:56 +0000501 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100502 .CP0_LLAddr_rw_bitmask = 0,
503 .CP0_LLAddr_shift = 0,
thsd2123ea2007-10-29 09:38:43 +0000504 .SYNCI_Step = 32,
505 .CCRes = 2,
506 .CP0_Status_rw_bitmask = 0x36FBFFFF,
thsea4b07f2007-12-28 12:35:05 +0000507 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
508 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
509 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
ths6d355242007-12-25 03:13:56 +0000510 .SEGBITS = 42,
511 /* The architectural limit is 59, but we have hardcoded 36 bit
512 in some places...
513 .PABITS = 59, */ /* the architectural limit */
514 .PABITS = 36,
thsd2123ea2007-10-29 09:38:43 +0000515 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
ths6d355242007-12-25 03:13:56 +0000516 .mmu_type = MMU_TYPE_R4000,
thsd2123ea2007-10-29 09:38:43 +0000517 },
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800518 {
519 .name = "Loongson-2E",
520 .CP0_PRid = 0x6302,
521 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
522 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
523 (0x1<<4) | (0x1<<1),
524 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
525 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
526 .SYNCI_Step = 16,
527 .CCRes = 2,
528 .CP0_Status_rw_bitmask = 0x35D0FFFF,
529 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
530 .SEGBITS = 40,
531 .PABITS = 40,
532 .insn_flags = CPU_LOONGSON2E,
533 .mmu_type = MMU_TYPE_R4000,
534 },
535 {
536 .name = "Loongson-2F",
537 .CP0_PRid = 0x6303,
538 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
539 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
540 (0x1<<4) | (0x1<<1),
541 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
542 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
543 .SYNCI_Step = 16,
544 .CCRes = 2,
Stefan Weilebabb672011-04-26 10:29:36 +0200545 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800546 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
547 .SEGBITS = 40,
548 .PABITS = 40,
549 .insn_flags = CPU_LOONGSON2F,
550 .mmu_type = MMU_TYPE_R4000,
551 },
Jia Liuaf13ae02012-10-24 22:17:12 +0800552 {
553 /* A generic CPU providing MIPS64 ASE DSP 2 features.
554 FIXME: Eventually this should be replaced by a real CPU model. */
555 .name = "mips64dspr2",
556 .CP0_PRid = 0x00010000,
557 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
558 (MMU_TYPE_R4000 << CP0C0_MT),
559 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
560 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
561 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
562 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
563 .CP0_Config2 = MIPS_CONFIG2,
564 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
565 .CP0_LLAddr_rw_bitmask = 0,
566 .CP0_LLAddr_shift = 0,
567 .SYNCI_Step = 32,
568 .CCRes = 2,
569 .CP0_Status_rw_bitmask = 0x37FBFFFF,
570 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
571 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
572 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
573 .SEGBITS = 42,
574 /* The architectural limit is 59, but we have hardcoded 36 bit
575 in some places...
576 .PABITS = 59, */ /* the architectural limit */
577 .PABITS = 36,
578 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
579 .mmu_type = MMU_TYPE_R4000,
580 },
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800581
ths33d68b52007-03-18 00:30:29 +0000582#endif
583};
584
Anthony Liguoric227f092009-10-01 16:12:16 -0500585static const mips_def_t *cpu_mips_find_by_name (const char *name)
ths33d68b52007-03-18 00:30:29 +0000586{
bellardaaed9092007-11-10 15:15:54 +0000587 int i;
ths33d68b52007-03-18 00:30:29 +0000588
malcb1503cd2008-12-22 20:33:55 +0000589 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
ths33d68b52007-03-18 00:30:29 +0000590 if (strcasecmp(name, mips_defs[i].name) == 0) {
bellardaaed9092007-11-10 15:15:54 +0000591 return &mips_defs[i];
ths33d68b52007-03-18 00:30:29 +0000592 }
593 }
bellardaaed9092007-11-10 15:15:54 +0000594 return NULL;
ths33d68b52007-03-18 00:30:29 +0000595}
596
Stefan Weil9a78eea2010-10-22 23:03:33 +0200597void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
ths33d68b52007-03-18 00:30:29 +0000598{
599 int i;
600
malcb1503cd2008-12-22 20:33:55 +0000601 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
ths33d68b52007-03-18 00:30:29 +0000602 (*cpu_fprintf)(f, "MIPS '%s'\n",
603 mips_defs[i].name);
604 }
605}
606
thsf8a6ec52008-09-02 17:39:45 +0000607#ifndef CONFIG_USER_ONLY
Anthony Liguoric227f092009-10-01 16:12:16 -0500608static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
ths29929e32007-05-13 13:49:44 +0000609{
thsead93602007-09-06 00:18:15 +0000610 env->tlb->nb_tlb = 1;
611 env->tlb->map_address = &no_mmu_map_address;
ths29929e32007-05-13 13:49:44 +0000612}
613
Anthony Liguoric227f092009-10-01 16:12:16 -0500614static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
ths29929e32007-05-13 13:49:44 +0000615{
thsead93602007-09-06 00:18:15 +0000616 env->tlb->nb_tlb = 1;
617 env->tlb->map_address = &fixed_mmu_map_address;
ths29929e32007-05-13 13:49:44 +0000618}
619
Anthony Liguoric227f092009-10-01 16:12:16 -0500620static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
ths29929e32007-05-13 13:49:44 +0000621{
thsead93602007-09-06 00:18:15 +0000622 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
623 env->tlb->map_address = &r4k_map_address;
aurel32c01fccd2009-03-08 00:06:01 +0000624 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
625 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
626 env->tlb->helper_tlbp = r4k_helper_tlbp;
627 env->tlb->helper_tlbr = r4k_helper_tlbr;
thsead93602007-09-06 00:18:15 +0000628}
629
Anthony Liguoric227f092009-10-01 16:12:16 -0500630static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000631{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200632 MIPSCPU *cpu = mips_env_get_cpu(env);
633
Anthony Liguori7267c092011-08-20 22:09:37 -0500634 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
thsead93602007-09-06 00:18:15 +0000635
ths6d355242007-12-25 03:13:56 +0000636 switch (def->mmu_type) {
637 case MMU_TYPE_NONE:
thsead93602007-09-06 00:18:15 +0000638 no_mmu_init(env, def);
639 break;
ths6d355242007-12-25 03:13:56 +0000640 case MMU_TYPE_R4000:
thsead93602007-09-06 00:18:15 +0000641 r4k_mmu_init(env, def);
642 break;
ths6d355242007-12-25 03:13:56 +0000643 case MMU_TYPE_FMT:
thsead93602007-09-06 00:18:15 +0000644 fixed_mmu_init(env, def);
645 break;
ths6d355242007-12-25 03:13:56 +0000646 case MMU_TYPE_R3000:
647 case MMU_TYPE_R6000:
648 case MMU_TYPE_R8000:
thsead93602007-09-06 00:18:15 +0000649 default:
Andreas Färbera47dddd2013-09-03 17:38:47 +0200650 cpu_abort(CPU(cpu), "MMU type not supported\n");
thsead93602007-09-06 00:18:15 +0000651 }
ths29929e32007-05-13 13:49:44 +0000652}
thsf8a6ec52008-09-02 17:39:45 +0000653#endif /* CONFIG_USER_ONLY */
ths29929e32007-05-13 13:49:44 +0000654
Anthony Liguoric227f092009-10-01 16:12:16 -0500655static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000656{
thsf01be152008-09-18 11:57:27 +0000657 int i;
thsead93602007-09-06 00:18:15 +0000658
thsf01be152008-09-18 11:57:27 +0000659 for (i = 0; i < MIPS_FPU_MAX; i++)
660 env->fpus[i].fcr0 = def->CP1_fcr0;
661
662 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
thsead93602007-09-06 00:18:15 +0000663}
664
Anthony Liguoric227f092009-10-01 16:12:16 -0500665static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000666{
Anthony Liguori7267c092011-08-20 22:09:37 -0500667 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
thsead93602007-09-06 00:18:15 +0000668
669 /* MVPConf1 implemented, TLB sharable, no gating storage support,
670 programmable cache partitioning implemented, number of allocatable
671 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
672 implemented, 5 TCs implemented. */
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000673 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
thsead93602007-09-06 00:18:15 +0000674 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
thsead93602007-09-06 00:18:15 +0000675// TODO: actually do 2 VPEs.
676// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
677// (0x04 << CP0MVPC0_PTC);
678 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
Edgar E. Iglesias1dab0052011-08-29 23:07:38 +0200679 (0x00 << CP0MVPC0_PTC);
aurel32932e71c2009-01-12 21:33:13 +0000680#if !defined(CONFIG_USER_ONLY)
ths0eaef5a2008-07-23 16:14:22 +0000681 /* Usermode has no TLB support */
aurel32932e71c2009-01-12 21:33:13 +0000682 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
683#endif
ths0eaef5a2008-07-23 16:14:22 +0000684
thsead93602007-09-06 00:18:15 +0000685 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
686 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000687 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
thsead93602007-09-06 00:18:15 +0000688 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
689 (0x1 << CP0MVPC1_PCP1);
690}