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j_mayer4c9649a2007-04-05 06:58:33 +00001/*
2 * Alpha emulation cpu definitions for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer4c9649a2007-04-05 06:58:33 +00004 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
Chetan Pantd6ea4232020-10-23 12:33:53 +00009 * version 2.1 of the License, or (at your option) any later version.
j_mayer4c9649a2007-04-05 06:58:33 +000010 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
j_mayer4c9649a2007-04-05 06:58:33 +000018 */
19
Markus Armbruster07f5a252016-06-29 11:05:55 +020020#ifndef ALPHA_CPU_H
21#define ALPHA_CPU_H
j_mayer4c9649a2007-04-05 06:58:33 +000022
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +010023#include "cpu-qom.h"
Richard Henderson74433bf2019-03-22 11:51:19 -070024#include "exec/cpu-defs.h"
Marc-André Lureau69242e72022-03-23 19:57:39 +040025#include "qemu/cpu-float.h"
j_mayer4c9649a2007-04-05 06:58:33 +000026
Richard Henderson5ee4f3c2017-02-24 09:12:43 +110027/* Alpha processors have a weak memory model */
28#define TCG_GUEST_DEFAULT_MO (0)
29
j_mayer4c9649a2007-04-05 06:58:33 +000030#define ICACHE_LINE_SIZE 32
31#define DCACHE_LINE_SIZE 32
32
j_mayer4c9649a2007-04-05 06:58:33 +000033/* Alpha major type */
34enum {
35 ALPHA_EV3 = 1,
36 ALPHA_EV4 = 2,
37 ALPHA_SIM = 3,
38 ALPHA_LCA = 4,
39 ALPHA_EV5 = 5, /* 21164 */
40 ALPHA_EV45 = 6, /* 21064A */
41 ALPHA_EV56 = 7, /* 21164A */
42};
43
44/* EV4 minor type */
45enum {
46 ALPHA_EV4_2 = 0,
47 ALPHA_EV4_3 = 1,
48};
49
50/* LCA minor type */
51enum {
52 ALPHA_LCA_1 = 1, /* 21066 */
53 ALPHA_LCA_2 = 2, /* 20166 */
54 ALPHA_LCA_3 = 3, /* 21068 */
55 ALPHA_LCA_4 = 4, /* 21068 */
56 ALPHA_LCA_5 = 5, /* 21066A */
57 ALPHA_LCA_6 = 6, /* 21068A */
58};
59
60/* EV5 minor type */
61enum {
62 ALPHA_EV5_1 = 1, /* Rev BA, CA */
63 ALPHA_EV5_2 = 2, /* Rev DA, EA */
64 ALPHA_EV5_3 = 3, /* Pass 3 */
65 ALPHA_EV5_4 = 4, /* Pass 3.2 */
66 ALPHA_EV5_5 = 5, /* Pass 4 */
67};
68
69/* EV45 minor type */
70enum {
71 ALPHA_EV45_1 = 1, /* Pass 1 */
72 ALPHA_EV45_2 = 2, /* Pass 1.1 */
73 ALPHA_EV45_3 = 3, /* Pass 2 */
74};
75
76/* EV56 minor type */
77enum {
78 ALPHA_EV56_1 = 1, /* Pass 1 */
79 ALPHA_EV56_2 = 2, /* Pass 2 */
80};
81
82enum {
83 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
84 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
85 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
86 IMPLVER_21364 = 3, /* EV7 & EV79 */
87};
88
89enum {
90 AMASK_BWX = 0x00000001,
91 AMASK_FIX = 0x00000002,
92 AMASK_CIX = 0x00000004,
93 AMASK_MVI = 0x00000100,
94 AMASK_TRAP = 0x00000200,
95 AMASK_PREFETCH = 0x00001000,
96};
97
98enum {
99 VAX_ROUND_NORMAL = 0,
100 VAX_ROUND_CHOPPED,
101};
102
103enum {
104 IEEE_ROUND_NORMAL = 0,
105 IEEE_ROUND_DYNAMIC,
106 IEEE_ROUND_PLUS,
107 IEEE_ROUND_MINUS,
108 IEEE_ROUND_CHOPPED,
109};
110
111/* IEEE floating-point operations encoding */
112/* Trap mode */
113enum {
114 FP_TRAP_I = 0x0,
115 FP_TRAP_U = 0x1,
116 FP_TRAP_S = 0x4,
117 FP_TRAP_SU = 0x5,
118 FP_TRAP_SUI = 0x7,
119};
120
121/* Rounding mode */
122enum {
123 FP_ROUND_CHOPPED = 0x0,
124 FP_ROUND_MINUS = 0x1,
125 FP_ROUND_NORMAL = 0x2,
126 FP_ROUND_DYNAMIC = 0x3,
127};
128
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000129/* FPCR bits -- right-shifted 32 so we can use a uint32_t. */
130#define FPCR_SUM (1U << (63 - 32))
131#define FPCR_INED (1U << (62 - 32))
132#define FPCR_UNFD (1U << (61 - 32))
133#define FPCR_UNDZ (1U << (60 - 32))
134#define FPCR_DYN_SHIFT (58 - 32)
135#define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT)
136#define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT)
137#define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT)
138#define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT)
139#define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT)
140#define FPCR_IOV (1U << (57 - 32))
141#define FPCR_INE (1U << (56 - 32))
142#define FPCR_UNF (1U << (55 - 32))
143#define FPCR_OVF (1U << (54 - 32))
144#define FPCR_DZE (1U << (53 - 32))
145#define FPCR_INV (1U << (52 - 32))
146#define FPCR_OVFD (1U << (51 - 32))
147#define FPCR_DZED (1U << (50 - 32))
148#define FPCR_INVD (1U << (49 - 32))
149#define FPCR_DNZ (1U << (48 - 32))
150#define FPCR_DNOD (1U << (47 - 32))
151#define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
152 | FPCR_OVF | FPCR_DZE | FPCR_INV)
Richard Hendersonba0e2762009-12-09 15:56:29 -0800153
154/* The silly software trap enables implemented by the kernel emulation.
155 These are more or less architecturally required, since the real hardware
156 has read-as-zero bits in the FPCR when the features aren't implemented.
157 For the purposes of QEMU, we pretend the FPCR can hold everything. */
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000158#define SWCR_TRAP_ENABLE_INV (1U << 1)
159#define SWCR_TRAP_ENABLE_DZE (1U << 2)
160#define SWCR_TRAP_ENABLE_OVF (1U << 3)
161#define SWCR_TRAP_ENABLE_UNF (1U << 4)
162#define SWCR_TRAP_ENABLE_INE (1U << 5)
163#define SWCR_TRAP_ENABLE_DNO (1U << 6)
164#define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1))
Richard Hendersonba0e2762009-12-09 15:56:29 -0800165
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000166#define SWCR_MAP_DMZ (1U << 12)
167#define SWCR_MAP_UMZ (1U << 13)
168#define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
Richard Hendersonba0e2762009-12-09 15:56:29 -0800169
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000170#define SWCR_STATUS_INV (1U << 17)
171#define SWCR_STATUS_DZE (1U << 18)
172#define SWCR_STATUS_OVF (1U << 19)
173#define SWCR_STATUS_UNF (1U << 20)
174#define SWCR_STATUS_INE (1U << 21)
175#define SWCR_STATUS_DNO (1U << 22)
176#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
Richard Hendersonba0e2762009-12-09 15:56:29 -0800177
Richard Henderson21ba8562019-04-26 15:20:51 -0700178#define SWCR_STATUS_TO_EXCSUM_SHIFT 16
179
Richard Hendersonba0e2762009-12-09 15:56:29 -0800180#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
181
Richard Henderson84178452011-05-20 13:11:25 -0700182/* MMU modes definitions */
j_mayer4c9649a2007-04-05 06:58:33 +0000183
Richard Henderson6a73ecf2016-09-03 11:32:35 -0700184/* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
Richard Henderson84178452011-05-20 13:11:25 -0700185 The Unix PALcode only exposes the kernel and user modes; presumably
186 executive and supervisor are used by VMS.
187
188 PALcode itself uses physical mode for code and kernel mode for data;
189 there are PALmode instructions that can access data via physical mode
190 or via an os-installed "alternate mode", which is one of the 4 above.
191
Richard Henderson6a73ecf2016-09-03 11:32:35 -0700192 That said, we're only emulating Unix PALcode, and not attempting VMS,
193 so we don't need to implement Executive and Supervisor. QEMU's own
Michael Tokarev8b819682023-07-14 14:23:51 +0300194 PALcode cheats and uses the KSEG mapping for its code+data rather than
Richard Henderson6a73ecf2016-09-03 11:32:35 -0700195 physical addresses. */
Richard Henderson84178452011-05-20 13:11:25 -0700196
Richard Henderson84178452011-05-20 13:11:25 -0700197#define MMU_KERNEL_IDX 0
198#define MMU_USER_IDX 1
Richard Henderson6a73ecf2016-09-03 11:32:35 -0700199#define MMU_PHYS_IDX 2
Richard Henderson84178452011-05-20 13:11:25 -0700200
Philippe Mathieu-Daudé1ea4a062022-02-07 13:35:58 +0100201typedef struct CPUArchState {
j_mayer4c9649a2007-04-05 06:58:33 +0000202 uint64_t ir[31];
Richard Henderson8443eff2009-12-31 12:41:07 -0800203 float64 fir[31];
j_mayer4c9649a2007-04-05 06:58:33 +0000204 uint64_t pc;
j_mayer4c9649a2007-04-05 06:58:33 +0000205 uint64_t unique;
Richard Henderson6910b8f2010-04-07 15:42:26 -0700206 uint64_t lock_addr;
Richard Henderson6910b8f2010-04-07 15:42:26 -0700207 uint64_t lock_value;
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000208
209 /* The FPCR, and disassembled portions thereof. */
210 uint32_t fpcr;
Richard Henderson21ba8562019-04-26 15:20:51 -0700211#ifdef CONFIG_USER_ONLY
212 uint32_t swcr;
213#endif
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000214 uint32_t fpcr_exc_enable;
Richard Henderson8443eff2009-12-31 12:41:07 -0800215 float_status fp_status;
Richard Henderson8443eff2009-12-31 12:41:07 -0800216 uint8_t fpcr_dyn_round;
217 uint8_t fpcr_flush_to_zero;
Richard Henderson8443eff2009-12-31 12:41:07 -0800218
Richard Hendersonbcd26252017-07-06 09:45:07 -1000219 /* Mask of PALmode, Processor State et al. Most of this gets copied
220 into the TranslatorBlock flags and controls code generation. */
221 uint32_t flags;
Richard Henderson26b46092011-05-23 12:12:29 -0700222
Richard Hendersonbcd26252017-07-06 09:45:07 -1000223 /* The high 32-bits of the processor cycle counter. */
Richard Henderson26b46092011-05-23 12:12:29 -0700224 uint32_t pcc_ofs;
Richard Henderson129d8aa2011-05-20 13:30:00 -0700225
226 /* These pass data from the exception logic in the translator and
227 helpers to the OS entry point. This is used for both system
228 emulation and user-mode. */
229 uint64_t trap_arg0;
230 uint64_t trap_arg1;
231 uint64_t trap_arg2;
j_mayer4c9649a2007-04-05 06:58:33 +0000232
Richard Henderson26b46092011-05-23 12:12:29 -0700233#if !defined(CONFIG_USER_ONLY)
234 /* The internal data required by our emulation of the Unix PALcode. */
235 uint64_t exc_addr;
236 uint64_t palbr;
237 uint64_t ptbr;
238 uint64_t vptptr;
239 uint64_t sysval;
240 uint64_t usp;
241 uint64_t shadow[8];
242 uint64_t scratch[24];
243#endif
244
Richard Hendersonc781cf92011-04-28 10:40:08 -0700245 /* This alarm doesn't exist in real hardware; we wish it did. */
Richard Hendersonc781cf92011-04-28 10:40:08 -0700246 uint64_t alarm_expire;
247
j_mayer4c9649a2007-04-05 06:58:33 +0000248 int error_code;
j_mayer4c9649a2007-04-05 06:58:33 +0000249
250 uint32_t features;
251 uint32_t amask;
252 int implver;
Philippe Mathieu-Daudé1ea4a062022-02-07 13:35:58 +0100253} CPUAlphaState;
j_mayer4c9649a2007-04-05 06:58:33 +0000254
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100255/**
256 * AlphaCPU:
257 * @env: #CPUAlphaState
258 *
259 * An Alpha CPU.
260 */
Philippe Mathieu-Daudéb36e2392022-02-14 17:15:16 +0100261struct ArchCPU {
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100262 CPUState parent_obj;
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100263
264 CPUAlphaState env;
265
266 /* This alarm doesn't exist in real hardware; we wish it did. */
267 QEMUTimer *alarm_timer;
268};
269
Philippe Mathieu-Daudé93480282023-10-13 11:35:04 +0200270/**
271 * AlphaCPUClass:
272 * @parent_realize: The parent class' realize handler.
273 * @parent_reset: The parent class' reset handler.
274 *
275 * An Alpha CPU model.
276 */
277struct AlphaCPUClass {
278 CPUClass parent_class;
279
280 DeviceRealize parent_realize;
281 DeviceReset parent_reset;
282};
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100283
284#ifndef CONFIG_USER_ONLY
Markus Armbruster8a9358c2019-08-12 07:23:44 +0200285extern const VMStateDescription vmstate_alpha_cpu;
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100286
287void alpha_cpu_do_interrupt(CPUState *cpu);
288bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
Philippe Mathieu-Daudé6d2d4542022-12-06 16:20:51 +0100289hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
Philippe Mathieu-Daudé9354e692021-09-11 18:54:16 +0200290#endif /* !CONFIG_USER_ONLY */
Markus Armbruster90c84c52019-04-17 21:18:02 +0200291void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
Alex Bennéea010bdb2020-03-16 17:21:41 +0000292int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100293int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
Paolo Bonzini1dc8e6b2016-03-15 13:49:25 +0100294
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100295#include "exec/cpu-all.h"
j_mayer4c9649a2007-04-05 06:58:33 +0000296
297enum {
298 FEATURE_ASN = 0x00000001,
299 FEATURE_SPS = 0x00000002,
300 FEATURE_VIRBND = 0x00000004,
301 FEATURE_TBCHK = 0x00000008,
302};
303
304enum {
Richard Henderson07b6c132011-05-20 14:04:57 -0700305 EXCP_RESET,
306 EXCP_MCHK,
307 EXCP_SMP_INTERRUPT,
308 EXCP_CLK_INTERRUPT,
309 EXCP_DEV_INTERRUPT,
310 EXCP_MMFAULT,
311 EXCP_UNALIGN,
312 EXCP_OPCDEC,
313 EXCP_ARITH,
314 EXCP_FEN,
315 EXCP_CALL_PAL,
j_mayer4c9649a2007-04-05 06:58:33 +0000316};
317
Richard Henderson6a80e082011-04-18 15:09:09 -0700318/* Alpha-specific interrupt pending bits. */
319#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
320#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
321#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
322
Richard Hendersona3b9af12011-04-18 15:59:21 -0700323/* OSF/1 Page table bits. */
324enum {
325 PTE_VALID = 0x0001,
326 PTE_FOR = 0x0002, /* used for page protection (fault on read) */
327 PTE_FOW = 0x0004, /* used for page protection (fault on write) */
328 PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
329 PTE_ASM = 0x0010,
330 PTE_KRE = 0x0100,
331 PTE_URE = 0x0200,
332 PTE_KWE = 0x1000,
333 PTE_UWE = 0x2000
334};
335
Richard Hendersonea879fc2011-04-18 14:19:17 -0700336/* Hardware interrupt (entInt) constants. */
337enum {
338 INT_K_IP,
339 INT_K_CLK,
340 INT_K_MCHK,
341 INT_K_DEV,
342 INT_K_PERF,
343};
344
345/* Memory management (entMM) constants. */
346enum {
347 MM_K_TNV,
348 MM_K_ACV,
349 MM_K_FOR,
350 MM_K_FOE,
351 MM_K_FOW
352};
353
354/* Arithmetic exception (entArith) constants. */
355enum {
356 EXC_M_SWC = 1, /* Software completion */
357 EXC_M_INV = 2, /* Invalid operation */
358 EXC_M_DZE = 4, /* Division by zero */
359 EXC_M_FOV = 8, /* Overflow */
360 EXC_M_UNF = 16, /* Underflow */
361 EXC_M_INE = 32, /* Inexact result */
362 EXC_M_IOV = 64 /* Integer Overflow */
363};
364
365/* Processor status constants. */
Richard Hendersonbcd26252017-07-06 09:45:07 -1000366/* Low 3 bits are interrupt mask level. */
367#define PS_INT_MASK 7u
Richard Hendersonea879fc2011-04-18 14:19:17 -0700368
Richard Hendersonbcd26252017-07-06 09:45:07 -1000369/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
370 The Unix PALcode only uses bit 4. */
371#define PS_USER_MODE 8u
372
Michael Tokarev8b819682023-07-14 14:23:51 +0300373/* CPUAlphaState->flags constants. These are laid out so that we
Richard Hendersonbcd26252017-07-06 09:45:07 -1000374 can set or reset the pieces individually by assigning to the byte,
375 or manipulated as a whole. */
376
377#define ENV_FLAG_PAL_SHIFT 0
378#define ENV_FLAG_PS_SHIFT 8
379#define ENV_FLAG_RX_SHIFT 16
380#define ENV_FLAG_FEN_SHIFT 24
381
382#define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT)
383#define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT)
384#define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT)
385#define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT)
386
387#define ENV_FLAG_TB_MASK \
388 (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
Richard Hendersonea879fc2011-04-18 14:19:17 -0700389
Richard Hendersonfed14242021-12-27 07:01:25 -0800390#define TB_FLAG_UNALIGN (1u << 1)
391
Richard Henderson32a8ea12024-01-28 14:47:19 +1000392static inline int alpha_env_mmu_index(CPUAlphaState *env)
Richard Hendersonea879fc2011-04-18 14:19:17 -0700393{
Richard Hendersonbcd26252017-07-06 09:45:07 -1000394 int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
395 if (env->flags & ENV_FLAG_PAL_MODE) {
396 ret = MMU_KERNEL_IDX;
Richard Hendersonbba9bdc2011-05-20 14:14:44 -0700397 }
Richard Hendersonbcd26252017-07-06 09:45:07 -1000398 return ret;
Richard Hendersonea879fc2011-04-18 14:19:17 -0700399}
j_mayer4c9649a2007-04-05 06:58:33 +0000400
401enum {
j_mayer4c9649a2007-04-05 06:58:33 +0000402 IR_V0 = 0,
403 IR_T0 = 1,
404 IR_T1 = 2,
405 IR_T2 = 3,
406 IR_T3 = 4,
407 IR_T4 = 5,
408 IR_T5 = 6,
409 IR_T6 = 7,
410 IR_T7 = 8,
411 IR_S0 = 9,
412 IR_S1 = 10,
413 IR_S2 = 11,
414 IR_S3 = 12,
415 IR_S4 = 13,
416 IR_S5 = 14,
417 IR_S6 = 15,
Richard Hendersona4b388f2010-04-12 16:17:22 -0700418 IR_FP = IR_S6,
j_mayer4c9649a2007-04-05 06:58:33 +0000419 IR_A0 = 16,
420 IR_A1 = 17,
421 IR_A2 = 18,
422 IR_A3 = 19,
423 IR_A4 = 20,
424 IR_A5 = 21,
425 IR_T8 = 22,
426 IR_T9 = 23,
427 IR_T10 = 24,
428 IR_T11 = 25,
429 IR_RA = 26,
430 IR_T12 = 27,
Richard Hendersona4b388f2010-04-12 16:17:22 -0700431 IR_PV = IR_T12,
j_mayer4c9649a2007-04-05 06:58:33 +0000432 IR_AT = 28,
433 IR_GP = 29,
434 IR_SP = 30,
435 IR_ZERO = 31,
436};
437
Andreas Färber0c282462012-10-15 17:33:32 +0200438void alpha_translate_init(void);
439
Igor Mammedov0dacec82018-02-07 11:40:25 +0100440#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
Igor Mammedov73a25e82017-10-05 15:50:38 +0200441
Marc-André Lureau89057702022-04-20 17:26:02 +0400442G_NORETURN void dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
443G_NORETURN void arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
aurel3295870352008-12-11 22:42:42 +0000444
Andreas Färber4d5712f2012-03-14 01:38:21 +0100445uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
446void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
Richard Henderson59124382014-09-16 12:16:38 -0700447uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
448void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
Richard Henderson90113882021-10-05 19:31:14 -0700449
450#ifdef CONFIG_USER_ONLY
451void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
452 MMUAccessType access_type,
453 bool maperr, uintptr_t retaddr);
Richard Hendersone7424ab2021-07-23 12:20:55 -1000454void alpha_cpu_record_sigbus(CPUState *cs, vaddr address,
455 MMUAccessType access_type, uintptr_t retaddr);
Richard Henderson90113882021-10-05 19:31:14 -0700456#else
457bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
458 MMUAccessType access_type, int mmu_idx,
459 bool probe, uintptr_t retaddr);
Marc-André Lureau89057702022-04-20 17:26:02 +0400460G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
461 MMUAccessType access_type, int mmu_idx,
462 uintptr_t retaddr);
Peter Maydell6ad4d7e2017-08-08 13:42:52 +0100463void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
464 vaddr addr, unsigned size,
465 MMUAccessType access_type,
466 int mmu_idx, MemTxAttrs attrs,
467 MemTxResult response, uintptr_t retaddr);
Richard Henderson5b450402011-04-18 16:13:12 -0700468#endif
j_mayer4c9649a2007-04-05 06:58:33 +0000469
Anton Johanssonbb5de522023-06-21 15:56:24 +0200470static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
471 uint64_t *cs_base, uint32_t *pflags)
aliguori6b917542008-11-18 19:46:41 +0000472{
473 *pc = env->pc;
474 *cs_base = 0;
Richard Hendersonbcd26252017-07-06 09:45:07 -1000475 *pflags = env->flags & ENV_FLAG_TB_MASK;
Richard Hendersonfed14242021-12-27 07:01:25 -0800476#ifdef CONFIG_USER_ONLY
477 *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
478#endif
aliguori6b917542008-11-18 19:46:41 +0000479}
480
Richard Henderson21ba8562019-04-26 15:20:51 -0700481#ifdef CONFIG_USER_ONLY
482/* Copied from linux ieee_swcr_to_fpcr. */
483static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
484{
485 uint64_t fpcr = 0;
486
487 fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
488 fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
489 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
490 | SWCR_TRAP_ENABLE_DZE
491 | SWCR_TRAP_ENABLE_OVF)) << 48;
492 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
493 | SWCR_TRAP_ENABLE_INE)) << 57;
494 fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
495 fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
496
497 return fpcr;
498}
499
500/* Copied from linux ieee_fpcr_to_swcr. */
501static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
502{
503 uint64_t swcr = 0;
504
505 swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
506 swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
507 swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
508 | SWCR_TRAP_ENABLE_DZE
509 | SWCR_TRAP_ENABLE_OVF);
510 swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
511 swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
512 swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
513
514 return swcr;
515}
516#endif /* CONFIG_USER_ONLY */
517
Markus Armbruster07f5a252016-06-29 11:05:55 +0200518#endif /* ALPHA_CPU_H */