blob: 1610472cfc478e4b48fba5645590a4f35fdd641f [file] [log] [blame]
Andreas Färber8d725fa2011-03-07 01:34:04 +01001/*
2 * QEMU float support
3 *
Peter Maydell16017c42015-01-12 14:38:28 +00004 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 * the SoftFloat-2a license
10 * the BSD license
11 * GPL-v2-or-later
12 *
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
Andreas Färber8d725fa2011-03-07 01:34:04 +010016 */
bellard158142c2005-03-13 16:54:06 +000017
Peter Maydella7d1ac72015-01-12 14:38:25 +000018/*
19===============================================================================
bellard158142c2005-03-13 16:54:06 +000020This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
Peter Maydella7d1ac72015-01-12 14:38:25 +000021Arithmetic Package, Release 2a.
bellard158142c2005-03-13 16:54:06 +000022
23Written by John R. Hauser. This work was made possible in part by the
24International Computer Science Institute, located at Suite 600, 1947 Center
25Street, Berkeley, California 94704. Funding was partially provided by the
26National Science Foundation under grant MIP-9311980. The original version
27of this code was written as part of a project to build a fixed-point vector
28processor in collaboration with the University of California at Berkeley,
29overseen by Profs. Nelson Morgan and John Wawrzynek. More information
Peter Maydella7d1ac72015-01-12 14:38:25 +000030is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
bellard158142c2005-03-13 16:54:06 +000031arithmetic/SoftFloat.html'.
32
Peter Maydella7d1ac72015-01-12 14:38:25 +000033THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
bellard158142c2005-03-13 16:54:06 +000038
39Derivative works are acceptable, even for commercial purposes, so long as
Peter Maydella7d1ac72015-01-12 14:38:25 +000040(1) they include prominent notice that the work is derivative, and (2) they
41include prominent notice akin to these four paragraphs for those parts of
42this code that are retained.
bellard158142c2005-03-13 16:54:06 +000043
Peter Maydella7d1ac72015-01-12 14:38:25 +000044===============================================================================
45*/
bellard158142c2005-03-13 16:54:06 +000046
Peter Maydell16017c42015-01-12 14:38:28 +000047/* BSD licensing:
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
53 *
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
56 *
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 *
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
76 */
77
78/* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
80 */
81
Max Filippovcc43c692020-06-30 19:35:49 -070082/*
83 * Define whether architecture deviates from IEEE in not supporting
Max Filippov213ff4e2012-09-19 04:23:51 +040084 * signaling NaNs (so all NaNs are treated as quiet).
85 */
Max Filippovcc43c692020-06-30 19:35:49 -070086static inline bool no_signaling_nans(float_status *status)
87{
Richard Henderson03385df2018-05-10 14:48:17 -070088#if defined(TARGET_XTENSA)
Max Filippovcc43c692020-06-30 19:35:49 -070089 return status->no_signaling_nans;
90#else
91 return false;
Max Filippov213ff4e2012-09-19 04:23:51 +040092#endif
Max Filippovcc43c692020-06-30 19:35:49 -070093}
Max Filippov213ff4e2012-09-19 04:23:51 +040094
Richard Henderson03385df2018-05-10 14:48:17 -070095/* Define how the architecture discriminates signaling NaNs.
96 * This done with the most significant bit of the fraction.
97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
98 * the msb must be zero. MIPS is (so far) unique in supporting both the
99 * 2008 revision and backward compatibility with their original choice.
100 * Thus for MIPS we must make the choice at runtime.
101 */
Richard Hendersonc1203912020-05-04 19:54:57 -0700102static inline bool snan_bit_is_one(float_status *status)
Richard Henderson03385df2018-05-10 14:48:17 -0700103{
104#if defined(TARGET_MIPS)
105 return status->snan_bit_is_one;
Markus Armbruster43692232021-05-03 10:40:34 +0200106#elif defined(TARGET_HPPA) || defined(TARGET_SH4)
Richard Henderson03385df2018-05-10 14:48:17 -0700107 return 1;
108#else
109 return 0;
110#endif
111}
112
Paolo Bonzini789ec7c2011-07-28 12:10:29 +0200113/*----------------------------------------------------------------------------
Richard Henderson298b4682018-05-10 12:45:29 -0700114| For the deconstructed floating-point with fraction FRAC, return true
115| if the fraction represents a signalling NaN; otherwise false.
116*----------------------------------------------------------------------------*/
117
118static bool parts_is_snan_frac(uint64_t frac, float_status *status)
119{
Max Filippovcc43c692020-06-30 19:35:49 -0700120 if (no_signaling_nans(status)) {
121 return false;
122 } else {
123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
124 return msb == snan_bit_is_one(status);
125 }
Richard Henderson298b4682018-05-10 12:45:29 -0700126}
127
128/*----------------------------------------------------------------------------
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700129| The pattern for a default generated deconstructed floating-point NaN.
130*----------------------------------------------------------------------------*/
131
Richard Henderson0fc07ca2020-10-23 14:00:33 -0700132static void parts64_default_nan(FloatParts64 *p, float_status *status)
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700133{
134 bool sign = 0;
135 uint64_t frac;
136
137#if defined(TARGET_SPARC) || defined(TARGET_M68K)
Richard Henderson8fb3d902018-05-14 13:12:14 -0700138 /* !snan_bit_is_one, set all bits */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
Richard Henderson8fb3d902018-05-14 13:12:14 -0700140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
141 || defined(TARGET_MICROBLAZE)
142 /* !snan_bit_is_one, set sign and msb */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
Richard Henderson8fb3d902018-05-14 13:12:14 -0700144 sign = 1;
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700145#elif defined(TARGET_HPPA)
Richard Henderson8fb3d902018-05-14 13:12:14 -0700146 /* snan_bit_is_one, set msb-1. */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
Taylor Simpsonc0336c82021-04-08 20:07:38 -0500148#elif defined(TARGET_HEXAGON)
149 sign = 1;
150 frac = ~0ULL;
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700151#else
Markus Armbruster43692232021-05-03 10:40:34 +0200152 /*
153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
154 * S390, SH4, TriCore, and Xtensa. Our other supported targets,
155 * CRIS, Nios2, and Tile, do not have floating-point.
Richard Henderson8fb3d902018-05-14 13:12:14 -0700156 */
Richard Henderson03385df2018-05-10 14:48:17 -0700157 if (snan_bit_is_one(status)) {
Richard Henderson8fb3d902018-05-14 13:12:14 -0700158 /* set all bits other than msb */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
160 } else {
Richard Henderson8fb3d902018-05-14 13:12:14 -0700161 /* set msb */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700163 }
164#endif
165
Richard Henderson0fc07ca2020-10-23 14:00:33 -0700166 *p = (FloatParts64) {
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700167 .cls = float_class_qnan,
168 .sign = sign,
169 .exp = INT_MAX,
170 .frac = frac
171 };
172}
173
Richard Hendersone9034ea2020-10-23 16:37:01 -0700174static void parts128_default_nan(FloatParts128 *p, float_status *status)
175{
176 /*
177 * Extrapolate from the choices made by parts64_default_nan to fill
178 * in the quad-floating format. If the low bit is set, assume we
179 * want to set all non-snan bits.
180 */
181 FloatParts64 p64;
182 parts64_default_nan(&p64, status);
183
184 *p = (FloatParts128) {
185 .cls = float_class_qnan,
186 .sign = p64.sign,
187 .exp = INT_MAX,
188 .frac_hi = p64.frac,
189 .frac_lo = -(p64.frac & 1)
190 };
191}
192
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700193/*----------------------------------------------------------------------------
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700194| Returns a quiet NaN from a signalling NaN for the deconstructed
195| floating-point parts.
196*----------------------------------------------------------------------------*/
197
Richard Henderson92ff4262020-10-23 16:23:06 -0700198static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700199{
Max Filippovcc43c692020-06-30 19:35:49 -0700200 g_assert(!no_signaling_nans(status));
Richard Hendersona777d602020-10-22 09:23:46 -0700201
202 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
Richard Henderson03385df2018-05-10 14:48:17 -0700203 if (snan_bit_is_one(status)) {
Richard Henderson92ff4262020-10-23 16:23:06 -0700204 frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
205 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700206 } else {
Richard Henderson92ff4262020-10-23 16:23:06 -0700207 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700208 }
Richard Henderson92ff4262020-10-23 16:23:06 -0700209 return frac;
210}
211
212static void parts64_silence_nan(FloatParts64 *p, float_status *status)
213{
214 p->frac = parts_silence_nan_frac(p->frac, status);
215 p->cls = float_class_qnan;
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700216}
217
Richard Henderson0018b1f2020-10-23 16:36:19 -0700218static void parts128_silence_nan(FloatParts128 *p, float_status *status)
219{
220 p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
221 p->cls = float_class_qnan;
222}
223
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700224/*----------------------------------------------------------------------------
Paolo Bonzini789ec7c2011-07-28 12:10:29 +0200225| The pattern for a default generated extended double-precision NaN.
226*----------------------------------------------------------------------------*/
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200227floatx80 floatx80_default_nan(float_status *status)
228{
229 floatx80 r;
Richard Henderson0218a162018-05-14 13:56:44 -0700230
231 /* None of the targets that have snan_bit_is_one use floatx80. */
232 assert(!snan_bit_is_one(status));
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200233#if defined(TARGET_M68K)
Alex Bennéef7e81a92019-08-12 16:04:02 +0100234 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200235 r.high = 0x7FFF;
236#else
Richard Henderson0218a162018-05-14 13:56:44 -0700237 /* X86 */
Alex Bennéef7e81a92019-08-12 16:04:02 +0100238 r.low = UINT64_C(0xC000000000000000);
Richard Henderson0218a162018-05-14 13:56:44 -0700239 r.high = 0xFFFF;
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200240#endif
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200241 return r;
242}
Paolo Bonzini789ec7c2011-07-28 12:10:29 +0200243
244/*----------------------------------------------------------------------------
Laurent Vivier0f605c82018-02-24 21:18:01 +0100245| The pattern for a default generated extended double-precision inf.
246*----------------------------------------------------------------------------*/
247
248#define floatx80_infinity_high 0x7FFF
249#if defined(TARGET_M68K)
Alex Bennéef7e81a92019-08-12 16:04:02 +0100250#define floatx80_infinity_low UINT64_C(0x0000000000000000)
Laurent Vivier0f605c82018-02-24 21:18:01 +0100251#else
Alex Bennéef7e81a92019-08-12 16:04:02 +0100252#define floatx80_infinity_low UINT64_C(0x8000000000000000)
Laurent Vivier0f605c82018-02-24 21:18:01 +0100253#endif
254
255const floatx80 floatx80_infinity
256 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
257
258/*----------------------------------------------------------------------------
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000259| Returns 1 if the half-precision floating-point value `a' is a quiet
260| NaN; otherwise returns 0.
261*----------------------------------------------------------------------------*/
262
Richard Henderson150c7a92020-05-05 12:16:24 -0700263bool float16_is_quiet_nan(float16 a_, float_status *status)
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000264{
Max Filippovcc43c692020-06-30 19:35:49 -0700265 if (no_signaling_nans(status)) {
266 return float16_is_any_nan(a_);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200267 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700268 uint16_t a = float16_val(a_);
269 if (snan_bit_is_one(status)) {
270 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
271 } else {
272
273 return ((a >> 9) & 0x3F) == 0x3F;
274 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200275 }
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000276}
277
278/*----------------------------------------------------------------------------
LIU Zhiwei5ebf5f42020-08-13 15:14:21 +0800279| Returns 1 if the bfloat16 value `a' is a quiet
280| NaN; otherwise returns 0.
281*----------------------------------------------------------------------------*/
282
283bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
284{
285 if (no_signaling_nans(status)) {
286 return bfloat16_is_any_nan(a_);
287 } else {
288 uint16_t a = a_;
289 if (snan_bit_is_one(status)) {
290 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
291 } else {
292 return ((a >> 6) & 0x1FF) == 0x1FF;
293 }
294 }
295}
296
297/*----------------------------------------------------------------------------
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000298| Returns 1 if the half-precision floating-point value `a' is a signaling
299| NaN; otherwise returns 0.
300*----------------------------------------------------------------------------*/
301
Richard Henderson150c7a92020-05-05 12:16:24 -0700302bool float16_is_signaling_nan(float16 a_, float_status *status)
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000303{
Max Filippovcc43c692020-06-30 19:35:49 -0700304 if (no_signaling_nans(status)) {
305 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200306 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700307 uint16_t a = float16_val(a_);
308 if (snan_bit_is_one(status)) {
309 return ((a >> 9) & 0x3F) == 0x3F;
310 } else {
311 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
312 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200313 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700314}
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000315
316/*----------------------------------------------------------------------------
LIU Zhiwei5ebf5f42020-08-13 15:14:21 +0800317| Returns 1 if the bfloat16 value `a' is a signaling
318| NaN; otherwise returns 0.
319*----------------------------------------------------------------------------*/
320
321bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
322{
323 if (no_signaling_nans(status)) {
324 return 0;
325 } else {
326 uint16_t a = a_;
327 if (snan_bit_is_one(status)) {
328 return ((a >> 6) & 0x1FF) == 0x1FF;
329 } else {
330 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
331 }
332 }
333}
334
335/*----------------------------------------------------------------------------
ths5a6932d2007-11-16 14:57:36 +0000336| Returns 1 if the single-precision floating-point value `a' is a quiet
337| NaN; otherwise returns 0.
bellard158142c2005-03-13 16:54:06 +0000338*----------------------------------------------------------------------------*/
339
Richard Henderson150c7a92020-05-05 12:16:24 -0700340bool float32_is_quiet_nan(float32 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000341{
Max Filippovcc43c692020-06-30 19:35:49 -0700342 if (no_signaling_nans(status)) {
343 return float32_is_any_nan(a_);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200344 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700345 uint32_t a = float32_val(a_);
346 if (snan_bit_is_one(status)) {
347 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
348 } else {
349 return ((uint32_t)(a << 1) >= 0xFF800000);
350 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200351 }
bellard158142c2005-03-13 16:54:06 +0000352}
353
354/*----------------------------------------------------------------------------
355| Returns 1 if the single-precision floating-point value `a' is a signaling
356| NaN; otherwise returns 0.
357*----------------------------------------------------------------------------*/
358
Richard Henderson150c7a92020-05-05 12:16:24 -0700359bool float32_is_signaling_nan(float32 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000360{
Max Filippovcc43c692020-06-30 19:35:49 -0700361 if (no_signaling_nans(status)) {
362 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200363 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700364 uint32_t a = float32_val(a_);
365 if (snan_bit_is_one(status)) {
366 return ((uint32_t)(a << 1) >= 0xFF800000);
367 } else {
368 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
369 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200370 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700371}
bellard158142c2005-03-13 16:54:06 +0000372
373/*----------------------------------------------------------------------------
Peter Maydell354f2112010-12-16 11:51:17 +0000374| Select which NaN to propagate for a two-input operation.
375| IEEE754 doesn't specify all the details of this, so the
376| algorithm is target-specific.
377| The routine is passed various bits of information about the
378| two NaNs and should return 0 to select NaN a and 1 for NaN b.
379| Note that signalling NaNs are always squashed to quiet NaNs
Richard Henderson48853122018-05-10 14:11:15 -0700380| by the caller, by calling floatXX_silence_nan() before
Aurelien Jarno1f398e02011-01-06 15:38:19 +0100381| returning them.
Peter Maydell354f2112010-12-16 11:51:17 +0000382|
383| aIsLargerSignificand is only valid if both a and b are NaNs
384| of some kind, and is true if a has the larger significand,
385| or if both a and b have the same significand but a is
386| positive but b is negative. It is only needed for the x87
387| tie-break rule.
388*----------------------------------------------------------------------------*/
389
Richard Henderson4f251cf2018-05-10 15:21:31 -0700390static int pickNaN(FloatClass a_cls, FloatClass b_cls,
Max Filippov913602e2020-06-30 19:35:57 -0700391 bool aIsLargerSignificand, float_status *status)
Peter Maydell011da612010-12-16 11:51:18 +0000392{
Ilya Leoshkevich63dd7bc2022-07-13 20:26:11 +0200393#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \
Peter Maydellf45fd242022-07-20 14:13:32 +0100394 defined(TARGET_LOONGARCH64) || defined(TARGET_S390X)
Alex Bennée13894522017-07-19 11:49:42 +0100395 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
396 * the first of:
Peter Maydell011da612010-12-16 11:51:18 +0000397 * 1. A if it is signaling
398 * 2. B if it is signaling
399 * 3. A (quiet)
400 * 4. B (quiet)
401 * A signaling NaN is always quietened before returning it.
402 */
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100403 /* According to MIPS specifications, if one of the two operands is
404 * a sNaN, a new qNaN has to be generated. This is done in
Richard Henderson48853122018-05-10 14:11:15 -0700405 * floatXX_silence_nan(). For qNaN inputs the specifications
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100406 * says: "When possible, this QNaN result is one of the operand QNaN
407 * values." In practice it seems that most implementations choose
408 * the first operand if both operands are qNaN. In short this gives
409 * the following rules:
410 * 1. A if it is signaling
411 * 2. B if it is signaling
412 * 3. A (quiet)
413 * 4. B (quiet)
414 * A signaling NaN is always silenced before returning it.
415 */
Richard Henderson4f251cf2018-05-10 15:21:31 -0700416 if (is_snan(a_cls)) {
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100417 return 0;
Richard Henderson4f251cf2018-05-10 15:21:31 -0700418 } else if (is_snan(b_cls)) {
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100419 return 1;
Richard Henderson4f251cf2018-05-10 15:21:31 -0700420 } else if (is_qnan(a_cls)) {
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100421 return 0;
422 } else {
423 return 1;
424 }
Max Filippov913602e2020-06-30 19:35:57 -0700425#elif defined(TARGET_PPC) || defined(TARGET_M68K)
Aurelien Jarnoe024e882011-01-06 15:38:19 +0100426 /* PowerPC propagation rules:
427 * 1. A if it sNaN or qNaN
428 * 2. B if it sNaN or qNaN
429 * A signaling NaN is always silenced before returning it.
430 */
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200431 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
432 * 3.4 FLOATING-POINT INSTRUCTION DETAILS
433 * If either operand, but not both operands, of an operation is a
434 * nonsignaling NaN, then that NaN is returned as the result. If both
435 * operands are nonsignaling NaNs, then the destination operand
436 * nonsignaling NaN is returned as the result.
437 * If either operand to an operation is a signaling NaN (SNaN), then the
438 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
439 * is set in the FPCR ENABLE byte, then the exception is taken and the
440 * destination is not modified. If the SNaN exception enable bit is not
441 * set, setting the SNaN bit in the operand to a one converts the SNaN to
442 * a nonsignaling NaN. The operation then continues as described in the
443 * preceding paragraph for nonsignaling NaNs.
444 */
Richard Henderson4f251cf2018-05-10 15:21:31 -0700445 if (is_nan(a_cls)) {
446 return 0;
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200447 } else {
Richard Henderson4f251cf2018-05-10 15:21:31 -0700448 return 1;
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200449 }
Max Filippov913602e2020-06-30 19:35:57 -0700450#elif defined(TARGET_XTENSA)
451 /*
452 * Xtensa has two NaN propagation modes.
453 * Which one is active is controlled by float_status::use_first_nan.
454 */
455 if (status->use_first_nan) {
456 if (is_nan(a_cls)) {
457 return 0;
458 } else {
459 return 1;
460 }
461 } else {
462 if (is_nan(b_cls)) {
463 return 1;
464 } else {
465 return 0;
466 }
467 }
Peter Maydell011da612010-12-16 11:51:18 +0000468#else
Peter Maydell354f2112010-12-16 11:51:17 +0000469 /* This implements x87 NaN propagation rules:
470 * SNaN + QNaN => return the QNaN
471 * two SNaNs => return the one with the larger significand, silenced
472 * two QNaNs => return the one with the larger significand
473 * SNaN and a non-NaN => return the SNaN, silenced
474 * QNaN and a non-NaN => return the QNaN
475 *
476 * If we get down to comparing significands and they are the same,
477 * return the NaN with the positive sign bit (if any).
478 */
Richard Henderson4f251cf2018-05-10 15:21:31 -0700479 if (is_snan(a_cls)) {
480 if (is_snan(b_cls)) {
Peter Maydell354f2112010-12-16 11:51:17 +0000481 return aIsLargerSignificand ? 0 : 1;
482 }
Richard Henderson4f251cf2018-05-10 15:21:31 -0700483 return is_qnan(b_cls) ? 1 : 0;
484 } else if (is_qnan(a_cls)) {
485 if (is_snan(b_cls) || !is_qnan(b_cls)) {
Peter Maydell354f2112010-12-16 11:51:17 +0000486 return 0;
Aleksandar Markovica59eaea2016-06-10 11:57:29 +0200487 } else {
Peter Maydell354f2112010-12-16 11:51:17 +0000488 return aIsLargerSignificand ? 0 : 1;
489 }
490 } else {
491 return 1;
492 }
Peter Maydell011da612010-12-16 11:51:18 +0000493#endif
Richard Henderson4f251cf2018-05-10 15:21:31 -0700494}
Peter Maydell354f2112010-12-16 11:51:17 +0000495
496/*----------------------------------------------------------------------------
Peter Maydell369be8f2011-10-19 16:14:06 +0000497| Select which NaN to propagate for a three-input operation.
498| For the moment we assume that no CPU needs the 'larger significand'
499| information.
500| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
501*----------------------------------------------------------------------------*/
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700502static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
503 bool infzero, float_status *status)
Peter Maydell369be8f2011-10-19 16:14:06 +0000504{
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700505#if defined(TARGET_ARM)
Peter Maydell369be8f2011-10-19 16:14:06 +0000506 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
507 * the default NaN
508 */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700509 if (infzero && is_qnan(c_cls)) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100510 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Peter Maydell369be8f2011-10-19 16:14:06 +0000511 return 3;
512 }
513
514 /* This looks different from the ARM ARM pseudocode, because the ARM ARM
515 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
516 */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700517 if (is_snan(c_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000518 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700519 } else if (is_snan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000520 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700521 } else if (is_snan(b_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000522 return 1;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700523 } else if (is_qnan(c_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000524 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700525 } else if (is_qnan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000526 return 0;
527 } else {
528 return 1;
529 }
Aurelien Jarnobbc1ded2012-10-09 21:53:20 +0200530#elif defined(TARGET_MIPS)
Richard Henderson03385df2018-05-10 14:48:17 -0700531 if (snan_bit_is_one(status)) {
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100532 /*
533 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
534 * case sets InvalidOp and returns the default NaN
535 */
536 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100537 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100538 return 3;
539 }
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200540 /* Prefer sNaN over qNaN, in the a, b, c order. */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700541 if (is_snan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200542 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700543 } else if (is_snan(b_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200544 return 1;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700545 } else if (is_snan(c_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200546 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700547 } else if (is_qnan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200548 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700549 } else if (is_qnan(b_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200550 return 1;
551 } else {
552 return 2;
553 }
Aurelien Jarnobbc1ded2012-10-09 21:53:20 +0200554 } else {
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100555 /*
556 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
557 * case sets InvalidOp and returns the input value 'c'
558 */
559 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100560 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100561 return 2;
562 }
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200563 /* Prefer sNaN over qNaN, in the c, a, b order. */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700564 if (is_snan(c_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200565 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700566 } else if (is_snan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200567 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700568 } else if (is_snan(b_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200569 return 1;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700570 } else if (is_qnan(c_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200571 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700572 } else if (is_qnan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200573 return 0;
574 } else {
575 return 1;
576 }
Aurelien Jarnobbc1ded2012-10-09 21:53:20 +0200577 }
Song Gao2344f982022-07-16 16:54:20 +0800578#elif defined(TARGET_LOONGARCH64)
579 /*
580 * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
581 * case sets InvalidOp and returns the input value 'c'
582 */
583 if (infzero) {
584 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
585 return 2;
586 }
587 /* Prefer sNaN over qNaN, in the c, a, b order. */
588 if (is_snan(c_cls)) {
589 return 2;
590 } else if (is_snan(a_cls)) {
591 return 0;
592 } else if (is_snan(b_cls)) {
593 return 1;
594 } else if (is_qnan(c_cls)) {
595 return 2;
596 } else if (is_qnan(a_cls)) {
597 return 0;
598 } else {
599 return 1;
600 }
Peter Maydell369be8f2011-10-19 16:14:06 +0000601#elif defined(TARGET_PPC)
Peter Maydell369be8f2011-10-19 16:14:06 +0000602 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
603 * to return an input NaN if we have one (ie c) rather than generating
604 * a default NaN
605 */
606 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100607 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Peter Maydell369be8f2011-10-19 16:14:06 +0000608 return 2;
609 }
610
611 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
612 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
613 */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700614 if (is_nan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000615 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700616 } else if (is_nan(c_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000617 return 2;
618 } else {
619 return 1;
620 }
Frank Chang3a7f7752021-04-20 09:31:48 +0800621#elif defined(TARGET_RISCV)
622 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
623 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100624 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Frank Chang3a7f7752021-04-20 09:31:48 +0800625 }
626 return 3; /* default NaN */
Max Filippovfbcc38e2020-07-03 17:02:47 -0700627#elif defined(TARGET_XTENSA)
628 /*
629 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
630 * an input NaN if we have one (ie c).
631 */
632 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100633 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Max Filippovfbcc38e2020-07-03 17:02:47 -0700634 return 2;
635 }
636 if (status->use_first_nan) {
637 if (is_nan(a_cls)) {
638 return 0;
639 } else if (is_nan(b_cls)) {
640 return 1;
641 } else {
642 return 2;
643 }
644 } else {
645 if (is_nan(c_cls)) {
646 return 2;
647 } else if (is_nan(b_cls)) {
648 return 1;
649 } else {
650 return 0;
651 }
652 }
Peter Maydell369be8f2011-10-19 16:14:06 +0000653#else
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700654 /* A default implementation: prefer a to b to c.
655 * This is unlikely to actually match any real implementation.
656 */
657 if (is_nan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000658 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700659 } else if (is_nan(b_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000660 return 1;
661 } else {
662 return 2;
663 }
Peter Maydell369be8f2011-10-19 16:14:06 +0000664#endif
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700665}
Peter Maydell369be8f2011-10-19 16:14:06 +0000666
667/*----------------------------------------------------------------------------
ths5a6932d2007-11-16 14:57:36 +0000668| Returns 1 if the double-precision floating-point value `a' is a quiet
669| NaN; otherwise returns 0.
bellard158142c2005-03-13 16:54:06 +0000670*----------------------------------------------------------------------------*/
671
Richard Henderson150c7a92020-05-05 12:16:24 -0700672bool float64_is_quiet_nan(float64 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000673{
Max Filippovcc43c692020-06-30 19:35:49 -0700674 if (no_signaling_nans(status)) {
675 return float64_is_any_nan(a_);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200676 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700677 uint64_t a = float64_val(a_);
678 if (snan_bit_is_one(status)) {
679 return (((a >> 51) & 0xFFF) == 0xFFE)
680 && (a & 0x0007FFFFFFFFFFFFULL);
681 } else {
682 return ((a << 1) >= 0xFFF0000000000000ULL);
683 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200684 }
bellard158142c2005-03-13 16:54:06 +0000685}
686
687/*----------------------------------------------------------------------------
688| Returns 1 if the double-precision floating-point value `a' is a signaling
689| NaN; otherwise returns 0.
690*----------------------------------------------------------------------------*/
691
Richard Henderson150c7a92020-05-05 12:16:24 -0700692bool float64_is_signaling_nan(float64 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000693{
Max Filippovcc43c692020-06-30 19:35:49 -0700694 if (no_signaling_nans(status)) {
695 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200696 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700697 uint64_t a = float64_val(a_);
698 if (snan_bit_is_one(status)) {
699 return ((a << 1) >= 0xFFF0000000000000ULL);
700 } else {
701 return (((a >> 51) & 0xFFF) == 0xFFE)
702 && (a & UINT64_C(0x0007FFFFFFFFFFFF));
703 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200704 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700705}
bellard158142c2005-03-13 16:54:06 +0000706
707/*----------------------------------------------------------------------------
bellard158142c2005-03-13 16:54:06 +0000708| Returns 1 if the extended double-precision floating-point value `a' is a
Aurelien Jarnode4af5f2011-01-17 19:29:33 +0100709| quiet NaN; otherwise returns 0. This slightly differs from the same
710| function for other types as floatx80 has an explicit bit.
bellard158142c2005-03-13 16:54:06 +0000711*----------------------------------------------------------------------------*/
712
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200713int floatx80_is_quiet_nan(floatx80 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000714{
Max Filippovcc43c692020-06-30 19:35:49 -0700715 if (no_signaling_nans(status)) {
716 return floatx80_is_any_nan(a);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200717 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700718 if (snan_bit_is_one(status)) {
719 uint64_t aLow;
720
721 aLow = a.low & ~0x4000000000000000ULL;
722 return ((a.high & 0x7FFF) == 0x7FFF)
723 && (aLow << 1)
724 && (a.low == aLow);
725 } else {
726 return ((a.high & 0x7FFF) == 0x7FFF)
727 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
728 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200729 }
bellard158142c2005-03-13 16:54:06 +0000730}
731
732/*----------------------------------------------------------------------------
733| Returns 1 if the extended double-precision floating-point value `a' is a
Aurelien Jarnode4af5f2011-01-17 19:29:33 +0100734| signaling NaN; otherwise returns 0. This slightly differs from the same
735| function for other types as floatx80 has an explicit bit.
bellard158142c2005-03-13 16:54:06 +0000736*----------------------------------------------------------------------------*/
737
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200738int floatx80_is_signaling_nan(floatx80 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000739{
Max Filippovcc43c692020-06-30 19:35:49 -0700740 if (no_signaling_nans(status)) {
741 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200742 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700743 if (snan_bit_is_one(status)) {
744 return ((a.high & 0x7FFF) == 0x7FFF)
745 && ((a.low << 1) >= 0x8000000000000000ULL);
746 } else {
747 uint64_t aLow;
bellard158142c2005-03-13 16:54:06 +0000748
Max Filippovcc43c692020-06-30 19:35:49 -0700749 aLow = a.low & ~UINT64_C(0x4000000000000000);
750 return ((a.high & 0x7FFF) == 0x7FFF)
751 && (uint64_t)(aLow << 1)
752 && (a.low == aLow);
753 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200754 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700755}
bellard158142c2005-03-13 16:54:06 +0000756
757/*----------------------------------------------------------------------------
Richard Hendersond619bb92018-05-10 11:39:48 -0700758| Returns a quiet NaN from a signalling NaN for the extended double-precision
759| floating point value `a'.
760*----------------------------------------------------------------------------*/
761
762floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
763{
Richard Henderson377ed922018-05-14 14:26:38 -0700764 /* None of the targets that have snan_bit_is_one use floatx80. */
765 assert(!snan_bit_is_one(status));
Alex Bennéef7e81a92019-08-12 16:04:02 +0100766 a.low |= UINT64_C(0xC000000000000000);
Richard Henderson377ed922018-05-14 14:26:38 -0700767 return a;
Richard Hendersond619bb92018-05-10 11:39:48 -0700768}
769
770/*----------------------------------------------------------------------------
bellard158142c2005-03-13 16:54:06 +0000771| Takes two extended double-precision floating-point values `a' and `b', one
772| of which is a NaN, and returns the appropriate NaN result. If either `a' or
773| `b' is a signaling NaN, the invalid exception is raised.
774*----------------------------------------------------------------------------*/
775
Laurent Vivier88857ac2018-02-24 21:17:59 +0100776floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000777{
Richard Hendersonc1203912020-05-04 19:54:57 -0700778 bool aIsLargerSignificand;
Richard Henderson4f251cf2018-05-10 15:21:31 -0700779 FloatClass a_cls, b_cls;
bellard158142c2005-03-13 16:54:06 +0000780
Richard Henderson4f251cf2018-05-10 15:21:31 -0700781 /* This is not complete, but is good enough for pickNaN. */
782 a_cls = (!floatx80_is_any_nan(a)
783 ? float_class_normal
784 : floatx80_is_signaling_nan(a, status)
785 ? float_class_snan
786 : float_class_qnan);
787 b_cls = (!floatx80_is_any_nan(b)
788 ? float_class_normal
789 : floatx80_is_signaling_nan(b, status)
790 ? float_class_snan
791 : float_class_qnan);
Aurelien Jarno1f398e02011-01-06 15:38:19 +0100792
Richard Henderson4f251cf2018-05-10 15:21:31 -0700793 if (is_snan(a_cls) || is_snan(b_cls)) {
Peter Maydellff32e162015-02-02 18:47:16 +0000794 float_raise(float_flag_invalid, status);
795 }
Peter Maydell354f2112010-12-16 11:51:17 +0000796
Peter Maydella2f2d282015-02-02 18:57:35 +0000797 if (status->default_nan_mode) {
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200798 return floatx80_default_nan(status);
Aurelien Jarno10201602011-01-14 20:39:17 +0100799 }
800
Peter Maydell354f2112010-12-16 11:51:17 +0000801 if (a.low < b.low) {
802 aIsLargerSignificand = 0;
803 } else if (b.low < a.low) {
804 aIsLargerSignificand = 1;
805 } else {
806 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
bellard158142c2005-03-13 16:54:06 +0000807 }
Peter Maydell354f2112010-12-16 11:51:17 +0000808
Max Filippov913602e2020-06-30 19:35:57 -0700809 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
Richard Henderson4f251cf2018-05-10 15:21:31 -0700810 if (is_snan(b_cls)) {
Richard Henderson48853122018-05-10 14:11:15 -0700811 return floatx80_silence_nan(b, status);
812 }
813 return b;
Peter Maydell354f2112010-12-16 11:51:17 +0000814 } else {
Richard Henderson4f251cf2018-05-10 15:21:31 -0700815 if (is_snan(a_cls)) {
Richard Henderson48853122018-05-10 14:11:15 -0700816 return floatx80_silence_nan(a, status);
817 }
818 return a;
bellard158142c2005-03-13 16:54:06 +0000819 }
bellard158142c2005-03-13 16:54:06 +0000820}
821
bellard158142c2005-03-13 16:54:06 +0000822/*----------------------------------------------------------------------------
ths5a6932d2007-11-16 14:57:36 +0000823| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
824| NaN; otherwise returns 0.
bellard158142c2005-03-13 16:54:06 +0000825*----------------------------------------------------------------------------*/
826
Richard Henderson150c7a92020-05-05 12:16:24 -0700827bool float128_is_quiet_nan(float128 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000828{
Max Filippovcc43c692020-06-30 19:35:49 -0700829 if (no_signaling_nans(status)) {
830 return float128_is_any_nan(a);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200831 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700832 if (snan_bit_is_one(status)) {
833 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
834 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
835 } else {
836 return ((a.high << 1) >= 0xFFFF000000000000ULL)
837 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
838 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200839 }
bellard158142c2005-03-13 16:54:06 +0000840}
841
842/*----------------------------------------------------------------------------
843| Returns 1 if the quadruple-precision floating-point value `a' is a
844| signaling NaN; otherwise returns 0.
845*----------------------------------------------------------------------------*/
846
Richard Henderson150c7a92020-05-05 12:16:24 -0700847bool float128_is_signaling_nan(float128 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000848{
Max Filippovcc43c692020-06-30 19:35:49 -0700849 if (no_signaling_nans(status)) {
850 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200851 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700852 if (snan_bit_is_one(status)) {
853 return ((a.high << 1) >= 0xFFFF000000000000ULL)
854 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
855 } else {
856 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
857 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
858 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200859 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700860}