Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of the Open Source and Linux Lab nor the |
| 13 | * names of its contributors may be used to endorse or promote products |
| 14 | * derived from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include "cpu.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 29 | #include "exec/exec-all.h" |
| 30 | #include "exec/gdbstub.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 31 | #include "qemu/host-utils.h" |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 32 | #if !defined(CONFIG_USER_ONLY) |
| 33 | #include "hw/loader.h" |
| 34 | #endif |
| 35 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 36 | static struct XtensaConfigList *xtensa_cores; |
| 37 | |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 38 | static void xtensa_core_class_init(ObjectClass *oc, void *data) |
| 39 | { |
Andreas Färber | a0e372f | 2013-06-28 23:18:47 +0200 | [diff] [blame] | 40 | CPUClass *cc = CPU_CLASS(oc); |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 41 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); |
| 42 | const XtensaConfig *config = data; |
| 43 | |
| 44 | xcc->config = config; |
Andreas Färber | a0e372f | 2013-06-28 23:18:47 +0200 | [diff] [blame] | 45 | |
| 46 | /* Use num_core_regs to see only non-privileged registers in an unmodified |
| 47 | * gdb. Use num_regs to see all registers. gdb modification is required |
| 48 | * for that: reset bit 0 in the 'flags' field of the registers definitions |
| 49 | * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. |
| 50 | */ |
| 51 | cc->gdb_num_core_regs = config->gdb_regmap.num_regs; |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 52 | } |
| 53 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 54 | void xtensa_register_core(XtensaConfigList *node) |
| 55 | { |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 56 | TypeInfo type = { |
| 57 | .parent = TYPE_XTENSA_CPU, |
| 58 | .class_init = xtensa_core_class_init, |
| 59 | .class_data = (void *)node->config, |
| 60 | }; |
| 61 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 62 | node->next = xtensa_cores; |
| 63 | xtensa_cores = node; |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 64 | type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name); |
| 65 | type_register(&type); |
| 66 | g_free((gpointer)type.name); |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 67 | } |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 68 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 69 | static uint32_t check_hw_breakpoints(CPUXtensaState *env) |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 70 | { |
| 71 | unsigned i; |
| 72 | |
| 73 | for (i = 0; i < env->config->ndbreak; ++i) { |
| 74 | if (env->cpu_watchpoint[i] && |
| 75 | env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { |
| 76 | return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); |
| 77 | } |
| 78 | } |
| 79 | return 0; |
| 80 | } |
| 81 | |
Andreas Färber | 25733ea | 2013-01-20 01:46:45 +0100 | [diff] [blame] | 82 | void xtensa_breakpoint_handler(CPUXtensaState *env) |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 83 | { |
| 84 | if (env->watchpoint_hit) { |
| 85 | if (env->watchpoint_hit->flags & BP_CPU) { |
| 86 | uint32_t cause; |
| 87 | |
| 88 | env->watchpoint_hit = NULL; |
| 89 | cause = check_hw_breakpoints(env); |
| 90 | if (cause) { |
| 91 | debug_exception_env(env, cause); |
| 92 | } |
| 93 | cpu_resume_from_signal(env, NULL); |
| 94 | } |
| 95 | } |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 96 | } |
| 97 | |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 98 | XtensaCPU *cpu_xtensa_init(const char *cpu_model) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 99 | { |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 100 | ObjectClass *oc; |
Andreas Färber | a4633e1 | 2012-04-11 18:24:48 +0200 | [diff] [blame] | 101 | XtensaCPU *cpu; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 102 | CPUXtensaState *env; |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 103 | |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 104 | oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model); |
| 105 | if (oc == NULL) { |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 106 | return NULL; |
| 107 | } |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 108 | |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 109 | cpu = XTENSA_CPU(object_new(object_class_get_name(oc))); |
Andreas Färber | a4633e1 | 2012-04-11 18:24:48 +0200 | [diff] [blame] | 110 | env = &cpu->env; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 111 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 112 | xtensa_irq_init(env); |
Andreas Färber | 5f6c964 | 2013-01-16 04:19:35 +0100 | [diff] [blame] | 113 | |
| 114 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
| 115 | |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 116 | return cpu; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | |
| 120 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) |
| 121 | { |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 122 | XtensaConfigList *core = xtensa_cores; |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 123 | cpu_fprintf(f, "Available CPUs:\n"); |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 124 | for (; core; core = core->next) { |
| 125 | cpu_fprintf(f, " %s\n", core->config->name); |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 126 | } |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 127 | } |
| 128 | |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 129 | hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 130 | { |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 131 | XtensaCPU *cpu = XTENSA_CPU(cs); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 132 | uint32_t paddr; |
| 133 | uint32_t page_size; |
| 134 | unsigned access; |
| 135 | |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 136 | if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 137 | &paddr, &page_size, &access) == 0) { |
| 138 | return paddr; |
| 139 | } |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 140 | if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 141 | &paddr, &page_size, &access) == 0) { |
| 142 | return paddr; |
| 143 | } |
| 144 | return ~0; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 145 | } |
| 146 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 147 | static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 148 | { |
| 149 | if (xtensa_option_enabled(env->config, |
| 150 | XTENSA_OPTION_RELOCATABLE_VECTOR)) { |
| 151 | return vector - env->config->vecbase + env->sregs[VECBASE]; |
| 152 | } else { |
| 153 | return vector; |
| 154 | } |
| 155 | } |
| 156 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 157 | /*! |
| 158 | * Handle penging IRQ. |
| 159 | * For the high priority interrupt jump to the corresponding interrupt vector. |
| 160 | * For the level-1 interrupt convert it to either user, kernel or double |
| 161 | * exception with the 'level-1 interrupt' exception cause. |
| 162 | */ |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 163 | static void handle_interrupt(CPUXtensaState *env) |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 164 | { |
| 165 | int level = env->pending_irq_level; |
| 166 | |
| 167 | if (level > xtensa_get_cintlevel(env) && |
| 168 | level <= env->config->nlevel && |
| 169 | (env->config->level_mask[level] & |
| 170 | env->sregs[INTSET] & |
| 171 | env->sregs[INTENABLE])) { |
| 172 | if (level > 1) { |
| 173 | env->sregs[EPC1 + level - 1] = env->pc; |
| 174 | env->sregs[EPS2 + level - 2] = env->sregs[PS]; |
| 175 | env->sregs[PS] = |
| 176 | (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 177 | env->pc = relocated_vector(env, |
| 178 | env->config->interrupt_vector[level]); |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 179 | } else { |
| 180 | env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE; |
| 181 | |
| 182 | if (env->sregs[PS] & PS_EXCM) { |
| 183 | if (env->config->ndepc) { |
| 184 | env->sregs[DEPC] = env->pc; |
| 185 | } else { |
| 186 | env->sregs[EPC1] = env->pc; |
| 187 | } |
| 188 | env->exception_index = EXC_DOUBLE; |
| 189 | } else { |
| 190 | env->sregs[EPC1] = env->pc; |
| 191 | env->exception_index = |
| 192 | (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; |
| 193 | } |
| 194 | env->sregs[PS] |= PS_EXCM; |
| 195 | } |
| 196 | env->exception_taken = 1; |
| 197 | } |
| 198 | } |
| 199 | |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 200 | void xtensa_cpu_do_interrupt(CPUState *cs) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 201 | { |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 202 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 203 | CPUXtensaState *env = &cpu->env; |
| 204 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 205 | if (env->exception_index == EXC_IRQ) { |
| 206 | qemu_log_mask(CPU_LOG_INT, |
| 207 | "%s(EXC_IRQ) level = %d, cintlevel = %d, " |
| 208 | "pc = %08x, a0 = %08x, ps = %08x, " |
| 209 | "intset = %08x, intenable = %08x, " |
| 210 | "ccount = %08x\n", |
| 211 | __func__, env->pending_irq_level, xtensa_get_cintlevel(env), |
| 212 | env->pc, env->regs[0], env->sregs[PS], |
| 213 | env->sregs[INTSET], env->sregs[INTENABLE], |
| 214 | env->sregs[CCOUNT]); |
| 215 | handle_interrupt(env); |
| 216 | } |
| 217 | |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 218 | switch (env->exception_index) { |
| 219 | case EXC_WINDOW_OVERFLOW4: |
| 220 | case EXC_WINDOW_UNDERFLOW4: |
| 221 | case EXC_WINDOW_OVERFLOW8: |
| 222 | case EXC_WINDOW_UNDERFLOW8: |
| 223 | case EXC_WINDOW_OVERFLOW12: |
| 224 | case EXC_WINDOW_UNDERFLOW12: |
| 225 | case EXC_KERNEL: |
| 226 | case EXC_USER: |
| 227 | case EXC_DOUBLE: |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 228 | case EXC_DEBUG: |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 229 | qemu_log_mask(CPU_LOG_INT, "%s(%d) " |
| 230 | "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", |
| 231 | __func__, env->exception_index, |
| 232 | env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 233 | if (env->config->exception_vector[env->exception_index]) { |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 234 | env->pc = relocated_vector(env, |
| 235 | env->config->exception_vector[env->exception_index]); |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 236 | env->exception_taken = 1; |
| 237 | } else { |
| 238 | qemu_log("%s(pc = %08x) bad exception_index: %d\n", |
| 239 | __func__, env->pc, env->exception_index); |
| 240 | } |
| 241 | break; |
| 242 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 243 | case EXC_IRQ: |
| 244 | break; |
| 245 | |
| 246 | default: |
| 247 | qemu_log("%s(pc = %08x) unknown exception_index: %d\n", |
| 248 | __func__, env->pc, env->exception_index); |
| 249 | break; |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 250 | } |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 251 | check_interrupts(env); |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 252 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 253 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 254 | static void reset_tlb_mmu_all_ways(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 255 | const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
| 256 | { |
| 257 | unsigned wi, ei; |
| 258 | |
| 259 | for (wi = 0; wi < tlb->nways; ++wi) { |
| 260 | for (ei = 0; ei < tlb->way_size[wi]; ++ei) { |
| 261 | entry[wi][ei].asid = 0; |
| 262 | entry[wi][ei].variable = true; |
| 263 | } |
| 264 | } |
| 265 | } |
| 266 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 267 | static void reset_tlb_mmu_ways56(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 268 | const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
| 269 | { |
| 270 | if (!tlb->varway56) { |
| 271 | static const xtensa_tlb_entry way5[] = { |
| 272 | { |
| 273 | .vaddr = 0xd0000000, |
| 274 | .paddr = 0, |
| 275 | .asid = 1, |
| 276 | .attr = 7, |
| 277 | .variable = false, |
| 278 | }, { |
| 279 | .vaddr = 0xd8000000, |
| 280 | .paddr = 0, |
| 281 | .asid = 1, |
| 282 | .attr = 3, |
| 283 | .variable = false, |
| 284 | } |
| 285 | }; |
| 286 | static const xtensa_tlb_entry way6[] = { |
| 287 | { |
| 288 | .vaddr = 0xe0000000, |
| 289 | .paddr = 0xf0000000, |
| 290 | .asid = 1, |
| 291 | .attr = 7, |
| 292 | .variable = false, |
| 293 | }, { |
| 294 | .vaddr = 0xf0000000, |
| 295 | .paddr = 0xf0000000, |
| 296 | .asid = 1, |
| 297 | .attr = 3, |
| 298 | .variable = false, |
| 299 | } |
| 300 | }; |
| 301 | memcpy(entry[5], way5, sizeof(way5)); |
| 302 | memcpy(entry[6], way6, sizeof(way6)); |
| 303 | } else { |
| 304 | uint32_t ei; |
| 305 | for (ei = 0; ei < 8; ++ei) { |
| 306 | entry[6][ei].vaddr = ei << 29; |
| 307 | entry[6][ei].paddr = ei << 29; |
| 308 | entry[6][ei].asid = 1; |
Max Filippov | 0fdd2e1 | 2011-11-22 11:59:16 +0400 | [diff] [blame] | 309 | entry[6][ei].attr = 3; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 310 | } |
| 311 | } |
| 312 | } |
| 313 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 314 | static void reset_tlb_region_way0(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 315 | xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
| 316 | { |
| 317 | unsigned ei; |
| 318 | |
| 319 | for (ei = 0; ei < 8; ++ei) { |
| 320 | entry[0][ei].vaddr = ei << 29; |
| 321 | entry[0][ei].paddr = ei << 29; |
| 322 | entry[0][ei].asid = 1; |
| 323 | entry[0][ei].attr = 2; |
| 324 | entry[0][ei].variable = true; |
| 325 | } |
| 326 | } |
| 327 | |
Andreas Färber | 5087a72 | 2012-04-11 18:24:49 +0200 | [diff] [blame] | 328 | void reset_mmu(CPUXtensaState *env) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 329 | { |
| 330 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { |
| 331 | env->sregs[RASID] = 0x04030201; |
| 332 | env->sregs[ITLBCFG] = 0; |
| 333 | env->sregs[DTLBCFG] = 0; |
| 334 | env->autorefill_idx = 0; |
| 335 | reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); |
| 336 | reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); |
| 337 | reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); |
| 338 | reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); |
| 339 | } else { |
| 340 | reset_tlb_region_way0(env, env->itlb); |
| 341 | reset_tlb_region_way0(env, env->dtlb); |
| 342 | } |
| 343 | } |
| 344 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 345 | static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 346 | { |
| 347 | unsigned i; |
| 348 | for (i = 0; i < 4; ++i) { |
| 349 | if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { |
| 350 | return i; |
| 351 | } |
| 352 | } |
| 353 | return 0xff; |
| 354 | } |
| 355 | |
| 356 | /*! |
| 357 | * Lookup xtensa TLB for the given virtual address. |
| 358 | * See ISA, 4.6.2.2 |
| 359 | * |
| 360 | * \param pwi: [out] way index |
| 361 | * \param pei: [out] entry index |
| 362 | * \param pring: [out] access ring |
| 363 | * \return 0 if ok, exception cause code otherwise |
| 364 | */ |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 365 | int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 366 | uint32_t *pwi, uint32_t *pei, uint8_t *pring) |
| 367 | { |
| 368 | const xtensa_tlb *tlb = dtlb ? |
| 369 | &env->config->dtlb : &env->config->itlb; |
| 370 | const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? |
| 371 | env->dtlb : env->itlb; |
| 372 | |
| 373 | int nhits = 0; |
| 374 | unsigned wi; |
| 375 | |
| 376 | for (wi = 0; wi < tlb->nways; ++wi) { |
| 377 | uint32_t vpn; |
| 378 | uint32_t ei; |
| 379 | split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); |
| 380 | if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { |
| 381 | unsigned ring = get_ring(env, entry[wi][ei].asid); |
| 382 | if (ring < 4) { |
| 383 | if (++nhits > 1) { |
| 384 | return dtlb ? |
| 385 | LOAD_STORE_TLB_MULTI_HIT_CAUSE : |
| 386 | INST_TLB_MULTI_HIT_CAUSE; |
| 387 | } |
| 388 | *pwi = wi; |
| 389 | *pei = ei; |
| 390 | *pring = ring; |
| 391 | } |
| 392 | } |
| 393 | } |
| 394 | return nhits ? 0 : |
| 395 | (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); |
| 396 | } |
| 397 | |
| 398 | /*! |
| 399 | * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. |
| 400 | * See ISA, 4.6.5.10 |
| 401 | */ |
| 402 | static unsigned mmu_attr_to_access(uint32_t attr) |
| 403 | { |
| 404 | unsigned access = 0; |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 405 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 406 | if (attr < 12) { |
| 407 | access |= PAGE_READ; |
| 408 | if (attr & 0x1) { |
| 409 | access |= PAGE_EXEC; |
| 410 | } |
| 411 | if (attr & 0x2) { |
| 412 | access |= PAGE_WRITE; |
| 413 | } |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 414 | |
| 415 | switch (attr & 0xc) { |
| 416 | case 0: |
| 417 | access |= PAGE_CACHE_BYPASS; |
| 418 | break; |
| 419 | |
| 420 | case 4: |
| 421 | access |= PAGE_CACHE_WB; |
| 422 | break; |
| 423 | |
| 424 | case 8: |
| 425 | access |= PAGE_CACHE_WT; |
| 426 | break; |
| 427 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 428 | } else if (attr == 13) { |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 429 | access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 430 | } |
| 431 | return access; |
| 432 | } |
| 433 | |
| 434 | /*! |
| 435 | * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. |
| 436 | * See ISA, 4.6.3.3 |
| 437 | */ |
| 438 | static unsigned region_attr_to_access(uint32_t attr) |
| 439 | { |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 440 | static const unsigned access[16] = { |
| 441 | [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, |
| 442 | [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, |
| 443 | [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, |
| 444 | [3] = PAGE_EXEC | PAGE_CACHE_WB, |
| 445 | [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, |
| 446 | [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, |
| 447 | [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, |
| 448 | }; |
| 449 | |
| 450 | return access[attr & 0xf]; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 451 | } |
| 452 | |
Max Filippov | 4e41d2f | 2012-12-05 07:15:21 +0400 | [diff] [blame] | 453 | /*! |
| 454 | * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. |
| 455 | * See ISA, A.2.14 The Cache Attribute Register |
| 456 | */ |
| 457 | static unsigned cacheattr_attr_to_access(uint32_t attr) |
| 458 | { |
| 459 | static const unsigned access[16] = { |
| 460 | [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, |
| 461 | [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, |
| 462 | [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, |
| 463 | [3] = PAGE_EXEC | PAGE_CACHE_WB, |
| 464 | [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, |
| 465 | [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, |
| 466 | }; |
| 467 | |
| 468 | return access[attr & 0xf]; |
| 469 | } |
| 470 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 471 | static bool is_access_granted(unsigned access, int is_write) |
| 472 | { |
| 473 | switch (is_write) { |
| 474 | case 0: |
| 475 | return access & PAGE_READ; |
| 476 | |
| 477 | case 1: |
| 478 | return access & PAGE_WRITE; |
| 479 | |
| 480 | case 2: |
| 481 | return access & PAGE_EXEC; |
| 482 | |
| 483 | default: |
| 484 | return 0; |
| 485 | } |
| 486 | } |
| 487 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 488 | static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 489 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 490 | static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 491 | uint32_t vaddr, int is_write, int mmu_idx, |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 492 | uint32_t *paddr, uint32_t *page_size, unsigned *access, |
| 493 | bool may_lookup_pt) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 494 | { |
| 495 | bool dtlb = is_write != 2; |
| 496 | uint32_t wi; |
| 497 | uint32_t ei; |
| 498 | uint8_t ring; |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 499 | uint32_t vpn; |
| 500 | uint32_t pte; |
| 501 | const xtensa_tlb_entry *entry = NULL; |
| 502 | xtensa_tlb_entry tmp_entry; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 503 | int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); |
| 504 | |
| 505 | if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 506 | may_lookup_pt && get_pte(env, vaddr, &pte) == 0) { |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 507 | ring = (pte >> 4) & 0x3; |
| 508 | wi = 0; |
| 509 | split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); |
| 510 | |
| 511 | if (update_tlb) { |
| 512 | wi = ++env->autorefill_idx & 0x3; |
| 513 | xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); |
| 514 | env->sregs[EXCVADDR] = vaddr; |
| 515 | qemu_log("%s: autorefill(%08x): %08x -> %08x\n", |
| 516 | __func__, vaddr, vpn, pte); |
| 517 | } else { |
| 518 | xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); |
| 519 | entry = &tmp_entry; |
| 520 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 521 | ret = 0; |
| 522 | } |
| 523 | if (ret != 0) { |
| 524 | return ret; |
| 525 | } |
| 526 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 527 | if (entry == NULL) { |
| 528 | entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); |
| 529 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 530 | |
| 531 | if (ring < mmu_idx) { |
| 532 | return dtlb ? |
| 533 | LOAD_STORE_PRIVILEGE_CAUSE : |
| 534 | INST_FETCH_PRIVILEGE_CAUSE; |
| 535 | } |
| 536 | |
Max Filippov | 659f807 | 2012-12-13 04:13:41 +0400 | [diff] [blame] | 537 | *access = mmu_attr_to_access(entry->attr) & |
| 538 | ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 539 | if (!is_access_granted(*access, is_write)) { |
| 540 | return dtlb ? |
| 541 | (is_write ? |
| 542 | STORE_PROHIBITED_CAUSE : |
| 543 | LOAD_PROHIBITED_CAUSE) : |
| 544 | INST_FETCH_PROHIBITED_CAUSE; |
| 545 | } |
| 546 | |
| 547 | *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); |
| 548 | *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; |
| 549 | |
| 550 | return 0; |
| 551 | } |
| 552 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 553 | static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 554 | { |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 555 | CPUState *cs = ENV_GET_CPU(env); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 556 | uint32_t paddr; |
| 557 | uint32_t page_size; |
| 558 | unsigned access; |
| 559 | uint32_t pt_vaddr = |
| 560 | (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 561 | int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 562 | &paddr, &page_size, &access, false); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 563 | |
| 564 | qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__, |
| 565 | vaddr, ret ? ~0 : paddr); |
| 566 | |
| 567 | if (ret == 0) { |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 568 | *pte = ldl_phys(cs->as, paddr); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 569 | } |
| 570 | return ret; |
| 571 | } |
| 572 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 573 | static int get_physical_addr_region(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 574 | uint32_t vaddr, int is_write, int mmu_idx, |
| 575 | uint32_t *paddr, uint32_t *page_size, unsigned *access) |
| 576 | { |
| 577 | bool dtlb = is_write != 2; |
| 578 | uint32_t wi = 0; |
| 579 | uint32_t ei = (vaddr >> 29) & 0x7; |
| 580 | const xtensa_tlb_entry *entry = |
| 581 | xtensa_tlb_get_entry(env, dtlb, wi, ei); |
| 582 | |
| 583 | *access = region_attr_to_access(entry->attr); |
| 584 | if (!is_access_granted(*access, is_write)) { |
| 585 | return dtlb ? |
| 586 | (is_write ? |
| 587 | STORE_PROHIBITED_CAUSE : |
| 588 | LOAD_PROHIBITED_CAUSE) : |
| 589 | INST_FETCH_PROHIBITED_CAUSE; |
| 590 | } |
| 591 | |
| 592 | *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); |
| 593 | *page_size = ~REGION_PAGE_MASK + 1; |
| 594 | |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | /*! |
| 599 | * Convert virtual address to physical addr. |
| 600 | * MMU may issue pagewalk and change xtensa autorefill TLB way entry. |
| 601 | * |
| 602 | * \return 0 if ok, exception cause code otherwise |
| 603 | */ |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 604 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 605 | uint32_t vaddr, int is_write, int mmu_idx, |
| 606 | uint32_t *paddr, uint32_t *page_size, unsigned *access) |
| 607 | { |
| 608 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 609 | return get_physical_addr_mmu(env, update_tlb, |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 610 | vaddr, is_write, mmu_idx, paddr, page_size, access, true); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 611 | } else if (xtensa_option_bits_enabled(env->config, |
| 612 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | |
| 613 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { |
| 614 | return get_physical_addr_region(env, vaddr, is_write, mmu_idx, |
| 615 | paddr, page_size, access); |
| 616 | } else { |
| 617 | *paddr = vaddr; |
| 618 | *page_size = TARGET_PAGE_SIZE; |
Max Filippov | 4e41d2f | 2012-12-05 07:15:21 +0400 | [diff] [blame] | 619 | *access = cacheattr_attr_to_access( |
| 620 | env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27)); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 621 | return 0; |
| 622 | } |
| 623 | } |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 624 | |
| 625 | static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 626 | CPUXtensaState *env, bool dtlb) |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 627 | { |
| 628 | unsigned wi, ei; |
| 629 | const xtensa_tlb *conf = |
| 630 | dtlb ? &env->config->dtlb : &env->config->itlb; |
| 631 | unsigned (*attr_to_access)(uint32_t) = |
| 632 | xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? |
| 633 | mmu_attr_to_access : region_attr_to_access; |
| 634 | |
| 635 | for (wi = 0; wi < conf->nways; ++wi) { |
| 636 | uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; |
| 637 | const char *sz_text; |
| 638 | bool print_header = true; |
| 639 | |
| 640 | if (sz >= 0x100000) { |
| 641 | sz >>= 20; |
| 642 | sz_text = "MB"; |
| 643 | } else { |
| 644 | sz >>= 10; |
| 645 | sz_text = "KB"; |
| 646 | } |
| 647 | |
| 648 | for (ei = 0; ei < conf->way_size[wi]; ++ei) { |
| 649 | const xtensa_tlb_entry *entry = |
| 650 | xtensa_tlb_get_entry(env, dtlb, wi, ei); |
| 651 | |
| 652 | if (entry->asid) { |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 653 | static const char * const cache_text[8] = { |
| 654 | [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", |
| 655 | [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", |
| 656 | [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", |
| 657 | [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", |
| 658 | }; |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 659 | unsigned access = attr_to_access(entry->attr); |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 660 | unsigned cache_idx = (access & PAGE_CACHE_MASK) >> |
| 661 | PAGE_CACHE_SHIFT; |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 662 | |
| 663 | if (print_header) { |
| 664 | print_header = false; |
| 665 | cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); |
| 666 | cpu_fprintf(f, |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 667 | "\tVaddr Paddr ASID Attr RWX Cache\n" |
| 668 | "\t---------- ---------- ---- ---- --- -------\n"); |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 669 | } |
| 670 | cpu_fprintf(f, |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 671 | "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 672 | entry->vaddr, |
| 673 | entry->paddr, |
| 674 | entry->asid, |
| 675 | entry->attr, |
| 676 | (access & PAGE_READ) ? 'R' : '-', |
| 677 | (access & PAGE_WRITE) ? 'W' : '-', |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 678 | (access & PAGE_EXEC) ? 'X' : '-', |
| 679 | cache_text[cache_idx] ? cache_text[cache_idx] : |
| 680 | "Invalid"); |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 681 | } |
| 682 | } |
| 683 | } |
| 684 | } |
| 685 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 686 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 687 | { |
| 688 | if (xtensa_option_bits_enabled(env->config, |
| 689 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | |
| 690 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | |
| 691 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { |
| 692 | |
| 693 | cpu_fprintf(f, "ITLB:\n"); |
| 694 | dump_tlb(f, cpu_fprintf, env, false); |
| 695 | cpu_fprintf(f, "\nDTLB:\n"); |
| 696 | dump_tlb(f, cpu_fprintf, env, true); |
| 697 | } else { |
| 698 | cpu_fprintf(f, "No TLB for this CPU core\n"); |
| 699 | } |
| 700 | } |