Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 1 | config ARM_VIRT |
| 2 | bool |
Paolo Bonzini | 1a67aed | 2024-01-25 13:36:37 +0100 | [diff] [blame] | 3 | default y |
| 4 | depends on ARM |
Thomas Huth | 7951c7b | 2019-02-08 07:17:55 +0100 | [diff] [blame] | 5 | imply PCI_DEVICES |
| 6 | imply TEST_DEVICES |
| 7 | imply VFIO_AMD_XGBE |
Paolo Bonzini | e0e312f | 2019-01-23 14:56:01 +0800 | [diff] [blame] | 8 | imply VFIO_PLATFORM |
Thomas Huth | 7951c7b | 2019-02-08 07:17:55 +0100 | [diff] [blame] | 9 | imply VFIO_XGMAC |
Eric Auger | c294ac3 | 2020-03-05 17:51:45 +0100 | [diff] [blame] | 10 | imply TPM_TIS_SYSBUS |
Ninad Palsule | 139fdb3 | 2023-04-14 17:07:54 -0500 | [diff] [blame] | 11 | imply TPM_TIS_I2C |
Philippe Mathieu-Daudé | cfa1f4b | 2021-05-11 17:53:50 +0200 | [diff] [blame] | 12 | imply NVDIMM |
Cédric Le Goater | 0970238 | 2023-11-21 16:44:18 +0800 | [diff] [blame] | 13 | imply IOMMUFD |
Andrew Jones | 3362c56 | 2020-11-17 12:56:32 +0000 | [diff] [blame] | 14 | select ARM_GIC |
Thomas Huth | 7951c7b | 2019-02-08 07:17:55 +0100 | [diff] [blame] | 15 | select ACPI |
| 16 | select ARM_SMMUV3 |
| 17 | select GPIO_KEY |
Paolo Bonzini | d641ec3 | 2024-04-30 21:08:15 +0200 | [diff] [blame] | 18 | select DEVICE_TREE |
Thomas Huth | 7951c7b | 2019-02-08 07:17:55 +0100 | [diff] [blame] | 19 | select FW_CFG_DMA |
| 20 | select PCI_EXPRESS |
| 21 | select PCI_EXPRESS_GENERIC_BRIDGE |
| 22 | select PFLASH_CFI01 |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 23 | select PL011 if !HAVE_RUST # UART |
| 24 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 7951c7b | 2019-02-08 07:17:55 +0100 | [diff] [blame] | 25 | select PL031 # RTC |
| 26 | select PL061 # GPIO |
Maxim Uvarov | daa726d | 2021-01-28 12:00:11 +0000 | [diff] [blame] | 27 | select GPIO_PWR |
Thomas Huth | 7951c7b | 2019-02-08 07:17:55 +0100 | [diff] [blame] | 28 | select PLATFORM_BUS |
| 29 | select SMBIOS |
| 30 | select VIRTIO_MMIO |
Wei Yang | f13a944 | 2019-05-21 14:28:35 +0800 | [diff] [blame] | 31 | select ACPI_PCI |
Eric Auger | 1f283ae | 2019-09-18 14:06:26 +0100 | [diff] [blame] | 32 | select MEM_DEVICE |
| 33 | select DIMM |
Shameer Kolothum | cff51ac | 2019-09-18 14:06:27 +0100 | [diff] [blame] | 34 | select ACPI_HW_REDUCED |
Philippe Mathieu-Daudé | b77a52a | 2020-10-08 18:14:14 +0200 | [diff] [blame] | 35 | select ACPI_APEI |
Jean-Philippe Brucker | cf1a5cc | 2021-12-10 17:04:09 +0000 | [diff] [blame] | 36 | select ACPI_VIOT |
Gavin Shan | b1b8732 | 2022-01-11 14:33:29 +0800 | [diff] [blame] | 37 | select VIRTIO_MEM_SUPPORTED |
Jonathan Cameron | fc1e01e | 2022-04-29 15:40:54 +0100 | [diff] [blame] | 38 | select ACPI_CXL |
Xiang Chen | 7cbd3fd | 2022-10-27 11:00:35 +0100 | [diff] [blame] | 39 | select ACPI_HMAT |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 40 | |
Thomas Huth | 5885e66 | 2019-02-08 10:18:15 +0100 | [diff] [blame] | 41 | config CUBIEBOARD |
| 42 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 43 | default y |
| 44 | depends on TCG && ARM |
Thomas Huth | 5885e66 | 2019-02-08 10:18:15 +0100 | [diff] [blame] | 45 | select ALLWINNER_A10 |
| 46 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 47 | config DIGIC |
| 48 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 49 | default y |
| 50 | depends on TCG && ARM |
Paolo Bonzini | 9533dcd | 2019-01-23 14:56:12 +0800 | [diff] [blame] | 51 | select PTIMER |
Thomas Huth | 627b06e | 2019-02-08 10:55:38 +0100 | [diff] [blame] | 52 | select PFLASH_CFI02 |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 53 | |
| 54 | config EXYNOS4 |
| 55 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 56 | default y |
| 57 | depends on TCG && ARM |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 58 | imply I2C_DEVICES |
Thomas Huth | bb275e4 | 2019-02-07 10:28:01 +0100 | [diff] [blame] | 59 | select A9MPCORE |
| 60 | select I2C |
| 61 | select LAN9118 |
| 62 | select PL310 # cache controller |
Paolo Bonzini | 9533dcd | 2019-01-23 14:56:12 +0800 | [diff] [blame] | 63 | select PTIMER |
Thomas Huth | bb275e4 | 2019-02-07 10:28:01 +0100 | [diff] [blame] | 64 | select SDHCI |
| 65 | select USB_EHCI_SYSBUS |
Philippe Mathieu-Daudé | 5900c7a | 2021-01-31 19:44:45 +0100 | [diff] [blame] | 66 | select OR_IRQ |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 67 | |
| 68 | config HIGHBANK |
| 69 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 70 | default y |
| 71 | depends on TCG && ARM |
Thomas Huth | 08bcda0 | 2019-02-07 10:35:22 +0100 | [diff] [blame] | 72 | select A9MPCORE |
| 73 | select A15MPCORE |
| 74 | select AHCI |
| 75 | select ARM_TIMER # sp804 |
| 76 | select ARM_V7M |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 77 | select PL011 if !HAVE_RUST # UART |
| 78 | select X_PL011_RUST if HAVE_RUST # UART |
Philippe Mathieu-Daudé | 58f7f3c | 2020-06-17 09:25:36 +0200 | [diff] [blame] | 79 | select PL022 # SPI |
Thomas Huth | 08bcda0 | 2019-02-07 10:35:22 +0100 | [diff] [blame] | 80 | select PL031 # RTC |
| 81 | select PL061 # GPIO |
| 82 | select PL310 # cache controller |
| 83 | select XGMAC # ethernet |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 84 | |
| 85 | config INTEGRATOR |
| 86 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 87 | default y |
| 88 | depends on TCG && ARM |
Thomas Huth | 4cdea98 | 2019-02-07 15:21:27 +0100 | [diff] [blame] | 89 | select ARM_TIMER |
| 90 | select INTEGRATOR_DEBUG |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 91 | select PL011 if !HAVE_RUST # UART |
| 92 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 4cdea98 | 2019-02-07 15:21:27 +0100 | [diff] [blame] | 93 | select PL031 # RTC |
Philippe Mathieu-Daudé | 5df2cfb | 2020-02-24 00:30:32 +0100 | [diff] [blame] | 94 | select PL041 # audio |
Thomas Huth | 4cdea98 | 2019-02-07 15:21:27 +0100 | [diff] [blame] | 95 | select PL050 # keyboard/mouse |
| 96 | select PL110 # pl111 LCD controller |
| 97 | select PL181 # display |
| 98 | select SMC91C111 |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 99 | |
Peter Maydell | 273a70a | 2024-02-06 13:29:26 +0000 | [diff] [blame] | 100 | config MPS3R |
| 101 | bool |
| 102 | default y |
| 103 | depends on TCG && ARM |
| 104 | |
Thomas Huth | 08cbacc | 2019-02-22 19:09:51 +0100 | [diff] [blame] | 105 | config MUSCA |
| 106 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 107 | default y |
| 108 | depends on TCG && ARM |
Thomas Huth | 08cbacc | 2019-02-22 19:09:51 +0100 | [diff] [blame] | 109 | select ARMSSE |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 110 | select PL011 if !HAVE_RUST # UART |
| 111 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 08cbacc | 2019-02-22 19:09:51 +0100 | [diff] [blame] | 112 | select PL031 |
Thomas Huth | 853c016 | 2019-05-14 10:24:28 +0200 | [diff] [blame] | 113 | select SPLIT_IRQ |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 114 | select UNIMP |
Thomas Huth | 08cbacc | 2019-02-22 19:09:51 +0100 | [diff] [blame] | 115 | |
Philippe Mathieu-Daudé | 9adfbf1 | 2022-01-07 19:44:27 +0100 | [diff] [blame] | 116 | config MARVELL_88W8618 |
| 117 | bool |
| 118 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 119 | config MUSICPAL |
| 120 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 121 | default y |
| 122 | depends on TCG && ARM |
Philippe Mathieu-Daudé | 498661d | 2020-11-07 20:34:02 +0100 | [diff] [blame] | 123 | select OR_IRQ |
Thomas Huth | 59dd3eb | 2019-02-07 17:05:38 +0100 | [diff] [blame] | 124 | select BITBANG_I2C |
| 125 | select MARVELL_88W8618 |
Paolo Bonzini | 9533dcd | 2019-01-23 14:56:12 +0800 | [diff] [blame] | 126 | select PTIMER |
Thomas Huth | 59dd3eb | 2019-02-07 17:05:38 +0100 | [diff] [blame] | 127 | select PFLASH_CFI02 |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 128 | select SERIAL_MM |
Thomas Huth | 59dd3eb | 2019-02-07 17:05:38 +0100 | [diff] [blame] | 129 | select WM8750 |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 130 | |
| 131 | config NETDUINO2 |
| 132 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 133 | default y |
| 134 | depends on TCG && ARM |
Thomas Huth | 6239ac7 | 2019-02-08 08:52:57 +0100 | [diff] [blame] | 135 | select STM32F205_SOC |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 136 | |
Alistair Francis | 870c034 | 2020-01-17 14:09:29 +0000 | [diff] [blame] | 137 | config NETDUINOPLUS2 |
| 138 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 139 | default y |
| 140 | depends on TCG && ARM |
Alistair Francis | 870c034 | 2020-01-17 14:09:29 +0000 | [diff] [blame] | 141 | select STM32F405_SOC |
| 142 | |
Felipe Balbi | ee5bffa | 2022-12-30 16:57:33 +0200 | [diff] [blame] | 143 | config OLIMEX_STM32_H405 |
| 144 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 145 | default y |
| 146 | depends on TCG && ARM |
Felipe Balbi | ee5bffa | 2022-12-30 16:57:33 +0200 | [diff] [blame] | 147 | select STM32F405_SOC |
| 148 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 149 | config OMAP |
| 150 | bool |
Thomas Huth | 4826ac6 | 2019-02-07 17:12:14 +0100 | [diff] [blame] | 151 | select FRAMEBUFFER |
| 152 | select I2C |
Thomas Huth | 4826ac6 | 2019-02-07 17:12:14 +0100 | [diff] [blame] | 153 | select NAND |
| 154 | select PFLASH_CFI01 |
| 155 | select SD |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 156 | select SERIAL_MM |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 157 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 158 | config REALVIEW |
| 159 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 160 | default y |
| 161 | depends on TCG && ARM |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 162 | imply PCI_DEVICES |
| 163 | imply PCI_TESTDEV |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 164 | imply I2C_DEVICES |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 165 | select SMC91C111 |
| 166 | select LAN9118 |
| 167 | select A9MPCORE |
| 168 | select A15MPCORE |
| 169 | select ARM11MPCORE |
| 170 | select ARM_TIMER |
| 171 | select VERSATILE_PCI |
| 172 | select WM8750 # audio codec |
| 173 | select LSI_SCSI_PCI |
| 174 | select PCI |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 175 | select PL011 if !HAVE_RUST # UART |
| 176 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 177 | select PL031 # RTC |
| 178 | select PL041 # audio codec |
| 179 | select PL050 # keyboard/mouse |
| 180 | select PL061 # GPIO |
| 181 | select PL080 # DMA controller |
| 182 | select PL110 |
| 183 | select PL181 # display |
| 184 | select PL310 # cache controller |
Philippe Mathieu-Daudé | 500a64d | 2023-01-10 09:25:08 +0100 | [diff] [blame] | 185 | select ARM_SBCON_I2C |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 186 | select DS1338 # I2C RTC+NVRAM |
Paolo Bonzini | 15f07fb | 2024-02-23 13:44:05 +0100 | [diff] [blame] | 187 | select USB_OHCI_SYSBUS |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 188 | |
Hongbo Zhang | 6458090 | 2019-07-01 17:26:18 +0100 | [diff] [blame] | 189 | config SBSA_REF |
| 190 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 191 | default y |
| 192 | depends on TCG && AARCH64 |
Hongbo Zhang | 6458090 | 2019-07-01 17:26:18 +0100 | [diff] [blame] | 193 | imply PCI_DEVICES |
Paolo Bonzini | d641ec3 | 2024-04-30 21:08:15 +0200 | [diff] [blame] | 194 | select DEVICE_TREE |
Hongbo Zhang | 6458090 | 2019-07-01 17:26:18 +0100 | [diff] [blame] | 195 | select AHCI |
| 196 | select ARM_SMMUV3 |
| 197 | select GPIO_KEY |
| 198 | select PCI_EXPRESS |
| 199 | select PCI_EXPRESS_GENERIC_BRIDGE |
| 200 | select PFLASH_CFI01 |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 201 | select PL011 if !HAVE_RUST # UART |
| 202 | select X_PL011_RUST if HAVE_RUST # UART |
Hongbo Zhang | 6458090 | 2019-07-01 17:26:18 +0100 | [diff] [blame] | 203 | select PL031 # RTC |
| 204 | select PL061 # GPIO |
Yuquan Wang | 62c2b87 | 2023-07-04 14:08:47 +0100 | [diff] [blame] | 205 | select USB_XHCI_SYSBUS |
Shashi Mallela | 4204c5f | 2020-10-26 21:59:26 -0400 | [diff] [blame] | 206 | select WDT_SBSA |
Marcin Juszkiewicz | 93faf3b | 2023-06-07 11:21:12 +0200 | [diff] [blame] | 207 | select BOCHS_DISPLAY |
Thomas Huth | 7bd8b0d | 2024-02-20 09:55:00 +0100 | [diff] [blame] | 208 | select IDE_BUS |
| 209 | select IDE_DEV |
Hongbo Zhang | 6458090 | 2019-07-01 17:26:18 +0100 | [diff] [blame] | 210 | |
Thomas Huth | 5c6e99a | 2019-02-08 11:28:13 +0100 | [diff] [blame] | 211 | config SABRELITE |
| 212 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 213 | default y |
| 214 | depends on TCG && ARM |
Thomas Huth | 5c6e99a | 2019-02-08 11:28:13 +0100 | [diff] [blame] | 215 | select FSL_IMX6 |
| 216 | select SSI_M25P80 |
| 217 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 218 | config STELLARIS |
| 219 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 220 | default y |
| 221 | depends on TCG && ARM |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 222 | imply I2C_DEVICES |
Thomas Huth | 782ef8c | 2019-02-07 17:33:50 +0100 | [diff] [blame] | 223 | select ARM_V7M |
| 224 | select CMSDK_APB_WATCHDOG |
| 225 | select I2C |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 226 | select PL011 if !HAVE_RUST # UART |
| 227 | select X_PL011_RUST if HAVE_RUST # UART |
Philippe Mathieu-Daudé | 58f7f3c | 2020-06-17 09:25:36 +0200 | [diff] [blame] | 228 | select PL022 # SPI |
Thomas Huth | 782ef8c | 2019-02-07 17:33:50 +0100 | [diff] [blame] | 229 | select PL061 # GPIO |
| 230 | select SSD0303 # OLED display |
| 231 | select SSD0323 # OLED display |
| 232 | select SSI_SD |
Peter Maydell | c45460d | 2023-10-30 11:47:57 +0000 | [diff] [blame] | 233 | select STELLARIS_GAMEPAD |
Thomas Huth | 782ef8c | 2019-02-07 17:33:50 +0100 | [diff] [blame] | 234 | select STELLARIS_ENET # ethernet |
Peter Maydell | f3eb755 | 2021-08-12 10:33:54 +0100 | [diff] [blame] | 235 | select STELLARIS_GPTM # general purpose timer module |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 236 | select UNIMP |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 237 | |
Alexandre Iooss | 2ac2410 | 2021-06-17 18:56:45 +0200 | [diff] [blame] | 238 | config STM32VLDISCOVERY |
| 239 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 240 | default y |
| 241 | depends on TCG && ARM |
Alexandre Iooss | 2ac2410 | 2021-06-17 18:56:45 +0200 | [diff] [blame] | 242 | select STM32F100_SOC |
| 243 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 244 | config STRONGARM |
| 245 | bool |
Peter Maydell | 4dba046 | 2024-09-03 17:07:11 +0100 | [diff] [blame] | 246 | select PXA2XX_TIMER |
| 247 | select SSI |
Thomas Huth | 839507a | 2019-02-08 06:39:48 +0100 | [diff] [blame] | 248 | |
| 249 | config COLLIE |
| 250 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 251 | default y |
| 252 | depends on TCG && ARM |
Thomas Huth | 839507a | 2019-02-08 06:39:48 +0100 | [diff] [blame] | 253 | select PFLASH_CFI01 |
Peter Maydell | 504f935 | 2024-09-03 17:07:05 +0100 | [diff] [blame] | 254 | select ZAURUS_SCOOP |
Thomas Huth | 839507a | 2019-02-08 06:39:48 +0100 | [diff] [blame] | 255 | select STRONGARM |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 256 | |
Thomas Huth | 4826ac6 | 2019-02-07 17:12:14 +0100 | [diff] [blame] | 257 | config SX1 |
| 258 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 259 | default y |
| 260 | depends on TCG && ARM |
Thomas Huth | 4826ac6 | 2019-02-07 17:12:14 +0100 | [diff] [blame] | 261 | select OMAP |
| 262 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 263 | config VERSATILE |
| 264 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 265 | default y |
| 266 | depends on TCG && ARM |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 267 | select ARM_TIMER # sp804 |
| 268 | select PFLASH_CFI01 |
| 269 | select LSI_SCSI_PCI |
| 270 | select PL050 # keyboard/mouse |
| 271 | select PL080 # DMA controller |
| 272 | select PL190 # Vector PIC |
| 273 | select REALVIEW |
Paolo Bonzini | 15f07fb | 2024-02-23 13:44:05 +0100 | [diff] [blame] | 274 | select USB_OHCI_SYSBUS |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 275 | |
| 276 | config VEXPRESS |
| 277 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 278 | default y |
| 279 | depends on TCG && ARM |
Paolo Bonzini | d641ec3 | 2024-04-30 21:08:15 +0200 | [diff] [blame] | 280 | select DEVICE_TREE |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 281 | select A9MPCORE |
| 282 | select A15MPCORE |
| 283 | select ARM_MPTIMER |
| 284 | select ARM_TIMER # sp804 |
| 285 | select LAN9118 |
| 286 | select PFLASH_CFI01 |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 287 | select PL011 if !HAVE_RUST # UART |
| 288 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 79e93e2 | 2019-02-07 20:05:05 +0100 | [diff] [blame] | 289 | select PL041 # audio codec |
| 290 | select PL181 # display |
| 291 | select REALVIEW |
| 292 | select SII9022 |
| 293 | select VIRTIO_MMIO |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 294 | |
| 295 | config ZYNQ |
| 296 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 297 | default y |
| 298 | depends on TCG && ARM |
Thomas Huth | 31576a9 | 2019-02-07 20:26:34 +0100 | [diff] [blame] | 299 | select A9MPCORE |
| 300 | select CADENCE # UART |
| 301 | select PFLASH_CFI02 |
Sebastian Huber | f271877 | 2024-05-24 14:08:36 +0200 | [diff] [blame] | 302 | select PL310 # cache controller |
Thomas Huth | 31576a9 | 2019-02-07 20:26:34 +0100 | [diff] [blame] | 303 | select PL330 |
| 304 | select SDHCI |
| 305 | select SSI_M25P80 |
| 306 | select USB_EHCI_SYSBUS |
| 307 | select XILINX # UART |
| 308 | select XILINX_AXI |
| 309 | select XILINX_SPI |
| 310 | select XILINX_SPIPS |
| 311 | select ZYNQ_DEVCFG |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 312 | |
| 313 | config ARM_V7M |
| 314 | bool |
Alex Bennée | cd43648 | 2021-07-07 14:17:42 +0100 | [diff] [blame] | 315 | # currently v7M must be included in a TCG build due to translate.c |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 316 | default y |
| 317 | depends on TCG && ARM |
Andrew Jones | 9ad5f6b | 2020-11-04 11:33:43 +0100 | [diff] [blame] | 318 | select PTIMER |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 319 | |
| 320 | config ALLWINNER_A10 |
| 321 | bool |
Thomas Huth | 5885e66 | 2019-02-08 10:18:15 +0100 | [diff] [blame] | 322 | select AHCI |
| 323 | select ALLWINNER_A10_PIT |
| 324 | select ALLWINNER_A10_PIC |
Strahinja Jankovic | 423ec28 | 2022-12-26 23:02:57 +0100 | [diff] [blame] | 325 | select ALLWINNER_A10_CCM |
Strahinja Jankovic | edd3a59 | 2022-12-26 23:02:58 +0100 | [diff] [blame] | 326 | select ALLWINNER_A10_DRAMC |
Strahinja Jankovic | 470f9f2 | 2023-04-20 10:21:13 +0100 | [diff] [blame] | 327 | select ALLWINNER_WDT |
Thomas Huth | 5885e66 | 2019-02-08 10:18:15 +0100 | [diff] [blame] | 328 | select ALLWINNER_EMAC |
Strahinja Jankovic | 9be8a82 | 2022-12-26 23:02:59 +0100 | [diff] [blame] | 329 | select ALLWINNER_I2C |
Strahinja Jankovic | 3341d1c | 2024-10-14 17:05:52 +0100 | [diff] [blame] | 330 | select ALLWINNER_A10_SPI |
qianfan Zhao | a954543 | 2023-06-06 10:19:32 +0100 | [diff] [blame] | 331 | select AXP2XX_PMU |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 332 | select SERIAL_MM |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 333 | select UNIMP |
Paolo Bonzini | 15f07fb | 2024-02-23 13:44:05 +0100 | [diff] [blame] | 334 | select USB_OHCI_SYSBUS |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 335 | |
Niek Linnenbank | 740dafc | 2020-03-11 23:18:37 +0100 | [diff] [blame] | 336 | config ALLWINNER_H3 |
| 337 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 338 | default y |
| 339 | depends on TCG && ARM |
Niek Linnenbank | 740dafc | 2020-03-11 23:18:37 +0100 | [diff] [blame] | 340 | select ALLWINNER_A10_PIT |
Niek Linnenbank | 29d0897 | 2020-03-11 23:18:45 +0100 | [diff] [blame] | 341 | select ALLWINNER_SUN8I_EMAC |
Strahinja Jankovic | 9be8a82 | 2022-12-26 23:02:59 +0100 | [diff] [blame] | 342 | select ALLWINNER_I2C |
Strahinja Jankovic | c663fc9 | 2023-04-20 10:21:14 +0100 | [diff] [blame] | 343 | select ALLWINNER_WDT |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 344 | select SERIAL_MM |
Niek Linnenbank | 740dafc | 2020-03-11 23:18:37 +0100 | [diff] [blame] | 345 | select ARM_TIMER |
| 346 | select ARM_GIC |
| 347 | select UNIMP |
Paolo Bonzini | 15f07fb | 2024-02-23 13:44:05 +0100 | [diff] [blame] | 348 | select USB_OHCI_SYSBUS |
Niek Linnenbank | 2e4dfe8 | 2020-03-11 23:18:40 +0100 | [diff] [blame] | 349 | select USB_EHCI_SYSBUS |
Niek Linnenbank | 82e4838 | 2020-03-11 23:18:44 +0100 | [diff] [blame] | 350 | select SD |
Niek Linnenbank | 740dafc | 2020-03-11 23:18:37 +0100 | [diff] [blame] | 351 | |
qianfan Zhao | 8d9006a | 2023-06-06 10:19:31 +0100 | [diff] [blame] | 352 | config ALLWINNER_R40 |
| 353 | bool |
| 354 | default y if TCG && ARM |
Guenter Roeck | 2a02da7 | 2024-01-15 10:27:56 -0800 | [diff] [blame] | 355 | select AHCI |
qianfan Zhao | 05def91 | 2023-06-06 10:19:33 +0100 | [diff] [blame] | 356 | select ALLWINNER_SRAMC |
qianfan Zhao | 8d9006a | 2023-06-06 10:19:31 +0100 | [diff] [blame] | 357 | select ALLWINNER_A10_PIT |
Guenter Roeck | 2af71d2 | 2024-01-15 10:27:57 -0800 | [diff] [blame] | 358 | select ALLWINNER_WDT |
qianfan Zhao | a954543 | 2023-06-06 10:19:32 +0100 | [diff] [blame] | 359 | select AXP2XX_PMU |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 360 | select SERIAL_MM |
qianfan Zhao | 8d9006a | 2023-06-06 10:19:31 +0100 | [diff] [blame] | 361 | select ARM_TIMER |
| 362 | select ARM_GIC |
| 363 | select UNIMP |
Paolo Bonzini | 15f07fb | 2024-02-23 13:44:05 +0100 | [diff] [blame] | 364 | select USB_OHCI_SYSBUS |
Guenter Roeck | 43eef24 | 2024-01-15 10:27:55 -0800 | [diff] [blame] | 365 | select USB_EHCI_SYSBUS |
qianfan Zhao | 8d9006a | 2023-06-06 10:19:31 +0100 | [diff] [blame] | 366 | select SD |
| 367 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 368 | config RASPI |
| 369 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 370 | default y |
| 371 | depends on TCG && ARM |
Thomas Huth | 1ad846a | 2019-02-08 10:22:54 +0100 | [diff] [blame] | 372 | select FRAMEBUFFER |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 373 | select PL011 if !HAVE_RUST # UART |
| 374 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 1ad846a | 2019-02-08 10:22:54 +0100 | [diff] [blame] | 375 | select SDHCI |
Thomas Huth | 8d94298 | 2020-07-22 17:47:19 +0200 | [diff] [blame] | 376 | select USB_DWC2 |
Rayhan Faizel | f09c2b7 | 2024-01-30 03:48:08 +0530 | [diff] [blame] | 377 | select BCM2835_SPI |
Rayhan Faizel | f5c6320 | 2024-02-25 00:40:37 +0530 | [diff] [blame] | 378 | select BCM2835_I2C |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 379 | |
Alexandre Iooss | 0f76deb | 2021-06-17 18:56:44 +0200 | [diff] [blame] | 380 | config STM32F100_SOC |
| 381 | bool |
| 382 | select ARM_V7M |
| 383 | select STM32F2XX_USART |
| 384 | select STM32F2XX_SPI |
| 385 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 386 | config STM32F205_SOC |
| 387 | bool |
Thomas Huth | 6239ac7 | 2019-02-08 08:52:57 +0100 | [diff] [blame] | 388 | select ARM_V7M |
Thomas Huth | 282467f | 2019-05-14 08:13:28 +0200 | [diff] [blame] | 389 | select OR_IRQ |
Thomas Huth | 6239ac7 | 2019-02-08 08:52:57 +0100 | [diff] [blame] | 390 | select STM32F2XX_TIMER |
| 391 | select STM32F2XX_USART |
| 392 | select STM32F2XX_SYSCFG |
| 393 | select STM32F2XX_ADC |
| 394 | select STM32F2XX_SPI |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 395 | |
Alistair Francis | 870c034 | 2020-01-17 14:09:29 +0000 | [diff] [blame] | 396 | config STM32F405_SOC |
| 397 | bool |
| 398 | select ARM_V7M |
Philippe Mathieu-Daudé | 9e39983 | 2021-01-31 19:44:44 +0100 | [diff] [blame] | 399 | select OR_IRQ |
Román Cárdenas Rodríguez | 950dff9 | 2024-10-14 17:05:50 +0100 | [diff] [blame] | 400 | select STM32_RCC |
Alistair Francis | 870c034 | 2020-01-17 14:09:29 +0000 | [diff] [blame] | 401 | select STM32F4XX_SYSCFG |
Alistair Francis | e64d8c8 | 2020-01-17 14:09:29 +0000 | [diff] [blame] | 402 | select STM32F4XX_EXTI |
Alistair Francis | 870c034 | 2020-01-17 14:09:29 +0000 | [diff] [blame] | 403 | |
Inès Varhol | 41581f1 | 2024-01-08 14:58:29 +0100 | [diff] [blame] | 404 | config B_L475E_IOT01A |
| 405 | bool |
| 406 | default y |
| 407 | depends on TCG && ARM |
| 408 | select STM32L4X5_SOC |
Inès Varhol | 4915720 | 2024-04-24 22:06:54 +0200 | [diff] [blame] | 409 | imply DM163 |
Inès Varhol | 41581f1 | 2024-01-08 14:58:29 +0100 | [diff] [blame] | 410 | |
Inès Varhol | 04a7c7b | 2024-01-08 14:58:28 +0100 | [diff] [blame] | 411 | config STM32L4X5_SOC |
| 412 | bool |
| 413 | select ARM_V7M |
| 414 | select OR_IRQ |
Inès Varhol | 52671f6 | 2024-01-09 17:06:03 +0100 | [diff] [blame] | 415 | select STM32L4X5_EXTI |
Inès Varhol | 1c38129 | 2024-03-05 22:03:11 +0100 | [diff] [blame] | 416 | select STM32L4X5_SYSCFG |
Arnaud Minier | d6b55a0 | 2024-03-03 15:06:36 +0100 | [diff] [blame] | 417 | select STM32L4X5_RCC |
Inès Varhol | 1c38129 | 2024-03-05 22:03:11 +0100 | [diff] [blame] | 418 | select STM32L4X5_GPIO |
Arnaud Minier | 9274143 | 2024-03-29 18:44:01 +0100 | [diff] [blame] | 419 | select STM32L4X5_USART |
Inès Varhol | 04a7c7b | 2024-01-08 14:58:28 +0100 | [diff] [blame] | 420 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 421 | config XLNX_ZYNQMP_ARM |
| 422 | bool |
Marc-André Lureau | 04c4cc1 | 2023-08-30 13:38:38 +0400 | [diff] [blame] | 423 | default y if PIXMAN |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 424 | depends on TCG && AARCH64 |
Thomas Huth | f3c3a1e | 2019-02-08 14:52:40 +0100 | [diff] [blame] | 425 | select AHCI |
| 426 | select ARM_GIC |
| 427 | select CADENCE |
Thomas Huth | 259181d | 2024-04-15 08:56:55 +0200 | [diff] [blame] | 428 | select CPU_CLUSTER |
Thomas Huth | f3c3a1e | 2019-02-08 14:52:40 +0100 | [diff] [blame] | 429 | select DDC |
| 430 | select DPCD |
Paolo Bonzini | d641ec3 | 2024-04-30 21:08:15 +0200 | [diff] [blame] | 431 | select DEVICE_TREE |
Thomas Huth | f3c3a1e | 2019-02-08 14:52:40 +0100 | [diff] [blame] | 432 | select SDHCI |
| 433 | select SSI |
| 434 | select SSI_M25P80 |
| 435 | select XILINX_AXI |
| 436 | select XILINX_SPIPS |
Xuzhou Cheng | 668351a | 2021-03-03 21:52:52 +0800 | [diff] [blame] | 437 | select XLNX_CSU_DMA |
Marc-André Lureau | 04c4cc1 | 2023-08-30 13:38:38 +0400 | [diff] [blame] | 438 | select XLNX_DISPLAYPORT |
Thomas Huth | f3c3a1e | 2019-02-08 14:52:40 +0100 | [diff] [blame] | 439 | select XLNX_ZYNQMP |
Philippe Mathieu-Daudé | 6bfaec7 | 2021-01-31 19:44:46 +0100 | [diff] [blame] | 440 | select XLNX_ZDMA |
Philippe Mathieu-Daudé | f4880c2 | 2023-02-16 10:23:27 +0100 | [diff] [blame] | 441 | select USB_DWC3 |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 442 | |
| 443 | config XLNX_VERSAL |
| 444 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 445 | default y |
| 446 | depends on TCG && AARCH64 |
Thomas Huth | 24c7bb3 | 2019-02-09 07:16:05 +0100 | [diff] [blame] | 447 | select ARM_GIC |
Thomas Huth | 259181d | 2024-04-15 08:56:55 +0200 | [diff] [blame] | 448 | select CPU_CLUSTER |
Paolo Bonzini | d641ec3 | 2024-04-30 21:08:15 +0200 | [diff] [blame] | 449 | select DEVICE_TREE |
Paolo Bonzini | d0f0cd5 | 2024-10-10 16:11:28 +0200 | [diff] [blame] | 450 | select PL011 if !HAVE_RUST # UART |
| 451 | select X_PL011_RUST if HAVE_RUST # UART |
Thomas Huth | 24c7bb3 | 2019-02-09 07:16:05 +0100 | [diff] [blame] | 452 | select CADENCE |
| 453 | select VIRTIO_MMIO |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 454 | select UNIMP |
Philippe Mathieu-Daudé | 6bfaec7 | 2021-01-31 19:44:46 +0100 | [diff] [blame] | 455 | select XLNX_ZDMA |
Philippe Mathieu-Daudé | 1de3b49 | 2021-01-31 19:44:47 +0100 | [diff] [blame] | 456 | select XLNX_ZYNQMP |
Alex Bennée | d064c19 | 2021-07-07 14:17:41 +0100 | [diff] [blame] | 457 | select OR_IRQ |
Tong Ho | 393185b | 2021-09-16 22:23:56 -0700 | [diff] [blame] | 458 | select XLNX_BBRAM |
Tong Ho | 5f4910f | 2021-09-16 22:23:57 -0700 | [diff] [blame] | 459 | select XLNX_EFUSE_VERSAL |
Fabiano Rosas | b9353ac | 2023-05-03 10:12:29 +0100 | [diff] [blame] | 460 | select XLNX_USB_SUBSYS |
Tong Ho | 3b22376 | 2023-10-31 11:46:10 -0700 | [diff] [blame] | 461 | select XLNX_VERSAL_TRNG |
Marc-André Lureau | b271b6a | 2023-11-03 19:09:03 +0400 | [diff] [blame] | 462 | select XLNX_CSU_DMA |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 463 | |
Havard Skinnemoen | e5a7ba8 | 2020-09-10 22:20:48 -0700 | [diff] [blame] | 464 | config NPCM7XX |
| 465 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 466 | default y |
| 467 | depends on TCG && ARM |
Havard Skinnemoen | 2d8f048 | 2020-09-10 22:20:51 -0700 | [diff] [blame] | 468 | select A9MPCORE |
Titus Rwantare | 6f351a7 | 2023-10-23 23:46:44 +0000 | [diff] [blame] | 469 | select ADM1266 |
Titus Rwantare | c93488f | 2021-07-08 10:25:53 -0700 | [diff] [blame] | 470 | select ADM1272 |
Havard Skinnemoen | 2d8f048 | 2020-09-10 22:20:51 -0700 | [diff] [blame] | 471 | select ARM_GIC |
Philippe Mathieu-Daudé | d43bb04 | 2021-05-13 08:55:50 +0200 | [diff] [blame] | 472 | select SMBUS |
Hao Wu | 2ef1e0d | 2021-02-10 14:04:24 -0800 | [diff] [blame] | 473 | select AT24C # EEPROM |
Titus Rwantare | 7215456 | 2021-07-08 10:25:55 -0700 | [diff] [blame] | 474 | select MAX34451 |
Titus Rwantare | ffcdae6 | 2022-03-07 12:06:03 -0800 | [diff] [blame] | 475 | select ISL_PMBUS_VR |
Havard Skinnemoen | 2d8f048 | 2020-09-10 22:20:51 -0700 | [diff] [blame] | 476 | select PL310 # cache controller |
Titus Rwantare | 3746d5c | 2021-07-08 10:25:52 -0700 | [diff] [blame] | 477 | select PMBUS |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 478 | select SERIAL_MM |
Havard Skinnemoen | b821242 | 2020-09-10 22:20:57 -0700 | [diff] [blame] | 479 | select SSI |
Havard Skinnemoen | 2d8f048 | 2020-09-10 22:20:51 -0700 | [diff] [blame] | 480 | select UNIMP |
Patrick Venture | 6229659 | 2021-06-08 13:25:21 -0700 | [diff] [blame] | 481 | select PCA954X |
Paolo Bonzini | 15f07fb | 2024-02-23 13:44:05 +0100 | [diff] [blame] | 482 | select USB_OHCI_SYSBUS |
Havard Skinnemoen | e5a7ba8 | 2020-09-10 22:20:48 -0700 | [diff] [blame] | 483 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 484 | config FSL_IMX25 |
| 485 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 486 | default y |
| 487 | depends on TCG && ARM |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 488 | imply I2C_DEVICES |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 489 | select IMX |
| 490 | select IMX_FEC |
| 491 | select IMX_I2C |
Guenter Roeck | 4f0aff0 | 2020-05-17 09:21:30 -0700 | [diff] [blame] | 492 | select WDT_IMX2 |
Philippe Mathieu-Daudé | ee9ffe0 | 2021-05-13 15:20:23 +0200 | [diff] [blame] | 493 | select SDHCI |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 494 | |
| 495 | config FSL_IMX31 |
| 496 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 497 | default y |
| 498 | depends on TCG && ARM |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 499 | imply I2C_DEVICES |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 500 | select SERIAL_MM |
Thomas Huth | 73129f4 | 2019-02-07 16:51:56 +0100 | [diff] [blame] | 501 | select IMX |
| 502 | select IMX_I2C |
Guenter Roeck | b9e521d | 2020-05-17 09:21:31 -0700 | [diff] [blame] | 503 | select WDT_IMX2 |
Thomas Huth | 73129f4 | 2019-02-07 16:51:56 +0100 | [diff] [blame] | 504 | select LAN9118 |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 505 | |
| 506 | config FSL_IMX6 |
| 507 | bool |
Nikita Ostrenkov | 5e6be95 | 2024-01-08 14:03:25 +0000 | [diff] [blame] | 508 | imply PCIE_DEVICES |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 509 | imply I2C_DEVICES |
Thomas Huth | 5c6e99a | 2019-02-08 11:28:13 +0100 | [diff] [blame] | 510 | select A9MPCORE |
| 511 | select IMX |
| 512 | select IMX_FEC |
| 513 | select IMX_I2C |
Guenter Roeck | 0701a5e | 2020-03-12 18:45:47 -0700 | [diff] [blame] | 514 | select IMX_USBPHY |
Guenter Roeck | 37f95959 | 2020-05-17 09:21:28 -0700 | [diff] [blame] | 515 | select WDT_IMX2 |
Nikita Ostrenkov | f7f5784 | 2024-01-08 14:32:58 +0000 | [diff] [blame] | 516 | select PL310 # cache controller |
Nikita Ostrenkov | 5e6be95 | 2024-01-08 14:03:25 +0000 | [diff] [blame] | 517 | select PCI_EXPRESS_DESIGNWARE |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 518 | select SDHCI |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 519 | |
| 520 | config ASPEED_SOC |
| 521 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 522 | default y |
| 523 | depends on TCG && ARM |
Thomas Huth | 68e44dd | 2019-02-08 06:53:04 +0100 | [diff] [blame] | 524 | select DS1338 |
| 525 | select FTGMAC100 |
| 526 | select I2C |
Joel Stanley | 46560cb | 2021-09-20 08:50:59 +0200 | [diff] [blame] | 527 | select DPS310 |
Thomas Huth | 68e44dd | 2019-02-08 06:53:04 +0100 | [diff] [blame] | 528 | select PCA9552 |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 529 | select SERIAL_MM |
Thomas Huth | 68e44dd | 2019-02-08 06:53:04 +0100 | [diff] [blame] | 530 | select SMBUS_EEPROM |
Patrick Venture | 3ec75e3 | 2021-06-08 13:25:22 -0700 | [diff] [blame] | 531 | select PCA954X |
Thomas Huth | 68e44dd | 2019-02-08 06:53:04 +0100 | [diff] [blame] | 532 | select SSI |
| 533 | select SSI_M25P80 |
| 534 | select TMP105 |
| 535 | select TMP421 |
John Wang | 5e623f2 | 2020-12-10 12:11:03 +0100 | [diff] [blame] | 536 | select EMC141X |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 537 | select UNIMP |
Philippe Mathieu-Daudé | 7cfbde5 | 2020-06-20 18:54:41 +0200 | [diff] [blame] | 538 | select LED |
Maheswara Kurapati | 2a75e8c | 2022-06-30 09:21:13 +0200 | [diff] [blame] | 539 | select PMBUS |
| 540 | select MAX31785 |
Ninad Palsule | eb04c35 | 2024-01-26 04:49:52 -0600 | [diff] [blame] | 541 | select FSI_APB2OPB_ASPEED |
Patrick Leis | deb771d | 2024-10-28 18:14:20 +0000 | [diff] [blame] | 542 | select AT24C |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 543 | |
| 544 | config MPS2 |
| 545 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 546 | default y |
| 547 | depends on TCG && ARM |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 548 | imply I2C_DEVICES |
Thomas Huth | d2a99d7 | 2019-02-08 10:19:41 +0100 | [diff] [blame] | 549 | select ARMSSE |
| 550 | select LAN9118 |
| 551 | select MPS2_FPGAIO |
| 552 | select MPS2_SCC |
Thomas Huth | 282467f | 2019-05-14 08:13:28 +0200 | [diff] [blame] | 553 | select OR_IRQ |
Philippe Mathieu-Daudé | 58f7f3c | 2020-06-17 09:25:36 +0200 | [diff] [blame] | 554 | select PL022 # SPI |
Thomas Huth | d2a99d7 | 2019-02-08 10:19:41 +0100 | [diff] [blame] | 555 | select PL080 # DMA controller |
Thomas Huth | 853c016 | 2019-05-14 10:24:28 +0200 | [diff] [blame] | 556 | select SPLIT_IRQ |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 557 | select UNIMP |
Philippe Mathieu-Daudé | ecbe51a | 2020-06-17 09:25:33 +0200 | [diff] [blame] | 558 | select CMSDK_APB_WATCHDOG |
Philippe Mathieu-Daudé | 500a64d | 2023-01-10 09:25:08 +0100 | [diff] [blame] | 559 | select ARM_SBCON_I2C |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 560 | |
| 561 | config FSL_IMX7 |
| 562 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 563 | default y |
| 564 | depends on TCG && ARM |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 565 | imply PCI_DEVICES |
| 566 | imply TEST_DEVICES |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 567 | imply I2C_DEVICES |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 568 | select A15MPCORE |
| 569 | select PCI |
| 570 | select IMX |
| 571 | select IMX_FEC |
| 572 | select IMX_I2C |
Guenter Roeck | 37f95959 | 2020-05-17 09:21:28 -0700 | [diff] [blame] | 573 | select WDT_IMX2 |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 574 | select PCI_EXPRESS_DESIGNWARE |
| 575 | select SDHCI |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 576 | select UNIMP |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 577 | |
| 578 | config ARM_SMMUV3 |
| 579 | bool |
| 580 | |
| 581 | config FSL_IMX6UL |
| 582 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 583 | default y |
| 584 | depends on TCG && ARM |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 585 | imply I2C_DEVICES |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 586 | select A15MPCORE |
| 587 | select IMX |
| 588 | select IMX_FEC |
| 589 | select IMX_I2C |
Guenter Roeck | 37f95959 | 2020-05-17 09:21:28 -0700 | [diff] [blame] | 590 | select WDT_IMX2 |
Thomas Huth | 0204762 | 2019-02-08 13:18:31 +0100 | [diff] [blame] | 591 | select SDHCI |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 592 | select UNIMP |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 593 | |
Thomas Huth | c1c60b0 | 2019-02-08 13:33:40 +0100 | [diff] [blame] | 594 | config MICROBIT |
| 595 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 596 | default y |
| 597 | depends on TCG && ARM |
Thomas Huth | c1c60b0 | 2019-02-08 13:33:40 +0100 | [diff] [blame] | 598 | select NRF51_SOC |
| 599 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 600 | config NRF51_SOC |
| 601 | bool |
Peter Maydell | e117e97 | 2022-02-08 15:59:11 +0000 | [diff] [blame] | 602 | imply I2C_DEVICES |
Thomas Huth | c1c60b0 | 2019-02-08 13:33:40 +0100 | [diff] [blame] | 603 | select I2C |
| 604 | select ARM_V7M |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 605 | select UNIMP |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 606 | |
Thomas Huth | b6e2b22 | 2019-02-08 12:00:29 +0100 | [diff] [blame] | 607 | config EMCRAFT_SF2 |
| 608 | bool |
Fabiano Rosas | 441d701 | 2023-05-23 15:05:25 -0300 | [diff] [blame] | 609 | default y |
| 610 | depends on TCG && ARM |
Thomas Huth | b6e2b22 | 2019-02-08 12:00:29 +0100 | [diff] [blame] | 611 | select MSF2 |
| 612 | select SSI_M25P80 |
| 613 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 614 | config MSF2 |
| 615 | bool |
Thomas Huth | b6e2b22 | 2019-02-08 12:00:29 +0100 | [diff] [blame] | 616 | select ARM_V7M |
Paolo Bonzini | 9533dcd | 2019-01-23 14:56:12 +0800 | [diff] [blame] | 617 | select PTIMER |
Bernhard Beschow | 7e6b549 | 2024-09-05 09:38:32 +0200 | [diff] [blame] | 618 | select SERIAL_MM |
Thomas Huth | b6e2b22 | 2019-02-08 12:00:29 +0100 | [diff] [blame] | 619 | select SSI |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 620 | select UNIMP |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 621 | |
Paolo Bonzini | 82f5181 | 2019-01-23 14:56:00 +0800 | [diff] [blame] | 622 | config ARMSSE |
| 623 | bool |
Thomas Huth | d2a99d7 | 2019-02-08 10:19:41 +0100 | [diff] [blame] | 624 | select ARM_V7M |
Peter Maydell | 4239b31 | 2021-02-19 14:45:53 +0000 | [diff] [blame] | 625 | select ARMSSE_CPU_PWRCTRL |
Thomas Huth | d2a99d7 | 2019-02-08 10:19:41 +0100 | [diff] [blame] | 626 | select ARMSSE_CPUID |
| 627 | select ARMSSE_MHU |
| 628 | select CMSDK_APB_TIMER |
| 629 | select CMSDK_APB_DUALTIMER |
| 630 | select CMSDK_APB_UART |
| 631 | select CMSDK_APB_WATCHDOG |
Thomas Huth | 259181d | 2024-04-15 08:56:55 +0200 | [diff] [blame] | 632 | select CPU_CLUSTER |
Thomas Huth | d2a99d7 | 2019-02-08 10:19:41 +0100 | [diff] [blame] | 633 | select IOTKIT_SECCTL |
| 634 | select IOTKIT_SYSCTL |
| 635 | select IOTKIT_SYSINFO |
Thomas Huth | 282467f | 2019-05-14 08:13:28 +0200 | [diff] [blame] | 636 | select OR_IRQ |
Thomas Huth | 853c016 | 2019-05-14 10:24:28 +0200 | [diff] [blame] | 637 | select SPLIT_IRQ |
Thomas Huth | d2a99d7 | 2019-02-08 10:19:41 +0100 | [diff] [blame] | 638 | select TZ_MPC |
| 639 | select TZ_MSC |
| 640 | select TZ_PPC |
Thomas Huth | 5aa78a8 | 2019-05-14 07:26:53 +0200 | [diff] [blame] | 641 | select UNIMP |
Peter Maydell | 0d10df3 | 2021-02-19 14:45:44 +0000 | [diff] [blame] | 642 | select SSE_COUNTER |
Peter Maydell | 0b8ceee | 2021-02-19 14:45:45 +0000 | [diff] [blame] | 643 | select SSE_TIMER |