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bellard7d132992003-03-06 23:23:54 +00001/*
2 * i386 emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard7d132992003-03-06 23:23:54 +000018 */
bellarde4533c72003-06-15 19:51:39 +000019#include "config.h"
bellard93ac68b2003-09-30 20:57:29 +000020#include "exec.h"
bellard956034d2003-04-29 20:40:53 +000021#include "disas.h"
bellard7cb69ca2008-05-10 10:55:51 +000022#include "tcg.h"
aliguori7ba1e612008-11-05 16:04:33 +000023#include "kvm.h"
Jan Kiszka1d93f0f2010-06-25 16:56:49 +020024#include "qemu-barrier.h"
bellard7d132992003-03-06 23:23:54 +000025
bellardfbf9eeb2004-04-25 21:21:33 +000026#if !defined(CONFIG_SOFTMMU)
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
blueswir184778502008-10-26 20:33:16 +000037#ifdef __linux__
bellardfbf9eeb2004-04-25 21:21:33 +000038#include <sys/ucontext.h>
39#endif
blueswir184778502008-10-26 20:33:16 +000040#endif
bellardfbf9eeb2004-04-25 21:21:33 +000041
Juan Quinteladfe5fff2009-07-27 16:12:40 +020042#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
blueswir1572a9d42008-05-17 07:38:10 +000043// Work around ugly bugs in glibc that mangle global register contents
44#undef env
45#define env cpu_single_env
46#endif
47
bellard36bdbe52003-11-19 22:12:02 +000048int tb_invalidated_flag;
49
Juan Quintelaf0667e62009-07-27 16:13:05 +020050//#define CONFIG_DEBUG_EXEC
bellard9de5e442003-03-23 16:49:39 +000051//#define DEBUG_SIGNAL
bellard7d132992003-03-06 23:23:54 +000052
aliguori6a4955a2009-04-24 18:03:20 +000053int qemu_cpu_has_work(CPUState *env)
54{
55 return cpu_has_work(env);
56}
57
bellarde4533c72003-06-15 19:51:39 +000058void cpu_loop_exit(void)
59{
Paolo Bonzini1c3569f2010-01-15 09:42:07 +010060 env->current_tb = NULL;
bellarde4533c72003-06-15 19:51:39 +000061 longjmp(env->jmp_env, 1);
62}
thsbfed01f2007-06-03 17:44:37 +000063
bellardfbf9eeb2004-04-25 21:21:33 +000064/* exit the current TB from a signal handler. The host registers are
65 restored in a state compatible with the CPU emulator
66 */
ths5fafdf22007-09-16 21:08:06 +000067void cpu_resume_from_signal(CPUState *env1, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000068{
69#if !defined(CONFIG_SOFTMMU)
blueswir184778502008-10-26 20:33:16 +000070#ifdef __linux__
bellardfbf9eeb2004-04-25 21:21:33 +000071 struct ucontext *uc = puc;
blueswir184778502008-10-26 20:33:16 +000072#elif defined(__OpenBSD__)
73 struct sigcontext *uc = puc;
74#endif
bellardfbf9eeb2004-04-25 21:21:33 +000075#endif
76
77 env = env1;
78
79 /* XXX: restore cpu registers saved in host registers */
80
81#if !defined(CONFIG_SOFTMMU)
82 if (puc) {
83 /* XXX: use siglongjmp ? */
blueswir184778502008-10-26 20:33:16 +000084#ifdef __linux__
Aurelien Jarno60e99242010-03-29 02:12:51 +020085#ifdef __ia64
86 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
87#else
bellardfbf9eeb2004-04-25 21:21:33 +000088 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
Aurelien Jarno60e99242010-03-29 02:12:51 +020089#endif
blueswir184778502008-10-26 20:33:16 +000090#elif defined(__OpenBSD__)
91 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
92#endif
bellardfbf9eeb2004-04-25 21:21:33 +000093 }
94#endif
pbrook9a3ea652008-12-19 12:49:13 +000095 env->exception_index = -1;
bellardfbf9eeb2004-04-25 21:21:33 +000096 longjmp(env->jmp_env, 1);
97}
98
pbrook2e70f6e2008-06-29 01:03:05 +000099/* Execute the code without caching the generated code. An interpreter
100 could be used if available. */
101static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
102{
103 unsigned long next_tb;
104 TranslationBlock *tb;
105
106 /* Should never happen.
107 We only end up here when an existing TB is too long. */
108 if (max_cycles > CF_COUNT_MASK)
109 max_cycles = CF_COUNT_MASK;
110
111 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
112 max_cycles);
113 env->current_tb = tb;
114 /* execute the generated code */
115 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
Paolo Bonzini1c3569f2010-01-15 09:42:07 +0100116 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000117
118 if ((next_tb & 3) == 2) {
119 /* Restore PC. This may happen if async event occurs before
120 the TB starts executing. */
aliguori622ed362008-11-18 19:36:03 +0000121 cpu_pc_from_tb(env, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000122 }
123 tb_phys_invalidate(tb, -1);
124 tb_free(tb);
125}
126
bellard8a40a182005-11-20 10:35:40 +0000127static TranslationBlock *tb_find_slow(target_ulong pc,
128 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +0000129 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +0000130{
131 TranslationBlock *tb, **ptb1;
bellard8a40a182005-11-20 10:35:40 +0000132 unsigned int h;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000133 tb_page_addr_t phys_pc, phys_page1, phys_page2;
134 target_ulong virt_page2;
ths3b46e622007-09-17 08:09:54 +0000135
bellard8a40a182005-11-20 10:35:40 +0000136 tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +0000137
bellard8a40a182005-11-20 10:35:40 +0000138 /* find translated block using physical mappings */
Paul Brook41c1b1c2010-03-12 16:54:58 +0000139 phys_pc = get_page_addr_code(env, pc);
bellard8a40a182005-11-20 10:35:40 +0000140 phys_page1 = phys_pc & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 h = tb_phys_hash_func(phys_pc);
143 ptb1 = &tb_phys_hash[h];
144 for(;;) {
145 tb = *ptb1;
146 if (!tb)
147 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000148 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000149 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000150 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000151 tb->flags == flags) {
152 /* check next page if needed */
153 if (tb->page_addr[1] != -1) {
ths5fafdf22007-09-16 21:08:06 +0000154 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000155 TARGET_PAGE_SIZE;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000156 phys_page2 = get_page_addr_code(env, virt_page2);
bellard8a40a182005-11-20 10:35:40 +0000157 if (tb->page_addr[1] == phys_page2)
158 goto found;
159 } else {
160 goto found;
161 }
162 }
163 ptb1 = &tb->phys_hash_next;
164 }
165 not_found:
pbrook2e70f6e2008-06-29 01:03:05 +0000166 /* if no translated code available, then translate it now */
167 tb = tb_gen_code(env, pc, cs_base, flags, 0);
ths3b46e622007-09-17 08:09:54 +0000168
bellard8a40a182005-11-20 10:35:40 +0000169 found:
bellard8a40a182005-11-20 10:35:40 +0000170 /* we add the TB in the virtual pc hash table */
171 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
bellard8a40a182005-11-20 10:35:40 +0000172 return tb;
173}
174
175static inline TranslationBlock *tb_find_fast(void)
176{
177 TranslationBlock *tb;
178 target_ulong cs_base, pc;
aliguori6b917542008-11-18 19:46:41 +0000179 int flags;
bellard8a40a182005-11-20 10:35:40 +0000180
181 /* we record a subset of the CPU state. It will
182 always be the same before a given translated block
183 is executed. */
aliguori6b917542008-11-18 19:46:41 +0000184 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bellardbce61842008-02-01 22:18:51 +0000185 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
ths551bd272008-07-03 17:57:36 +0000186 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
187 tb->flags != flags)) {
bellard8a40a182005-11-20 10:35:40 +0000188 tb = tb_find_slow(pc, cs_base, flags);
189 }
190 return tb;
191}
192
aliguoridde23672008-11-18 20:50:36 +0000193static CPUDebugExcpHandler *debug_excp_handler;
194
195CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
196{
197 CPUDebugExcpHandler *old_handler = debug_excp_handler;
198
199 debug_excp_handler = handler;
200 return old_handler;
201}
202
aliguori6e140f22008-11-18 20:37:55 +0000203static void cpu_handle_debug_exception(CPUState *env)
204{
205 CPUWatchpoint *wp;
206
207 if (!env->watchpoint_hit)
Blue Swirl72cf2d42009-09-12 07:36:22 +0000208 QTAILQ_FOREACH(wp, &env->watchpoints, entry)
aliguori6e140f22008-11-18 20:37:55 +0000209 wp->flags &= ~BP_WATCHPOINT_HIT;
aliguoridde23672008-11-18 20:50:36 +0000210
211 if (debug_excp_handler)
212 debug_excp_handler(env);
aliguori6e140f22008-11-18 20:37:55 +0000213}
214
bellard7d132992003-03-06 23:23:54 +0000215/* main execution loop */
216
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300217volatile sig_atomic_t exit_request;
218
bellarde4533c72003-06-15 19:51:39 +0000219int cpu_exec(CPUState *env1)
bellard7d132992003-03-06 23:23:54 +0000220{
Paolo Bonzini1d9000e2010-02-23 19:21:00 +0100221 volatile host_reg_t saved_env_reg;
bellard8a40a182005-11-20 10:35:40 +0000222 int ret, interrupt_request;
bellard8a40a182005-11-20 10:35:40 +0000223 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000224 uint8_t *tc_ptr;
pbrookd5975362008-06-07 20:50:51 +0000225 unsigned long next_tb;
bellard8c6939c2003-06-09 15:28:00 +0000226
thsbfed01f2007-06-03 17:44:37 +0000227 if (cpu_halted(env1) == EXCP_HALTED)
228 return EXCP_HALTED;
bellard5a1e3cf2005-11-23 21:02:53 +0000229
ths5fafdf22007-09-16 21:08:06 +0000230 cpu_single_env = env1;
bellard6a00d602005-11-21 23:25:50 +0000231
Paolo Bonzini24ebf5f2010-02-18 21:25:23 +0100232 /* the access to env below is actually saving the global register's
233 value, so that files not including target-xyz/exec.h are free to
234 use it. */
235 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
236 saved_env_reg = (host_reg_t) env;
Jan Kiszka1d93f0f2010-06-25 16:56:49 +0200237 barrier();
bellardc27004e2005-01-03 23:35:10 +0000238 env = env1;
bellarde4533c72003-06-15 19:51:39 +0000239
Jan Kiszkac629a4b2010-06-25 16:56:52 +0200240 if (unlikely(exit_request)) {
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300241 env->exit_request = 1;
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300242 }
243
thsecb644f2007-06-03 18:45:53 +0000244#if defined(TARGET_I386)
Jan Kiszka14dcc3e2010-02-19 18:21:20 +0100245 if (!kvm_enabled()) {
246 /* put eflags in CPU temporary format */
247 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
248 DF = 1 - (2 * ((env->eflags >> 10) & 1));
249 CC_OP = CC_OP_EFLAGS;
250 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
251 }
bellard93ac68b2003-09-30 20:57:29 +0000252#elif defined(TARGET_SPARC)
pbrooke6e59062006-10-22 00:18:54 +0000253#elif defined(TARGET_M68K)
254 env->cc_op = CC_OP_FLAGS;
255 env->cc_dest = env->sr & 0xf;
256 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000257#elif defined(TARGET_ALPHA)
258#elif defined(TARGET_ARM)
259#elif defined(TARGET_PPC)
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200260#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000261#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000262#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000263#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100264#elif defined(TARGET_S390X)
bellardfdf9b3e2006-04-27 21:07:38 +0000265 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000266#else
267#error unsupported target CPU
268#endif
bellard3fb2ded2003-06-24 13:22:59 +0000269 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000270
bellard7d132992003-03-06 23:23:54 +0000271 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000272 for(;;) {
273 if (setjmp(env->jmp_env) == 0) {
Juan Quinteladfe5fff2009-07-27 16:12:40 +0200274#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
blueswir19ddff3d2009-04-04 07:41:20 +0000275#undef env
276 env = cpu_single_env;
277#define env cpu_single_env
278#endif
bellard3fb2ded2003-06-24 13:22:59 +0000279 /* if an exception is pending, we execute it here */
280 if (env->exception_index >= 0) {
281 if (env->exception_index >= EXCP_INTERRUPT) {
282 /* exit request from the cpu execution loop */
283 ret = env->exception_index;
aliguori6e140f22008-11-18 20:37:55 +0000284 if (ret == EXCP_DEBUG)
285 cpu_handle_debug_exception(env);
bellard3fb2ded2003-06-24 13:22:59 +0000286 break;
aurel3272d239e2009-01-14 19:40:27 +0000287 } else {
288#if defined(CONFIG_USER_ONLY)
bellard3fb2ded2003-06-24 13:22:59 +0000289 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000290 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000291 loop */
bellard83479e72003-06-25 16:12:37 +0000292#if defined(TARGET_I386)
ths5fafdf22007-09-16 21:08:06 +0000293 do_interrupt_user(env->exception_index,
294 env->exception_is_int,
295 env->error_code,
bellard3fb2ded2003-06-24 13:22:59 +0000296 env->exception_next_eip);
bellardeba01622008-05-12 12:04:40 +0000297 /* successfully delivered */
298 env->old_exception = -1;
bellard83479e72003-06-25 16:12:37 +0000299#endif
bellard3fb2ded2003-06-24 13:22:59 +0000300 ret = env->exception_index;
301 break;
aurel3272d239e2009-01-14 19:40:27 +0000302#else
bellard83479e72003-06-25 16:12:37 +0000303#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000304 /* simulate a real cpu exception. On i386, it can
305 trigger new exceptions, but we do not handle
306 double or triple faults yet. */
ths5fafdf22007-09-16 21:08:06 +0000307 do_interrupt(env->exception_index,
308 env->exception_is_int,
309 env->error_code,
bellardd05e66d2003-08-20 21:34:35 +0000310 env->exception_next_eip, 0);
ths678dde12007-03-31 20:28:52 +0000311 /* successfully delivered */
312 env->old_exception = -1;
bellardce097762004-01-04 23:53:18 +0000313#elif defined(TARGET_PPC)
314 do_interrupt(env);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200315#elif defined(TARGET_MICROBLAZE)
316 do_interrupt(env);
bellard6af0bf92005-07-02 14:58:51 +0000317#elif defined(TARGET_MIPS)
318 do_interrupt(env);
bellarde95c8d52004-09-30 22:22:08 +0000319#elif defined(TARGET_SPARC)
blueswir1f2bc7e72008-05-27 17:35:30 +0000320 do_interrupt(env);
bellardb5ff1b32005-11-26 10:38:39 +0000321#elif defined(TARGET_ARM)
322 do_interrupt(env);
bellardfdf9b3e2006-04-27 21:07:38 +0000323#elif defined(TARGET_SH4)
324 do_interrupt(env);
j_mayereddf68a2007-04-05 07:22:49 +0000325#elif defined(TARGET_ALPHA)
326 do_interrupt(env);
thsf1ccf902007-10-08 13:16:14 +0000327#elif defined(TARGET_CRIS)
328 do_interrupt(env);
pbrook06338792007-05-23 19:58:11 +0000329#elif defined(TARGET_M68K)
330 do_interrupt(0);
bellard83479e72003-06-25 16:12:37 +0000331#endif
Paolo Bonzini301d2902010-01-15 09:41:01 +0100332 env->exception_index = -1;
aurel3272d239e2009-01-14 19:40:27 +0000333#endif
bellard3fb2ded2003-06-24 13:22:59 +0000334 }
ths5fafdf22007-09-16 21:08:06 +0000335 }
bellard9df217a2005-02-10 22:05:51 +0000336
aliguori7ba1e612008-11-05 16:04:33 +0000337 if (kvm_enabled()) {
aliguoribecfc392008-11-10 15:55:14 +0000338 kvm_cpu_exec(env);
339 longjmp(env->jmp_env, 1);
aliguori7ba1e612008-11-05 16:04:33 +0000340 }
341
blueswir1b5fc09a2008-05-04 06:38:18 +0000342 next_tb = 0; /* force lookup of first TB */
bellard3fb2ded2003-06-24 13:22:59 +0000343 for(;;) {
bellard68a79312003-06-30 13:12:32 +0000344 interrupt_request = env->interrupt_request;
malce1638bd2008-11-06 18:54:46 +0000345 if (unlikely(interrupt_request)) {
346 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
347 /* Mask out external interrupts for this step. */
348 interrupt_request &= ~(CPU_INTERRUPT_HARD |
349 CPU_INTERRUPT_FIQ |
350 CPU_INTERRUPT_SMI |
351 CPU_INTERRUPT_NMI);
352 }
pbrook6658ffb2007-03-16 23:58:11 +0000353 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
354 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
355 env->exception_index = EXCP_DEBUG;
356 cpu_loop_exit();
357 }
balroga90b7312007-05-01 01:28:01 +0000358#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200359 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
360 defined(TARGET_MICROBLAZE)
balroga90b7312007-05-01 01:28:01 +0000361 if (interrupt_request & CPU_INTERRUPT_HALT) {
362 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
363 env->halted = 1;
364 env->exception_index = EXCP_HLT;
365 cpu_loop_exit();
366 }
367#endif
bellard68a79312003-06-30 13:12:32 +0000368#if defined(TARGET_I386)
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300369 if (interrupt_request & CPU_INTERRUPT_INIT) {
370 svm_check_intercept(SVM_EXIT_INIT);
371 do_cpu_init(env);
372 env->exception_index = EXCP_HALTED;
373 cpu_loop_exit();
374 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
375 do_cpu_sipi(env);
376 } else if (env->hflags2 & HF2_GIF_MASK) {
bellarddb620f42008-06-04 17:02:19 +0000377 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
378 !(env->hflags & HF_SMM_MASK)) {
379 svm_check_intercept(SVM_EXIT_SMI);
380 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
381 do_smm_enter();
382 next_tb = 0;
383 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
384 !(env->hflags2 & HF2_NMI_MASK)) {
385 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
386 env->hflags2 |= HF2_NMI_MASK;
387 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
388 next_tb = 0;
Huang Ying79c4f6b2009-06-23 10:05:14 +0800389 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
390 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
391 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
392 next_tb = 0;
bellarddb620f42008-06-04 17:02:19 +0000393 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
394 (((env->hflags2 & HF2_VINTR_MASK) &&
395 (env->hflags2 & HF2_HIF_MASK)) ||
396 (!(env->hflags2 & HF2_VINTR_MASK) &&
397 (env->eflags & IF_MASK &&
398 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
399 int intno;
400 svm_check_intercept(SVM_EXIT_INTR);
401 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
402 intno = cpu_get_pic_interrupt(env);
aliguori93fcfe32009-01-15 22:34:14 +0000403 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
Juan Quinteladfe5fff2009-07-27 16:12:40 +0200404#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
blueswir19ddff3d2009-04-04 07:41:20 +0000405#undef env
406 env = cpu_single_env;
407#define env cpu_single_env
408#endif
bellarddb620f42008-06-04 17:02:19 +0000409 do_interrupt(intno, 0, 0, 0, 1);
410 /* ensure that no TB jump will be modified as
411 the program flow was changed */
412 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000413#if !defined(CONFIG_USER_ONLY)
bellarddb620f42008-06-04 17:02:19 +0000414 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
415 (env->eflags & IF_MASK) &&
416 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
417 int intno;
418 /* FIXME: this should respect TPR */
419 svm_check_intercept(SVM_EXIT_VINTR);
bellarddb620f42008-06-04 17:02:19 +0000420 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
aliguori93fcfe32009-01-15 22:34:14 +0000421 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
bellarddb620f42008-06-04 17:02:19 +0000422 do_interrupt(intno, 0, 0, 0, 1);
aurel32d40c54d2008-12-13 12:33:02 +0000423 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
bellarddb620f42008-06-04 17:02:19 +0000424 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000425#endif
bellarddb620f42008-06-04 17:02:19 +0000426 }
bellard68a79312003-06-30 13:12:32 +0000427 }
bellardce097762004-01-04 23:53:18 +0000428#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000429#if 0
430 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
Blue Swirld84bda42009-11-07 10:36:04 +0000431 cpu_reset(env);
bellard9fddaa02004-05-21 12:59:32 +0000432 }
433#endif
j_mayer47103572007-03-30 09:38:04 +0000434 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000435 ppc_hw_interrupt(env);
436 if (env->pending_interrupts == 0)
437 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
blueswir1b5fc09a2008-05-04 06:38:18 +0000438 next_tb = 0;
bellardce097762004-01-04 23:53:18 +0000439 }
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200440#elif defined(TARGET_MICROBLAZE)
441 if ((interrupt_request & CPU_INTERRUPT_HARD)
442 && (env->sregs[SR_MSR] & MSR_IE)
443 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
444 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
445 env->exception_index = EXCP_IRQ;
446 do_interrupt(env);
447 next_tb = 0;
448 }
bellard6af0bf92005-07-02 14:58:51 +0000449#elif defined(TARGET_MIPS)
450 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
Edgar E. Iglesias138afb02010-08-06 12:21:16 +0200451 cpu_mips_hw_interrupts_pending(env) &&
bellard6af0bf92005-07-02 14:58:51 +0000452 (env->CP0_Status & (1 << CP0St_IE)) &&
ths24c7b0e2007-03-30 16:44:54 +0000453 !(env->CP0_Status & (1 << CP0St_EXL)) &&
454 !(env->CP0_Status & (1 << CP0St_ERL)) &&
bellard6af0bf92005-07-02 14:58:51 +0000455 !(env->hflags & MIPS_HFLAG_DM)) {
456 /* Raise it */
457 env->exception_index = EXCP_EXT_INTERRUPT;
458 env->error_code = 0;
459 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000460 next_tb = 0;
bellard6af0bf92005-07-02 14:58:51 +0000461 }
bellarde95c8d52004-09-30 22:22:08 +0000462#elif defined(TARGET_SPARC)
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300463 if (interrupt_request & CPU_INTERRUPT_HARD) {
464 if (cpu_interrupts_enabled(env) &&
465 env->interrupt_index > 0) {
466 int pil = env->interrupt_index & 0xf;
467 int type = env->interrupt_index & 0xf0;
bellard66321a12005-04-06 20:47:48 +0000468
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300469 if (((type == TT_EXTINT) &&
470 cpu_pil_allowed(env, pil)) ||
471 type != TT_EXTINT) {
472 env->exception_index = env->interrupt_index;
473 do_interrupt(env);
474 next_tb = 0;
475 }
476 }
bellarde95c8d52004-09-30 22:22:08 +0000477 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
478 //do_interrupt(0, 0, 0, 0, 0);
479 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
balroga90b7312007-05-01 01:28:01 +0000480 }
bellardb5ff1b32005-11-26 10:38:39 +0000481#elif defined(TARGET_ARM)
482 if (interrupt_request & CPU_INTERRUPT_FIQ
483 && !(env->uncached_cpsr & CPSR_F)) {
484 env->exception_index = EXCP_FIQ;
485 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000486 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000487 }
pbrook9ee6e8b2007-11-11 00:04:49 +0000488 /* ARMv7-M interrupt return works by loading a magic value
489 into the PC. On real hardware the load causes the
490 return to occur. The qemu implementation performs the
491 jump normally, then does the exception return when the
492 CPU tries to execute code at the magic address.
493 This will cause the magic PC value to be pushed to
494 the stack if an interrupt occured at the wrong time.
495 We avoid this by disabling interrupts when
496 pc contains a magic address. */
bellardb5ff1b32005-11-26 10:38:39 +0000497 if (interrupt_request & CPU_INTERRUPT_HARD
pbrook9ee6e8b2007-11-11 00:04:49 +0000498 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
499 || !(env->uncached_cpsr & CPSR_I))) {
bellardb5ff1b32005-11-26 10:38:39 +0000500 env->exception_index = EXCP_IRQ;
501 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000502 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000503 }
bellardfdf9b3e2006-04-27 21:07:38 +0000504#elif defined(TARGET_SH4)
thse96e2042007-12-02 06:18:24 +0000505 if (interrupt_request & CPU_INTERRUPT_HARD) {
506 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000507 next_tb = 0;
thse96e2042007-12-02 06:18:24 +0000508 }
j_mayereddf68a2007-04-05 07:22:49 +0000509#elif defined(TARGET_ALPHA)
510 if (interrupt_request & CPU_INTERRUPT_HARD) {
511 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000512 next_tb = 0;
j_mayereddf68a2007-04-05 07:22:49 +0000513 }
thsf1ccf902007-10-08 13:16:14 +0000514#elif defined(TARGET_CRIS)
edgar_igl1b1a38b2008-06-09 23:18:06 +0000515 if (interrupt_request & CPU_INTERRUPT_HARD
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100516 && (env->pregs[PR_CCS] & I_FLAG)
517 && !env->locked_irq) {
edgar_igl1b1a38b2008-06-09 23:18:06 +0000518 env->exception_index = EXCP_IRQ;
519 do_interrupt(env);
520 next_tb = 0;
521 }
522 if (interrupt_request & CPU_INTERRUPT_NMI
523 && (env->pregs[PR_CCS] & M_FLAG)) {
524 env->exception_index = EXCP_NMI;
thsf1ccf902007-10-08 13:16:14 +0000525 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000526 next_tb = 0;
thsf1ccf902007-10-08 13:16:14 +0000527 }
pbrook06338792007-05-23 19:58:11 +0000528#elif defined(TARGET_M68K)
529 if (interrupt_request & CPU_INTERRUPT_HARD
530 && ((env->sr & SR_I) >> SR_I_SHIFT)
531 < env->pending_level) {
532 /* Real hardware gets the interrupt vector via an
533 IACK cycle at this point. Current emulated
534 hardware doesn't rely on this, so we
535 provide/save the vector when the interrupt is
536 first signalled. */
537 env->exception_index = env->pending_vector;
538 do_interrupt(1);
blueswir1b5fc09a2008-05-04 06:38:18 +0000539 next_tb = 0;
pbrook06338792007-05-23 19:58:11 +0000540 }
bellard68a79312003-06-30 13:12:32 +0000541#endif
bellard9d050952006-05-22 22:03:52 +0000542 /* Don't use the cached interupt_request value,
543 do_interrupt may have updated the EXITTB flag. */
bellardb5ff1b32005-11-26 10:38:39 +0000544 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bellardbf3e8bf2004-02-16 21:58:54 +0000545 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
546 /* ensure that no TB jump will be modified as
547 the program flow was changed */
blueswir1b5fc09a2008-05-04 06:38:18 +0000548 next_tb = 0;
bellardbf3e8bf2004-02-16 21:58:54 +0000549 }
aurel32be214e62009-03-06 21:48:00 +0000550 }
551 if (unlikely(env->exit_request)) {
552 env->exit_request = 0;
553 env->exception_index = EXCP_INTERRUPT;
554 cpu_loop_exit();
bellard3fb2ded2003-06-24 13:22:59 +0000555 }
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700556#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
aliguori8fec2b82009-01-15 22:36:53 +0000557 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
bellard3fb2ded2003-06-24 13:22:59 +0000558 /* restore flags in standard format */
thsecb644f2007-06-03 18:45:53 +0000559#if defined(TARGET_I386)
pbrooka7812ae2008-11-17 14:43:54 +0000560 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
aliguori93fcfe32009-01-15 22:34:14 +0000561 log_cpu_state(env, X86_DUMP_CCOP);
bellard3fb2ded2003-06-24 13:22:59 +0000562 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
pbrooke6e59062006-10-22 00:18:54 +0000563#elif defined(TARGET_M68K)
564 cpu_m68k_flush_flags(env, env->cc_op);
565 env->cc_op = CC_OP_FLAGS;
566 env->sr = (env->sr & 0xffe0)
567 | env->cc_dest | (env->cc_x << 4);
aliguori93fcfe32009-01-15 22:34:14 +0000568 log_cpu_state(env, 0);
bellarde4533c72003-06-15 19:51:39 +0000569#else
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700570 log_cpu_state(env, 0);
bellarde4533c72003-06-15 19:51:39 +0000571#endif
bellard3fb2ded2003-06-24 13:22:59 +0000572 }
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700573#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
pbrookd5975362008-06-07 20:50:51 +0000574 spin_lock(&tb_lock);
bellard8a40a182005-11-20 10:35:40 +0000575 tb = tb_find_fast();
pbrookd5975362008-06-07 20:50:51 +0000576 /* Note: we do it here to avoid a gcc bug on Mac OS X when
577 doing it in tb_find_slow */
578 if (tb_invalidated_flag) {
579 /* as some TB could have been invalidated because
580 of memory exceptions while generating the code, we
581 must recompute the hash index here */
582 next_tb = 0;
pbrook2e70f6e2008-06-29 01:03:05 +0000583 tb_invalidated_flag = 0;
pbrookd5975362008-06-07 20:50:51 +0000584 }
Juan Quintelaf0667e62009-07-27 16:13:05 +0200585#ifdef CONFIG_DEBUG_EXEC
aliguori93fcfe32009-01-15 22:34:14 +0000586 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
587 (long)tb->tc_ptr, tb->pc,
588 lookup_symbol(tb->pc));
bellard9d27abd2003-05-10 13:13:54 +0000589#endif
bellard8a40a182005-11-20 10:35:40 +0000590 /* see if we can patch the calling TB. When the TB
591 spans two pages, we cannot safely do a direct
592 jump. */
Paolo Bonzini040f2fb2010-01-15 08:56:36 +0100593 if (next_tb != 0 && tb->page_addr[1] == -1) {
blueswir1b5fc09a2008-05-04 06:38:18 +0000594 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
bellard3fb2ded2003-06-24 13:22:59 +0000595 }
pbrookd5975362008-06-07 20:50:51 +0000596 spin_unlock(&tb_lock);
malc55e8b852008-11-04 14:18:13 +0000597
598 /* cpu_interrupt might be called while translating the
599 TB, but before it is linked into a potentially
600 infinite loop and becomes env->current_tb. Avoid
601 starting execution if there is a pending interrupt. */
Jan Kiszkab0052d12010-06-25 16:56:50 +0200602 env->current_tb = tb;
603 barrier();
604 if (likely(!env->exit_request)) {
pbrook2e70f6e2008-06-29 01:03:05 +0000605 tc_ptr = tb->tc_ptr;
bellard3fb2ded2003-06-24 13:22:59 +0000606 /* execute the generated code */
Juan Quinteladfe5fff2009-07-27 16:12:40 +0200607#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
blueswir1572a9d42008-05-17 07:38:10 +0000608#undef env
pbrook2e70f6e2008-06-29 01:03:05 +0000609 env = cpu_single_env;
blueswir1572a9d42008-05-17 07:38:10 +0000610#define env cpu_single_env
611#endif
pbrook2e70f6e2008-06-29 01:03:05 +0000612 next_tb = tcg_qemu_tb_exec(tc_ptr);
pbrook2e70f6e2008-06-29 01:03:05 +0000613 if ((next_tb & 3) == 2) {
thsbf20dc02008-06-30 17:22:19 +0000614 /* Instruction counter expired. */
pbrook2e70f6e2008-06-29 01:03:05 +0000615 int insns_left;
616 tb = (TranslationBlock *)(long)(next_tb & ~3);
617 /* Restore PC. */
aliguori622ed362008-11-18 19:36:03 +0000618 cpu_pc_from_tb(env, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000619 insns_left = env->icount_decr.u32;
620 if (env->icount_extra && insns_left >= 0) {
621 /* Refill decrementer and continue execution. */
622 env->icount_extra += insns_left;
623 if (env->icount_extra > 0xffff) {
624 insns_left = 0xffff;
625 } else {
626 insns_left = env->icount_extra;
627 }
628 env->icount_extra -= insns_left;
629 env->icount_decr.u16.low = insns_left;
630 } else {
631 if (insns_left > 0) {
632 /* Execute remaining instructions. */
633 cpu_exec_nocache(insns_left, tb);
634 }
635 env->exception_index = EXCP_INTERRUPT;
636 next_tb = 0;
637 cpu_loop_exit();
638 }
639 }
640 }
Jan Kiszkab0052d12010-06-25 16:56:50 +0200641 env->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000642 /* reset soft MMU for next block (it can currently
643 only be set by a memory fault) */
ths50a518e2007-06-03 18:52:15 +0000644 } /* for(;;) */
bellard7d132992003-03-06 23:23:54 +0000645 }
bellard3fb2ded2003-06-24 13:22:59 +0000646 } /* for(;;) */
647
bellard7d132992003-03-06 23:23:54 +0000648
bellarde4533c72003-06-15 19:51:39 +0000649#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000650 /* restore flags in standard format */
pbrooka7812ae2008-11-17 14:43:54 +0000651 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000652#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000653 /* XXX: Save/restore host fpu exception state?. */
bellard93ac68b2003-09-30 20:57:29 +0000654#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000655#elif defined(TARGET_PPC)
pbrooke6e59062006-10-22 00:18:54 +0000656#elif defined(TARGET_M68K)
657 cpu_m68k_flush_flags(env, env->cc_op);
658 env->cc_op = CC_OP_FLAGS;
659 env->sr = (env->sr & 0xffe0)
660 | env->cc_dest | (env->cc_x << 4);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200661#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000662#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000663#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000664#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000665#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100666#elif defined(TARGET_S390X)
bellardfdf9b3e2006-04-27 21:07:38 +0000667 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000668#else
669#error unsupported target CPU
670#endif
pbrook1057eaa2007-02-04 13:37:44 +0000671
672 /* restore global registers */
Jan Kiszka1d93f0f2010-06-25 16:56:49 +0200673 barrier();
Paolo Bonzini24ebf5f2010-02-18 21:25:23 +0100674 env = (void *) saved_env_reg;
pbrook1057eaa2007-02-04 13:37:44 +0000675
bellard6a00d602005-11-21 23:25:50 +0000676 /* fail safe : never use cpu_single_env outside cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000677 cpu_single_env = NULL;
bellard7d132992003-03-06 23:23:54 +0000678 return ret;
679}
bellard6dbad632003-03-16 18:05:05 +0000680
bellardfbf9eeb2004-04-25 21:21:33 +0000681/* must only be called from the generated code as an exception can be
682 generated */
683void tb_invalidate_page_range(target_ulong start, target_ulong end)
684{
bellarddc5d0b32004-06-22 18:43:30 +0000685 /* XXX: cannot enable it yet because it yields to MMU exception
686 where NIP != read address on PowerPC */
687#if 0
bellardfbf9eeb2004-04-25 21:21:33 +0000688 target_ulong phys_addr;
689 phys_addr = get_phys_addr_code(env, start);
690 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
bellarddc5d0b32004-06-22 18:43:30 +0000691#endif
bellardfbf9eeb2004-04-25 21:21:33 +0000692}
693
bellard1a18c712003-10-30 01:07:51 +0000694#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
bellarde4533c72003-06-15 19:51:39 +0000695
bellard6dbad632003-03-16 18:05:05 +0000696void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
697{
698 CPUX86State *saved_env;
699
700 saved_env = env;
701 env = s;
bellarda412ac52003-07-26 18:01:40 +0000702 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
bellarda513fe12003-05-27 23:29:48 +0000703 selector &= 0xffff;
ths5fafdf22007-09-16 21:08:06 +0000704 cpu_x86_load_seg_cache(env, seg_reg, selector,
bellardc27004e2005-01-03 23:35:10 +0000705 (selector << 4), 0xffff, 0);
bellarda513fe12003-05-27 23:29:48 +0000706 } else {
bellard5d975592008-05-12 22:05:33 +0000707 helper_load_seg(seg_reg, selector);
bellarda513fe12003-05-27 23:29:48 +0000708 }
bellard6dbad632003-03-16 18:05:05 +0000709 env = saved_env;
710}
bellard9de5e442003-03-23 16:49:39 +0000711
bellard6f12a2a2007-11-11 22:16:56 +0000712void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
bellardd0a1ffc2003-05-29 20:04:28 +0000713{
714 CPUX86State *saved_env;
715
716 saved_env = env;
717 env = s;
ths3b46e622007-09-17 08:09:54 +0000718
bellard6f12a2a2007-11-11 22:16:56 +0000719 helper_fsave(ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000720
721 env = saved_env;
722}
723
bellard6f12a2a2007-11-11 22:16:56 +0000724void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
bellardd0a1ffc2003-05-29 20:04:28 +0000725{
726 CPUX86State *saved_env;
727
728 saved_env = env;
729 env = s;
ths3b46e622007-09-17 08:09:54 +0000730
bellard6f12a2a2007-11-11 22:16:56 +0000731 helper_frstor(ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000732
733 env = saved_env;
734}
735
bellarde4533c72003-06-15 19:51:39 +0000736#endif /* TARGET_I386 */
737
bellard67b915a2004-03-31 23:37:16 +0000738#if !defined(CONFIG_SOFTMMU)
739
bellard3fb2ded2003-06-24 13:22:59 +0000740#if defined(TARGET_I386)
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700741#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
742#else
743#define EXCEPTION_ACTION cpu_loop_exit()
744#endif
bellard3fb2ded2003-06-24 13:22:59 +0000745
bellardb56dad12003-05-08 15:38:04 +0000746/* 'pc' is the host PC at which the exception was raised. 'address' is
bellardfd6ce8f2003-05-14 19:00:11 +0000747 the effective address of the memory exception. 'is_write' is 1 if a
748 write caused the exception and otherwise 0'. 'old_set' is the
749 signal set which should be restored */
bellard2b413142003-05-14 23:01:10 +0000750static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
ths5fafdf22007-09-16 21:08:06 +0000751 int is_write, sigset_t *old_set,
bellardbf3e8bf2004-02-16 21:58:54 +0000752 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000753{
bellarda513fe12003-05-27 23:29:48 +0000754 TranslationBlock *tb;
755 int ret;
bellard68a79312003-06-30 13:12:32 +0000756
bellard83479e72003-06-25 16:12:37 +0000757 if (cpu_single_env)
758 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellardfd6ce8f2003-05-14 19:00:11 +0000759#if defined(DEBUG_SIGNAL)
ths5fafdf22007-09-16 21:08:06 +0000760 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bellardbf3e8bf2004-02-16 21:58:54 +0000761 pc, address, is_write, *(unsigned long *)old_set);
bellard9de5e442003-03-23 16:49:39 +0000762#endif
bellard25eb4482003-05-14 21:50:54 +0000763 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000764 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellardfd6ce8f2003-05-14 19:00:11 +0000765 return 1;
766 }
bellardfbf9eeb2004-04-25 21:21:33 +0000767
bellard3fb2ded2003-06-24 13:22:59 +0000768 /* see if it is an MMU fault */
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700769 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
bellard3fb2ded2003-06-24 13:22:59 +0000770 if (ret < 0)
771 return 0; /* not an MMU fault */
772 if (ret == 0)
773 return 1; /* the MMU fault was handled without causing real CPU fault */
774 /* now we have a real cpu fault */
bellarda513fe12003-05-27 23:29:48 +0000775 tb = tb_find_pc(pc);
776 if (tb) {
bellard9de5e442003-03-23 16:49:39 +0000777 /* the PC is inside the translated code. It means that we have
778 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +0000779 cpu_restore_state(tb, env, pc, puc);
bellard3fb2ded2003-06-24 13:22:59 +0000780 }
bellard3fb2ded2003-06-24 13:22:59 +0000781
bellard68016c62005-02-07 23:12:27 +0000782 /* we restore the process signal mask as the sigreturn should
783 do it (XXX: use sigsetjmp) */
784 sigprocmask(SIG_SETMASK, old_set, NULL);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700785 EXCEPTION_ACTION;
786
aurel32968c74d2008-04-11 04:55:17 +0000787 /* never comes here */
788 return 1;
bellard3fb2ded2003-06-24 13:22:59 +0000789}
bellard9de5e442003-03-23 16:49:39 +0000790
bellard2b413142003-05-14 23:01:10 +0000791#if defined(__i386__)
792
bellardd8ecc0b2007-02-05 21:41:46 +0000793#if defined(__APPLE__)
794# include <sys/ucontext.h>
795
796# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
797# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
798# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
blueswir1d39bb242009-04-10 07:29:34 +0000799# define MASK_sig(context) ((context)->uc_sigmask)
Juergen Lock78cfb072009-10-17 00:34:26 +0200800#elif defined (__NetBSD__)
801# include <ucontext.h>
802
803# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
804# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
805# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
806# define MASK_sig(context) ((context)->uc_sigmask)
807#elif defined (__FreeBSD__) || defined(__DragonFly__)
808# include <ucontext.h>
809
810# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
811# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
812# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
813# define MASK_sig(context) ((context)->uc_sigmask)
blueswir1d39bb242009-04-10 07:29:34 +0000814#elif defined(__OpenBSD__)
815# define EIP_sig(context) ((context)->sc_eip)
816# define TRAP_sig(context) ((context)->sc_trapno)
817# define ERROR_sig(context) ((context)->sc_err)
818# define MASK_sig(context) ((context)->sc_mask)
bellardd8ecc0b2007-02-05 21:41:46 +0000819#else
820# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
821# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
822# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
blueswir1d39bb242009-04-10 07:29:34 +0000823# define MASK_sig(context) ((context)->uc_sigmask)
bellardd8ecc0b2007-02-05 21:41:46 +0000824#endif
825
ths5fafdf22007-09-16 21:08:06 +0000826int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +0000827 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000828{
ths5a7b5422007-01-31 12:16:51 +0000829 siginfo_t *info = pinfo;
Juergen Lock78cfb072009-10-17 00:34:26 +0200830#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
831 ucontext_t *uc = puc;
832#elif defined(__OpenBSD__)
blueswir1d39bb242009-04-10 07:29:34 +0000833 struct sigcontext *uc = puc;
834#else
bellard9de5e442003-03-23 16:49:39 +0000835 struct ucontext *uc = puc;
blueswir1d39bb242009-04-10 07:29:34 +0000836#endif
bellard9de5e442003-03-23 16:49:39 +0000837 unsigned long pc;
bellardbf3e8bf2004-02-16 21:58:54 +0000838 int trapno;
bellard97eb5b12004-02-25 23:19:55 +0000839
bellardd691f662003-03-24 21:58:34 +0000840#ifndef REG_EIP
841/* for glibc 2.1 */
bellardfd6ce8f2003-05-14 19:00:11 +0000842#define REG_EIP EIP
843#define REG_ERR ERR
844#define REG_TRAPNO TRAPNO
bellardd691f662003-03-24 21:58:34 +0000845#endif
bellardd8ecc0b2007-02-05 21:41:46 +0000846 pc = EIP_sig(uc);
847 trapno = TRAP_sig(uc);
bellardec6338b2007-11-08 14:25:03 +0000848 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
849 trapno == 0xe ?
850 (ERROR_sig(uc) >> 1) & 1 : 0,
blueswir1d39bb242009-04-10 07:29:34 +0000851 &MASK_sig(uc), puc);
bellard2b413142003-05-14 23:01:10 +0000852}
853
bellardbc51c5c2004-03-17 23:46:04 +0000854#elif defined(__x86_64__)
855
blueswir1b3efe5c2008-12-05 17:55:45 +0000856#ifdef __NetBSD__
blueswir1d397abb2009-04-10 13:00:29 +0000857#define PC_sig(context) _UC_MACHINE_PC(context)
858#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
859#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
860#define MASK_sig(context) ((context)->uc_sigmask)
861#elif defined(__OpenBSD__)
862#define PC_sig(context) ((context)->sc_rip)
863#define TRAP_sig(context) ((context)->sc_trapno)
864#define ERROR_sig(context) ((context)->sc_err)
865#define MASK_sig(context) ((context)->sc_mask)
Juergen Lock78cfb072009-10-17 00:34:26 +0200866#elif defined (__FreeBSD__) || defined(__DragonFly__)
867#include <ucontext.h>
868
869#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
870#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
871#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
872#define MASK_sig(context) ((context)->uc_sigmask)
blueswir1b3efe5c2008-12-05 17:55:45 +0000873#else
blueswir1d397abb2009-04-10 13:00:29 +0000874#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
875#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
876#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
877#define MASK_sig(context) ((context)->uc_sigmask)
blueswir1b3efe5c2008-12-05 17:55:45 +0000878#endif
879
ths5a7b5422007-01-31 12:16:51 +0000880int cpu_signal_handler(int host_signum, void *pinfo,
bellardbc51c5c2004-03-17 23:46:04 +0000881 void *puc)
882{
ths5a7b5422007-01-31 12:16:51 +0000883 siginfo_t *info = pinfo;
bellardbc51c5c2004-03-17 23:46:04 +0000884 unsigned long pc;
Juergen Lock78cfb072009-10-17 00:34:26 +0200885#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
blueswir1b3efe5c2008-12-05 17:55:45 +0000886 ucontext_t *uc = puc;
blueswir1d397abb2009-04-10 13:00:29 +0000887#elif defined(__OpenBSD__)
888 struct sigcontext *uc = puc;
blueswir1b3efe5c2008-12-05 17:55:45 +0000889#else
890 struct ucontext *uc = puc;
891#endif
bellardbc51c5c2004-03-17 23:46:04 +0000892
blueswir1d397abb2009-04-10 13:00:29 +0000893 pc = PC_sig(uc);
ths5fafdf22007-09-16 21:08:06 +0000894 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
blueswir1d397abb2009-04-10 13:00:29 +0000895 TRAP_sig(uc) == 0xe ?
896 (ERROR_sig(uc) >> 1) & 1 : 0,
897 &MASK_sig(uc), puc);
bellardbc51c5c2004-03-17 23:46:04 +0000898}
899
malce58ffeb2009-01-14 18:39:49 +0000900#elif defined(_ARCH_PPC)
bellard2b413142003-05-14 23:01:10 +0000901
bellard83fb7ad2004-07-05 21:25:26 +0000902/***********************************************************************
903 * signal context platform-specific definitions
904 * From Wine
905 */
906#ifdef linux
907/* All Registers access - only for local access */
908# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
909/* Gpr Registers access */
910# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
911# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
912# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
913# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
914# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
915# define LR_sig(context) REG_sig(link, context) /* Link register */
916# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
917/* Float Registers access */
918# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
919# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
920/* Exception Registers access */
921# define DAR_sig(context) REG_sig(dar, context)
922# define DSISR_sig(context) REG_sig(dsisr, context)
923# define TRAP_sig(context) REG_sig(trap, context)
924#endif /* linux */
925
Juergen Lock58d9b1e2010-02-19 19:29:25 +0100926#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
927#include <ucontext.h>
928# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
929# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
930# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
931# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
932# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
933# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
934/* Exception Registers access */
935# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
936# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
937# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
938#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
939
bellard83fb7ad2004-07-05 21:25:26 +0000940#ifdef __APPLE__
941# include <sys/ucontext.h>
942typedef struct ucontext SIGCONTEXT;
943/* All Registers access - only for local access */
944# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
945# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
946# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
947# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
948/* Gpr Registers access */
949# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
950# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
951# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
952# define CTR_sig(context) REG_sig(ctr, context)
953# define XER_sig(context) REG_sig(xer, context) /* Link register */
954# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
955# define CR_sig(context) REG_sig(cr, context) /* Condition register */
956/* Float Registers access */
957# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
958# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
959/* Exception Registers access */
960# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
961# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
962# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
963#endif /* __APPLE__ */
964
ths5fafdf22007-09-16 21:08:06 +0000965int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +0000966 void *puc)
bellard2b413142003-05-14 23:01:10 +0000967{
ths5a7b5422007-01-31 12:16:51 +0000968 siginfo_t *info = pinfo;
Juergen Lock58d9b1e2010-02-19 19:29:25 +0100969#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
970 ucontext_t *uc = puc;
971#else
bellard25eb4482003-05-14 21:50:54 +0000972 struct ucontext *uc = puc;
Juergen Lock58d9b1e2010-02-19 19:29:25 +0100973#endif
bellard25eb4482003-05-14 21:50:54 +0000974 unsigned long pc;
bellard25eb4482003-05-14 21:50:54 +0000975 int is_write;
976
bellard83fb7ad2004-07-05 21:25:26 +0000977 pc = IAR_sig(uc);
bellard25eb4482003-05-14 21:50:54 +0000978 is_write = 0;
979#if 0
980 /* ppc 4xx case */
bellard83fb7ad2004-07-05 21:25:26 +0000981 if (DSISR_sig(uc) & 0x00800000)
bellard25eb4482003-05-14 21:50:54 +0000982 is_write = 1;
bellard9de5e442003-03-23 16:49:39 +0000983#else
bellard83fb7ad2004-07-05 21:25:26 +0000984 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
bellard25eb4482003-05-14 21:50:54 +0000985 is_write = 1;
986#endif
ths5fafdf22007-09-16 21:08:06 +0000987 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +0000988 is_write, &uc->uc_sigmask, puc);
bellard9de5e442003-03-23 16:49:39 +0000989}
bellard2b413142003-05-14 23:01:10 +0000990
bellard2f87c602003-06-02 20:38:09 +0000991#elif defined(__alpha__)
992
ths5fafdf22007-09-16 21:08:06 +0000993int cpu_signal_handler(int host_signum, void *pinfo,
bellard2f87c602003-06-02 20:38:09 +0000994 void *puc)
995{
ths5a7b5422007-01-31 12:16:51 +0000996 siginfo_t *info = pinfo;
bellard2f87c602003-06-02 20:38:09 +0000997 struct ucontext *uc = puc;
998 uint32_t *pc = uc->uc_mcontext.sc_pc;
999 uint32_t insn = *pc;
1000 int is_write = 0;
1001
bellard8c6939c2003-06-09 15:28:00 +00001002 /* XXX: need kernel patch to get write flag faster */
bellard2f87c602003-06-02 20:38:09 +00001003 switch (insn >> 26) {
1004 case 0x0d: // stw
1005 case 0x0e: // stb
1006 case 0x0f: // stq_u
1007 case 0x24: // stf
1008 case 0x25: // stg
1009 case 0x26: // sts
1010 case 0x27: // stt
1011 case 0x2c: // stl
1012 case 0x2d: // stq
1013 case 0x2e: // stl_c
1014 case 0x2f: // stq_c
1015 is_write = 1;
1016 }
1017
ths5fafdf22007-09-16 21:08:06 +00001018 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001019 is_write, &uc->uc_sigmask, puc);
bellard2f87c602003-06-02 20:38:09 +00001020}
bellard8c6939c2003-06-09 15:28:00 +00001021#elif defined(__sparc__)
1022
ths5fafdf22007-09-16 21:08:06 +00001023int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001024 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001025{
ths5a7b5422007-01-31 12:16:51 +00001026 siginfo_t *info = pinfo;
bellard8c6939c2003-06-09 15:28:00 +00001027 int is_write;
1028 uint32_t insn;
Juan Quinteladfe5fff2009-07-27 16:12:40 +02001029#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
blueswir1c9e1e2b2008-05-18 06:40:16 +00001030 uint32_t *regs = (uint32_t *)(info + 1);
1031 void *sigmask = (regs + 20);
bellard8c6939c2003-06-09 15:28:00 +00001032 /* XXX: is there a standard glibc define ? */
blueswir1c9e1e2b2008-05-18 06:40:16 +00001033 unsigned long pc = regs[1];
1034#else
blueswir184778502008-10-26 20:33:16 +00001035#ifdef __linux__
blueswir1c9e1e2b2008-05-18 06:40:16 +00001036 struct sigcontext *sc = puc;
1037 unsigned long pc = sc->sigc_regs.tpc;
1038 void *sigmask = (void *)sc->sigc_mask;
blueswir184778502008-10-26 20:33:16 +00001039#elif defined(__OpenBSD__)
1040 struct sigcontext *uc = puc;
1041 unsigned long pc = uc->sc_pc;
1042 void *sigmask = (void *)(long)uc->sc_mask;
1043#endif
blueswir1c9e1e2b2008-05-18 06:40:16 +00001044#endif
1045
bellard8c6939c2003-06-09 15:28:00 +00001046 /* XXX: need kernel patch to get write flag faster */
1047 is_write = 0;
1048 insn = *(uint32_t *)pc;
1049 if ((insn >> 30) == 3) {
1050 switch((insn >> 19) & 0x3f) {
1051 case 0x05: // stb
Blue Swirld877fa52009-04-25 19:07:16 +00001052 case 0x15: // stba
bellard8c6939c2003-06-09 15:28:00 +00001053 case 0x06: // sth
Blue Swirld877fa52009-04-25 19:07:16 +00001054 case 0x16: // stha
bellard8c6939c2003-06-09 15:28:00 +00001055 case 0x04: // st
Blue Swirld877fa52009-04-25 19:07:16 +00001056 case 0x14: // sta
bellard8c6939c2003-06-09 15:28:00 +00001057 case 0x07: // std
Blue Swirld877fa52009-04-25 19:07:16 +00001058 case 0x17: // stda
1059 case 0x0e: // stx
1060 case 0x1e: // stxa
bellard8c6939c2003-06-09 15:28:00 +00001061 case 0x24: // stf
Blue Swirld877fa52009-04-25 19:07:16 +00001062 case 0x34: // stfa
bellard8c6939c2003-06-09 15:28:00 +00001063 case 0x27: // stdf
Blue Swirld877fa52009-04-25 19:07:16 +00001064 case 0x37: // stdfa
1065 case 0x26: // stqf
1066 case 0x36: // stqfa
bellard8c6939c2003-06-09 15:28:00 +00001067 case 0x25: // stfsr
Blue Swirld877fa52009-04-25 19:07:16 +00001068 case 0x3c: // casa
1069 case 0x3e: // casxa
bellard8c6939c2003-06-09 15:28:00 +00001070 is_write = 1;
1071 break;
1072 }
1073 }
ths5fafdf22007-09-16 21:08:06 +00001074 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001075 is_write, sigmask, NULL);
bellard8c6939c2003-06-09 15:28:00 +00001076}
1077
1078#elif defined(__arm__)
1079
ths5fafdf22007-09-16 21:08:06 +00001080int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001081 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001082{
ths5a7b5422007-01-31 12:16:51 +00001083 siginfo_t *info = pinfo;
bellard8c6939c2003-06-09 15:28:00 +00001084 struct ucontext *uc = puc;
1085 unsigned long pc;
1086 int is_write;
ths3b46e622007-09-17 08:09:54 +00001087
blueswir148bbf112008-07-08 18:35:02 +00001088#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
balrog5c49b362008-06-02 01:01:18 +00001089 pc = uc->uc_mcontext.gregs[R15];
1090#else
balrog4eee57f2008-05-06 14:47:19 +00001091 pc = uc->uc_mcontext.arm_pc;
balrog5c49b362008-06-02 01:01:18 +00001092#endif
bellard8c6939c2003-06-09 15:28:00 +00001093 /* XXX: compute is_write */
1094 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001095 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellard8c6939c2003-06-09 15:28:00 +00001096 is_write,
pbrookf3a96762006-07-29 19:09:31 +00001097 &uc->uc_sigmask, puc);
bellard8c6939c2003-06-09 15:28:00 +00001098}
1099
bellard38e584a2003-08-10 22:14:22 +00001100#elif defined(__mc68000)
1101
ths5fafdf22007-09-16 21:08:06 +00001102int cpu_signal_handler(int host_signum, void *pinfo,
bellard38e584a2003-08-10 22:14:22 +00001103 void *puc)
1104{
ths5a7b5422007-01-31 12:16:51 +00001105 siginfo_t *info = pinfo;
bellard38e584a2003-08-10 22:14:22 +00001106 struct ucontext *uc = puc;
1107 unsigned long pc;
1108 int is_write;
ths3b46e622007-09-17 08:09:54 +00001109
bellard38e584a2003-08-10 22:14:22 +00001110 pc = uc->uc_mcontext.gregs[16];
1111 /* XXX: compute is_write */
1112 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001113 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellard38e584a2003-08-10 22:14:22 +00001114 is_write,
bellardbf3e8bf2004-02-16 21:58:54 +00001115 &uc->uc_sigmask, puc);
bellard38e584a2003-08-10 22:14:22 +00001116}
1117
bellardb8076a72005-04-07 22:20:31 +00001118#elif defined(__ia64)
1119
1120#ifndef __ISR_VALID
1121 /* This ought to be in <bits/siginfo.h>... */
1122# define __ISR_VALID 1
bellardb8076a72005-04-07 22:20:31 +00001123#endif
1124
ths5a7b5422007-01-31 12:16:51 +00001125int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
bellardb8076a72005-04-07 22:20:31 +00001126{
ths5a7b5422007-01-31 12:16:51 +00001127 siginfo_t *info = pinfo;
bellardb8076a72005-04-07 22:20:31 +00001128 struct ucontext *uc = puc;
1129 unsigned long ip;
1130 int is_write = 0;
1131
1132 ip = uc->uc_mcontext.sc_ip;
1133 switch (host_signum) {
1134 case SIGILL:
1135 case SIGFPE:
1136 case SIGSEGV:
1137 case SIGBUS:
1138 case SIGTRAP:
bellardfd4a43e2006-04-24 20:32:17 +00001139 if (info->si_code && (info->si_segvflags & __ISR_VALID))
bellardb8076a72005-04-07 22:20:31 +00001140 /* ISR.W (write-access) is bit 33: */
1141 is_write = (info->si_isr >> 33) & 1;
1142 break;
1143
1144 default:
1145 break;
1146 }
1147 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1148 is_write,
Aurelien Jarno60e99242010-03-29 02:12:51 +02001149 (sigset_t *)&uc->uc_sigmask, puc);
bellardb8076a72005-04-07 22:20:31 +00001150}
1151
bellard90cb9492005-07-24 15:11:38 +00001152#elif defined(__s390__)
1153
ths5fafdf22007-09-16 21:08:06 +00001154int cpu_signal_handler(int host_signum, void *pinfo,
bellard90cb9492005-07-24 15:11:38 +00001155 void *puc)
1156{
ths5a7b5422007-01-31 12:16:51 +00001157 siginfo_t *info = pinfo;
bellard90cb9492005-07-24 15:11:38 +00001158 struct ucontext *uc = puc;
1159 unsigned long pc;
Richard Henderson6a1621b2010-06-04 12:14:12 -07001160 uint16_t *pinsn;
1161 int is_write = 0;
ths3b46e622007-09-17 08:09:54 +00001162
bellard90cb9492005-07-24 15:11:38 +00001163 pc = uc->uc_mcontext.psw.addr;
Richard Henderson6a1621b2010-06-04 12:14:12 -07001164
1165 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1166 of the normal 2 arguments. The 3rd argument contains the "int_code"
1167 from the hardware which does in fact contain the is_write value.
1168 The rt signal handler, as far as I can tell, does not give this value
1169 at all. Not that we could get to it from here even if it were. */
1170 /* ??? This is not even close to complete, since it ignores all
1171 of the read-modify-write instructions. */
1172 pinsn = (uint16_t *)pc;
1173 switch (pinsn[0] >> 8) {
1174 case 0x50: /* ST */
1175 case 0x42: /* STC */
1176 case 0x40: /* STH */
1177 is_write = 1;
1178 break;
1179 case 0xc4: /* RIL format insns */
1180 switch (pinsn[0] & 0xf) {
1181 case 0xf: /* STRL */
1182 case 0xb: /* STGRL */
1183 case 0x7: /* STHRL */
1184 is_write = 1;
1185 }
1186 break;
1187 case 0xe3: /* RXY format insns */
1188 switch (pinsn[2] & 0xff) {
1189 case 0x50: /* STY */
1190 case 0x24: /* STG */
1191 case 0x72: /* STCY */
1192 case 0x70: /* STHY */
1193 case 0x8e: /* STPQ */
1194 case 0x3f: /* STRVH */
1195 case 0x3e: /* STRV */
1196 case 0x2f: /* STRVG */
1197 is_write = 1;
1198 }
1199 break;
1200 }
ths5fafdf22007-09-16 21:08:06 +00001201 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
thsc4b89d12007-05-05 19:23:11 +00001202 is_write, &uc->uc_sigmask, puc);
1203}
1204
1205#elif defined(__mips__)
1206
ths5fafdf22007-09-16 21:08:06 +00001207int cpu_signal_handler(int host_signum, void *pinfo,
thsc4b89d12007-05-05 19:23:11 +00001208 void *puc)
1209{
ths9617efe2007-05-08 21:05:55 +00001210 siginfo_t *info = pinfo;
thsc4b89d12007-05-05 19:23:11 +00001211 struct ucontext *uc = puc;
1212 greg_t pc = uc->uc_mcontext.pc;
1213 int is_write;
ths3b46e622007-09-17 08:09:54 +00001214
thsc4b89d12007-05-05 19:23:11 +00001215 /* XXX: compute is_write */
1216 is_write = 0;
ths5fafdf22007-09-16 21:08:06 +00001217 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
thsc4b89d12007-05-05 19:23:11 +00001218 is_write, &uc->uc_sigmask, puc);
bellard90cb9492005-07-24 15:11:38 +00001219}
1220
aurel32f54b3f92008-04-12 20:14:54 +00001221#elif defined(__hppa__)
1222
1223int cpu_signal_handler(int host_signum, void *pinfo,
1224 void *puc)
1225{
1226 struct siginfo *info = pinfo;
1227 struct ucontext *uc = puc;
Richard Hendersonf57040b2010-03-12 15:58:08 +01001228 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1229 uint32_t insn = *(uint32_t *)pc;
1230 int is_write = 0;
aurel32f54b3f92008-04-12 20:14:54 +00001231
Richard Hendersonf57040b2010-03-12 15:58:08 +01001232 /* XXX: need kernel patch to get write flag faster. */
1233 switch (insn >> 26) {
1234 case 0x1a: /* STW */
1235 case 0x19: /* STH */
1236 case 0x18: /* STB */
1237 case 0x1b: /* STWM */
1238 is_write = 1;
1239 break;
1240
1241 case 0x09: /* CSTWX, FSTWX, FSTWS */
1242 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1243 /* Distinguish from coprocessor load ... */
1244 is_write = (insn >> 9) & 1;
1245 break;
1246
1247 case 0x03:
1248 switch ((insn >> 6) & 15) {
1249 case 0xa: /* STWS */
1250 case 0x9: /* STHS */
1251 case 0x8: /* STBS */
1252 case 0xe: /* STWAS */
1253 case 0xc: /* STBYS */
1254 is_write = 1;
1255 }
1256 break;
1257 }
1258
aurel32f54b3f92008-04-12 20:14:54 +00001259 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
Richard Hendersonf57040b2010-03-12 15:58:08 +01001260 is_write, &uc->uc_sigmask, puc);
aurel32f54b3f92008-04-12 20:14:54 +00001261}
1262
bellard2b413142003-05-14 23:01:10 +00001263#else
1264
bellard3fb2ded2003-06-24 13:22:59 +00001265#error host CPU specific signal handler needed
bellard2b413142003-05-14 23:01:10 +00001266
1267#endif
bellard67b915a2004-03-31 23:37:16 +00001268
1269#endif /* !defined(CONFIG_SOFTMMU) */