bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 18 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 20 | #include "exec.h" |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 21 | #include "disas.h" |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 22 | #include "tcg.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 23 | #include "kvm.h" |
Jan Kiszka | 1d93f0f | 2010-06-25 16:56:49 +0200 | [diff] [blame] | 24 | #include "qemu-barrier.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 25 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 26 | #if !defined(CONFIG_SOFTMMU) |
| 27 | #undef EAX |
| 28 | #undef ECX |
| 29 | #undef EDX |
| 30 | #undef EBX |
| 31 | #undef ESP |
| 32 | #undef EBP |
| 33 | #undef ESI |
| 34 | #undef EDI |
| 35 | #undef EIP |
| 36 | #include <signal.h> |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 37 | #ifdef __linux__ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 38 | #include <sys/ucontext.h> |
| 39 | #endif |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 40 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 41 | |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 42 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 572a9d4 | 2008-05-17 07:38:10 +0000 | [diff] [blame] | 43 | // Work around ugly bugs in glibc that mangle global register contents |
| 44 | #undef env |
| 45 | #define env cpu_single_env |
| 46 | #endif |
| 47 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 48 | int tb_invalidated_flag; |
| 49 | |
Juan Quintela | f0667e6 | 2009-07-27 16:13:05 +0200 | [diff] [blame] | 50 | //#define CONFIG_DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 51 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 52 | |
aliguori | 6a4955a | 2009-04-24 18:03:20 +0000 | [diff] [blame] | 53 | int qemu_cpu_has_work(CPUState *env) |
| 54 | { |
| 55 | return cpu_has_work(env); |
| 56 | } |
| 57 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 58 | void cpu_loop_exit(void) |
| 59 | { |
Paolo Bonzini | 1c3569f | 2010-01-15 09:42:07 +0100 | [diff] [blame] | 60 | env->current_tb = NULL; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 61 | longjmp(env->jmp_env, 1); |
| 62 | } |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 63 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 64 | /* exit the current TB from a signal handler. The host registers are |
| 65 | restored in a state compatible with the CPU emulator |
| 66 | */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 67 | void cpu_resume_from_signal(CPUState *env1, void *puc) |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 68 | { |
| 69 | #if !defined(CONFIG_SOFTMMU) |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 70 | #ifdef __linux__ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 71 | struct ucontext *uc = puc; |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 72 | #elif defined(__OpenBSD__) |
| 73 | struct sigcontext *uc = puc; |
| 74 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 75 | #endif |
| 76 | |
| 77 | env = env1; |
| 78 | |
| 79 | /* XXX: restore cpu registers saved in host registers */ |
| 80 | |
| 81 | #if !defined(CONFIG_SOFTMMU) |
| 82 | if (puc) { |
| 83 | /* XXX: use siglongjmp ? */ |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 84 | #ifdef __linux__ |
Aurelien Jarno | 60e9924 | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 85 | #ifdef __ia64 |
| 86 | sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL); |
| 87 | #else |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 88 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
Aurelien Jarno | 60e9924 | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 89 | #endif |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 90 | #elif defined(__OpenBSD__) |
| 91 | sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); |
| 92 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 93 | } |
| 94 | #endif |
pbrook | 9a3ea65 | 2008-12-19 12:49:13 +0000 | [diff] [blame] | 95 | env->exception_index = -1; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 96 | longjmp(env->jmp_env, 1); |
| 97 | } |
| 98 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 99 | /* Execute the code without caching the generated code. An interpreter |
| 100 | could be used if available. */ |
| 101 | static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb) |
| 102 | { |
| 103 | unsigned long next_tb; |
| 104 | TranslationBlock *tb; |
| 105 | |
| 106 | /* Should never happen. |
| 107 | We only end up here when an existing TB is too long. */ |
| 108 | if (max_cycles > CF_COUNT_MASK) |
| 109 | max_cycles = CF_COUNT_MASK; |
| 110 | |
| 111 | tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, |
| 112 | max_cycles); |
| 113 | env->current_tb = tb; |
| 114 | /* execute the generated code */ |
| 115 | next_tb = tcg_qemu_tb_exec(tb->tc_ptr); |
Paolo Bonzini | 1c3569f | 2010-01-15 09:42:07 +0100 | [diff] [blame] | 116 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 117 | |
| 118 | if ((next_tb & 3) == 2) { |
| 119 | /* Restore PC. This may happen if async event occurs before |
| 120 | the TB starts executing. */ |
aliguori | 622ed36 | 2008-11-18 19:36:03 +0000 | [diff] [blame] | 121 | cpu_pc_from_tb(env, tb); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 122 | } |
| 123 | tb_phys_invalidate(tb, -1); |
| 124 | tb_free(tb); |
| 125 | } |
| 126 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 127 | static TranslationBlock *tb_find_slow(target_ulong pc, |
| 128 | target_ulong cs_base, |
j_mayer | c068688 | 2007-09-20 22:47:42 +0000 | [diff] [blame] | 129 | uint64_t flags) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 130 | { |
| 131 | TranslationBlock *tb, **ptb1; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 132 | unsigned int h; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 133 | tb_page_addr_t phys_pc, phys_page1, phys_page2; |
| 134 | target_ulong virt_page2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 135 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 136 | tb_invalidated_flag = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 137 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 138 | /* find translated block using physical mappings */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 139 | phys_pc = get_page_addr_code(env, pc); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 140 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
| 141 | phys_page2 = -1; |
| 142 | h = tb_phys_hash_func(phys_pc); |
| 143 | ptb1 = &tb_phys_hash[h]; |
| 144 | for(;;) { |
| 145 | tb = *ptb1; |
| 146 | if (!tb) |
| 147 | goto not_found; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 148 | if (tb->pc == pc && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 149 | tb->page_addr[0] == phys_page1 && |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 150 | tb->cs_base == cs_base && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 151 | tb->flags == flags) { |
| 152 | /* check next page if needed */ |
| 153 | if (tb->page_addr[1] != -1) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 154 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 155 | TARGET_PAGE_SIZE; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 156 | phys_page2 = get_page_addr_code(env, virt_page2); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 157 | if (tb->page_addr[1] == phys_page2) |
| 158 | goto found; |
| 159 | } else { |
| 160 | goto found; |
| 161 | } |
| 162 | } |
| 163 | ptb1 = &tb->phys_hash_next; |
| 164 | } |
| 165 | not_found: |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 166 | /* if no translated code available, then translate it now */ |
| 167 | tb = tb_gen_code(env, pc, cs_base, flags, 0); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 168 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 169 | found: |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 170 | /* we add the TB in the virtual pc hash table */ |
| 171 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 172 | return tb; |
| 173 | } |
| 174 | |
| 175 | static inline TranslationBlock *tb_find_fast(void) |
| 176 | { |
| 177 | TranslationBlock *tb; |
| 178 | target_ulong cs_base, pc; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 179 | int flags; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 180 | |
| 181 | /* we record a subset of the CPU state. It will |
| 182 | always be the same before a given translated block |
| 183 | is executed. */ |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 184 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); |
bellard | bce6184 | 2008-02-01 22:18:51 +0000 | [diff] [blame] | 185 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
ths | 551bd27 | 2008-07-03 17:57:36 +0000 | [diff] [blame] | 186 | if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || |
| 187 | tb->flags != flags)) { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 188 | tb = tb_find_slow(pc, cs_base, flags); |
| 189 | } |
| 190 | return tb; |
| 191 | } |
| 192 | |
aliguori | dde2367 | 2008-11-18 20:50:36 +0000 | [diff] [blame] | 193 | static CPUDebugExcpHandler *debug_excp_handler; |
| 194 | |
| 195 | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) |
| 196 | { |
| 197 | CPUDebugExcpHandler *old_handler = debug_excp_handler; |
| 198 | |
| 199 | debug_excp_handler = handler; |
| 200 | return old_handler; |
| 201 | } |
| 202 | |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 203 | static void cpu_handle_debug_exception(CPUState *env) |
| 204 | { |
| 205 | CPUWatchpoint *wp; |
| 206 | |
| 207 | if (!env->watchpoint_hit) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 208 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 209 | wp->flags &= ~BP_WATCHPOINT_HIT; |
aliguori | dde2367 | 2008-11-18 20:50:36 +0000 | [diff] [blame] | 210 | |
| 211 | if (debug_excp_handler) |
| 212 | debug_excp_handler(env); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 213 | } |
| 214 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 215 | /* main execution loop */ |
| 216 | |
Marcelo Tosatti | 1a28cac | 2010-05-04 09:45:20 -0300 | [diff] [blame] | 217 | volatile sig_atomic_t exit_request; |
| 218 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 219 | int cpu_exec(CPUState *env1) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 220 | { |
Paolo Bonzini | 1d9000e | 2010-02-23 19:21:00 +0100 | [diff] [blame] | 221 | volatile host_reg_t saved_env_reg; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 222 | int ret, interrupt_request; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 223 | TranslationBlock *tb; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 224 | uint8_t *tc_ptr; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 225 | unsigned long next_tb; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 226 | |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 227 | if (cpu_halted(env1) == EXCP_HALTED) |
| 228 | return EXCP_HALTED; |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 229 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 230 | cpu_single_env = env1; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 231 | |
Paolo Bonzini | 24ebf5f | 2010-02-18 21:25:23 +0100 | [diff] [blame] | 232 | /* the access to env below is actually saving the global register's |
| 233 | value, so that files not including target-xyz/exec.h are free to |
| 234 | use it. */ |
| 235 | QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env)); |
| 236 | saved_env_reg = (host_reg_t) env; |
Jan Kiszka | 1d93f0f | 2010-06-25 16:56:49 +0200 | [diff] [blame] | 237 | barrier(); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 238 | env = env1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 239 | |
Jan Kiszka | c629a4b | 2010-06-25 16:56:52 +0200 | [diff] [blame] | 240 | if (unlikely(exit_request)) { |
Marcelo Tosatti | 1a28cac | 2010-05-04 09:45:20 -0300 | [diff] [blame] | 241 | env->exit_request = 1; |
Marcelo Tosatti | 1a28cac | 2010-05-04 09:45:20 -0300 | [diff] [blame] | 242 | } |
| 243 | |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 244 | #if defined(TARGET_I386) |
Jan Kiszka | 14dcc3e | 2010-02-19 18:21:20 +0100 | [diff] [blame] | 245 | if (!kvm_enabled()) { |
| 246 | /* put eflags in CPU temporary format */ |
| 247 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 248 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 249 | CC_OP = CC_OP_EFLAGS; |
| 250 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 251 | } |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 252 | #elif defined(TARGET_SPARC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 253 | #elif defined(TARGET_M68K) |
| 254 | env->cc_op = CC_OP_FLAGS; |
| 255 | env->cc_dest = env->sr & 0xf; |
| 256 | env->cc_x = (env->sr >> 4) & 1; |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 257 | #elif defined(TARGET_ALPHA) |
| 258 | #elif defined(TARGET_ARM) |
| 259 | #elif defined(TARGET_PPC) |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 260 | #elif defined(TARGET_MICROBLAZE) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 261 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 262 | #elif defined(TARGET_SH4) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 263 | #elif defined(TARGET_CRIS) |
Alexander Graf | 10ec511 | 2009-12-05 12:44:21 +0100 | [diff] [blame] | 264 | #elif defined(TARGET_S390X) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 265 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 266 | #else |
| 267 | #error unsupported target CPU |
| 268 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 269 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 270 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 271 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 272 | for(;;) { |
| 273 | if (setjmp(env->jmp_env) == 0) { |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 274 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 9ddff3d | 2009-04-04 07:41:20 +0000 | [diff] [blame] | 275 | #undef env |
| 276 | env = cpu_single_env; |
| 277 | #define env cpu_single_env |
| 278 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 279 | /* if an exception is pending, we execute it here */ |
| 280 | if (env->exception_index >= 0) { |
| 281 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 282 | /* exit request from the cpu execution loop */ |
| 283 | ret = env->exception_index; |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 284 | if (ret == EXCP_DEBUG) |
| 285 | cpu_handle_debug_exception(env); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 286 | break; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 287 | } else { |
| 288 | #if defined(CONFIG_USER_ONLY) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 289 | /* if user mode only, we simulate a fake exception |
ths | 9f08349 | 2006-12-07 18:28:42 +0000 | [diff] [blame] | 290 | which will be handled outside the cpu execution |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 291 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 292 | #if defined(TARGET_I386) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 293 | do_interrupt_user(env->exception_index, |
| 294 | env->exception_is_int, |
| 295 | env->error_code, |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 296 | env->exception_next_eip); |
bellard | eba0162 | 2008-05-12 12:04:40 +0000 | [diff] [blame] | 297 | /* successfully delivered */ |
| 298 | env->old_exception = -1; |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 299 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 300 | ret = env->exception_index; |
| 301 | break; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 302 | #else |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 303 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 304 | /* simulate a real cpu exception. On i386, it can |
| 305 | trigger new exceptions, but we do not handle |
| 306 | double or triple faults yet. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 307 | do_interrupt(env->exception_index, |
| 308 | env->exception_is_int, |
| 309 | env->error_code, |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 310 | env->exception_next_eip, 0); |
ths | 678dde1 | 2007-03-31 20:28:52 +0000 | [diff] [blame] | 311 | /* successfully delivered */ |
| 312 | env->old_exception = -1; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 313 | #elif defined(TARGET_PPC) |
| 314 | do_interrupt(env); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 315 | #elif defined(TARGET_MICROBLAZE) |
| 316 | do_interrupt(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 317 | #elif defined(TARGET_MIPS) |
| 318 | do_interrupt(env); |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 319 | #elif defined(TARGET_SPARC) |
blueswir1 | f2bc7e7 | 2008-05-27 17:35:30 +0000 | [diff] [blame] | 320 | do_interrupt(env); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 321 | #elif defined(TARGET_ARM) |
| 322 | do_interrupt(env); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 323 | #elif defined(TARGET_SH4) |
| 324 | do_interrupt(env); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 325 | #elif defined(TARGET_ALPHA) |
| 326 | do_interrupt(env); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 327 | #elif defined(TARGET_CRIS) |
| 328 | do_interrupt(env); |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 329 | #elif defined(TARGET_M68K) |
| 330 | do_interrupt(0); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 331 | #endif |
Paolo Bonzini | 301d290 | 2010-01-15 09:41:01 +0100 | [diff] [blame] | 332 | env->exception_index = -1; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 333 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 334 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 335 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 336 | |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 337 | if (kvm_enabled()) { |
aliguori | becfc39 | 2008-11-10 15:55:14 +0000 | [diff] [blame] | 338 | kvm_cpu_exec(env); |
| 339 | longjmp(env->jmp_env, 1); |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 340 | } |
| 341 | |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 342 | next_tb = 0; /* force lookup of first TB */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 343 | for(;;) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 344 | interrupt_request = env->interrupt_request; |
malc | e1638bd | 2008-11-06 18:54:46 +0000 | [diff] [blame] | 345 | if (unlikely(interrupt_request)) { |
| 346 | if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { |
| 347 | /* Mask out external interrupts for this step. */ |
| 348 | interrupt_request &= ~(CPU_INTERRUPT_HARD | |
| 349 | CPU_INTERRUPT_FIQ | |
| 350 | CPU_INTERRUPT_SMI | |
| 351 | CPU_INTERRUPT_NMI); |
| 352 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 353 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
| 354 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; |
| 355 | env->exception_index = EXCP_DEBUG; |
| 356 | cpu_loop_exit(); |
| 357 | } |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 358 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 359 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
| 360 | defined(TARGET_MICROBLAZE) |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 361 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
| 362 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
| 363 | env->halted = 1; |
| 364 | env->exception_index = EXCP_HLT; |
| 365 | cpu_loop_exit(); |
| 366 | } |
| 367 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 368 | #if defined(TARGET_I386) |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 369 | if (interrupt_request & CPU_INTERRUPT_INIT) { |
| 370 | svm_check_intercept(SVM_EXIT_INIT); |
| 371 | do_cpu_init(env); |
| 372 | env->exception_index = EXCP_HALTED; |
| 373 | cpu_loop_exit(); |
| 374 | } else if (interrupt_request & CPU_INTERRUPT_SIPI) { |
| 375 | do_cpu_sipi(env); |
| 376 | } else if (env->hflags2 & HF2_GIF_MASK) { |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 377 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
| 378 | !(env->hflags & HF_SMM_MASK)) { |
| 379 | svm_check_intercept(SVM_EXIT_SMI); |
| 380 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
| 381 | do_smm_enter(); |
| 382 | next_tb = 0; |
| 383 | } else if ((interrupt_request & CPU_INTERRUPT_NMI) && |
| 384 | !(env->hflags2 & HF2_NMI_MASK)) { |
| 385 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; |
| 386 | env->hflags2 |= HF2_NMI_MASK; |
| 387 | do_interrupt(EXCP02_NMI, 0, 0, 0, 1); |
| 388 | next_tb = 0; |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 389 | } else if (interrupt_request & CPU_INTERRUPT_MCE) { |
| 390 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; |
| 391 | do_interrupt(EXCP12_MCHK, 0, 0, 0, 0); |
| 392 | next_tb = 0; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 393 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 394 | (((env->hflags2 & HF2_VINTR_MASK) && |
| 395 | (env->hflags2 & HF2_HIF_MASK)) || |
| 396 | (!(env->hflags2 & HF2_VINTR_MASK) && |
| 397 | (env->eflags & IF_MASK && |
| 398 | !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { |
| 399 | int intno; |
| 400 | svm_check_intercept(SVM_EXIT_INTR); |
| 401 | env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); |
| 402 | intno = cpu_get_pic_interrupt(env); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 403 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 404 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 9ddff3d | 2009-04-04 07:41:20 +0000 | [diff] [blame] | 405 | #undef env |
| 406 | env = cpu_single_env; |
| 407 | #define env cpu_single_env |
| 408 | #endif |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 409 | do_interrupt(intno, 0, 0, 0, 1); |
| 410 | /* ensure that no TB jump will be modified as |
| 411 | the program flow was changed */ |
| 412 | next_tb = 0; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 413 | #if !defined(CONFIG_USER_ONLY) |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 414 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
| 415 | (env->eflags & IF_MASK) && |
| 416 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
| 417 | int intno; |
| 418 | /* FIXME: this should respect TPR */ |
| 419 | svm_check_intercept(SVM_EXIT_VINTR); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 420 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 421 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 422 | do_interrupt(intno, 0, 0, 0, 1); |
aurel32 | d40c54d | 2008-12-13 12:33:02 +0000 | [diff] [blame] | 423 | env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 424 | next_tb = 0; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 425 | #endif |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 426 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 427 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 428 | #elif defined(TARGET_PPC) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 429 | #if 0 |
| 430 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
Blue Swirl | d84bda4 | 2009-11-07 10:36:04 +0000 | [diff] [blame] | 431 | cpu_reset(env); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 432 | } |
| 433 | #endif |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 434 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 435 | ppc_hw_interrupt(env); |
| 436 | if (env->pending_interrupts == 0) |
| 437 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 438 | next_tb = 0; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 439 | } |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 440 | #elif defined(TARGET_MICROBLAZE) |
| 441 | if ((interrupt_request & CPU_INTERRUPT_HARD) |
| 442 | && (env->sregs[SR_MSR] & MSR_IE) |
| 443 | && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) |
| 444 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { |
| 445 | env->exception_index = EXCP_IRQ; |
| 446 | do_interrupt(env); |
| 447 | next_tb = 0; |
| 448 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 449 | #elif defined(TARGET_MIPS) |
| 450 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
Edgar E. Iglesias | 138afb0 | 2010-08-06 12:21:16 +0200 | [diff] [blame] | 451 | cpu_mips_hw_interrupts_pending(env) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 452 | (env->CP0_Status & (1 << CP0St_IE)) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 453 | !(env->CP0_Status & (1 << CP0St_EXL)) && |
| 454 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 455 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 456 | /* Raise it */ |
| 457 | env->exception_index = EXCP_EXT_INTERRUPT; |
| 458 | env->error_code = 0; |
| 459 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 460 | next_tb = 0; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 461 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 462 | #elif defined(TARGET_SPARC) |
Igor V. Kovalenko | d532b26 | 2010-01-07 23:28:31 +0300 | [diff] [blame] | 463 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 464 | if (cpu_interrupts_enabled(env) && |
| 465 | env->interrupt_index > 0) { |
| 466 | int pil = env->interrupt_index & 0xf; |
| 467 | int type = env->interrupt_index & 0xf0; |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 468 | |
Igor V. Kovalenko | d532b26 | 2010-01-07 23:28:31 +0300 | [diff] [blame] | 469 | if (((type == TT_EXTINT) && |
| 470 | cpu_pil_allowed(env, pil)) || |
| 471 | type != TT_EXTINT) { |
| 472 | env->exception_index = env->interrupt_index; |
| 473 | do_interrupt(env); |
| 474 | next_tb = 0; |
| 475 | } |
| 476 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 477 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 478 | //do_interrupt(0, 0, 0, 0, 0); |
| 479 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 480 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 481 | #elif defined(TARGET_ARM) |
| 482 | if (interrupt_request & CPU_INTERRUPT_FIQ |
| 483 | && !(env->uncached_cpsr & CPSR_F)) { |
| 484 | env->exception_index = EXCP_FIQ; |
| 485 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 486 | next_tb = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 487 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 488 | /* ARMv7-M interrupt return works by loading a magic value |
| 489 | into the PC. On real hardware the load causes the |
| 490 | return to occur. The qemu implementation performs the |
| 491 | jump normally, then does the exception return when the |
| 492 | CPU tries to execute code at the magic address. |
| 493 | This will cause the magic PC value to be pushed to |
| 494 | the stack if an interrupt occured at the wrong time. |
| 495 | We avoid this by disabling interrupts when |
| 496 | pc contains a magic address. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 497 | if (interrupt_request & CPU_INTERRUPT_HARD |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 498 | && ((IS_M(env) && env->regs[15] < 0xfffffff0) |
| 499 | || !(env->uncached_cpsr & CPSR_I))) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 500 | env->exception_index = EXCP_IRQ; |
| 501 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 502 | next_tb = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 503 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 504 | #elif defined(TARGET_SH4) |
ths | e96e204 | 2007-12-02 06:18:24 +0000 | [diff] [blame] | 505 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 506 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 507 | next_tb = 0; |
ths | e96e204 | 2007-12-02 06:18:24 +0000 | [diff] [blame] | 508 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 509 | #elif defined(TARGET_ALPHA) |
| 510 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 511 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 512 | next_tb = 0; |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 513 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 514 | #elif defined(TARGET_CRIS) |
edgar_igl | 1b1a38b | 2008-06-09 23:18:06 +0000 | [diff] [blame] | 515 | if (interrupt_request & CPU_INTERRUPT_HARD |
Edgar E. Iglesias | fb9fb69 | 2010-02-15 11:17:33 +0100 | [diff] [blame] | 516 | && (env->pregs[PR_CCS] & I_FLAG) |
| 517 | && !env->locked_irq) { |
edgar_igl | 1b1a38b | 2008-06-09 23:18:06 +0000 | [diff] [blame] | 518 | env->exception_index = EXCP_IRQ; |
| 519 | do_interrupt(env); |
| 520 | next_tb = 0; |
| 521 | } |
| 522 | if (interrupt_request & CPU_INTERRUPT_NMI |
| 523 | && (env->pregs[PR_CCS] & M_FLAG)) { |
| 524 | env->exception_index = EXCP_NMI; |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 525 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 526 | next_tb = 0; |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 527 | } |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 528 | #elif defined(TARGET_M68K) |
| 529 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 530 | && ((env->sr & SR_I) >> SR_I_SHIFT) |
| 531 | < env->pending_level) { |
| 532 | /* Real hardware gets the interrupt vector via an |
| 533 | IACK cycle at this point. Current emulated |
| 534 | hardware doesn't rely on this, so we |
| 535 | provide/save the vector when the interrupt is |
| 536 | first signalled. */ |
| 537 | env->exception_index = env->pending_vector; |
| 538 | do_interrupt(1); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 539 | next_tb = 0; |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 540 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 541 | #endif |
bellard | 9d05095 | 2006-05-22 22:03:52 +0000 | [diff] [blame] | 542 | /* Don't use the cached interupt_request value, |
| 543 | do_interrupt may have updated the EXITTB flag. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 544 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 545 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
| 546 | /* ensure that no TB jump will be modified as |
| 547 | the program flow was changed */ |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 548 | next_tb = 0; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 549 | } |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 550 | } |
| 551 | if (unlikely(env->exit_request)) { |
| 552 | env->exit_request = 0; |
| 553 | env->exception_index = EXCP_INTERRUPT; |
| 554 | cpu_loop_exit(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 555 | } |
Richard Henderson | a73b1fd | 2010-04-28 16:07:57 -0700 | [diff] [blame] | 556 | #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC) |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 557 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 558 | /* restore flags in standard format */ |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 559 | #if defined(TARGET_I386) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 560 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 561 | log_cpu_state(env, X86_DUMP_CCOP); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 562 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 563 | #elif defined(TARGET_M68K) |
| 564 | cpu_m68k_flush_flags(env, env->cc_op); |
| 565 | env->cc_op = CC_OP_FLAGS; |
| 566 | env->sr = (env->sr & 0xffe0) |
| 567 | | env->cc_dest | (env->cc_x << 4); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 568 | log_cpu_state(env, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 569 | #else |
Richard Henderson | a73b1fd | 2010-04-28 16:07:57 -0700 | [diff] [blame] | 570 | log_cpu_state(env, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 571 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 572 | } |
Richard Henderson | a73b1fd | 2010-04-28 16:07:57 -0700 | [diff] [blame] | 573 | #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */ |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 574 | spin_lock(&tb_lock); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 575 | tb = tb_find_fast(); |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 576 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
| 577 | doing it in tb_find_slow */ |
| 578 | if (tb_invalidated_flag) { |
| 579 | /* as some TB could have been invalidated because |
| 580 | of memory exceptions while generating the code, we |
| 581 | must recompute the hash index here */ |
| 582 | next_tb = 0; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 583 | tb_invalidated_flag = 0; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 584 | } |
Juan Quintela | f0667e6 | 2009-07-27 16:13:05 +0200 | [diff] [blame] | 585 | #ifdef CONFIG_DEBUG_EXEC |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 586 | qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
| 587 | (long)tb->tc_ptr, tb->pc, |
| 588 | lookup_symbol(tb->pc)); |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 589 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 590 | /* see if we can patch the calling TB. When the TB |
| 591 | spans two pages, we cannot safely do a direct |
| 592 | jump. */ |
Paolo Bonzini | 040f2fb | 2010-01-15 08:56:36 +0100 | [diff] [blame] | 593 | if (next_tb != 0 && tb->page_addr[1] == -1) { |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 594 | tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 595 | } |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 596 | spin_unlock(&tb_lock); |
malc | 55e8b85 | 2008-11-04 14:18:13 +0000 | [diff] [blame] | 597 | |
| 598 | /* cpu_interrupt might be called while translating the |
| 599 | TB, but before it is linked into a potentially |
| 600 | infinite loop and becomes env->current_tb. Avoid |
| 601 | starting execution if there is a pending interrupt. */ |
Jan Kiszka | b0052d1 | 2010-06-25 16:56:50 +0200 | [diff] [blame] | 602 | env->current_tb = tb; |
| 603 | barrier(); |
| 604 | if (likely(!env->exit_request)) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 605 | tc_ptr = tb->tc_ptr; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 606 | /* execute the generated code */ |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 607 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 572a9d4 | 2008-05-17 07:38:10 +0000 | [diff] [blame] | 608 | #undef env |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 609 | env = cpu_single_env; |
blueswir1 | 572a9d4 | 2008-05-17 07:38:10 +0000 | [diff] [blame] | 610 | #define env cpu_single_env |
| 611 | #endif |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 612 | next_tb = tcg_qemu_tb_exec(tc_ptr); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 613 | if ((next_tb & 3) == 2) { |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 614 | /* Instruction counter expired. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 615 | int insns_left; |
| 616 | tb = (TranslationBlock *)(long)(next_tb & ~3); |
| 617 | /* Restore PC. */ |
aliguori | 622ed36 | 2008-11-18 19:36:03 +0000 | [diff] [blame] | 618 | cpu_pc_from_tb(env, tb); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 619 | insns_left = env->icount_decr.u32; |
| 620 | if (env->icount_extra && insns_left >= 0) { |
| 621 | /* Refill decrementer and continue execution. */ |
| 622 | env->icount_extra += insns_left; |
| 623 | if (env->icount_extra > 0xffff) { |
| 624 | insns_left = 0xffff; |
| 625 | } else { |
| 626 | insns_left = env->icount_extra; |
| 627 | } |
| 628 | env->icount_extra -= insns_left; |
| 629 | env->icount_decr.u16.low = insns_left; |
| 630 | } else { |
| 631 | if (insns_left > 0) { |
| 632 | /* Execute remaining instructions. */ |
| 633 | cpu_exec_nocache(insns_left, tb); |
| 634 | } |
| 635 | env->exception_index = EXCP_INTERRUPT; |
| 636 | next_tb = 0; |
| 637 | cpu_loop_exit(); |
| 638 | } |
| 639 | } |
| 640 | } |
Jan Kiszka | b0052d1 | 2010-06-25 16:56:50 +0200 | [diff] [blame] | 641 | env->current_tb = NULL; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 642 | /* reset soft MMU for next block (it can currently |
| 643 | only be set by a memory fault) */ |
ths | 50a518e | 2007-06-03 18:52:15 +0000 | [diff] [blame] | 644 | } /* for(;;) */ |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 645 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 646 | } /* for(;;) */ |
| 647 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 648 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 649 | #if defined(TARGET_I386) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 650 | /* restore flags in standard format */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 651 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 652 | #elif defined(TARGET_ARM) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 653 | /* XXX: Save/restore host fpu exception state?. */ |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 654 | #elif defined(TARGET_SPARC) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 655 | #elif defined(TARGET_PPC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 656 | #elif defined(TARGET_M68K) |
| 657 | cpu_m68k_flush_flags(env, env->cc_op); |
| 658 | env->cc_op = CC_OP_FLAGS; |
| 659 | env->sr = (env->sr & 0xffe0) |
| 660 | | env->cc_dest | (env->cc_x << 4); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 661 | #elif defined(TARGET_MICROBLAZE) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 662 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 663 | #elif defined(TARGET_SH4) |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 664 | #elif defined(TARGET_ALPHA) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 665 | #elif defined(TARGET_CRIS) |
Alexander Graf | 10ec511 | 2009-12-05 12:44:21 +0100 | [diff] [blame] | 666 | #elif defined(TARGET_S390X) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 667 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 668 | #else |
| 669 | #error unsupported target CPU |
| 670 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 671 | |
| 672 | /* restore global registers */ |
Jan Kiszka | 1d93f0f | 2010-06-25 16:56:49 +0200 | [diff] [blame] | 673 | barrier(); |
Paolo Bonzini | 24ebf5f | 2010-02-18 21:25:23 +0100 | [diff] [blame] | 674 | env = (void *) saved_env_reg; |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 675 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 676 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 677 | cpu_single_env = NULL; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 678 | return ret; |
| 679 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 680 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 681 | /* must only be called from the generated code as an exception can be |
| 682 | generated */ |
| 683 | void tb_invalidate_page_range(target_ulong start, target_ulong end) |
| 684 | { |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 685 | /* XXX: cannot enable it yet because it yields to MMU exception |
| 686 | where NIP != read address on PowerPC */ |
| 687 | #if 0 |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 688 | target_ulong phys_addr; |
| 689 | phys_addr = get_phys_addr_code(env, start); |
| 690 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 691 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 692 | } |
| 693 | |
bellard | 1a18c71 | 2003-10-30 01:07:51 +0000 | [diff] [blame] | 694 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 695 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 696 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 697 | { |
| 698 | CPUX86State *saved_env; |
| 699 | |
| 700 | saved_env = env; |
| 701 | env = s; |
bellard | a412ac5 | 2003-07-26 18:01:40 +0000 | [diff] [blame] | 702 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 703 | selector &= 0xffff; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 704 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 705 | (selector << 4), 0xffff, 0); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 706 | } else { |
bellard | 5d97559 | 2008-05-12 22:05:33 +0000 | [diff] [blame] | 707 | helper_load_seg(seg_reg, selector); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 708 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 709 | env = saved_env; |
| 710 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 711 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 712 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32) |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 713 | { |
| 714 | CPUX86State *saved_env; |
| 715 | |
| 716 | saved_env = env; |
| 717 | env = s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 718 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 719 | helper_fsave(ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 720 | |
| 721 | env = saved_env; |
| 722 | } |
| 723 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 724 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32) |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 725 | { |
| 726 | CPUX86State *saved_env; |
| 727 | |
| 728 | saved_env = env; |
| 729 | env = s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 730 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 731 | helper_frstor(ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 732 | |
| 733 | env = saved_env; |
| 734 | } |
| 735 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 736 | #endif /* TARGET_I386 */ |
| 737 | |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 738 | #if !defined(CONFIG_SOFTMMU) |
| 739 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 740 | #if defined(TARGET_I386) |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 741 | #define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code) |
| 742 | #else |
| 743 | #define EXCEPTION_ACTION cpu_loop_exit() |
| 744 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 745 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 746 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 747 | the effective address of the memory exception. 'is_write' is 1 if a |
| 748 | write caused the exception and otherwise 0'. 'old_set' is the |
| 749 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 750 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 751 | int is_write, sigset_t *old_set, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 752 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 753 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 754 | TranslationBlock *tb; |
| 755 | int ret; |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 756 | |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 757 | if (cpu_single_env) |
| 758 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 759 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 760 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 761 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 762 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 763 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 764 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 765 | return 1; |
| 766 | } |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 767 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 768 | /* see if it is an MMU fault */ |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 769 | ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 770 | if (ret < 0) |
| 771 | return 0; /* not an MMU fault */ |
| 772 | if (ret == 0) |
| 773 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 774 | /* now we have a real cpu fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 775 | tb = tb_find_pc(pc); |
| 776 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 777 | /* the PC is inside the translated code. It means that we have |
| 778 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 779 | cpu_restore_state(tb, env, pc, puc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 780 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 781 | |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 782 | /* we restore the process signal mask as the sigreturn should |
| 783 | do it (XXX: use sigsetjmp) */ |
| 784 | sigprocmask(SIG_SETMASK, old_set, NULL); |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 785 | EXCEPTION_ACTION; |
| 786 | |
aurel32 | 968c74d | 2008-04-11 04:55:17 +0000 | [diff] [blame] | 787 | /* never comes here */ |
| 788 | return 1; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 789 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 790 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 791 | #if defined(__i386__) |
| 792 | |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 793 | #if defined(__APPLE__) |
| 794 | # include <sys/ucontext.h> |
| 795 | |
| 796 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) |
| 797 | # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) |
| 798 | # define ERROR_sig(context) ((context)->uc_mcontext->es.err) |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 799 | # define MASK_sig(context) ((context)->uc_sigmask) |
Juergen Lock | 78cfb07 | 2009-10-17 00:34:26 +0200 | [diff] [blame] | 800 | #elif defined (__NetBSD__) |
| 801 | # include <ucontext.h> |
| 802 | |
| 803 | # define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) |
| 804 | # define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) |
| 805 | # define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) |
| 806 | # define MASK_sig(context) ((context)->uc_sigmask) |
| 807 | #elif defined (__FreeBSD__) || defined(__DragonFly__) |
| 808 | # include <ucontext.h> |
| 809 | |
| 810 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip)) |
| 811 | # define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) |
| 812 | # define ERROR_sig(context) ((context)->uc_mcontext.mc_err) |
| 813 | # define MASK_sig(context) ((context)->uc_sigmask) |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 814 | #elif defined(__OpenBSD__) |
| 815 | # define EIP_sig(context) ((context)->sc_eip) |
| 816 | # define TRAP_sig(context) ((context)->sc_trapno) |
| 817 | # define ERROR_sig(context) ((context)->sc_err) |
| 818 | # define MASK_sig(context) ((context)->sc_mask) |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 819 | #else |
| 820 | # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) |
| 821 | # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
| 822 | # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 823 | # define MASK_sig(context) ((context)->uc_sigmask) |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 824 | #endif |
| 825 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 826 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 827 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 828 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 829 | siginfo_t *info = pinfo; |
Juergen Lock | 78cfb07 | 2009-10-17 00:34:26 +0200 | [diff] [blame] | 830 | #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__) |
| 831 | ucontext_t *uc = puc; |
| 832 | #elif defined(__OpenBSD__) |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 833 | struct sigcontext *uc = puc; |
| 834 | #else |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 835 | struct ucontext *uc = puc; |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 836 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 837 | unsigned long pc; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 838 | int trapno; |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 839 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 840 | #ifndef REG_EIP |
| 841 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 842 | #define REG_EIP EIP |
| 843 | #define REG_ERR ERR |
| 844 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 845 | #endif |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 846 | pc = EIP_sig(uc); |
| 847 | trapno = TRAP_sig(uc); |
bellard | ec6338b | 2007-11-08 14:25:03 +0000 | [diff] [blame] | 848 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 849 | trapno == 0xe ? |
| 850 | (ERROR_sig(uc) >> 1) & 1 : 0, |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 851 | &MASK_sig(uc), puc); |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 852 | } |
| 853 | |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 854 | #elif defined(__x86_64__) |
| 855 | |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 856 | #ifdef __NetBSD__ |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 857 | #define PC_sig(context) _UC_MACHINE_PC(context) |
| 858 | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) |
| 859 | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) |
| 860 | #define MASK_sig(context) ((context)->uc_sigmask) |
| 861 | #elif defined(__OpenBSD__) |
| 862 | #define PC_sig(context) ((context)->sc_rip) |
| 863 | #define TRAP_sig(context) ((context)->sc_trapno) |
| 864 | #define ERROR_sig(context) ((context)->sc_err) |
| 865 | #define MASK_sig(context) ((context)->sc_mask) |
Juergen Lock | 78cfb07 | 2009-10-17 00:34:26 +0200 | [diff] [blame] | 866 | #elif defined (__FreeBSD__) || defined(__DragonFly__) |
| 867 | #include <ucontext.h> |
| 868 | |
| 869 | #define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip)) |
| 870 | #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) |
| 871 | #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) |
| 872 | #define MASK_sig(context) ((context)->uc_sigmask) |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 873 | #else |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 874 | #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) |
| 875 | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
| 876 | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
| 877 | #define MASK_sig(context) ((context)->uc_sigmask) |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 878 | #endif |
| 879 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 880 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 881 | void *puc) |
| 882 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 883 | siginfo_t *info = pinfo; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 884 | unsigned long pc; |
Juergen Lock | 78cfb07 | 2009-10-17 00:34:26 +0200 | [diff] [blame] | 885 | #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__) |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 886 | ucontext_t *uc = puc; |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 887 | #elif defined(__OpenBSD__) |
| 888 | struct sigcontext *uc = puc; |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 889 | #else |
| 890 | struct ucontext *uc = puc; |
| 891 | #endif |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 892 | |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 893 | pc = PC_sig(uc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 894 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 895 | TRAP_sig(uc) == 0xe ? |
| 896 | (ERROR_sig(uc) >> 1) & 1 : 0, |
| 897 | &MASK_sig(uc), puc); |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 898 | } |
| 899 | |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 900 | #elif defined(_ARCH_PPC) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 901 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 902 | /*********************************************************************** |
| 903 | * signal context platform-specific definitions |
| 904 | * From Wine |
| 905 | */ |
| 906 | #ifdef linux |
| 907 | /* All Registers access - only for local access */ |
| 908 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) |
| 909 | /* Gpr Registers access */ |
| 910 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) |
| 911 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
| 912 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
| 913 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
| 914 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
| 915 | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
| 916 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
| 917 | /* Float Registers access */ |
| 918 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
| 919 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
| 920 | /* Exception Registers access */ |
| 921 | # define DAR_sig(context) REG_sig(dar, context) |
| 922 | # define DSISR_sig(context) REG_sig(dsisr, context) |
| 923 | # define TRAP_sig(context) REG_sig(trap, context) |
| 924 | #endif /* linux */ |
| 925 | |
Juergen Lock | 58d9b1e | 2010-02-19 19:29:25 +0100 | [diff] [blame] | 926 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
| 927 | #include <ucontext.h> |
| 928 | # define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) |
| 929 | # define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) |
| 930 | # define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) |
| 931 | # define XER_sig(context) ((context)->uc_mcontext.mc_xer) |
| 932 | # define LR_sig(context) ((context)->uc_mcontext.mc_lr) |
| 933 | # define CR_sig(context) ((context)->uc_mcontext.mc_cr) |
| 934 | /* Exception Registers access */ |
| 935 | # define DAR_sig(context) ((context)->uc_mcontext.mc_dar) |
| 936 | # define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) |
| 937 | # define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) |
| 938 | #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ |
| 939 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 940 | #ifdef __APPLE__ |
| 941 | # include <sys/ucontext.h> |
| 942 | typedef struct ucontext SIGCONTEXT; |
| 943 | /* All Registers access - only for local access */ |
| 944 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) |
| 945 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) |
| 946 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) |
| 947 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) |
| 948 | /* Gpr Registers access */ |
| 949 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
| 950 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
| 951 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
| 952 | # define CTR_sig(context) REG_sig(ctr, context) |
| 953 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
| 954 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
| 955 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
| 956 | /* Float Registers access */ |
| 957 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) |
| 958 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
| 959 | /* Exception Registers access */ |
| 960 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
| 961 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) |
| 962 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
| 963 | #endif /* __APPLE__ */ |
| 964 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 965 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 966 | void *puc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 967 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 968 | siginfo_t *info = pinfo; |
Juergen Lock | 58d9b1e | 2010-02-19 19:29:25 +0100 | [diff] [blame] | 969 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
| 970 | ucontext_t *uc = puc; |
| 971 | #else |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 972 | struct ucontext *uc = puc; |
Juergen Lock | 58d9b1e | 2010-02-19 19:29:25 +0100 | [diff] [blame] | 973 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 974 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 975 | int is_write; |
| 976 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 977 | pc = IAR_sig(uc); |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 978 | is_write = 0; |
| 979 | #if 0 |
| 980 | /* ppc 4xx case */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 981 | if (DSISR_sig(uc) & 0x00800000) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 982 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 983 | #else |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 984 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 985 | is_write = 1; |
| 986 | #endif |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 987 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 988 | is_write, &uc->uc_sigmask, puc); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 989 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 990 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 991 | #elif defined(__alpha__) |
| 992 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 993 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 994 | void *puc) |
| 995 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 996 | siginfo_t *info = pinfo; |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 997 | struct ucontext *uc = puc; |
| 998 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 999 | uint32_t insn = *pc; |
| 1000 | int is_write = 0; |
| 1001 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1002 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1003 | switch (insn >> 26) { |
| 1004 | case 0x0d: // stw |
| 1005 | case 0x0e: // stb |
| 1006 | case 0x0f: // stq_u |
| 1007 | case 0x24: // stf |
| 1008 | case 0x25: // stg |
| 1009 | case 0x26: // sts |
| 1010 | case 0x27: // stt |
| 1011 | case 0x2c: // stl |
| 1012 | case 0x2d: // stq |
| 1013 | case 0x2e: // stl_c |
| 1014 | case 0x2f: // stq_c |
| 1015 | is_write = 1; |
| 1016 | } |
| 1017 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1018 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1019 | is_write, &uc->uc_sigmask, puc); |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1020 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1021 | #elif defined(__sparc__) |
| 1022 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1023 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1024 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1025 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1026 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1027 | int is_write; |
| 1028 | uint32_t insn; |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 1029 | #if !defined(__arch64__) || defined(CONFIG_SOLARIS) |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1030 | uint32_t *regs = (uint32_t *)(info + 1); |
| 1031 | void *sigmask = (regs + 20); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1032 | /* XXX: is there a standard glibc define ? */ |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1033 | unsigned long pc = regs[1]; |
| 1034 | #else |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 1035 | #ifdef __linux__ |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1036 | struct sigcontext *sc = puc; |
| 1037 | unsigned long pc = sc->sigc_regs.tpc; |
| 1038 | void *sigmask = (void *)sc->sigc_mask; |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 1039 | #elif defined(__OpenBSD__) |
| 1040 | struct sigcontext *uc = puc; |
| 1041 | unsigned long pc = uc->sc_pc; |
| 1042 | void *sigmask = (void *)(long)uc->sc_mask; |
| 1043 | #endif |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1044 | #endif |
| 1045 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1046 | /* XXX: need kernel patch to get write flag faster */ |
| 1047 | is_write = 0; |
| 1048 | insn = *(uint32_t *)pc; |
| 1049 | if ((insn >> 30) == 3) { |
| 1050 | switch((insn >> 19) & 0x3f) { |
| 1051 | case 0x05: // stb |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1052 | case 0x15: // stba |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1053 | case 0x06: // sth |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1054 | case 0x16: // stha |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1055 | case 0x04: // st |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1056 | case 0x14: // sta |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1057 | case 0x07: // std |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1058 | case 0x17: // stda |
| 1059 | case 0x0e: // stx |
| 1060 | case 0x1e: // stxa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1061 | case 0x24: // stf |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1062 | case 0x34: // stfa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1063 | case 0x27: // stdf |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1064 | case 0x37: // stdfa |
| 1065 | case 0x26: // stqf |
| 1066 | case 0x36: // stqfa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1067 | case 0x25: // stfsr |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1068 | case 0x3c: // casa |
| 1069 | case 0x3e: // casxa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1070 | is_write = 1; |
| 1071 | break; |
| 1072 | } |
| 1073 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1074 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1075 | is_write, sigmask, NULL); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1076 | } |
| 1077 | |
| 1078 | #elif defined(__arm__) |
| 1079 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1080 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1081 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1082 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1083 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1084 | struct ucontext *uc = puc; |
| 1085 | unsigned long pc; |
| 1086 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1087 | |
blueswir1 | 48bbf11 | 2008-07-08 18:35:02 +0000 | [diff] [blame] | 1088 | #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) |
balrog | 5c49b36 | 2008-06-02 01:01:18 +0000 | [diff] [blame] | 1089 | pc = uc->uc_mcontext.gregs[R15]; |
| 1090 | #else |
balrog | 4eee57f | 2008-05-06 14:47:19 +0000 | [diff] [blame] | 1091 | pc = uc->uc_mcontext.arm_pc; |
balrog | 5c49b36 | 2008-06-02 01:01:18 +0000 | [diff] [blame] | 1092 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1093 | /* XXX: compute is_write */ |
| 1094 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1095 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1096 | is_write, |
pbrook | f3a9676 | 2006-07-29 19:09:31 +0000 | [diff] [blame] | 1097 | &uc->uc_sigmask, puc); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1098 | } |
| 1099 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1100 | #elif defined(__mc68000) |
| 1101 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1102 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1103 | void *puc) |
| 1104 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1105 | siginfo_t *info = pinfo; |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1106 | struct ucontext *uc = puc; |
| 1107 | unsigned long pc; |
| 1108 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1109 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1110 | pc = uc->uc_mcontext.gregs[16]; |
| 1111 | /* XXX: compute is_write */ |
| 1112 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1113 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1114 | is_write, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1115 | &uc->uc_sigmask, puc); |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1118 | #elif defined(__ia64) |
| 1119 | |
| 1120 | #ifndef __ISR_VALID |
| 1121 | /* This ought to be in <bits/siginfo.h>... */ |
| 1122 | # define __ISR_VALID 1 |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1123 | #endif |
| 1124 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1125 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1126 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1127 | siginfo_t *info = pinfo; |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1128 | struct ucontext *uc = puc; |
| 1129 | unsigned long ip; |
| 1130 | int is_write = 0; |
| 1131 | |
| 1132 | ip = uc->uc_mcontext.sc_ip; |
| 1133 | switch (host_signum) { |
| 1134 | case SIGILL: |
| 1135 | case SIGFPE: |
| 1136 | case SIGSEGV: |
| 1137 | case SIGBUS: |
| 1138 | case SIGTRAP: |
bellard | fd4a43e | 2006-04-24 20:32:17 +0000 | [diff] [blame] | 1139 | if (info->si_code && (info->si_segvflags & __ISR_VALID)) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1140 | /* ISR.W (write-access) is bit 33: */ |
| 1141 | is_write = (info->si_isr >> 33) & 1; |
| 1142 | break; |
| 1143 | |
| 1144 | default: |
| 1145 | break; |
| 1146 | } |
| 1147 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 1148 | is_write, |
Aurelien Jarno | 60e9924 | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 1149 | (sigset_t *)&uc->uc_sigmask, puc); |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1150 | } |
| 1151 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1152 | #elif defined(__s390__) |
| 1153 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1154 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1155 | void *puc) |
| 1156 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1157 | siginfo_t *info = pinfo; |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1158 | struct ucontext *uc = puc; |
| 1159 | unsigned long pc; |
Richard Henderson | 6a1621b | 2010-06-04 12:14:12 -0700 | [diff] [blame] | 1160 | uint16_t *pinsn; |
| 1161 | int is_write = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1162 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1163 | pc = uc->uc_mcontext.psw.addr; |
Richard Henderson | 6a1621b | 2010-06-04 12:14:12 -0700 | [diff] [blame] | 1164 | |
| 1165 | /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead |
| 1166 | of the normal 2 arguments. The 3rd argument contains the "int_code" |
| 1167 | from the hardware which does in fact contain the is_write value. |
| 1168 | The rt signal handler, as far as I can tell, does not give this value |
| 1169 | at all. Not that we could get to it from here even if it were. */ |
| 1170 | /* ??? This is not even close to complete, since it ignores all |
| 1171 | of the read-modify-write instructions. */ |
| 1172 | pinsn = (uint16_t *)pc; |
| 1173 | switch (pinsn[0] >> 8) { |
| 1174 | case 0x50: /* ST */ |
| 1175 | case 0x42: /* STC */ |
| 1176 | case 0x40: /* STH */ |
| 1177 | is_write = 1; |
| 1178 | break; |
| 1179 | case 0xc4: /* RIL format insns */ |
| 1180 | switch (pinsn[0] & 0xf) { |
| 1181 | case 0xf: /* STRL */ |
| 1182 | case 0xb: /* STGRL */ |
| 1183 | case 0x7: /* STHRL */ |
| 1184 | is_write = 1; |
| 1185 | } |
| 1186 | break; |
| 1187 | case 0xe3: /* RXY format insns */ |
| 1188 | switch (pinsn[2] & 0xff) { |
| 1189 | case 0x50: /* STY */ |
| 1190 | case 0x24: /* STG */ |
| 1191 | case 0x72: /* STCY */ |
| 1192 | case 0x70: /* STHY */ |
| 1193 | case 0x8e: /* STPQ */ |
| 1194 | case 0x3f: /* STRVH */ |
| 1195 | case 0x3e: /* STRV */ |
| 1196 | case 0x2f: /* STRVG */ |
| 1197 | is_write = 1; |
| 1198 | } |
| 1199 | break; |
| 1200 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1201 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1202 | is_write, &uc->uc_sigmask, puc); |
| 1203 | } |
| 1204 | |
| 1205 | #elif defined(__mips__) |
| 1206 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1207 | int cpu_signal_handler(int host_signum, void *pinfo, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1208 | void *puc) |
| 1209 | { |
ths | 9617efe | 2007-05-08 21:05:55 +0000 | [diff] [blame] | 1210 | siginfo_t *info = pinfo; |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1211 | struct ucontext *uc = puc; |
| 1212 | greg_t pc = uc->uc_mcontext.pc; |
| 1213 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1214 | |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1215 | /* XXX: compute is_write */ |
| 1216 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1217 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1218 | is_write, &uc->uc_sigmask, puc); |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1219 | } |
| 1220 | |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 1221 | #elif defined(__hppa__) |
| 1222 | |
| 1223 | int cpu_signal_handler(int host_signum, void *pinfo, |
| 1224 | void *puc) |
| 1225 | { |
| 1226 | struct siginfo *info = pinfo; |
| 1227 | struct ucontext *uc = puc; |
Richard Henderson | f57040b | 2010-03-12 15:58:08 +0100 | [diff] [blame] | 1228 | unsigned long pc = uc->uc_mcontext.sc_iaoq[0]; |
| 1229 | uint32_t insn = *(uint32_t *)pc; |
| 1230 | int is_write = 0; |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 1231 | |
Richard Henderson | f57040b | 2010-03-12 15:58:08 +0100 | [diff] [blame] | 1232 | /* XXX: need kernel patch to get write flag faster. */ |
| 1233 | switch (insn >> 26) { |
| 1234 | case 0x1a: /* STW */ |
| 1235 | case 0x19: /* STH */ |
| 1236 | case 0x18: /* STB */ |
| 1237 | case 0x1b: /* STWM */ |
| 1238 | is_write = 1; |
| 1239 | break; |
| 1240 | |
| 1241 | case 0x09: /* CSTWX, FSTWX, FSTWS */ |
| 1242 | case 0x0b: /* CSTDX, FSTDX, FSTDS */ |
| 1243 | /* Distinguish from coprocessor load ... */ |
| 1244 | is_write = (insn >> 9) & 1; |
| 1245 | break; |
| 1246 | |
| 1247 | case 0x03: |
| 1248 | switch ((insn >> 6) & 15) { |
| 1249 | case 0xa: /* STWS */ |
| 1250 | case 0x9: /* STHS */ |
| 1251 | case 0x8: /* STBS */ |
| 1252 | case 0xe: /* STWAS */ |
| 1253 | case 0xc: /* STBYS */ |
| 1254 | is_write = 1; |
| 1255 | } |
| 1256 | break; |
| 1257 | } |
| 1258 | |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 1259 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
Richard Henderson | f57040b | 2010-03-12 15:58:08 +0100 | [diff] [blame] | 1260 | is_write, &uc->uc_sigmask, puc); |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 1261 | } |
| 1262 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1263 | #else |
| 1264 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 1265 | #error host CPU specific signal handler needed |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1266 | |
| 1267 | #endif |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 1268 | |
| 1269 | #endif /* !defined(CONFIG_SOFTMMU) */ |