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bellard6af0bf92005-07-02 14:58:51 +00001#if !defined (__MIPS_CPU_H__)
2#define __MIPS_CPU_H__
3
bellard4ad40f32005-12-05 19:59:36 +00004#define TARGET_HAS_ICE 1
5
ths9042c0e2006-12-23 14:18:40 +00006#define ELF_MACHINE EM_MIPS
7
pbrookc2764712009-03-07 15:24:59 +00008#define CPUState struct CPUMIPSState
9
bellardc5d6edc2006-06-14 16:49:24 +000010#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020011#include "qemu-common.h"
bellard6af0bf92005-07-02 14:58:51 +000012#include "mips-defs.h"
13#include "cpu-defs.h"
bellard6af0bf92005-07-02 14:58:51 +000014#include "softfloat.h"
15
bellardfdbb4692006-06-14 17:32:25 +000016// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
17// XXX: move that elsewhere
Juan Quinteladfe5fff2009-07-27 16:12:40 +020018#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
bellardfdbb4692006-06-14 17:32:25 +000019typedef unsigned char uint_fast8_t;
20typedef unsigned int uint_fast16_t;
21#endif
22
thsead93602007-09-06 00:18:15 +000023struct CPUMIPSState;
bellard6af0bf92005-07-02 14:58:51 +000024
Anthony Liguoric227f092009-10-01 16:12:16 -050025typedef struct r4k_tlb_t r4k_tlb_t;
26struct r4k_tlb_t {
bellard6af0bf92005-07-02 14:58:51 +000027 target_ulong VPN;
ths9c2149c2007-01-23 22:45:22 +000028 uint32_t PageMask;
pbrook98c1b822006-03-11 16:20:36 +000029 uint_fast8_t ASID;
30 uint_fast16_t G:1;
31 uint_fast16_t C0:3;
32 uint_fast16_t C1:3;
33 uint_fast16_t V0:1;
34 uint_fast16_t V1:1;
35 uint_fast16_t D0:1;
36 uint_fast16_t D1:1;
bellard6af0bf92005-07-02 14:58:51 +000037 target_ulong PFN[2];
38};
bellard6af0bf92005-07-02 14:58:51 +000039
Paul Brook3c7b48b2010-03-01 04:11:28 +000040#if !defined(CONFIG_USER_ONLY)
thsead93602007-09-06 00:18:15 +000041typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
42struct CPUMIPSTLBContext {
43 uint32_t nb_tlb;
44 uint32_t tlb_in_use;
Aurelien Jarno60c9af02009-11-22 14:37:04 +010045 int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
aurel32c01fccd2009-03-08 00:06:01 +000046 void (*helper_tlbwi) (void);
47 void (*helper_tlbwr) (void);
48 void (*helper_tlbp) (void);
49 void (*helper_tlbr) (void);
thsead93602007-09-06 00:18:15 +000050 union {
51 struct {
Anthony Liguoric227f092009-10-01 16:12:16 -050052 r4k_tlb_t tlb[MIPS_TLB_MAX];
thsead93602007-09-06 00:18:15 +000053 } r4k;
54 } mmu;
55};
Paul Brook3c7b48b2010-03-01 04:11:28 +000056#endif
ths51b27722007-05-30 20:46:02 +000057
Anthony Liguoric227f092009-10-01 16:12:16 -050058typedef union fpr_t fpr_t;
59union fpr_t {
thsead93602007-09-06 00:18:15 +000060 float64 fd; /* ieee double precision */
61 float32 fs[2];/* ieee single precision */
62 uint64_t d; /* binary double fixed-point */
63 uint32_t w[2]; /* binary single fixed-point */
64};
65/* define FP_ENDIAN_IDX to access the same location
Stefan Weil4ff97862011-03-13 15:44:02 +010066 * in the fpr_t union regardless of the host endianness
thsead93602007-09-06 00:18:15 +000067 */
Juan Quintelae2542fe2009-07-27 16:13:06 +020068#if defined(HOST_WORDS_BIGENDIAN)
thsead93602007-09-06 00:18:15 +000069# define FP_ENDIAN_IDX 1
70#else
71# define FP_ENDIAN_IDX 0
thsc570fd12006-12-21 01:19:56 +000072#endif
thsead93602007-09-06 00:18:15 +000073
74typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
75struct CPUMIPSFPUContext {
bellard6af0bf92005-07-02 14:58:51 +000076 /* Floating point registers */
Anthony Liguoric227f092009-10-01 16:12:16 -050077 fpr_t fpr[32];
bellard6ea83fe2006-06-14 12:56:19 +000078 float_status fp_status;
ths5a5012e2007-05-07 13:55:33 +000079 /* fpu implementation/revision register (fir) */
bellard6af0bf92005-07-02 14:58:51 +000080 uint32_t fcr0;
ths5a5012e2007-05-07 13:55:33 +000081#define FCR0_F64 22
82#define FCR0_L 21
83#define FCR0_W 20
84#define FCR0_3D 19
85#define FCR0_PS 18
86#define FCR0_D 17
87#define FCR0_S 16
88#define FCR0_PRID 8
89#define FCR0_REV 0
bellard6ea83fe2006-06-14 12:56:19 +000090 /* fcsr */
91 uint32_t fcr31;
thsf01be152008-09-18 11:57:27 +000092#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
93#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
94#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
ths5a5012e2007-05-07 13:55:33 +000095#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
96#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
97#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
98#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
99#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
100#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
101#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
bellard6ea83fe2006-06-14 12:56:19 +0000102#define FP_INEXACT 1
103#define FP_UNDERFLOW 2
104#define FP_OVERFLOW 4
105#define FP_DIV0 8
106#define FP_INVALID 16
107#define FP_UNIMPLEMENTED 32
thsead93602007-09-06 00:18:15 +0000108};
ths36d23952007-02-28 22:37:42 +0000109
ths623a9302007-10-28 19:45:05 +0000110#define NB_MMU_MODES 3
j_mayer6ebbf392007-10-14 07:07:08 +0000111
thsead93602007-09-06 00:18:15 +0000112typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
113struct CPUMIPSMVPContext {
114 int32_t CP0_MVPControl;
115#define CP0MVPCo_CPA 3
116#define CP0MVPCo_STLB 2
117#define CP0MVPCo_VPC 1
118#define CP0MVPCo_EVP 0
119 int32_t CP0_MVPConf0;
120#define CP0MVPC0_M 31
121#define CP0MVPC0_TLBS 29
122#define CP0MVPC0_GS 28
123#define CP0MVPC0_PCP 27
124#define CP0MVPC0_PTLBE 16
125#define CP0MVPC0_TCA 15
126#define CP0MVPC0_PVPE 10
127#define CP0MVPC0_PTC 0
128 int32_t CP0_MVPConf1;
129#define CP0MVPC1_CIM 31
130#define CP0MVPC1_CIF 30
131#define CP0MVPC1_PCX 20
132#define CP0MVPC1_PCP2 10
133#define CP0MVPC1_PCP1 0
134};
135
Anthony Liguoric227f092009-10-01 16:12:16 -0500136typedef struct mips_def_t mips_def_t;
thsead93602007-09-06 00:18:15 +0000137
138#define MIPS_SHADOW_SET_MAX 16
139#define MIPS_TC_MAX 5
thsf01be152008-09-18 11:57:27 +0000140#define MIPS_FPU_MAX 1
thsead93602007-09-06 00:18:15 +0000141#define MIPS_DSP_ACC 4
142
thsb5dc7732008-06-27 10:02:35 +0000143typedef struct TCState TCState;
144struct TCState {
145 target_ulong gpr[32];
146 target_ulong PC;
147 target_ulong HI[MIPS_DSP_ACC];
148 target_ulong LO[MIPS_DSP_ACC];
149 target_ulong ACX[MIPS_DSP_ACC];
150 target_ulong DSPControl;
151 int32_t CP0_TCStatus;
152#define CP0TCSt_TCU3 31
153#define CP0TCSt_TCU2 30
154#define CP0TCSt_TCU1 29
155#define CP0TCSt_TCU0 28
156#define CP0TCSt_TMX 27
157#define CP0TCSt_RNST 23
158#define CP0TCSt_TDS 21
159#define CP0TCSt_DT 20
160#define CP0TCSt_DA 15
161#define CP0TCSt_A 13
162#define CP0TCSt_TKSU 11
163#define CP0TCSt_IXMT 10
164#define CP0TCSt_TASID 0
165 int32_t CP0_TCBind;
166#define CP0TCBd_CurTC 21
167#define CP0TCBd_TBE 17
168#define CP0TCBd_CurVPE 0
169 target_ulong CP0_TCHalt;
170 target_ulong CP0_TCContext;
171 target_ulong CP0_TCSchedule;
172 target_ulong CP0_TCScheFBack;
173 int32_t CP0_Debug_tcstatus;
174};
175
thsead93602007-09-06 00:18:15 +0000176typedef struct CPUMIPSState CPUMIPSState;
177struct CPUMIPSState {
thsb5dc7732008-06-27 10:02:35 +0000178 TCState active_tc;
thsf01be152008-09-18 11:57:27 +0000179 CPUMIPSFPUContext active_fpu;
thsb5dc7732008-06-27 10:02:35 +0000180
thsead93602007-09-06 00:18:15 +0000181 uint32_t current_tc;
thsf01be152008-09-18 11:57:27 +0000182 uint32_t current_fpu;
thsead93602007-09-06 00:18:15 +0000183
thse034e2c2007-06-23 18:04:12 +0000184 uint32_t SEGBITS;
ths6d355242007-12-25 03:13:56 +0000185 uint32_t PABITS;
thsb6d96be2008-07-09 11:05:10 +0000186 target_ulong SEGMask;
ths6d355242007-12-25 03:13:56 +0000187 target_ulong PAMask;
ths29929e32007-05-13 13:49:44 +0000188
ths9c2149c2007-01-23 22:45:22 +0000189 int32_t CP0_Index;
thsead93602007-09-06 00:18:15 +0000190 /* CP0_MVP* are per MVP registers. */
ths9c2149c2007-01-23 22:45:22 +0000191 int32_t CP0_Random;
thsead93602007-09-06 00:18:15 +0000192 int32_t CP0_VPEControl;
193#define CP0VPECo_YSI 21
194#define CP0VPECo_GSI 20
195#define CP0VPECo_EXCPT 16
196#define CP0VPECo_TE 15
197#define CP0VPECo_TargTC 0
198 int32_t CP0_VPEConf0;
199#define CP0VPEC0_M 31
200#define CP0VPEC0_XTC 21
201#define CP0VPEC0_TCS 19
202#define CP0VPEC0_SCS 18
203#define CP0VPEC0_DSC 17
204#define CP0VPEC0_ICS 16
205#define CP0VPEC0_MVP 1
206#define CP0VPEC0_VPA 0
207 int32_t CP0_VPEConf1;
208#define CP0VPEC1_NCX 20
209#define CP0VPEC1_NCP2 10
210#define CP0VPEC1_NCP1 0
211 target_ulong CP0_YQMask;
212 target_ulong CP0_VPESchedule;
213 target_ulong CP0_VPEScheFBack;
214 int32_t CP0_VPEOpt;
215#define CP0VPEOpt_IWX7 15
216#define CP0VPEOpt_IWX6 14
217#define CP0VPEOpt_IWX5 13
218#define CP0VPEOpt_IWX4 12
219#define CP0VPEOpt_IWX3 11
220#define CP0VPEOpt_IWX2 10
221#define CP0VPEOpt_IWX1 9
222#define CP0VPEOpt_IWX0 8
223#define CP0VPEOpt_DWX7 7
224#define CP0VPEOpt_DWX6 6
225#define CP0VPEOpt_DWX5 5
226#define CP0VPEOpt_DWX4 4
227#define CP0VPEOpt_DWX3 3
228#define CP0VPEOpt_DWX2 2
229#define CP0VPEOpt_DWX1 1
230#define CP0VPEOpt_DWX0 0
ths9c2149c2007-01-23 22:45:22 +0000231 target_ulong CP0_EntryLo0;
232 target_ulong CP0_EntryLo1;
233 target_ulong CP0_Context;
234 int32_t CP0_PageMask;
235 int32_t CP0_PageGrain;
236 int32_t CP0_Wired;
thsead93602007-09-06 00:18:15 +0000237 int32_t CP0_SRSConf0_rw_bitmask;
238 int32_t CP0_SRSConf0;
239#define CP0SRSC0_M 31
240#define CP0SRSC0_SRS3 20
241#define CP0SRSC0_SRS2 10
242#define CP0SRSC0_SRS1 0
243 int32_t CP0_SRSConf1_rw_bitmask;
244 int32_t CP0_SRSConf1;
245#define CP0SRSC1_M 31
246#define CP0SRSC1_SRS6 20
247#define CP0SRSC1_SRS5 10
248#define CP0SRSC1_SRS4 0
249 int32_t CP0_SRSConf2_rw_bitmask;
250 int32_t CP0_SRSConf2;
251#define CP0SRSC2_M 31
252#define CP0SRSC2_SRS9 20
253#define CP0SRSC2_SRS8 10
254#define CP0SRSC2_SRS7 0
255 int32_t CP0_SRSConf3_rw_bitmask;
256 int32_t CP0_SRSConf3;
257#define CP0SRSC3_M 31
258#define CP0SRSC3_SRS12 20
259#define CP0SRSC3_SRS11 10
260#define CP0SRSC3_SRS10 0
261 int32_t CP0_SRSConf4_rw_bitmask;
262 int32_t CP0_SRSConf4;
263#define CP0SRSC4_SRS15 20
264#define CP0SRSC4_SRS14 10
265#define CP0SRSC4_SRS13 0
ths9c2149c2007-01-23 22:45:22 +0000266 int32_t CP0_HWREna;
thsc570fd12006-12-21 01:19:56 +0000267 target_ulong CP0_BadVAddr;
ths9c2149c2007-01-23 22:45:22 +0000268 int32_t CP0_Count;
269 target_ulong CP0_EntryHi;
270 int32_t CP0_Compare;
271 int32_t CP0_Status;
bellard6af0bf92005-07-02 14:58:51 +0000272#define CP0St_CU3 31
273#define CP0St_CU2 30
274#define CP0St_CU1 29
275#define CP0St_CU0 28
276#define CP0St_RP 27
bellard6ea83fe2006-06-14 12:56:19 +0000277#define CP0St_FR 26
bellard6af0bf92005-07-02 14:58:51 +0000278#define CP0St_RE 25
ths7a387ff2006-12-06 20:17:30 +0000279#define CP0St_MX 24
280#define CP0St_PX 23
bellard6af0bf92005-07-02 14:58:51 +0000281#define CP0St_BEV 22
282#define CP0St_TS 21
283#define CP0St_SR 20
284#define CP0St_NMI 19
285#define CP0St_IM 8
ths7a387ff2006-12-06 20:17:30 +0000286#define CP0St_KX 7
287#define CP0St_SX 6
288#define CP0St_UX 5
ths623a9302007-10-28 19:45:05 +0000289#define CP0St_KSU 3
bellard6af0bf92005-07-02 14:58:51 +0000290#define CP0St_ERL 2
291#define CP0St_EXL 1
292#define CP0St_IE 0
ths9c2149c2007-01-23 22:45:22 +0000293 int32_t CP0_IntCtl;
thsead93602007-09-06 00:18:15 +0000294#define CP0IntCtl_IPTI 29
295#define CP0IntCtl_IPPC1 26
296#define CP0IntCtl_VS 5
ths9c2149c2007-01-23 22:45:22 +0000297 int32_t CP0_SRSCtl;
thsead93602007-09-06 00:18:15 +0000298#define CP0SRSCtl_HSS 26
299#define CP0SRSCtl_EICSS 18
300#define CP0SRSCtl_ESS 12
301#define CP0SRSCtl_PSS 6
302#define CP0SRSCtl_CSS 0
ths9c2149c2007-01-23 22:45:22 +0000303 int32_t CP0_SRSMap;
thsead93602007-09-06 00:18:15 +0000304#define CP0SRSMap_SSV7 28
305#define CP0SRSMap_SSV6 24
306#define CP0SRSMap_SSV5 20
307#define CP0SRSMap_SSV4 16
308#define CP0SRSMap_SSV3 12
309#define CP0SRSMap_SSV2 8
310#define CP0SRSMap_SSV1 4
311#define CP0SRSMap_SSV0 0
ths9c2149c2007-01-23 22:45:22 +0000312 int32_t CP0_Cause;
ths7a387ff2006-12-06 20:17:30 +0000313#define CP0Ca_BD 31
314#define CP0Ca_TI 30
315#define CP0Ca_CE 28
316#define CP0Ca_DC 27
317#define CP0Ca_PCI 26
bellard6af0bf92005-07-02 14:58:51 +0000318#define CP0Ca_IV 23
ths7a387ff2006-12-06 20:17:30 +0000319#define CP0Ca_WP 22
320#define CP0Ca_IP 8
ths4de9b242007-01-24 01:47:51 +0000321#define CP0Ca_IP_mask 0x0000FF00
ths7a387ff2006-12-06 20:17:30 +0000322#define CP0Ca_EC 2
thsc570fd12006-12-21 01:19:56 +0000323 target_ulong CP0_EPC;
ths9c2149c2007-01-23 22:45:22 +0000324 int32_t CP0_PRid;
thsb29a0342007-01-24 18:01:23 +0000325 int32_t CP0_EBase;
ths9c2149c2007-01-23 22:45:22 +0000326 int32_t CP0_Config0;
bellard6af0bf92005-07-02 14:58:51 +0000327#define CP0C0_M 31
328#define CP0C0_K23 28
329#define CP0C0_KU 25
330#define CP0C0_MDU 20
331#define CP0C0_MM 17
332#define CP0C0_BM 16
333#define CP0C0_BE 15
334#define CP0C0_AT 13
335#define CP0C0_AR 10
336#define CP0C0_MT 7
ths7a387ff2006-12-06 20:17:30 +0000337#define CP0C0_VI 3
bellard6af0bf92005-07-02 14:58:51 +0000338#define CP0C0_K0 0
ths9c2149c2007-01-23 22:45:22 +0000339 int32_t CP0_Config1;
ths7a387ff2006-12-06 20:17:30 +0000340#define CP0C1_M 31
bellard6af0bf92005-07-02 14:58:51 +0000341#define CP0C1_MMU 25
342#define CP0C1_IS 22
343#define CP0C1_IL 19
344#define CP0C1_IA 16
345#define CP0C1_DS 13
346#define CP0C1_DL 10
347#define CP0C1_DA 7
ths7a387ff2006-12-06 20:17:30 +0000348#define CP0C1_C2 6
349#define CP0C1_MD 5
bellard6af0bf92005-07-02 14:58:51 +0000350#define CP0C1_PC 4
351#define CP0C1_WR 3
352#define CP0C1_CA 2
353#define CP0C1_EP 1
354#define CP0C1_FP 0
ths9c2149c2007-01-23 22:45:22 +0000355 int32_t CP0_Config2;
ths7a387ff2006-12-06 20:17:30 +0000356#define CP0C2_M 31
357#define CP0C2_TU 28
358#define CP0C2_TS 24
359#define CP0C2_TL 20
360#define CP0C2_TA 16
361#define CP0C2_SU 12
362#define CP0C2_SS 8
363#define CP0C2_SL 4
364#define CP0C2_SA 0
ths9c2149c2007-01-23 22:45:22 +0000365 int32_t CP0_Config3;
ths7a387ff2006-12-06 20:17:30 +0000366#define CP0C3_M 31
Nathan Froydbbfa8f72010-06-08 13:30:01 -0700367#define CP0C3_ISA_ON_EXC 16
ths7a387ff2006-12-06 20:17:30 +0000368#define CP0C3_DSPP 10
369#define CP0C3_LPA 7
370#define CP0C3_VEIC 6
371#define CP0C3_VInt 5
372#define CP0C3_SP 4
373#define CP0C3_MT 2
374#define CP0C3_SM 1
375#define CP0C3_TL 0
thse397ee32007-03-23 00:43:28 +0000376 int32_t CP0_Config6;
377 int32_t CP0_Config7;
thsead93602007-09-06 00:18:15 +0000378 /* XXX: Maybe make LLAddr per-TC? */
Aurelien Jarno5499b6f2009-11-22 13:08:14 +0100379 target_ulong lladdr;
Paul Brook590bc602009-07-09 17:45:17 +0100380 target_ulong llval;
381 target_ulong llnewval;
382 target_ulong llreg;
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100383 target_ulong CP0_LLAddr_rw_bitmask;
384 int CP0_LLAddr_shift;
thsfd88b6a2007-05-23 08:24:25 +0000385 target_ulong CP0_WatchLo[8];
386 int32_t CP0_WatchHi[8];
ths9c2149c2007-01-23 22:45:22 +0000387 target_ulong CP0_XContext;
388 int32_t CP0_Framemask;
389 int32_t CP0_Debug;
thsead93602007-09-06 00:18:15 +0000390#define CP0DB_DBD 31
bellard6af0bf92005-07-02 14:58:51 +0000391#define CP0DB_DM 30
392#define CP0DB_LSNM 28
393#define CP0DB_Doze 27
394#define CP0DB_Halt 26
395#define CP0DB_CNT 25
396#define CP0DB_IBEP 24
397#define CP0DB_DBEP 21
398#define CP0DB_IEXI 20
399#define CP0DB_VER 15
400#define CP0DB_DEC 10
401#define CP0DB_SSt 8
402#define CP0DB_DINT 5
403#define CP0DB_DIB 4
404#define CP0DB_DDBS 3
405#define CP0DB_DDBL 2
406#define CP0DB_DBp 1
407#define CP0DB_DSS 0
thsc570fd12006-12-21 01:19:56 +0000408 target_ulong CP0_DEPC;
ths9c2149c2007-01-23 22:45:22 +0000409 int32_t CP0_Performance0;
410 int32_t CP0_TagLo;
411 int32_t CP0_DataLo;
412 int32_t CP0_TagHi;
413 int32_t CP0_DataHi;
thsc570fd12006-12-21 01:19:56 +0000414 target_ulong CP0_ErrorEPC;
ths9c2149c2007-01-23 22:45:22 +0000415 int32_t CP0_DESAVE;
thsb5dc7732008-06-27 10:02:35 +0000416 /* We waste some space so we can handle shadow registers like TCs. */
417 TCState tcs[MIPS_SHADOW_SET_MAX];
thsf01be152008-09-18 11:57:27 +0000418 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
bellard6af0bf92005-07-02 14:58:51 +0000419 /* Qemu */
bellard6af0bf92005-07-02 14:58:51 +0000420 int error_code;
bellard6af0bf92005-07-02 14:58:51 +0000421 uint32_t hflags; /* CPU State */
422 /* TMASK defines different execution modes */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800423#define MIPS_HFLAG_TMASK 0x007FF
424#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
ths623a9302007-10-28 19:45:05 +0000425 /* The KSU flags must be the lowest bits in hflags. The flag order
426 must be the same as defined for CP0 Status. This allows to use
427 the bits as the value of mmu_idx. */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800428#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
429#define MIPS_HFLAG_UM 0x00002 /* user mode flag */
430#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
431#define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
432#define MIPS_HFLAG_DM 0x00004 /* Debug mode */
433#define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
434#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
435#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
436#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
thsb8aa4592007-12-30 15:36:58 +0000437 /* True if the MIPS IV COP1X instructions can be used. This also
438 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
439 and RSQRT.D. */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800440#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
441#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
442#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
443#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
444#define MIPS_HFLAG_M16_SHIFT 10
bellard4ad40f32005-12-05 19:59:36 +0000445 /* If translation is interrupted between the branch instruction and
446 * the delay slot, record what type of branch it is so that we can
447 * resume translation properly. It might be possible to reduce
448 * this from three bits to two. */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800449#define MIPS_HFLAG_BMASK_BASE 0x03800
450#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
451#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
452#define MIPS_HFLAG_BL 0x01800 /* Likely branch */
453#define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
454 /* Extra flags about the current pending branch. */
455#define MIPS_HFLAG_BMASK_EXT 0x3C000
456#define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
457#define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
458#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
459#define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
460#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
bellard6af0bf92005-07-02 14:58:51 +0000461 target_ulong btarget; /* Jump / branch target */
aurel321ba74fb2009-03-29 01:18:52 +0000462 target_ulong bcond; /* Branch condition (if needed) */
bellarda316d332005-11-20 10:32:34 +0000463
ths7a387ff2006-12-06 20:17:30 +0000464 int SYNCI_Step; /* Address step size for SYNCI */
465 int CCRes; /* Cycle count resolution/divisor */
thsead93602007-09-06 00:18:15 +0000466 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
467 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
thse189e742007-09-24 12:48:00 +0000468 int insn_flags; /* Supported instruction set */
ths7a387ff2006-12-06 20:17:30 +0000469
ths0eaef5a2008-07-23 16:14:22 +0000470 target_ulong tls_value; /* For usermode emulation */
ths6f5b89a2007-03-02 20:48:00 +0000471
bellarda316d332005-11-20 10:32:34 +0000472 CPU_COMMON
ths6ae81772006-12-06 17:48:52 +0000473
Blue Swirl51cc2e72009-11-08 12:50:21 +0200474 CPUMIPSMVPContext *mvp;
Paul Brook3c7b48b2010-03-01 04:11:28 +0000475#if !defined(CONFIG_USER_ONLY)
Blue Swirl51cc2e72009-11-08 12:50:21 +0200476 CPUMIPSTLBContext *tlb;
Paul Brook3c7b48b2010-03-01 04:11:28 +0000477#endif
Blue Swirl51cc2e72009-11-08 12:50:21 +0200478
Anthony Liguoric227f092009-10-01 16:12:16 -0500479 const mips_def_t *cpu_model;
ths33ac7f12007-05-31 16:18:58 +0000480 void *irq[8];
ths6ae81772006-12-06 17:48:52 +0000481 struct QEMUTimer *timer; /* Internal timer */
bellard6af0bf92005-07-02 14:58:51 +0000482};
483
Paul Brook3c7b48b2010-03-01 04:11:28 +0000484#if !defined(CONFIG_USER_ONLY)
Aurelien Jarno60c9af02009-11-22 14:37:04 +0100485int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
ths29929e32007-05-13 13:49:44 +0000486 target_ulong address, int rw, int access_type);
Aurelien Jarno60c9af02009-11-22 14:37:04 +0100487int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
ths29929e32007-05-13 13:49:44 +0000488 target_ulong address, int rw, int access_type);
Aurelien Jarno60c9af02009-11-22 14:37:04 +0100489int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
ths29929e32007-05-13 13:49:44 +0000490 target_ulong address, int rw, int access_type);
aurel32c01fccd2009-03-08 00:06:01 +0000491void r4k_helper_tlbwi (void);
492void r4k_helper_tlbwr (void);
493void r4k_helper_tlbp (void);
494void r4k_helper_tlbr (void);
ths33d68b52007-03-18 00:30:29 +0000495
Anthony Liguoric227f092009-10-01 16:12:16 -0500496void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
blueswir1e18231a2008-10-06 18:46:28 +0000497 int unused, int size);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000498#endif
499
Stefan Weil9a78eea2010-10-22 23:03:33 +0200500void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
ths647de6c2007-10-20 19:45:44 +0000501
ths9467d442007-06-03 21:02:38 +0000502#define cpu_init cpu_mips_init
503#define cpu_exec cpu_mips_exec
504#define cpu_gen_code cpu_mips_gen_code
505#define cpu_signal_handler cpu_mips_signal_handler
j_mayerc732abe2007-10-12 06:47:46 +0000506#define cpu_list mips_cpu_list
ths9467d442007-06-03 21:02:38 +0000507
pbrookb3c77242008-06-30 16:31:04 +0000508#define CPU_SAVE_VERSION 3
509
ths623a9302007-10-28 19:45:05 +0000510/* MMU modes definitions. We carefully match the indices with our
511 hflags layout. */
j_mayer6ebbf392007-10-14 07:07:08 +0000512#define MMU_MODE0_SUFFIX _kernel
ths623a9302007-10-28 19:45:05 +0000513#define MMU_MODE1_SUFFIX _super
514#define MMU_MODE2_SUFFIX _user
515#define MMU_USER_IDX 2
j_mayer6ebbf392007-10-14 07:07:08 +0000516static inline int cpu_mmu_index (CPUState *env)
517{
ths623a9302007-10-28 19:45:05 +0000518 return env->hflags & MIPS_HFLAG_KSU;
j_mayer6ebbf392007-10-14 07:07:08 +0000519}
520
pbrook6e68e072008-05-30 17:22:15 +0000521static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
522{
pbrookf8ed7072008-05-30 17:54:15 +0000523 if (newsp)
thsb5dc7732008-06-27 10:02:35 +0000524 env->active_tc.gpr[29] = newsp;
525 env->active_tc.gpr[7] = 0;
526 env->active_tc.gpr[2] = 0;
pbrook6e68e072008-05-30 17:22:15 +0000527}
pbrook6e68e072008-05-30 17:22:15 +0000528
Edgar E. Iglesias138afb02010-08-06 12:21:16 +0200529static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
530{
531 int32_t pending;
532 int32_t status;
533 int r;
534
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100535 if (!(env->CP0_Status & (1 << CP0St_IE)) ||
536 (env->CP0_Status & (1 << CP0St_EXL)) ||
537 (env->CP0_Status & (1 << CP0St_ERL)) ||
538 (env->hflags & MIPS_HFLAG_DM)) {
539 /* Interrupts are disabled */
540 return 0;
541 }
542
Edgar E. Iglesias138afb02010-08-06 12:21:16 +0200543 pending = env->CP0_Cause & CP0Ca_IP_mask;
544 status = env->CP0_Status & CP0Ca_IP_mask;
545
546 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
547 /* A MIPS configured with a vectorizing external interrupt controller
548 will feed a vector into the Cause pending lines. The core treats
549 the status lines as a vector level, not as indiviual masks. */
550 r = pending > status;
551 } else {
552 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
553 treats the pending lines as individual interrupt lines, the status
554 lines are individual masks. */
555 r = pending & status;
556 }
557 return r;
558}
559
bellard6af0bf92005-07-02 14:58:51 +0000560#include "cpu-all.h"
561
562/* Memory access type :
563 * may be needed for precise access rights control and precise exceptions.
564 */
565enum {
566 /* 1 bit to define user level / supervisor access */
567 ACCESS_USER = 0x00,
568 ACCESS_SUPER = 0x01,
569 /* 1 bit to indicate direction */
570 ACCESS_STORE = 0x02,
571 /* Type of instruction that generated the access */
572 ACCESS_CODE = 0x10, /* Code fetch access */
573 ACCESS_INT = 0x20, /* Integer load/store access */
574 ACCESS_FLOAT = 0x30, /* floating point load/store access */
575};
576
577/* Exceptions */
578enum {
579 EXCP_NONE = -1,
580 EXCP_RESET = 0,
581 EXCP_SRESET,
582 EXCP_DSS,
583 EXCP_DINT,
ths14e51cc2007-12-26 19:34:03 +0000584 EXCP_DDBL,
585 EXCP_DDBS,
bellard6af0bf92005-07-02 14:58:51 +0000586 EXCP_NMI,
587 EXCP_MCHECK,
ths14e51cc2007-12-26 19:34:03 +0000588 EXCP_EXT_INTERRUPT, /* 8 */
bellard6af0bf92005-07-02 14:58:51 +0000589 EXCP_DFWATCH,
ths14e51cc2007-12-26 19:34:03 +0000590 EXCP_DIB,
bellard6af0bf92005-07-02 14:58:51 +0000591 EXCP_IWATCH,
592 EXCP_AdEL,
593 EXCP_AdES,
594 EXCP_TLBF,
595 EXCP_IBE,
ths14e51cc2007-12-26 19:34:03 +0000596 EXCP_DBp, /* 16 */
bellard6af0bf92005-07-02 14:58:51 +0000597 EXCP_SYSCALL,
ths14e51cc2007-12-26 19:34:03 +0000598 EXCP_BREAK,
bellard4ad40f32005-12-05 19:59:36 +0000599 EXCP_CpU,
bellard6af0bf92005-07-02 14:58:51 +0000600 EXCP_RI,
601 EXCP_OVERFLOW,
602 EXCP_TRAP,
ths5a5012e2007-05-07 13:55:33 +0000603 EXCP_FPE,
ths14e51cc2007-12-26 19:34:03 +0000604 EXCP_DWATCH, /* 24 */
bellard6af0bf92005-07-02 14:58:51 +0000605 EXCP_LTLBL,
606 EXCP_TLBL,
607 EXCP_TLBS,
608 EXCP_DBE,
thsead93602007-09-06 00:18:15 +0000609 EXCP_THREAD,
ths14e51cc2007-12-26 19:34:03 +0000610 EXCP_MDMX,
611 EXCP_C2E,
612 EXCP_CACHE, /* 32 */
613
614 EXCP_LAST = EXCP_CACHE,
bellard6af0bf92005-07-02 14:58:51 +0000615};
Paul Brook590bc602009-07-09 17:45:17 +0100616/* Dummy exception for conditional stores. */
617#define EXCP_SC 0x100
bellard6af0bf92005-07-02 14:58:51 +0000618
bellard6af0bf92005-07-02 14:58:51 +0000619int cpu_mips_exec(CPUMIPSState *s);
bellardaaed9092007-11-10 15:15:54 +0000620CPUMIPSState *cpu_mips_init(const char *cpu_model);
thsf9480ff2008-12-20 19:42:14 +0000621//~ uint32_t cpu_mips_get_clock (void);
ths388bb212007-05-13 13:58:00 +0000622int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
bellard6af0bf92005-07-02 14:58:51 +0000623
thsf9480ff2008-12-20 19:42:14 +0000624/* mips_timer.c */
625uint32_t cpu_mips_get_random (CPUState *env);
626uint32_t cpu_mips_get_count (CPUState *env);
627void cpu_mips_store_count (CPUState *env, uint32_t value);
628void cpu_mips_store_compare (CPUState *env, uint32_t value);
629void cpu_mips_start_count(CPUState *env);
630void cpu_mips_stop_count(CPUState *env);
631
Aurelien Jarno5dc5d9f2010-07-25 16:51:29 +0200632/* mips_int.c */
633void cpu_mips_soft_irq(CPUState *env, int irq, int level);
634
thsf9480ff2008-12-20 19:42:14 +0000635/* helper.c */
636int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
637 int mmu_idx, int is_softmmu);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700638#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
thsf9480ff2008-12-20 19:42:14 +0000639void do_interrupt (CPUState *env);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000640#if !defined(CONFIG_USER_ONLY)
thsf9480ff2008-12-20 19:42:14 +0000641void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
Aurelien Jarnoc36bbb22010-02-06 17:02:45 +0100642target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
643 int rw);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000644#endif
thsf9480ff2008-12-20 19:42:14 +0000645
aliguori6b917542008-11-18 19:46:41 +0000646static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
647 target_ulong *cs_base, int *flags)
648{
649 *pc = env->active_tc.PC;
650 *cs_base = 0;
651 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
652}
653
Paul Brookff867dd2009-07-09 15:07:57 +0100654static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
655{
656 env->tls_value = newtls;
657}
658
Blue Swirlf081c762011-05-21 07:10:23 +0000659static inline int cpu_has_work(CPUState *env)
660{
661 int has_work = 0;
662
663 /* It is implementation dependent if non-enabled interrupts
664 wake-up the CPU, however most of the implementations only
665 check for interrupts that can be taken. */
666 if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
667 cpu_mips_hw_interrupts_pending(env)) {
668 has_work = 1;
669 }
670
671 return has_work;
672}
673
674#include "exec-all.h"
675
676static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
677{
678 env->active_tc.PC = tb->pc;
679 env->hflags &= ~MIPS_HFLAG_BMASK;
680 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
681}
682
bellard6af0bf92005-07-02 14:58:51 +0000683#endif /* !defined (__MIPS_CPU_H__) */