bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1 | #if !defined (__MIPS_CPU_H__) |
| 2 | #define __MIPS_CPU_H__ |
| 3 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 4 | #define TARGET_HAS_ICE 1 |
| 5 | |
ths | 9042c0e | 2006-12-23 14:18:40 +0000 | [diff] [blame] | 6 | #define ELF_MACHINE EM_MIPS |
| 7 | |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 8 | #define CPUState struct CPUMIPSState |
| 9 | |
bellard | c5d6edc | 2006-06-14 16:49:24 +0000 | [diff] [blame] | 10 | #include "config.h" |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 11 | #include "qemu-common.h" |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 12 | #include "mips-defs.h" |
| 13 | #include "cpu-defs.h" |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 14 | #include "softfloat.h" |
| 15 | |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 16 | // uint_fast8_t and uint_fast16_t not in <sys/int_types.h> |
| 17 | // XXX: move that elsewhere |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 18 | #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 19 | typedef unsigned char uint_fast8_t; |
| 20 | typedef unsigned int uint_fast16_t; |
| 21 | #endif |
| 22 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 23 | struct CPUMIPSState; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 24 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 25 | typedef struct r4k_tlb_t r4k_tlb_t; |
| 26 | struct r4k_tlb_t { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 27 | target_ulong VPN; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 28 | uint32_t PageMask; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 29 | uint_fast8_t ASID; |
| 30 | uint_fast16_t G:1; |
| 31 | uint_fast16_t C0:3; |
| 32 | uint_fast16_t C1:3; |
| 33 | uint_fast16_t V0:1; |
| 34 | uint_fast16_t V1:1; |
| 35 | uint_fast16_t D0:1; |
| 36 | uint_fast16_t D1:1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 37 | target_ulong PFN[2]; |
| 38 | }; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 39 | |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 40 | #if !defined(CONFIG_USER_ONLY) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 41 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
| 42 | struct CPUMIPSTLBContext { |
| 43 | uint32_t nb_tlb; |
| 44 | uint32_t tlb_in_use; |
Aurelien Jarno | 60c9af0 | 2009-11-22 14:37:04 +0100 | [diff] [blame] | 45 | int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 46 | void (*helper_tlbwi) (void); |
| 47 | void (*helper_tlbwr) (void); |
| 48 | void (*helper_tlbp) (void); |
| 49 | void (*helper_tlbr) (void); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 50 | union { |
| 51 | struct { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 52 | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 53 | } r4k; |
| 54 | } mmu; |
| 55 | }; |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 56 | #endif |
ths | 51b2772 | 2007-05-30 20:46:02 +0000 | [diff] [blame] | 57 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 58 | typedef union fpr_t fpr_t; |
| 59 | union fpr_t { |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 60 | float64 fd; /* ieee double precision */ |
| 61 | float32 fs[2];/* ieee single precision */ |
| 62 | uint64_t d; /* binary double fixed-point */ |
| 63 | uint32_t w[2]; /* binary single fixed-point */ |
| 64 | }; |
| 65 | /* define FP_ENDIAN_IDX to access the same location |
Stefan Weil | 4ff9786 | 2011-03-13 15:44:02 +0100 | [diff] [blame] | 66 | * in the fpr_t union regardless of the host endianness |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 67 | */ |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 68 | #if defined(HOST_WORDS_BIGENDIAN) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 69 | # define FP_ENDIAN_IDX 1 |
| 70 | #else |
| 71 | # define FP_ENDIAN_IDX 0 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 72 | #endif |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 73 | |
| 74 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
| 75 | struct CPUMIPSFPUContext { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 76 | /* Floating point registers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 77 | fpr_t fpr[32]; |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 78 | float_status fp_status; |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 79 | /* fpu implementation/revision register (fir) */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 80 | uint32_t fcr0; |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 81 | #define FCR0_F64 22 |
| 82 | #define FCR0_L 21 |
| 83 | #define FCR0_W 20 |
| 84 | #define FCR0_3D 19 |
| 85 | #define FCR0_PS 18 |
| 86 | #define FCR0_D 17 |
| 87 | #define FCR0_S 16 |
| 88 | #define FCR0_PRID 8 |
| 89 | #define FCR0_REV 0 |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 90 | /* fcsr */ |
| 91 | uint32_t fcr31; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 92 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
| 93 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
| 94 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 95 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
| 96 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
| 97 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
| 98 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
| 99 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
| 100 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
| 101 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 102 | #define FP_INEXACT 1 |
| 103 | #define FP_UNDERFLOW 2 |
| 104 | #define FP_OVERFLOW 4 |
| 105 | #define FP_DIV0 8 |
| 106 | #define FP_INVALID 16 |
| 107 | #define FP_UNIMPLEMENTED 32 |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 108 | }; |
ths | 36d2395 | 2007-02-28 22:37:42 +0000 | [diff] [blame] | 109 | |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 110 | #define NB_MMU_MODES 3 |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 111 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 112 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
| 113 | struct CPUMIPSMVPContext { |
| 114 | int32_t CP0_MVPControl; |
| 115 | #define CP0MVPCo_CPA 3 |
| 116 | #define CP0MVPCo_STLB 2 |
| 117 | #define CP0MVPCo_VPC 1 |
| 118 | #define CP0MVPCo_EVP 0 |
| 119 | int32_t CP0_MVPConf0; |
| 120 | #define CP0MVPC0_M 31 |
| 121 | #define CP0MVPC0_TLBS 29 |
| 122 | #define CP0MVPC0_GS 28 |
| 123 | #define CP0MVPC0_PCP 27 |
| 124 | #define CP0MVPC0_PTLBE 16 |
| 125 | #define CP0MVPC0_TCA 15 |
| 126 | #define CP0MVPC0_PVPE 10 |
| 127 | #define CP0MVPC0_PTC 0 |
| 128 | int32_t CP0_MVPConf1; |
| 129 | #define CP0MVPC1_CIM 31 |
| 130 | #define CP0MVPC1_CIF 30 |
| 131 | #define CP0MVPC1_PCX 20 |
| 132 | #define CP0MVPC1_PCP2 10 |
| 133 | #define CP0MVPC1_PCP1 0 |
| 134 | }; |
| 135 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 136 | typedef struct mips_def_t mips_def_t; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 137 | |
| 138 | #define MIPS_SHADOW_SET_MAX 16 |
| 139 | #define MIPS_TC_MAX 5 |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 140 | #define MIPS_FPU_MAX 1 |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 141 | #define MIPS_DSP_ACC 4 |
| 142 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 143 | typedef struct TCState TCState; |
| 144 | struct TCState { |
| 145 | target_ulong gpr[32]; |
| 146 | target_ulong PC; |
| 147 | target_ulong HI[MIPS_DSP_ACC]; |
| 148 | target_ulong LO[MIPS_DSP_ACC]; |
| 149 | target_ulong ACX[MIPS_DSP_ACC]; |
| 150 | target_ulong DSPControl; |
| 151 | int32_t CP0_TCStatus; |
| 152 | #define CP0TCSt_TCU3 31 |
| 153 | #define CP0TCSt_TCU2 30 |
| 154 | #define CP0TCSt_TCU1 29 |
| 155 | #define CP0TCSt_TCU0 28 |
| 156 | #define CP0TCSt_TMX 27 |
| 157 | #define CP0TCSt_RNST 23 |
| 158 | #define CP0TCSt_TDS 21 |
| 159 | #define CP0TCSt_DT 20 |
| 160 | #define CP0TCSt_DA 15 |
| 161 | #define CP0TCSt_A 13 |
| 162 | #define CP0TCSt_TKSU 11 |
| 163 | #define CP0TCSt_IXMT 10 |
| 164 | #define CP0TCSt_TASID 0 |
| 165 | int32_t CP0_TCBind; |
| 166 | #define CP0TCBd_CurTC 21 |
| 167 | #define CP0TCBd_TBE 17 |
| 168 | #define CP0TCBd_CurVPE 0 |
| 169 | target_ulong CP0_TCHalt; |
| 170 | target_ulong CP0_TCContext; |
| 171 | target_ulong CP0_TCSchedule; |
| 172 | target_ulong CP0_TCScheFBack; |
| 173 | int32_t CP0_Debug_tcstatus; |
| 174 | }; |
| 175 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 176 | typedef struct CPUMIPSState CPUMIPSState; |
| 177 | struct CPUMIPSState { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 178 | TCState active_tc; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 179 | CPUMIPSFPUContext active_fpu; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 180 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 181 | uint32_t current_tc; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 182 | uint32_t current_fpu; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 183 | |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 184 | uint32_t SEGBITS; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 185 | uint32_t PABITS; |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 186 | target_ulong SEGMask; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 187 | target_ulong PAMask; |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 188 | |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 189 | int32_t CP0_Index; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 190 | /* CP0_MVP* are per MVP registers. */ |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 191 | int32_t CP0_Random; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 192 | int32_t CP0_VPEControl; |
| 193 | #define CP0VPECo_YSI 21 |
| 194 | #define CP0VPECo_GSI 20 |
| 195 | #define CP0VPECo_EXCPT 16 |
| 196 | #define CP0VPECo_TE 15 |
| 197 | #define CP0VPECo_TargTC 0 |
| 198 | int32_t CP0_VPEConf0; |
| 199 | #define CP0VPEC0_M 31 |
| 200 | #define CP0VPEC0_XTC 21 |
| 201 | #define CP0VPEC0_TCS 19 |
| 202 | #define CP0VPEC0_SCS 18 |
| 203 | #define CP0VPEC0_DSC 17 |
| 204 | #define CP0VPEC0_ICS 16 |
| 205 | #define CP0VPEC0_MVP 1 |
| 206 | #define CP0VPEC0_VPA 0 |
| 207 | int32_t CP0_VPEConf1; |
| 208 | #define CP0VPEC1_NCX 20 |
| 209 | #define CP0VPEC1_NCP2 10 |
| 210 | #define CP0VPEC1_NCP1 0 |
| 211 | target_ulong CP0_YQMask; |
| 212 | target_ulong CP0_VPESchedule; |
| 213 | target_ulong CP0_VPEScheFBack; |
| 214 | int32_t CP0_VPEOpt; |
| 215 | #define CP0VPEOpt_IWX7 15 |
| 216 | #define CP0VPEOpt_IWX6 14 |
| 217 | #define CP0VPEOpt_IWX5 13 |
| 218 | #define CP0VPEOpt_IWX4 12 |
| 219 | #define CP0VPEOpt_IWX3 11 |
| 220 | #define CP0VPEOpt_IWX2 10 |
| 221 | #define CP0VPEOpt_IWX1 9 |
| 222 | #define CP0VPEOpt_IWX0 8 |
| 223 | #define CP0VPEOpt_DWX7 7 |
| 224 | #define CP0VPEOpt_DWX6 6 |
| 225 | #define CP0VPEOpt_DWX5 5 |
| 226 | #define CP0VPEOpt_DWX4 4 |
| 227 | #define CP0VPEOpt_DWX3 3 |
| 228 | #define CP0VPEOpt_DWX2 2 |
| 229 | #define CP0VPEOpt_DWX1 1 |
| 230 | #define CP0VPEOpt_DWX0 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 231 | target_ulong CP0_EntryLo0; |
| 232 | target_ulong CP0_EntryLo1; |
| 233 | target_ulong CP0_Context; |
| 234 | int32_t CP0_PageMask; |
| 235 | int32_t CP0_PageGrain; |
| 236 | int32_t CP0_Wired; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 237 | int32_t CP0_SRSConf0_rw_bitmask; |
| 238 | int32_t CP0_SRSConf0; |
| 239 | #define CP0SRSC0_M 31 |
| 240 | #define CP0SRSC0_SRS3 20 |
| 241 | #define CP0SRSC0_SRS2 10 |
| 242 | #define CP0SRSC0_SRS1 0 |
| 243 | int32_t CP0_SRSConf1_rw_bitmask; |
| 244 | int32_t CP0_SRSConf1; |
| 245 | #define CP0SRSC1_M 31 |
| 246 | #define CP0SRSC1_SRS6 20 |
| 247 | #define CP0SRSC1_SRS5 10 |
| 248 | #define CP0SRSC1_SRS4 0 |
| 249 | int32_t CP0_SRSConf2_rw_bitmask; |
| 250 | int32_t CP0_SRSConf2; |
| 251 | #define CP0SRSC2_M 31 |
| 252 | #define CP0SRSC2_SRS9 20 |
| 253 | #define CP0SRSC2_SRS8 10 |
| 254 | #define CP0SRSC2_SRS7 0 |
| 255 | int32_t CP0_SRSConf3_rw_bitmask; |
| 256 | int32_t CP0_SRSConf3; |
| 257 | #define CP0SRSC3_M 31 |
| 258 | #define CP0SRSC3_SRS12 20 |
| 259 | #define CP0SRSC3_SRS11 10 |
| 260 | #define CP0SRSC3_SRS10 0 |
| 261 | int32_t CP0_SRSConf4_rw_bitmask; |
| 262 | int32_t CP0_SRSConf4; |
| 263 | #define CP0SRSC4_SRS15 20 |
| 264 | #define CP0SRSC4_SRS14 10 |
| 265 | #define CP0SRSC4_SRS13 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 266 | int32_t CP0_HWREna; |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 267 | target_ulong CP0_BadVAddr; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 268 | int32_t CP0_Count; |
| 269 | target_ulong CP0_EntryHi; |
| 270 | int32_t CP0_Compare; |
| 271 | int32_t CP0_Status; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 272 | #define CP0St_CU3 31 |
| 273 | #define CP0St_CU2 30 |
| 274 | #define CP0St_CU1 29 |
| 275 | #define CP0St_CU0 28 |
| 276 | #define CP0St_RP 27 |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 277 | #define CP0St_FR 26 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 278 | #define CP0St_RE 25 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 279 | #define CP0St_MX 24 |
| 280 | #define CP0St_PX 23 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 281 | #define CP0St_BEV 22 |
| 282 | #define CP0St_TS 21 |
| 283 | #define CP0St_SR 20 |
| 284 | #define CP0St_NMI 19 |
| 285 | #define CP0St_IM 8 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 286 | #define CP0St_KX 7 |
| 287 | #define CP0St_SX 6 |
| 288 | #define CP0St_UX 5 |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 289 | #define CP0St_KSU 3 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 290 | #define CP0St_ERL 2 |
| 291 | #define CP0St_EXL 1 |
| 292 | #define CP0St_IE 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 293 | int32_t CP0_IntCtl; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 294 | #define CP0IntCtl_IPTI 29 |
| 295 | #define CP0IntCtl_IPPC1 26 |
| 296 | #define CP0IntCtl_VS 5 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 297 | int32_t CP0_SRSCtl; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 298 | #define CP0SRSCtl_HSS 26 |
| 299 | #define CP0SRSCtl_EICSS 18 |
| 300 | #define CP0SRSCtl_ESS 12 |
| 301 | #define CP0SRSCtl_PSS 6 |
| 302 | #define CP0SRSCtl_CSS 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 303 | int32_t CP0_SRSMap; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 304 | #define CP0SRSMap_SSV7 28 |
| 305 | #define CP0SRSMap_SSV6 24 |
| 306 | #define CP0SRSMap_SSV5 20 |
| 307 | #define CP0SRSMap_SSV4 16 |
| 308 | #define CP0SRSMap_SSV3 12 |
| 309 | #define CP0SRSMap_SSV2 8 |
| 310 | #define CP0SRSMap_SSV1 4 |
| 311 | #define CP0SRSMap_SSV0 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 312 | int32_t CP0_Cause; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 313 | #define CP0Ca_BD 31 |
| 314 | #define CP0Ca_TI 30 |
| 315 | #define CP0Ca_CE 28 |
| 316 | #define CP0Ca_DC 27 |
| 317 | #define CP0Ca_PCI 26 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 318 | #define CP0Ca_IV 23 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 319 | #define CP0Ca_WP 22 |
| 320 | #define CP0Ca_IP 8 |
ths | 4de9b24 | 2007-01-24 01:47:51 +0000 | [diff] [blame] | 321 | #define CP0Ca_IP_mask 0x0000FF00 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 322 | #define CP0Ca_EC 2 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 323 | target_ulong CP0_EPC; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 324 | int32_t CP0_PRid; |
ths | b29a034 | 2007-01-24 18:01:23 +0000 | [diff] [blame] | 325 | int32_t CP0_EBase; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 326 | int32_t CP0_Config0; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 327 | #define CP0C0_M 31 |
| 328 | #define CP0C0_K23 28 |
| 329 | #define CP0C0_KU 25 |
| 330 | #define CP0C0_MDU 20 |
| 331 | #define CP0C0_MM 17 |
| 332 | #define CP0C0_BM 16 |
| 333 | #define CP0C0_BE 15 |
| 334 | #define CP0C0_AT 13 |
| 335 | #define CP0C0_AR 10 |
| 336 | #define CP0C0_MT 7 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 337 | #define CP0C0_VI 3 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 338 | #define CP0C0_K0 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 339 | int32_t CP0_Config1; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 340 | #define CP0C1_M 31 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 341 | #define CP0C1_MMU 25 |
| 342 | #define CP0C1_IS 22 |
| 343 | #define CP0C1_IL 19 |
| 344 | #define CP0C1_IA 16 |
| 345 | #define CP0C1_DS 13 |
| 346 | #define CP0C1_DL 10 |
| 347 | #define CP0C1_DA 7 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 348 | #define CP0C1_C2 6 |
| 349 | #define CP0C1_MD 5 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 350 | #define CP0C1_PC 4 |
| 351 | #define CP0C1_WR 3 |
| 352 | #define CP0C1_CA 2 |
| 353 | #define CP0C1_EP 1 |
| 354 | #define CP0C1_FP 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 355 | int32_t CP0_Config2; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 356 | #define CP0C2_M 31 |
| 357 | #define CP0C2_TU 28 |
| 358 | #define CP0C2_TS 24 |
| 359 | #define CP0C2_TL 20 |
| 360 | #define CP0C2_TA 16 |
| 361 | #define CP0C2_SU 12 |
| 362 | #define CP0C2_SS 8 |
| 363 | #define CP0C2_SL 4 |
| 364 | #define CP0C2_SA 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 365 | int32_t CP0_Config3; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 366 | #define CP0C3_M 31 |
Nathan Froyd | bbfa8f7 | 2010-06-08 13:30:01 -0700 | [diff] [blame] | 367 | #define CP0C3_ISA_ON_EXC 16 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 368 | #define CP0C3_DSPP 10 |
| 369 | #define CP0C3_LPA 7 |
| 370 | #define CP0C3_VEIC 6 |
| 371 | #define CP0C3_VInt 5 |
| 372 | #define CP0C3_SP 4 |
| 373 | #define CP0C3_MT 2 |
| 374 | #define CP0C3_SM 1 |
| 375 | #define CP0C3_TL 0 |
ths | e397ee3 | 2007-03-23 00:43:28 +0000 | [diff] [blame] | 376 | int32_t CP0_Config6; |
| 377 | int32_t CP0_Config7; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 378 | /* XXX: Maybe make LLAddr per-TC? */ |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 379 | target_ulong lladdr; |
Paul Brook | 590bc60 | 2009-07-09 17:45:17 +0100 | [diff] [blame] | 380 | target_ulong llval; |
| 381 | target_ulong llnewval; |
| 382 | target_ulong llreg; |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 383 | target_ulong CP0_LLAddr_rw_bitmask; |
| 384 | int CP0_LLAddr_shift; |
ths | fd88b6a | 2007-05-23 08:24:25 +0000 | [diff] [blame] | 385 | target_ulong CP0_WatchLo[8]; |
| 386 | int32_t CP0_WatchHi[8]; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 387 | target_ulong CP0_XContext; |
| 388 | int32_t CP0_Framemask; |
| 389 | int32_t CP0_Debug; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 390 | #define CP0DB_DBD 31 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 391 | #define CP0DB_DM 30 |
| 392 | #define CP0DB_LSNM 28 |
| 393 | #define CP0DB_Doze 27 |
| 394 | #define CP0DB_Halt 26 |
| 395 | #define CP0DB_CNT 25 |
| 396 | #define CP0DB_IBEP 24 |
| 397 | #define CP0DB_DBEP 21 |
| 398 | #define CP0DB_IEXI 20 |
| 399 | #define CP0DB_VER 15 |
| 400 | #define CP0DB_DEC 10 |
| 401 | #define CP0DB_SSt 8 |
| 402 | #define CP0DB_DINT 5 |
| 403 | #define CP0DB_DIB 4 |
| 404 | #define CP0DB_DDBS 3 |
| 405 | #define CP0DB_DDBL 2 |
| 406 | #define CP0DB_DBp 1 |
| 407 | #define CP0DB_DSS 0 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 408 | target_ulong CP0_DEPC; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 409 | int32_t CP0_Performance0; |
| 410 | int32_t CP0_TagLo; |
| 411 | int32_t CP0_DataLo; |
| 412 | int32_t CP0_TagHi; |
| 413 | int32_t CP0_DataHi; |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 414 | target_ulong CP0_ErrorEPC; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 415 | int32_t CP0_DESAVE; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 416 | /* We waste some space so we can handle shadow registers like TCs. */ |
| 417 | TCState tcs[MIPS_SHADOW_SET_MAX]; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 418 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 419 | /* Qemu */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 420 | int error_code; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 421 | uint32_t hflags; /* CPU State */ |
| 422 | /* TMASK defines different execution modes */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 423 | #define MIPS_HFLAG_TMASK 0x007FF |
| 424 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 425 | /* The KSU flags must be the lowest bits in hflags. The flag order |
| 426 | must be the same as defined for CP0 Status. This allows to use |
| 427 | the bits as the value of mmu_idx. */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 428 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
| 429 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ |
| 430 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ |
| 431 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ |
| 432 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ |
| 433 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ |
| 434 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ |
| 435 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ |
| 436 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ |
ths | b8aa459 | 2007-12-30 15:36:58 +0000 | [diff] [blame] | 437 | /* True if the MIPS IV COP1X instructions can be used. This also |
| 438 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S |
| 439 | and RSQRT.D. */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 440 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
| 441 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ |
| 442 | #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ |
| 443 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
| 444 | #define MIPS_HFLAG_M16_SHIFT 10 |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 445 | /* If translation is interrupted between the branch instruction and |
| 446 | * the delay slot, record what type of branch it is so that we can |
| 447 | * resume translation properly. It might be possible to reduce |
| 448 | * this from three bits to two. */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 449 | #define MIPS_HFLAG_BMASK_BASE 0x03800 |
| 450 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
| 451 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ |
| 452 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ |
| 453 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ |
| 454 | /* Extra flags about the current pending branch. */ |
| 455 | #define MIPS_HFLAG_BMASK_EXT 0x3C000 |
| 456 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
| 457 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ |
| 458 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ |
| 459 | #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ |
| 460 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 461 | target_ulong btarget; /* Jump / branch target */ |
aurel32 | 1ba74fb | 2009-03-29 01:18:52 +0000 | [diff] [blame] | 462 | target_ulong bcond; /* Branch condition (if needed) */ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 463 | |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 464 | int SYNCI_Step; /* Address step size for SYNCI */ |
| 465 | int CCRes; /* Cycle count resolution/divisor */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 466 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
| 467 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 468 | int insn_flags; /* Supported instruction set */ |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 469 | |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 470 | target_ulong tls_value; /* For usermode emulation */ |
ths | 6f5b89a | 2007-03-02 20:48:00 +0000 | [diff] [blame] | 471 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 472 | CPU_COMMON |
ths | 6ae8177 | 2006-12-06 17:48:52 +0000 | [diff] [blame] | 473 | |
Blue Swirl | 51cc2e7 | 2009-11-08 12:50:21 +0200 | [diff] [blame] | 474 | CPUMIPSMVPContext *mvp; |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 475 | #if !defined(CONFIG_USER_ONLY) |
Blue Swirl | 51cc2e7 | 2009-11-08 12:50:21 +0200 | [diff] [blame] | 476 | CPUMIPSTLBContext *tlb; |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 477 | #endif |
Blue Swirl | 51cc2e7 | 2009-11-08 12:50:21 +0200 | [diff] [blame] | 478 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 479 | const mips_def_t *cpu_model; |
ths | 33ac7f1 | 2007-05-31 16:18:58 +0000 | [diff] [blame] | 480 | void *irq[8]; |
ths | 6ae8177 | 2006-12-06 17:48:52 +0000 | [diff] [blame] | 481 | struct QEMUTimer *timer; /* Internal timer */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 482 | }; |
| 483 | |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 484 | #if !defined(CONFIG_USER_ONLY) |
Aurelien Jarno | 60c9af0 | 2009-11-22 14:37:04 +0100 | [diff] [blame] | 485 | int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 486 | target_ulong address, int rw, int access_type); |
Aurelien Jarno | 60c9af0 | 2009-11-22 14:37:04 +0100 | [diff] [blame] | 487 | int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 488 | target_ulong address, int rw, int access_type); |
Aurelien Jarno | 60c9af0 | 2009-11-22 14:37:04 +0100 | [diff] [blame] | 489 | int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 490 | target_ulong address, int rw, int access_type); |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 491 | void r4k_helper_tlbwi (void); |
| 492 | void r4k_helper_tlbwr (void); |
| 493 | void r4k_helper_tlbp (void); |
| 494 | void r4k_helper_tlbr (void); |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 495 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 496 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 497 | int unused, int size); |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 498 | #endif |
| 499 | |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 500 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 501 | |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 502 | #define cpu_init cpu_mips_init |
| 503 | #define cpu_exec cpu_mips_exec |
| 504 | #define cpu_gen_code cpu_mips_gen_code |
| 505 | #define cpu_signal_handler cpu_mips_signal_handler |
j_mayer | c732abe | 2007-10-12 06:47:46 +0000 | [diff] [blame] | 506 | #define cpu_list mips_cpu_list |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 507 | |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 508 | #define CPU_SAVE_VERSION 3 |
| 509 | |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 510 | /* MMU modes definitions. We carefully match the indices with our |
| 511 | hflags layout. */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 512 | #define MMU_MODE0_SUFFIX _kernel |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 513 | #define MMU_MODE1_SUFFIX _super |
| 514 | #define MMU_MODE2_SUFFIX _user |
| 515 | #define MMU_USER_IDX 2 |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 516 | static inline int cpu_mmu_index (CPUState *env) |
| 517 | { |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 518 | return env->hflags & MIPS_HFLAG_KSU; |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 519 | } |
| 520 | |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 521 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
| 522 | { |
pbrook | f8ed707 | 2008-05-30 17:54:15 +0000 | [diff] [blame] | 523 | if (newsp) |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 524 | env->active_tc.gpr[29] = newsp; |
| 525 | env->active_tc.gpr[7] = 0; |
| 526 | env->active_tc.gpr[2] = 0; |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 527 | } |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 528 | |
Edgar E. Iglesias | 138afb0 | 2010-08-06 12:21:16 +0200 | [diff] [blame] | 529 | static inline int cpu_mips_hw_interrupts_pending(CPUState *env) |
| 530 | { |
| 531 | int32_t pending; |
| 532 | int32_t status; |
| 533 | int r; |
| 534 | |
Aurelien Jarno | 4cdc1cd | 2010-12-25 22:56:32 +0100 | [diff] [blame] | 535 | if (!(env->CP0_Status & (1 << CP0St_IE)) || |
| 536 | (env->CP0_Status & (1 << CP0St_EXL)) || |
| 537 | (env->CP0_Status & (1 << CP0St_ERL)) || |
| 538 | (env->hflags & MIPS_HFLAG_DM)) { |
| 539 | /* Interrupts are disabled */ |
| 540 | return 0; |
| 541 | } |
| 542 | |
Edgar E. Iglesias | 138afb0 | 2010-08-06 12:21:16 +0200 | [diff] [blame] | 543 | pending = env->CP0_Cause & CP0Ca_IP_mask; |
| 544 | status = env->CP0_Status & CP0Ca_IP_mask; |
| 545 | |
| 546 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
| 547 | /* A MIPS configured with a vectorizing external interrupt controller |
| 548 | will feed a vector into the Cause pending lines. The core treats |
| 549 | the status lines as a vector level, not as indiviual masks. */ |
| 550 | r = pending > status; |
| 551 | } else { |
| 552 | /* A MIPS configured with compatibility or VInt (Vectored Interrupts) |
| 553 | treats the pending lines as individual interrupt lines, the status |
| 554 | lines are individual masks. */ |
| 555 | r = pending & status; |
| 556 | } |
| 557 | return r; |
| 558 | } |
| 559 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 560 | #include "cpu-all.h" |
| 561 | |
| 562 | /* Memory access type : |
| 563 | * may be needed for precise access rights control and precise exceptions. |
| 564 | */ |
| 565 | enum { |
| 566 | /* 1 bit to define user level / supervisor access */ |
| 567 | ACCESS_USER = 0x00, |
| 568 | ACCESS_SUPER = 0x01, |
| 569 | /* 1 bit to indicate direction */ |
| 570 | ACCESS_STORE = 0x02, |
| 571 | /* Type of instruction that generated the access */ |
| 572 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 573 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 574 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 575 | }; |
| 576 | |
| 577 | /* Exceptions */ |
| 578 | enum { |
| 579 | EXCP_NONE = -1, |
| 580 | EXCP_RESET = 0, |
| 581 | EXCP_SRESET, |
| 582 | EXCP_DSS, |
| 583 | EXCP_DINT, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 584 | EXCP_DDBL, |
| 585 | EXCP_DDBS, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 586 | EXCP_NMI, |
| 587 | EXCP_MCHECK, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 588 | EXCP_EXT_INTERRUPT, /* 8 */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 589 | EXCP_DFWATCH, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 590 | EXCP_DIB, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 591 | EXCP_IWATCH, |
| 592 | EXCP_AdEL, |
| 593 | EXCP_AdES, |
| 594 | EXCP_TLBF, |
| 595 | EXCP_IBE, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 596 | EXCP_DBp, /* 16 */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 597 | EXCP_SYSCALL, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 598 | EXCP_BREAK, |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 599 | EXCP_CpU, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 600 | EXCP_RI, |
| 601 | EXCP_OVERFLOW, |
| 602 | EXCP_TRAP, |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 603 | EXCP_FPE, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 604 | EXCP_DWATCH, /* 24 */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 605 | EXCP_LTLBL, |
| 606 | EXCP_TLBL, |
| 607 | EXCP_TLBS, |
| 608 | EXCP_DBE, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 609 | EXCP_THREAD, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 610 | EXCP_MDMX, |
| 611 | EXCP_C2E, |
| 612 | EXCP_CACHE, /* 32 */ |
| 613 | |
| 614 | EXCP_LAST = EXCP_CACHE, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 615 | }; |
Paul Brook | 590bc60 | 2009-07-09 17:45:17 +0100 | [diff] [blame] | 616 | /* Dummy exception for conditional stores. */ |
| 617 | #define EXCP_SC 0x100 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 618 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 619 | int cpu_mips_exec(CPUMIPSState *s); |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 620 | CPUMIPSState *cpu_mips_init(const char *cpu_model); |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 621 | //~ uint32_t cpu_mips_get_clock (void); |
ths | 388bb21 | 2007-05-13 13:58:00 +0000 | [diff] [blame] | 622 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 623 | |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 624 | /* mips_timer.c */ |
| 625 | uint32_t cpu_mips_get_random (CPUState *env); |
| 626 | uint32_t cpu_mips_get_count (CPUState *env); |
| 627 | void cpu_mips_store_count (CPUState *env, uint32_t value); |
| 628 | void cpu_mips_store_compare (CPUState *env, uint32_t value); |
| 629 | void cpu_mips_start_count(CPUState *env); |
| 630 | void cpu_mips_stop_count(CPUState *env); |
| 631 | |
Aurelien Jarno | 5dc5d9f | 2010-07-25 16:51:29 +0200 | [diff] [blame] | 632 | /* mips_int.c */ |
| 633 | void cpu_mips_soft_irq(CPUState *env, int irq, int level); |
| 634 | |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 635 | /* helper.c */ |
| 636 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 637 | int mmu_idx, int is_softmmu); |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 638 | #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 639 | void do_interrupt (CPUState *env); |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 640 | #if !defined(CONFIG_USER_ONLY) |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 641 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 642 | target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address, |
| 643 | int rw); |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 644 | #endif |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 645 | |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 646 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
| 647 | target_ulong *cs_base, int *flags) |
| 648 | { |
| 649 | *pc = env->active_tc.PC; |
| 650 | *cs_base = 0; |
| 651 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
| 652 | } |
| 653 | |
Paul Brook | ff867dd | 2009-07-09 15:07:57 +0100 | [diff] [blame] | 654 | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
| 655 | { |
| 656 | env->tls_value = newtls; |
| 657 | } |
| 658 | |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 659 | static inline int cpu_has_work(CPUState *env) |
| 660 | { |
| 661 | int has_work = 0; |
| 662 | |
| 663 | /* It is implementation dependent if non-enabled interrupts |
| 664 | wake-up the CPU, however most of the implementations only |
| 665 | check for interrupts that can be taken. */ |
| 666 | if ((env->interrupt_request & CPU_INTERRUPT_HARD) && |
| 667 | cpu_mips_hw_interrupts_pending(env)) { |
| 668 | has_work = 1; |
| 669 | } |
| 670 | |
| 671 | return has_work; |
| 672 | } |
| 673 | |
| 674 | #include "exec-all.h" |
| 675 | |
| 676 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
| 677 | { |
| 678 | env->active_tc.PC = tb->pc; |
| 679 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 680 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
| 681 | } |
| 682 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 683 | #endif /* !defined (__MIPS_CPU_H__) */ |