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Markus Armbruster2a6a4072016-06-29 13:47:03 +02001#ifndef QEMU_MIPS_DEFS_H
2#define QEMU_MIPS_DEFS_H
bellard6af0bf92005-07-02 14:58:51 +00003
thse9c71dd2007-12-25 20:46:56 +00004/* Real pages are variable size... */
ths814b9a42006-12-06 17:42:40 +00005#define MIPS_TLB_MAX 128
bellard6af0bf92005-07-02 14:58:51 +00006
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +02007/*
8 * bit definitions for insn_flags (ISAs/ASEs flags)
9 * ------------------------------------------------
10 */
11/*
Huacai Chenaf868992020-06-02 10:39:15 +080012 * bits 0-23: MIPS base instruction sets
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020013 */
14#define ISA_MIPS1 0x0000000000000001ULL
15#define ISA_MIPS2 0x0000000000000002ULL
Philippe Mathieu-Daudéb0586b32020-12-16 12:41:25 +010016#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020017#define ISA_MIPS4 0x0000000000000008ULL
18#define ISA_MIPS5 0x0000000000000010ULL
Philippe Mathieu-Daudébbd5e4a2020-12-16 12:26:56 +010019#define ISA_MIPS_R1 0x0000000000000020ULL
Philippe Mathieu-Daudé7a47bae2020-12-16 12:29:00 +010020#define ISA_MIPS_R2 0x0000000000000040ULL
Philippe Mathieu-Daudébae4b152020-12-16 12:29:34 +010021#define ISA_MIPS_R3 0x0000000000000080ULL
Philippe Mathieu-Daudé5f89ce42020-12-16 12:30:11 +010022#define ISA_MIPS_R5 0x0000000000000100ULL
Philippe Mathieu-Daudé2e211e02020-12-16 12:34:42 +010023#define ISA_MIPS_R6 0x0000000000000200ULL
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020024#define ISA_NANOMIPS32 0x0000000000008000ULL
25/*
Huacai Chenaf868992020-06-02 10:39:15 +080026 * bits 24-39: MIPS ASEs
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020027 */
Huacai Chenaf868992020-06-02 10:39:15 +080028#define ASE_MIPS16 0x0000000001000000ULL
29#define ASE_MIPS3D 0x0000000002000000ULL
30#define ASE_MDMX 0x0000000004000000ULL
31#define ASE_DSP 0x0000000008000000ULL
32#define ASE_DSP_R2 0x0000000010000000ULL
33#define ASE_DSP_R3 0x0000000020000000ULL
34#define ASE_MT 0x0000000040000000ULL
35#define ASE_SMARTMIPS 0x0000000080000000ULL
36#define ASE_MICROMIPS 0x0000000100000000ULL
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020037/*
Huacai Chenaf868992020-06-02 10:39:15 +080038 * bits 40-51: vendor-specific base instruction sets
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020039 */
Huacai Chenaf868992020-06-02 10:39:15 +080040#define INSN_VR54XX 0x0000010000000000ULL
41#define INSN_R5900 0x0000020000000000ULL
42#define INSN_LOONGSON2E 0x0000040000000000ULL
43#define INSN_LOONGSON2F 0x0000080000000000ULL
44#define INSN_LOONGSON3A 0x0000100000000000ULL
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020045/*
Huacai Chenaf868992020-06-02 10:39:15 +080046 * bits 52-63: vendor-specific ASEs
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020047 */
Jiaxun Yang7f4d0652020-06-14 16:00:47 +080048/* MultiMedia Instructions defined by R5900 */
Huacai Chenaf868992020-06-02 10:39:15 +080049#define ASE_MMI 0x0010000000000000ULL
Jiaxun Yang7f4d0652020-06-14 16:00:47 +080050/* MIPS eXtension/enhanced Unit defined by Ingenic */
Huacai Chenaf868992020-06-02 10:39:15 +080051#define ASE_MXU 0x0020000000000000ULL
Jiaxun Yang7f4d0652020-06-14 16:00:47 +080052/* Loongson MultiMedia Instructions */
Huacai Chenaf868992020-06-02 10:39:15 +080053#define ASE_LMMI 0x0040000000000000ULL
Jiaxun Yang7f4d0652020-06-14 16:00:47 +080054/* Loongson EXTensions */
Huacai Chenaf868992020-06-02 10:39:15 +080055#define ASE_LEXT 0x0080000000000000ULL
thse189e742007-09-24 12:48:00 +000056
thse9c71dd2007-12-25 20:46:56 +000057/* MIPS CPU defines. */
Aleksandar Markovicf8232132019-09-24 15:26:35 +020058#define CPU_MIPS1 (ISA_MIPS1)
59#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
60#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
61#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
Philippe Mathieu-Daudébf552372020-12-16 12:23:38 +010062#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
thse9c71dd2007-12-25 20:46:56 +000063
Philippe Mathieu-Daudéb0586b32020-12-16 12:41:25 +010064#define CPU_MIPS64 (ISA_MIPS3)
65
thse9c71dd2007-12-25 20:46:56 +000066/* MIPS Technologies "Release 1" */
Philippe Mathieu-Daudébbd5e4a2020-12-16 12:26:56 +010067#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1)
Philippe Mathieu-Daudé08e22622020-12-16 17:23:15 +010068#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
thse189e742007-09-24 12:48:00 +000069
thse9c71dd2007-12-25 20:46:56 +000070/* MIPS Technologies "Release 2" */
Philippe Mathieu-Daudé7a47bae2020-12-16 12:29:00 +010071#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2)
Philippe Mathieu-Daudéf395cef2020-12-16 12:06:51 +010072#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
thse189e742007-09-24 12:48:00 +000073
Petar Jovanovice5275262014-01-15 17:01:46 +010074/* MIPS Technologies "Release 3" */
Philippe Mathieu-Daudébae4b152020-12-16 12:29:34 +010075#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
Philippe Mathieu-Daudé4d1524d2020-12-16 12:08:40 +010076#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
Petar Jovanovice5275262014-01-15 17:01:46 +010077
78/* MIPS Technologies "Release 5" */
Philippe Mathieu-Daudé5f89ce42020-12-16 12:30:11 +010079#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
Philippe Mathieu-Daudéd913c392020-12-16 12:09:08 +010080#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
Leon Alraefa0d2f62014-06-27 08:49:00 +010081
82/* MIPS Technologies "Release 6" */
Philippe Mathieu-Daudé2e211e02020-12-16 12:34:42 +010083#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
Philippe Mathieu-Daudé13514fc2020-12-16 12:14:00 +010084#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
Petar Jovanovice5275262014-01-15 17:01:46 +010085
Aleksandar Markovicf8232132019-09-24 15:26:35 +020086/*
87 * Strictly follow the architecture standard:
88 * - Disallow "special" instruction handling for PMON/SPIM.
89 * Note that we still maintain Count/Compare to match the host clock.
90 *
91 * #define MIPS_STRICT_STANDARD 1
92 */
thsb48cfdf2007-04-11 02:24:14 +000093
Markus Armbruster2a6a4072016-06-29 13:47:03 +020094#endif /* QEMU_MIPS_DEFS_H */