Markus Armbruster | 2a6a407 | 2016-06-29 13:47:03 +0200 | [diff] [blame] | 1 | #ifndef QEMU_MIPS_DEFS_H |
| 2 | #define QEMU_MIPS_DEFS_H |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 3 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 4 | /* Real pages are variable size... */ |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 5 | #define MIPS_TLB_MAX 128 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 6 | |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 7 | /* |
| 8 | * bit definitions for insn_flags (ISAs/ASEs flags) |
| 9 | * ------------------------------------------------ |
| 10 | */ |
| 11 | /* |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 12 | * bits 0-23: MIPS base instruction sets |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 13 | */ |
| 14 | #define ISA_MIPS1 0x0000000000000001ULL |
| 15 | #define ISA_MIPS2 0x0000000000000002ULL |
Philippe Mathieu-Daudé | b0586b3 | 2020-12-16 12:41:25 +0100 | [diff] [blame] | 16 | #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 17 | #define ISA_MIPS4 0x0000000000000008ULL |
| 18 | #define ISA_MIPS5 0x0000000000000010ULL |
Philippe Mathieu-Daudé | bbd5e4a | 2020-12-16 12:26:56 +0100 | [diff] [blame] | 19 | #define ISA_MIPS_R1 0x0000000000000020ULL |
Philippe Mathieu-Daudé | 7a47bae | 2020-12-16 12:29:00 +0100 | [diff] [blame] | 20 | #define ISA_MIPS_R2 0x0000000000000040ULL |
Philippe Mathieu-Daudé | bae4b15 | 2020-12-16 12:29:34 +0100 | [diff] [blame] | 21 | #define ISA_MIPS_R3 0x0000000000000080ULL |
Philippe Mathieu-Daudé | 5f89ce4 | 2020-12-16 12:30:11 +0100 | [diff] [blame] | 22 | #define ISA_MIPS_R5 0x0000000000000100ULL |
Philippe Mathieu-Daudé | 2e211e0 | 2020-12-16 12:34:42 +0100 | [diff] [blame] | 23 | #define ISA_MIPS_R6 0x0000000000000200ULL |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 24 | #define ISA_NANOMIPS32 0x0000000000008000ULL |
| 25 | /* |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 26 | * bits 24-39: MIPS ASEs |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 27 | */ |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 28 | #define ASE_MIPS16 0x0000000001000000ULL |
| 29 | #define ASE_MIPS3D 0x0000000002000000ULL |
| 30 | #define ASE_MDMX 0x0000000004000000ULL |
| 31 | #define ASE_DSP 0x0000000008000000ULL |
| 32 | #define ASE_DSP_R2 0x0000000010000000ULL |
| 33 | #define ASE_DSP_R3 0x0000000020000000ULL |
| 34 | #define ASE_MT 0x0000000040000000ULL |
| 35 | #define ASE_SMARTMIPS 0x0000000080000000ULL |
| 36 | #define ASE_MICROMIPS 0x0000000100000000ULL |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 37 | /* |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 38 | * bits 40-51: vendor-specific base instruction sets |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 39 | */ |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 40 | #define INSN_VR54XX 0x0000010000000000ULL |
| 41 | #define INSN_R5900 0x0000020000000000ULL |
| 42 | #define INSN_LOONGSON2E 0x0000040000000000ULL |
| 43 | #define INSN_LOONGSON2F 0x0000080000000000ULL |
| 44 | #define INSN_LOONGSON3A 0x0000100000000000ULL |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 45 | /* |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 46 | * bits 52-63: vendor-specific ASEs |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame] | 47 | */ |
Jiaxun Yang | 7f4d065 | 2020-06-14 16:00:47 +0800 | [diff] [blame] | 48 | /* MultiMedia Instructions defined by R5900 */ |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 49 | #define ASE_MMI 0x0010000000000000ULL |
Jiaxun Yang | 7f4d065 | 2020-06-14 16:00:47 +0800 | [diff] [blame] | 50 | /* MIPS eXtension/enhanced Unit defined by Ingenic */ |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 51 | #define ASE_MXU 0x0020000000000000ULL |
Jiaxun Yang | 7f4d065 | 2020-06-14 16:00:47 +0800 | [diff] [blame] | 52 | /* Loongson MultiMedia Instructions */ |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 53 | #define ASE_LMMI 0x0040000000000000ULL |
Jiaxun Yang | 7f4d065 | 2020-06-14 16:00:47 +0800 | [diff] [blame] | 54 | /* Loongson EXTensions */ |
Huacai Chen | af86899 | 2020-06-02 10:39:15 +0800 | [diff] [blame] | 55 | #define ASE_LEXT 0x0080000000000000ULL |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 56 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 57 | /* MIPS CPU defines. */ |
Aleksandar Markovic | f823213 | 2019-09-24 15:26:35 +0200 | [diff] [blame] | 58 | #define CPU_MIPS1 (ISA_MIPS1) |
| 59 | #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) |
| 60 | #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) |
| 61 | #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) |
Philippe Mathieu-Daudé | bf55237 | 2020-12-16 12:23:38 +0100 | [diff] [blame] | 62 | #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 63 | |
Philippe Mathieu-Daudé | b0586b3 | 2020-12-16 12:41:25 +0100 | [diff] [blame] | 64 | #define CPU_MIPS64 (ISA_MIPS3) |
| 65 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 66 | /* MIPS Technologies "Release 1" */ |
Philippe Mathieu-Daudé | bbd5e4a | 2020-12-16 12:26:56 +0100 | [diff] [blame] | 67 | #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1) |
Philippe Mathieu-Daudé | 08e2262 | 2020-12-16 17:23:15 +0100 | [diff] [blame] | 68 | #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 69 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 70 | /* MIPS Technologies "Release 2" */ |
Philippe Mathieu-Daudé | 7a47bae | 2020-12-16 12:29:00 +0100 | [diff] [blame] | 71 | #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) |
Philippe Mathieu-Daudé | f395cef | 2020-12-16 12:06:51 +0100 | [diff] [blame] | 72 | #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 73 | |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 74 | /* MIPS Technologies "Release 3" */ |
Philippe Mathieu-Daudé | bae4b15 | 2020-12-16 12:29:34 +0100 | [diff] [blame] | 75 | #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) |
Philippe Mathieu-Daudé | 4d1524d | 2020-12-16 12:08:40 +0100 | [diff] [blame] | 76 | #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 77 | |
| 78 | /* MIPS Technologies "Release 5" */ |
Philippe Mathieu-Daudé | 5f89ce4 | 2020-12-16 12:30:11 +0100 | [diff] [blame] | 79 | #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) |
Philippe Mathieu-Daudé | d913c39 | 2020-12-16 12:09:08 +0100 | [diff] [blame] | 80 | #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) |
Leon Alrae | fa0d2f6 | 2014-06-27 08:49:00 +0100 | [diff] [blame] | 81 | |
| 82 | /* MIPS Technologies "Release 6" */ |
Philippe Mathieu-Daudé | 2e211e0 | 2020-12-16 12:34:42 +0100 | [diff] [blame] | 83 | #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) |
Philippe Mathieu-Daudé | 13514fc | 2020-12-16 12:14:00 +0100 | [diff] [blame] | 84 | #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 85 | |
Aleksandar Markovic | f823213 | 2019-09-24 15:26:35 +0200 | [diff] [blame] | 86 | /* |
| 87 | * Strictly follow the architecture standard: |
| 88 | * - Disallow "special" instruction handling for PMON/SPIM. |
| 89 | * Note that we still maintain Count/Compare to match the host clock. |
| 90 | * |
| 91 | * #define MIPS_STRICT_STANDARD 1 |
| 92 | */ |
ths | b48cfdf | 2007-04-11 02:24:14 +0000 | [diff] [blame] | 93 | |
Markus Armbruster | 2a6a407 | 2016-06-29 13:47:03 +0200 | [diff] [blame] | 94 | #endif /* QEMU_MIPS_DEFS_H */ |