blob: 66b79539a54265470008048fbcf3f5ca4bd6bd1e [file] [log] [blame]
Markus Armbruster2a6a4072016-06-29 13:47:03 +02001#ifndef QEMU_MIPS_DEFS_H
2#define QEMU_MIPS_DEFS_H
bellard6af0bf92005-07-02 14:58:51 +00003
bellard6af0bf92005-07-02 14:58:51 +00004/* If we want to use host float regs... */
5//#define USE_HOST_FLOAT_REGS
6
thse9c71dd2007-12-25 20:46:56 +00007/* Real pages are variable size... */
bellard6af0bf92005-07-02 14:58:51 +00008#define TARGET_PAGE_BITS 12
ths814b9a42006-12-06 17:42:40 +00009#define MIPS_TLB_MAX 128
bellard6af0bf92005-07-02 14:58:51 +000010
thsd26bc212007-11-08 18:05:37 +000011#if defined(TARGET_MIPS64)
thsc570fd12006-12-21 01:19:56 +000012#define TARGET_LONG_BITS 64
Leon Alraee117f522015-04-14 10:09:38 +010013#define TARGET_PHYS_ADDR_SPACE_BITS 48
Yongbok Kim4dc89b72015-06-29 10:11:23 +010014#define TARGET_VIRT_ADDR_SPACE_BITS 48
thsc570fd12006-12-21 01:19:56 +000015#else
16#define TARGET_LONG_BITS 32
Leon Alraee117f522015-04-14 10:09:38 +010017#define TARGET_PHYS_ADDR_SPACE_BITS 40
Richard Henderson18e80c52017-10-05 10:36:00 -040018# ifdef CONFIG_USER_ONLY
19# define TARGET_VIRT_ADDR_SPACE_BITS 31
20# else
21# define TARGET_VIRT_ADDR_SPACE_BITS 32
22#endif
thsc570fd12006-12-21 01:19:56 +000023#endif
24
Philippe Mathieu-Daudé45ebdd22018-10-16 12:09:54 +020025/*
26 * bit definitions for insn_flags (ISAs/ASEs flags)
27 * ------------------------------------------------
28 */
29/*
30 * bits 0-31: MIPS base instruction sets
31 */
32#define ISA_MIPS1 0x0000000000000001ULL
33#define ISA_MIPS2 0x0000000000000002ULL
34#define ISA_MIPS3 0x0000000000000004ULL
35#define ISA_MIPS4 0x0000000000000008ULL
36#define ISA_MIPS5 0x0000000000000010ULL
37#define ISA_MIPS32 0x0000000000000020ULL
38#define ISA_MIPS32R2 0x0000000000000040ULL
39#define ISA_MIPS64 0x0000000000000080ULL
40#define ISA_MIPS64R2 0x0000000000000100ULL
41#define ISA_MIPS32R3 0x0000000000000200ULL
42#define ISA_MIPS64R3 0x0000000000000400ULL
43#define ISA_MIPS32R5 0x0000000000000800ULL
44#define ISA_MIPS64R5 0x0000000000001000ULL
45#define ISA_MIPS32R6 0x0000000000002000ULL
46#define ISA_MIPS64R6 0x0000000000004000ULL
47#define ISA_NANOMIPS32 0x0000000000008000ULL
48/*
49 * bits 32-47: MIPS ASEs
50 */
51#define ASE_MIPS16 0x0000000100000000ULL
52#define ASE_MIPS3D 0x0000000200000000ULL
53#define ASE_MDMX 0x0000000400000000ULL
54#define ASE_DSP 0x0000000800000000ULL
55#define ASE_DSPR2 0x0000001000000000ULL
56#define ASE_MT 0x0000004000000000ULL
57#define ASE_SMARTMIPS 0x0000008000000000ULL
58#define ASE_MICROMIPS 0x0000010000000000ULL
59#define ASE_MSA 0x0000020000000000ULL
60/*
61 * bits 48-55: vendor-specific base instruction sets
62 */
63#define INSN_LOONGSON2E 0x0001000000000000ULL
64#define INSN_LOONGSON2F 0x0002000000000000ULL
65#define INSN_VR54XX 0x0004000000000000ULL
66/*
67 * bits 56-63: vendor-specific ASEs
68 */
thse189e742007-09-24 12:48:00 +000069
thse9c71dd2007-12-25 20:46:56 +000070/* MIPS CPU defines. */
thse189e742007-09-24 12:48:00 +000071#define CPU_MIPS1 (ISA_MIPS1)
72#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
73#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
74#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
thse9c71dd2007-12-25 20:46:56 +000075#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
Huacai Chen5bc6fba2010-06-29 10:50:27 +080076#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
77#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
thse9c71dd2007-12-25 20:46:56 +000078
thse189e742007-09-24 12:48:00 +000079#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
80
thse9c71dd2007-12-25 20:46:56 +000081/* MIPS Technologies "Release 1" */
thse189e742007-09-24 12:48:00 +000082#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
83#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
84
thse9c71dd2007-12-25 20:46:56 +000085/* MIPS Technologies "Release 2" */
thse189e742007-09-24 12:48:00 +000086#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
87#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
88
Petar Jovanovice5275262014-01-15 17:01:46 +010089/* MIPS Technologies "Release 3" */
90#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
Leon Alraefa0d2f62014-06-27 08:49:00 +010091#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
Petar Jovanovice5275262014-01-15 17:01:46 +010092
93/* MIPS Technologies "Release 5" */
94#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
Leon Alraefa0d2f62014-06-27 08:49:00 +010095#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
96
97/* MIPS Technologies "Release 6" */
98#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
99#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
Petar Jovanovice5275262014-01-15 17:01:46 +0100100
Aleksandar Markovicfa7c0c92018-08-02 16:16:01 +0200101/* Wave Computing: "nanoMIPS" */
102#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
103
ths19221bd2007-04-19 16:35:09 +0000104/* Strictly follow the architecture standard:
105 - Disallow "special" instruction handling for PMON/SPIM.
106 Note that we still maintain Count/Compare to match the host clock. */
thsb48cfdf2007-04-11 02:24:14 +0000107//#define MIPS_STRICT_STANDARD 1
108
Markus Armbruster2a6a4072016-06-29 13:47:03 +0200109#endif /* QEMU_MIPS_DEFS_H */