Markus Armbruster | 2a6a407 | 2016-06-29 13:47:03 +0200 | [diff] [blame] | 1 | #ifndef QEMU_MIPS_DEFS_H |
| 2 | #define QEMU_MIPS_DEFS_H |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 3 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 4 | /* If we want to use host float regs... */ |
| 5 | //#define USE_HOST_FLOAT_REGS |
| 6 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 7 | /* Real pages are variable size... */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 8 | #define TARGET_PAGE_BITS 12 |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 9 | #define MIPS_TLB_MAX 128 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 10 | |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 11 | #if defined(TARGET_MIPS64) |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 12 | #define TARGET_LONG_BITS 64 |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 13 | #define TARGET_PHYS_ADDR_SPACE_BITS 48 |
Yongbok Kim | 4dc89b7 | 2015-06-29 10:11:23 +0100 | [diff] [blame] | 14 | #define TARGET_VIRT_ADDR_SPACE_BITS 48 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 15 | #else |
| 16 | #define TARGET_LONG_BITS 32 |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 17 | #define TARGET_PHYS_ADDR_SPACE_BITS 40 |
Richard Henderson | 18e80c5 | 2017-10-05 10:36:00 -0400 | [diff] [blame] | 18 | # ifdef CONFIG_USER_ONLY |
| 19 | # define TARGET_VIRT_ADDR_SPACE_BITS 31 |
| 20 | # else |
| 21 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 22 | #endif |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 23 | #endif |
| 24 | |
Philippe Mathieu-Daudé | 45ebdd2 | 2018-10-16 12:09:54 +0200 | [diff] [blame^] | 25 | /* |
| 26 | * bit definitions for insn_flags (ISAs/ASEs flags) |
| 27 | * ------------------------------------------------ |
| 28 | */ |
| 29 | /* |
| 30 | * bits 0-31: MIPS base instruction sets |
| 31 | */ |
| 32 | #define ISA_MIPS1 0x0000000000000001ULL |
| 33 | #define ISA_MIPS2 0x0000000000000002ULL |
| 34 | #define ISA_MIPS3 0x0000000000000004ULL |
| 35 | #define ISA_MIPS4 0x0000000000000008ULL |
| 36 | #define ISA_MIPS5 0x0000000000000010ULL |
| 37 | #define ISA_MIPS32 0x0000000000000020ULL |
| 38 | #define ISA_MIPS32R2 0x0000000000000040ULL |
| 39 | #define ISA_MIPS64 0x0000000000000080ULL |
| 40 | #define ISA_MIPS64R2 0x0000000000000100ULL |
| 41 | #define ISA_MIPS32R3 0x0000000000000200ULL |
| 42 | #define ISA_MIPS64R3 0x0000000000000400ULL |
| 43 | #define ISA_MIPS32R5 0x0000000000000800ULL |
| 44 | #define ISA_MIPS64R5 0x0000000000001000ULL |
| 45 | #define ISA_MIPS32R6 0x0000000000002000ULL |
| 46 | #define ISA_MIPS64R6 0x0000000000004000ULL |
| 47 | #define ISA_NANOMIPS32 0x0000000000008000ULL |
| 48 | /* |
| 49 | * bits 32-47: MIPS ASEs |
| 50 | */ |
| 51 | #define ASE_MIPS16 0x0000000100000000ULL |
| 52 | #define ASE_MIPS3D 0x0000000200000000ULL |
| 53 | #define ASE_MDMX 0x0000000400000000ULL |
| 54 | #define ASE_DSP 0x0000000800000000ULL |
| 55 | #define ASE_DSPR2 0x0000001000000000ULL |
| 56 | #define ASE_MT 0x0000004000000000ULL |
| 57 | #define ASE_SMARTMIPS 0x0000008000000000ULL |
| 58 | #define ASE_MICROMIPS 0x0000010000000000ULL |
| 59 | #define ASE_MSA 0x0000020000000000ULL |
| 60 | /* |
| 61 | * bits 48-55: vendor-specific base instruction sets |
| 62 | */ |
| 63 | #define INSN_LOONGSON2E 0x0001000000000000ULL |
| 64 | #define INSN_LOONGSON2F 0x0002000000000000ULL |
| 65 | #define INSN_VR54XX 0x0004000000000000ULL |
| 66 | /* |
| 67 | * bits 56-63: vendor-specific ASEs |
| 68 | */ |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 69 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 70 | /* MIPS CPU defines. */ |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 71 | #define CPU_MIPS1 (ISA_MIPS1) |
| 72 | #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) |
| 73 | #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) |
| 74 | #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 75 | #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) |
Huacai Chen | 5bc6fba | 2010-06-29 10:50:27 +0800 | [diff] [blame] | 76 | #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) |
| 77 | #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 78 | |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 79 | #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) |
| 80 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 81 | /* MIPS Technologies "Release 1" */ |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 82 | #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) |
| 83 | #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) |
| 84 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 85 | /* MIPS Technologies "Release 2" */ |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 86 | #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) |
| 87 | #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) |
| 88 | |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 89 | /* MIPS Technologies "Release 3" */ |
| 90 | #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) |
Leon Alrae | fa0d2f6 | 2014-06-27 08:49:00 +0100 | [diff] [blame] | 91 | #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 92 | |
| 93 | /* MIPS Technologies "Release 5" */ |
| 94 | #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) |
Leon Alrae | fa0d2f6 | 2014-06-27 08:49:00 +0100 | [diff] [blame] | 95 | #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) |
| 96 | |
| 97 | /* MIPS Technologies "Release 6" */ |
| 98 | #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) |
| 99 | #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) |
Petar Jovanovic | e527526 | 2014-01-15 17:01:46 +0100 | [diff] [blame] | 100 | |
Aleksandar Markovic | fa7c0c9 | 2018-08-02 16:16:01 +0200 | [diff] [blame] | 101 | /* Wave Computing: "nanoMIPS" */ |
| 102 | #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) |
| 103 | |
ths | 19221bd | 2007-04-19 16:35:09 +0000 | [diff] [blame] | 104 | /* Strictly follow the architecture standard: |
| 105 | - Disallow "special" instruction handling for PMON/SPIM. |
| 106 | Note that we still maintain Count/Compare to match the host clock. */ |
ths | b48cfdf | 2007-04-11 02:24:14 +0000 | [diff] [blame] | 107 | //#define MIPS_STRICT_STANDARD 1 |
| 108 | |
Markus Armbruster | 2a6a407 | 2016-06-29 13:47:03 +0200 | [diff] [blame] | 109 | #endif /* QEMU_MIPS_DEFS_H */ |