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Hannes Reineckee8f943c2012-05-29 13:51:17 +02001/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
Chetan Pant61f3c912020-10-23 12:44:24 +000010 * version 2.1 of the License, or (at your option) any later version.
Hannes Reineckee8f943c2012-05-29 13:51:17 +020011 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
Peter Maydella4ab4792016-01-26 18:17:16 +000021#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010022#include "hw/pci/pci.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020023#include "hw/qdev-properties.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010024#include "sysemu/dma.h"
Markus Armbruster4be74632014-10-07 13:59:18 +020025#include "sysemu/block-backend.h"
Peter Maydell2f93d8b2021-11-29 20:55:05 +000026#include "sysemu/rtc.h"
Hannes Reinecke4522b692014-04-16 16:44:15 +020027#include "hw/pci/msi.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010028#include "hw/pci/msix.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010029#include "qemu/iov.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020030#include "qemu/module.h"
Peter Maydell15e09912022-02-08 20:08:56 +000031#include "qemu/hw-version.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010032#include "hw/scsi/scsi.h"
Paolo Bonzini08e2c9f2017-08-22 09:23:55 +020033#include "scsi/constants.h"
Hannes Reineckee8f943c2012-05-29 13:51:17 +020034#include "trace.h"
Cao jin1108b2f2016-06-20 14:13:39 +080035#include "qapi/error.h"
Paolo Bonzini47b43a12013-03-18 17:36:02 +010036#include "mfi.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020037#include "migration/vmstate.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040038#include "qom/object.h"
Hannes Reineckee8f943c2012-05-29 13:51:17 +020039
Hannes Reineckee23d0492014-10-29 13:00:08 +010040#define MEGASAS_VERSION_GEN1 "1.70"
41#define MEGASAS_VERSION_GEN2 "1.80"
Hannes Reineckee8f943c2012-05-29 13:51:17 +020042#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
43#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
Hannes Reineckee23d0492014-10-29 13:00:08 +010044#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
Hannes Reineckee8f943c2012-05-29 13:51:17 +020045#define MEGASAS_MAX_SGE 128 /* Firmware limit */
46#define MEGASAS_DEFAULT_SGE 80
47#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
48#define MEGASAS_MAX_ARRAYS 128
49
Hannes Reineckefb654152012-08-24 12:36:41 +020050#define MEGASAS_HBA_SERIAL "QEMU123456"
Hannes Reinecke76b523d2012-08-01 12:46:50 +020051#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
52#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
53
Hannes Reineckee8f943c2012-05-29 13:51:17 +020054#define MEGASAS_FLAG_USE_JBOD 0
55#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
Cao jinb4b4a572016-06-20 14:13:37 +080056#define MEGASAS_FLAG_USE_QUEUE64 1
Hannes Reineckee8f943c2012-05-29 13:51:17 +020057#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
58
Hannes Reineckee8f943c2012-05-29 13:51:17 +020059typedef struct MegasasCmd {
60 uint32_t index;
61 uint16_t flags;
62 uint16_t count;
63 uint64_t context;
64
Avi Kivitya8170e52012-10-23 12:30:10 +020065 hwaddr pa;
66 hwaddr pa_size;
Paolo Bonzini5104fac2017-06-01 17:18:23 +020067 uint32_t dcmd_opcode;
Hannes Reineckee8f943c2012-05-29 13:51:17 +020068 union mfi_frame *frame;
69 SCSIRequest *req;
70 QEMUSGList qsg;
71 void *iov_buf;
72 size_t iov_size;
73 size_t iov_offset;
74 struct MegasasState *state;
75} MegasasCmd;
76
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040077struct MegasasState {
Andreas Färber52190c12013-06-30 14:02:53 +020078 /*< private >*/
79 PCIDevice parent_obj;
80 /*< public >*/
81
Hannes Reineckee8f943c2012-05-29 13:51:17 +020082 MemoryRegion mmio_io;
83 MemoryRegion port_io;
84 MemoryRegion queue_io;
85 uint32_t frame_hi;
86
Prasad J Pandit2b151292020-05-14 00:55:40 +053087 uint32_t fw_state;
Hannes Reineckee8f943c2012-05-29 13:51:17 +020088 uint32_t fw_sge;
89 uint32_t fw_cmds;
90 uint32_t flags;
Prasad J Pandit2b151292020-05-14 00:55:40 +053091 uint32_t fw_luns;
92 uint32_t intr_mask;
93 uint32_t doorbell;
94 uint32_t busy;
95 uint32_t diag;
96 uint32_t adp_reset;
Cao jinb4b4a572016-06-20 14:13:37 +080097 OnOffAuto msi;
98 OnOffAuto msix;
Hannes Reineckee8f943c2012-05-29 13:51:17 +020099
100 MegasasCmd *event_cmd;
Prasad J Pandit2b151292020-05-14 00:55:40 +0530101 uint16_t event_locale;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200102 int event_class;
Prasad J Pandit2b151292020-05-14 00:55:40 +0530103 uint32_t event_count;
104 uint32_t shutdown_event;
105 uint32_t boot_event;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200106
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200107 uint64_t sas_addr;
Hannes Reineckefb654152012-08-24 12:36:41 +0200108 char *hba_serial;
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200109
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200110 uint64_t reply_queue_pa;
111 void *reply_queue;
Prasad J Pandit2b151292020-05-14 00:55:40 +0530112 uint16_t reply_queue_len;
Philippe Mathieu-Daudé41d5e8d2021-12-17 22:43:05 +0100113 uint32_t reply_queue_head;
114 uint32_t reply_queue_tail;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200115 uint64_t consumer_pa;
116 uint64_t producer_pa;
117
118 MegasasCmd frames[MEGASAS_MAX_FRAMES];
Hannes Reinecke6df57182014-10-29 13:00:15 +0100119 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200120 SCSIBus bus;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -0400121};
122typedef struct MegasasState MegasasState;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200123
Eduardo Habkostdb1015e2020-09-03 16:43:22 -0400124struct MegasasBaseClass {
Hannes Reineckee23d0492014-10-29 13:00:08 +0100125 PCIDeviceClass parent_class;
126 const char *product_name;
127 const char *product_version;
128 int mmio_bar;
129 int ioport_bar;
130 int osts;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -0400131};
132typedef struct MegasasBaseClass MegasasBaseClass;
Hannes Reineckee23d0492014-10-29 13:00:08 +0100133
134#define TYPE_MEGASAS_BASE "megasas-base"
135#define TYPE_MEGASAS_GEN1 "megasas"
136#define TYPE_MEGASAS_GEN2 "megasas-gen2"
Peter Crosthwaitec79e16a2013-06-24 16:54:15 +1000137
Eduardo Habkost8110fa12020-08-31 17:07:33 -0400138DECLARE_OBJ_CHECKERS(MegasasState, MegasasBaseClass,
139 MEGASAS, TYPE_MEGASAS_BASE)
Hannes Reineckee23d0492014-10-29 13:00:08 +0100140
Peter Crosthwaitec79e16a2013-06-24 16:54:15 +1000141
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200142#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
143
144static bool megasas_intr_enabled(MegasasState *s)
145{
146 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
147 MEGASAS_INTR_DISABLED_MASK) {
148 return true;
149 }
150 return false;
151}
152
153static bool megasas_use_queue64(MegasasState *s)
154{
155 return s->flags & MEGASAS_MASK_USE_QUEUE64;
156}
157
158static bool megasas_use_msix(MegasasState *s)
159{
Cao jinb4b4a572016-06-20 14:13:37 +0800160 return s->msix != ON_OFF_AUTO_OFF;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200161}
162
163static bool megasas_is_jbod(MegasasState *s)
164{
165 return s->flags & MEGASAS_MASK_USE_JBOD;
166}
167
Paolo Bonzini16578c62015-03-23 17:15:17 +0100168static void megasas_frame_set_cmd_status(MegasasState *s,
169 unsigned long frame, uint8_t v)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200170{
Paolo Bonzini16578c62015-03-23 17:15:17 +0100171 PCIDevice *pci = &s->parent_obj;
Philippe Mathieu-Daudéa423a1b2021-12-17 22:39:42 +0100172 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status),
173 v, MEMTXATTRS_UNSPECIFIED);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200174}
175
Paolo Bonzini16578c62015-03-23 17:15:17 +0100176static void megasas_frame_set_scsi_status(MegasasState *s,
177 unsigned long frame, uint8_t v)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200178{
Paolo Bonzini16578c62015-03-23 17:15:17 +0100179 PCIDevice *pci = &s->parent_obj;
Philippe Mathieu-Daudéa423a1b2021-12-17 22:39:42 +0100180 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status),
181 v, MEMTXATTRS_UNSPECIFIED);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200182}
183
Thomas Huthee760ac2020-06-15 09:26:29 +0200184static inline const char *mfi_frame_desc(unsigned int cmd)
185{
186 static const char *mfi_frame_descs[] = {
187 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
188 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"
189 };
190
191 if (cmd < ARRAY_SIZE(mfi_frame_descs)) {
192 return mfi_frame_descs[cmd];
193 }
194
195 return "Unknown";
196}
197
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200198/*
199 * Context is considered opaque, but the HBA firmware is running
200 * in little endian mode. So convert it to little endian, too.
201 */
Paolo Bonzini16578c62015-03-23 17:15:17 +0100202static uint64_t megasas_frame_get_context(MegasasState *s,
203 unsigned long frame)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200204{
Paolo Bonzini16578c62015-03-23 17:15:17 +0100205 PCIDevice *pci = &s->parent_obj;
Philippe Mathieu-Daudé4a630542021-12-17 23:49:30 +0100206 uint64_t val;
207
208 ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context),
209 &val, MEMTXATTRS_UNSPECIFIED);
210
211 return val;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200212}
213
214static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
215{
216 return cmd->flags & MFI_FRAME_IEEE_SGL;
217}
218
219static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
220{
221 return cmd->flags & MFI_FRAME_SGL64;
222}
223
224static bool megasas_frame_is_sense64(MegasasCmd *cmd)
225{
226 return cmd->flags & MFI_FRAME_SENSE64;
227}
228
229static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
230 union mfi_sgl *sgl)
231{
232 uint64_t addr;
233
234 if (megasas_frame_is_ieee_sgl(cmd)) {
235 addr = le64_to_cpu(sgl->sg_skinny->addr);
236 } else if (megasas_frame_is_sgl64(cmd)) {
237 addr = le64_to_cpu(sgl->sg64->addr);
238 } else {
239 addr = le32_to_cpu(sgl->sg32->addr);
240 }
241 return addr;
242}
243
244static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
245 union mfi_sgl *sgl)
246{
247 uint32_t len;
248
249 if (megasas_frame_is_ieee_sgl(cmd)) {
250 len = le32_to_cpu(sgl->sg_skinny->len);
251 } else if (megasas_frame_is_sgl64(cmd)) {
252 len = le32_to_cpu(sgl->sg64->len);
253 } else {
254 len = le32_to_cpu(sgl->sg32->len);
255 }
256 return len;
257}
258
259static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
260 union mfi_sgl *sgl)
261{
262 uint8_t *next = (uint8_t *)sgl;
263
264 if (megasas_frame_is_ieee_sgl(cmd)) {
265 next += sizeof(struct mfi_sg_skinny);
266 } else if (megasas_frame_is_sgl64(cmd)) {
267 next += sizeof(struct mfi_sg64);
268 } else {
269 next += sizeof(struct mfi_sg32);
270 }
271
272 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
273 return NULL;
274 }
275 return (union mfi_sgl *)next;
276}
277
278static void megasas_soft_reset(MegasasState *s);
279
280static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
281{
282 int i;
283 int iov_count = 0;
284 size_t iov_size = 0;
285
286 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
287 iov_count = cmd->frame->header.sge_count;
Li Qiang4773a5f2020-08-15 07:19:40 -0700288 if (!iov_count || iov_count > MEGASAS_MAX_SGE) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200289 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
290 MEGASAS_MAX_SGE);
Li Qiang5ecfbae2020-08-15 07:19:39 -0700291 return -1;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200292 }
Andreas Färber52190c12013-06-30 14:02:53 +0200293 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200294 for (i = 0; i < iov_count; i++) {
295 dma_addr_t iov_pa, iov_size_p;
296
297 if (!sgl) {
298 trace_megasas_iovec_sgl_underflow(cmd->index, i);
299 goto unmap;
300 }
301 iov_pa = megasas_sgl_get_addr(cmd, sgl);
302 iov_size_p = megasas_sgl_get_len(cmd, sgl);
303 if (!iov_pa || !iov_size_p) {
304 trace_megasas_iovec_sgl_invalid(cmd->index, i,
305 iov_pa, iov_size_p);
306 goto unmap;
307 }
308 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
309 sgl = megasas_sgl_next(cmd, sgl);
310 iov_size += (size_t)iov_size_p;
311 }
312 if (cmd->iov_size > iov_size) {
313 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
Philippe Mathieu-Daudé97a2b072021-11-19 21:11:40 +0100314 goto unmap;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200315 } else if (cmd->iov_size < iov_size) {
Eric Blaked17e7442017-03-13 14:55:19 -0500316 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200317 }
318 cmd->iov_offset = 0;
319 return 0;
320unmap:
321 qemu_sglist_destroy(&cmd->qsg);
Li Qiang5ecfbae2020-08-15 07:19:39 -0700322 return -1;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200323}
324
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200325/*
326 * passthrough sense and io sense are at the same offset
327 */
328static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
329 uint8_t sense_len)
330{
Paolo Bonzini1016b232014-06-13 17:26:13 +0200331 PCIDevice *pcid = PCI_DEVICE(cmd->state);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200332 uint32_t pa_hi = 0, pa_lo;
Avi Kivitya8170e52012-10-23 12:30:10 +0200333 hwaddr pa;
Paolo Bonzini134550b2017-06-01 17:18:39 +0200334 int frame_sense_len;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200335
Paolo Bonzini134550b2017-06-01 17:18:39 +0200336 frame_sense_len = cmd->frame->header.sense_len;
337 if (sense_len > frame_sense_len) {
338 sense_len = frame_sense_len;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200339 }
340 if (sense_len) {
341 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
342 if (megasas_frame_is_sense64(cmd)) {
343 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
344 }
345 pa = ((uint64_t) pa_hi << 32) | pa_lo;
Paolo Bonzini1016b232014-06-13 17:26:13 +0200346 pci_dma_write(pcid, pa, sense_ptr, sense_len);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200347 cmd->frame->header.sense_len = sense_len;
348 }
349 return sense_len;
350}
351
352static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
353{
354 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
355 uint8_t sense_len = 18;
356
357 memset(sense_buf, 0, sense_len);
358 sense_buf[0] = 0xf0;
359 sense_buf[2] = sense.key;
360 sense_buf[7] = 10;
361 sense_buf[12] = sense.asc;
362 sense_buf[13] = sense.ascq;
363 megasas_build_sense(cmd, sense_buf, sense_len);
364}
365
366static void megasas_copy_sense(MegasasCmd *cmd)
367{
368 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
369 uint8_t sense_len;
370
371 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
372 SCSI_SENSE_BUF_SIZE);
373 megasas_build_sense(cmd, sense_buf, sense_len);
374}
375
376/*
377 * Format an INQUIRY CDB
378 */
379static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
380{
381 memset(cdb, 0, 6);
382 cdb[0] = INQUIRY;
383 if (pg > 0) {
384 cdb[1] = 0x1;
385 cdb[2] = pg;
386 }
Philippe Mathieu-Daudé2a0c5132021-12-18 12:19:12 +0100387 stw_be_p(&cdb[3], len);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200388 return len;
389}
390
391/*
392 * Encode lba and len into a READ_16/WRITE_16 CDB
393 */
394static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
395 uint32_t len, bool is_write)
396{
397 memset(cdb, 0x0, 16);
398 if (is_write) {
399 cdb[0] = WRITE_16;
400 } else {
401 cdb[0] = READ_16;
402 }
Philippe Mathieu-Daudé2a0c5132021-12-18 12:19:12 +0100403 stq_be_p(&cdb[2], lba);
404 stl_be_p(&cdb[2 + 8], len);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200405}
406
407/*
408 * Utility functions
409 */
410static uint64_t megasas_fw_time(void)
411{
412 struct tm curtime;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200413
414 qemu_get_timedate(&curtime, 0);
Eduardo Habkost9be38592016-06-13 18:57:58 -0300415 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200416 ((uint64_t)curtime.tm_min & 0xff) << 40 |
417 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
418 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
419 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
420 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200421}
422
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200423/*
424 * Default disk sata address
425 * 0x1221 is the magic number as
426 * present in real hardware,
427 * so use it here, too.
428 */
429static uint64_t megasas_get_sata_addr(uint16_t id)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200430{
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200431 uint64_t addr = (0x1221ULL << 48);
Paolo Bonzini8ef2eb82015-09-30 19:21:10 +0200432 return addr | ((uint64_t)id << 24);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200433}
434
435/*
436 * Frame handling
437 */
438static int megasas_next_index(MegasasState *s, int index, int limit)
439{
440 index++;
441 if (index == limit) {
442 index = 0;
443 }
444 return index;
445}
446
447static MegasasCmd *megasas_lookup_frame(MegasasState *s,
Avi Kivitya8170e52012-10-23 12:30:10 +0200448 hwaddr frame)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200449{
450 MegasasCmd *cmd = NULL;
451 int num = 0, index;
452
453 index = s->reply_queue_head;
454
Prasad J Panditf50ab862020-05-14 00:55:38 +0530455 while (num < s->fw_cmds && index < MEGASAS_MAX_FRAMES) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200456 if (s->frames[index].pa && s->frames[index].pa == frame) {
457 cmd = &s->frames[index];
458 break;
459 }
460 index = megasas_next_index(s, index, s->fw_cmds);
461 num++;
462 }
463
464 return cmd;
465}
466
Hannes Reinecke6df57182014-10-29 13:00:15 +0100467static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200468{
Hannes Reinecke6df57182014-10-29 13:00:15 +0100469 PCIDevice *p = PCI_DEVICE(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200470
Paolo Bonzini75f19f82016-09-16 00:36:58 +0200471 if (cmd->pa_size) {
472 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
473 }
Hannes Reinecke6df57182014-10-29 13:00:15 +0100474 cmd->frame = NULL;
475 cmd->pa = 0;
Paolo Bonzini75f19f82016-09-16 00:36:58 +0200476 cmd->pa_size = 0;
Marc-André Lureau48285ba2018-08-14 16:12:46 +0200477 qemu_sglist_destroy(&cmd->qsg);
Hannes Reinecke6df57182014-10-29 13:00:15 +0100478 clear_bit(cmd->index, s->frame_map);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200479}
480
Hannes Reinecke6df57182014-10-29 13:00:15 +0100481/*
482 * This absolutely needs to be locked if
483 * qemu ever goes multithreaded.
484 */
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200485static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
Avi Kivitya8170e52012-10-23 12:30:10 +0200486 hwaddr frame, uint64_t context, int count)
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200487{
Paolo Bonzini1016b232014-06-13 17:26:13 +0200488 PCIDevice *pcid = PCI_DEVICE(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200489 MegasasCmd *cmd = NULL;
Peter Lieven2e56fbc2019-04-04 14:10:15 +0200490 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
Avi Kivitya8170e52012-10-23 12:30:10 +0200491 hwaddr frame_size_p = frame_size;
Hannes Reinecke6df57182014-10-29 13:00:15 +0100492 unsigned long index;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200493
Hannes Reinecke6df57182014-10-29 13:00:15 +0100494 index = 0;
495 while (index < s->fw_cmds) {
496 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
497 if (!s->frames[index].pa)
498 break;
499 /* Busy frame found */
500 trace_megasas_qf_mapped(index);
501 }
502 if (index >= s->fw_cmds) {
503 /* All frames busy */
504 trace_megasas_qf_busy(frame);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200505 return NULL;
506 }
Hannes Reinecke6df57182014-10-29 13:00:15 +0100507 cmd = &s->frames[index];
508 set_bit(index, s->frame_map);
509 trace_megasas_qf_new(index, frame);
510
511 cmd->pa = frame;
512 /* Map all possible frames */
513 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
Prasad J Panditfd691852020-05-14 00:55:39 +0530514 if (!cmd->frame || frame_size_p != frame_size) {
Hannes Reinecke6df57182014-10-29 13:00:15 +0100515 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
516 if (cmd->frame) {
517 megasas_unmap_frame(s, cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200518 }
Hannes Reinecke6df57182014-10-29 13:00:15 +0100519 s->event_count++;
520 return NULL;
521 }
522 cmd->pa_size = frame_size_p;
523 cmd->context = context;
524 if (!megasas_use_queue64(s)) {
525 cmd->context &= (uint64_t)0xFFFFFFFF;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200526 }
527 cmd->count = count;
Paolo Bonzini5104fac2017-06-01 17:18:23 +0200528 cmd->dcmd_opcode = -1;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200529 s->busy++;
530
Hannes Reineckeaaf2a852014-10-29 13:00:14 +0100531 if (s->consumer_pa) {
Philippe Mathieu-Daudé4a630542021-12-17 23:49:30 +0100532 ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail,
533 MEMTXATTRS_UNSPECIFIED);
Hannes Reineckeaaf2a852014-10-29 13:00:14 +0100534 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200535 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
Hannes Reineckeaaf2a852014-10-29 13:00:14 +0100536 s->reply_queue_head, s->reply_queue_tail, s->busy);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200537
538 return cmd;
539}
540
541static void megasas_complete_frame(MegasasState *s, uint64_t context)
542{
Philippe Mathieu-Daudéa423a1b2021-12-17 22:39:42 +0100543 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
Andreas Färber52190c12013-06-30 14:02:53 +0200544 PCIDevice *pci_dev = PCI_DEVICE(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200545 int tail, queue_offset;
546
547 /* Decrement busy count */
548 s->busy--;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200549 if (s->reply_queue_pa) {
550 /*
551 * Put command on the reply queue.
552 * Context is opaque, but emulation is running in
553 * little endian. So convert it.
554 */
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200555 if (megasas_use_queue64(s)) {
Hannes Reinecke7957ee72014-10-29 13:00:16 +0100556 queue_offset = s->reply_queue_head * sizeof(uint64_t);
Philippe Mathieu-Daudéa423a1b2021-12-17 22:39:42 +0100557 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset,
558 context, attrs);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200559 } else {
Hannes Reinecke7957ee72014-10-29 13:00:16 +0100560 queue_offset = s->reply_queue_head * sizeof(uint32_t);
Philippe Mathieu-Daudéa423a1b2021-12-17 22:39:42 +0100561 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset,
562 context, attrs);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200563 }
Philippe Mathieu-Daudé4a630542021-12-17 23:49:30 +0100564 ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attrs);
Hannes Reineckeaaf2a852014-10-29 13:00:14 +0100565 trace_megasas_qf_complete(context, s->reply_queue_head,
Hannes Reinecke7957ee72014-10-29 13:00:16 +0100566 s->reply_queue_tail, s->busy);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200567 }
568
569 if (megasas_intr_enabled(s)) {
Hannes Reinecke7957ee72014-10-29 13:00:16 +0100570 /* Update reply queue pointer */
Philippe Mathieu-Daudé4a630542021-12-17 23:49:30 +0100571 ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attrs);
Hannes Reinecke7957ee72014-10-29 13:00:16 +0100572 tail = s->reply_queue_head;
573 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
574 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
575 s->busy);
Philippe Mathieu-Daudéa423a1b2021-12-17 22:39:42 +0100576 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head, attrs);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200577 /* Notify HBA */
Hannes Reinecke7957ee72014-10-29 13:00:16 +0100578 if (msix_enabled(pci_dev)) {
579 trace_megasas_msix_raise(0);
580 msix_notify(pci_dev, 0);
581 } else if (msi_enabled(pci_dev)) {
582 trace_megasas_msi_raise(0);
583 msi_notify(pci_dev, 0);
584 } else {
585 s->doorbell++;
586 if (s->doorbell == 1) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200587 trace_megasas_irq_raise();
Marcel Apfelbaum9e64f8a2013-10-07 10:36:39 +0300588 pci_irq_assert(pci_dev);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200589 }
590 }
591 } else {
592 trace_megasas_qf_complete_noirq(context);
593 }
594}
595
Paolo Bonzini9e55d582016-11-10 16:27:51 +0100596static void megasas_complete_command(MegasasCmd *cmd)
597{
Paolo Bonzini9e55d582016-11-10 16:27:51 +0100598 cmd->iov_size = 0;
599 cmd->iov_offset = 0;
600
601 cmd->req->hba_private = NULL;
602 scsi_req_unref(cmd->req);
603 cmd->req = NULL;
604
605 megasas_unmap_frame(cmd->state, cmd);
606 megasas_complete_frame(cmd->state, cmd->context);
607}
608
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200609static void megasas_reset_frames(MegasasState *s)
610{
611 int i;
612 MegasasCmd *cmd;
613
614 for (i = 0; i < s->fw_cmds; i++) {
615 cmd = &s->frames[i];
616 if (cmd->pa) {
Hannes Reinecke6df57182014-10-29 13:00:15 +0100617 megasas_unmap_frame(s, cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200618 }
619 }
Hannes Reinecke6df57182014-10-29 13:00:15 +0100620 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200621}
622
623static void megasas_abort_command(MegasasCmd *cmd)
624{
Paolo Bonzini9e55d582016-11-10 16:27:51 +0100625 /* Never abort internal commands. */
Paolo Bonzini87e459a2017-06-01 17:26:14 +0200626 if (cmd->dcmd_opcode != -1) {
627 return;
628 }
Paolo Bonzini9e55d582016-11-10 16:27:51 +0100629 if (cmd->req != NULL) {
Paolo Bonzinie2b06052012-07-12 15:02:29 +0200630 scsi_req_cancel(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200631 }
632}
633
634static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
635{
Philippe Mathieu-Daudé398f9a82021-12-17 23:45:06 +0100636 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
Paolo Bonzini1016b232014-06-13 17:26:13 +0200637 PCIDevice *pcid = PCI_DEVICE(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200638 uint32_t pa_hi, pa_lo;
Hannes Reinecke96f8f232014-10-29 13:00:12 +0100639 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
640 struct mfi_init_qinfo *initq = NULL;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200641 uint32_t flags;
642 int ret = MFI_STAT_OK;
643
Hannes Reinecke96f8f232014-10-29 13:00:12 +0100644 if (s->reply_queue_pa) {
645 trace_megasas_initq_mapped(s->reply_queue_pa);
646 goto out;
647 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200648 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
649 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
650 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
651 trace_megasas_init_firmware((uint64_t)iq_pa);
Paolo Bonzini1016b232014-06-13 17:26:13 +0200652 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200653 if (!initq || initq_size != sizeof(*initq)) {
654 trace_megasas_initq_map_failed(cmd->index);
655 s->event_count++;
656 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
657 goto out;
658 }
659 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
660 if (s->reply_queue_len > s->fw_cmds) {
661 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
662 s->event_count++;
663 ret = MFI_STAT_INVALID_PARAMETER;
664 goto out;
665 }
666 pa_lo = le32_to_cpu(initq->rq_addr_lo);
667 pa_hi = le32_to_cpu(initq->rq_addr_hi);
668 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
669 pa_lo = le32_to_cpu(initq->ci_addr_lo);
670 pa_hi = le32_to_cpu(initq->ci_addr_hi);
671 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
672 pa_lo = le32_to_cpu(initq->pi_addr_lo);
673 pa_hi = le32_to_cpu(initq->pi_addr_hi);
674 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
Philippe Mathieu-Daudé4a630542021-12-17 23:49:30 +0100675 ldl_le_pci_dma(pcid, s->producer_pa, &s->reply_queue_head, attrs);
Prasad J Panditb60bdd12016-05-25 17:55:10 +0530676 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
Philippe Mathieu-Daudé4a630542021-12-17 23:49:30 +0100677 ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail, attrs);
Prasad J Panditb60bdd12016-05-25 17:55:10 +0530678 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200679 flags = le32_to_cpu(initq->flags);
680 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
681 s->flags |= MEGASAS_MASK_USE_QUEUE64;
682 }
683 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
684 s->reply_queue_len, s->reply_queue_head,
685 s->reply_queue_tail, flags);
686 megasas_reset_frames(s);
687 s->fw_state = MFI_FWSTATE_OPERATIONAL;
688out:
689 if (initq) {
Paolo Bonzini1016b232014-06-13 17:26:13 +0200690 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200691 }
692 return ret;
693}
694
695static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
696{
697 dma_addr_t iov_pa, iov_size;
Paolo Bonzini24c0c772017-06-01 17:18:57 +0200698 int iov_count;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200699
700 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
Paolo Bonzini24c0c772017-06-01 17:18:57 +0200701 iov_count = cmd->frame->header.sge_count;
702 if (!iov_count) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200703 trace_megasas_dcmd_zero_sge(cmd->index);
704 cmd->iov_size = 0;
705 return 0;
Paolo Bonzini24c0c772017-06-01 17:18:57 +0200706 } else if (iov_count > 1) {
707 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200708 cmd->iov_size = 0;
Paolo Bonzini765a7072017-01-02 11:03:33 +0100709 return -EINVAL;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200710 }
711 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
712 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
Andreas Färber52190c12013-06-30 14:02:53 +0200713 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200714 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
715 cmd->iov_size = iov_size;
Paolo Bonzini765a7072017-01-02 11:03:33 +0100716 return 0;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200717}
718
719static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
720{
721 trace_megasas_finish_dcmd(cmd->index, iov_size);
722
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200723 if (iov_size > cmd->iov_size) {
724 if (megasas_frame_is_ieee_sgl(cmd)) {
725 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
726 } else if (megasas_frame_is_sgl64(cmd)) {
727 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
728 } else {
729 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
730 }
731 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200732}
733
734static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
735{
Andreas Färber52190c12013-06-30 14:02:53 +0200736 PCIDevice *pci_dev = PCI_DEVICE(s);
Hannes Reineckee23d0492014-10-29 13:00:08 +0100737 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
Eduardo Habkost2e0aec12020-08-25 15:19:58 -0400738 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200739 struct mfi_ctrl_info info;
740 size_t dcmd_size = sizeof(info);
741 BusChild *kid;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100742 int num_pd_disks = 0;
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100743 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200744
P J P36fef362015-12-21 15:13:13 +0530745 memset(&info, 0x0, dcmd_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200746 if (cmd->iov_size < dcmd_size) {
747 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
748 dcmd_size);
749 return MFI_STAT_INVALID_PARAMETER;
750 }
751
Hannes Reineckee23d0492014-10-29 13:00:08 +0100752 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
753 info.pci.device = cpu_to_le16(pci_class->device_id);
754 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
755 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200756
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200757 /*
758 * For some reason the firmware supports
759 * only up to 8 device ports.
760 * Despite supporting a far larger number
761 * of devices for the physical devices.
762 * So just display the first 8 devices
763 * in the device port list, independent
764 * of how many logical devices are actually
765 * present.
766 */
767 info.host.type = MFI_INFO_HOST_PCIE;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200768 info.device.type = MFI_INFO_DEV_SAS3G;
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200769 info.device.port_count = 8;
770 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
Cao jine1dc6812016-01-06 17:37:46 +0800771 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100772 uint16_t pd_id;
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200773
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100774 if (num_pd_disks < 8) {
775 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
776 info.device.port_addr[num_pd_disks] =
777 cpu_to_le64(megasas_get_sata_addr(pd_id));
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200778 }
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100779 num_pd_disks++;
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200780 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200781
Hannes Reineckee23d0492014-10-29 13:00:08 +0100782 memcpy(info.product_name, base_class->product_name, 24);
Hannes Reineckefb654152012-08-24 12:36:41 +0200783 snprintf(info.serial_number, 32, "%s", s->hba_serial);
Eduardo Habkost69fbd0e2015-10-30 17:36:09 -0200784 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200785 memcpy(info.image_component[0].name, "APP", 3);
Hannes Reineckee23d0492014-10-29 13:00:08 +0100786 snprintf(info.image_component[0].version, 10, "%s-QEMU",
787 base_class->product_version);
Olaf Hering5a7733b2014-04-03 15:47:34 +0200788 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
789 memcpy(info.image_component[0].build_time, "12:34:56", 8);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200790 info.image_component_count = 1;
Andreas Färber52190c12013-06-30 14:02:53 +0200791 if (pci_dev->has_rom) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200792 uint8_t biosver[32];
793 uint8_t *ptr;
794
Andreas Färber52190c12013-06-30 14:02:53 +0200795 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200796 memcpy(biosver, ptr + 0x41, 31);
Prasad J Pandit844864f2016-06-07 16:44:03 +0530797 biosver[31] = 0;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200798 memcpy(info.image_component[1].name, "BIOS", 4);
799 memcpy(info.image_component[1].version, biosver,
800 strlen((const char *)biosver));
801 info.image_component_count++;
802 }
803 info.current_fw_time = cpu_to_le32(megasas_fw_time());
804 info.max_arms = 32;
805 info.max_spans = 8;
806 info.max_arrays = MEGASAS_MAX_ARRAYS;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100807 info.max_lds = MFI_MAX_LD;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200808 info.max_cmds = cpu_to_le16(s->fw_cmds);
809 info.max_sg_elements = cpu_to_le16(s->fw_sge);
810 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100811 if (!megasas_is_jbod(s))
812 info.lds_present = cpu_to_le16(num_pd_disks);
813 info.pd_present = cpu_to_le16(num_pd_disks);
814 info.pd_disks_present = cpu_to_le16(num_pd_disks);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200815 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
816 MFI_INFO_HW_MEM |
817 MFI_INFO_HW_FLASH);
818 info.memory_size = cpu_to_le16(512);
819 info.nvram_size = cpu_to_le16(32);
820 info.flash_size = cpu_to_le16(16);
821 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
822 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
823 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
824 MFI_INFO_AOPS_MIXED_ARRAY);
825 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
826 MFI_INFO_LDOPS_ACCESS_POLICY |
827 MFI_INFO_LDOPS_IO_POLICY |
828 MFI_INFO_LDOPS_WRITE_POLICY |
829 MFI_INFO_LDOPS_READ_POLICY);
830 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
831 info.stripe_sz_ops.min = 3;
Stefan Hajnoczi786a4ea2015-03-23 15:29:26 +0000832 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200833 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
834 info.properties.intr_throttle_cnt = cpu_to_le16(16);
835 info.properties.intr_throttle_timeout = cpu_to_le16(50);
836 info.properties.rebuild_rate = 30;
837 info.properties.patrol_read_rate = 30;
838 info.properties.bgi_rate = 30;
839 info.properties.cc_rate = 30;
840 info.properties.recon_rate = 30;
841 info.properties.cache_flush_interval = 4;
842 info.properties.spinup_drv_cnt = 2;
843 info.properties.spinup_delay = 6;
844 info.properties.ecc_bucket_size = 15;
845 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
846 info.properties.expose_encl_devices = 1;
847 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
848 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
849 MFI_INFO_PDOPS_FORCE_OFFLINE);
850 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
851 MFI_INFO_PDMIX_SATA |
852 MFI_INFO_PDMIX_LD);
853
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100854 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
855 MEMTXATTRS_UNSPECIFIED);
856 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200857 return MFI_STAT_OK;
858}
859
860static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
861{
862 struct mfi_defaults info;
863 size_t dcmd_size = sizeof(struct mfi_defaults);
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100864 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200865
866 memset(&info, 0x0, dcmd_size);
867 if (cmd->iov_size < dcmd_size) {
868 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
869 dcmd_size);
870 return MFI_STAT_INVALID_PARAMETER;
871 }
872
Hannes Reinecke76b523d2012-08-01 12:46:50 +0200873 info.sas_addr = cpu_to_le64(s->sas_addr);
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200874 info.stripe_size = 3;
875 info.flush_time = 4;
876 info.background_rate = 30;
877 info.allow_mix_in_enclosure = 1;
878 info.allow_mix_in_ld = 1;
879 info.direct_pd_mapping = 1;
880 /* Enable for BIOS support */
881 info.bios_enumerate_lds = 1;
882 info.disable_ctrl_r = 1;
883 info.expose_enclosure_devices = 1;
884 info.disable_preboot_cli = 1;
885 info.cluster_disable = 1;
886
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100887 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
888 MEMTXATTRS_UNSPECIFIED);
889 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200890 return MFI_STAT_OK;
891}
892
893static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
894{
895 struct mfi_bios_data info;
896 size_t dcmd_size = sizeof(info);
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100897 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200898
899 memset(&info, 0x0, dcmd_size);
900 if (cmd->iov_size < dcmd_size) {
901 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
902 dcmd_size);
903 return MFI_STAT_INVALID_PARAMETER;
904 }
905 info.continue_on_error = 1;
906 info.verbose = 1;
907 if (megasas_is_jbod(s)) {
908 info.expose_all_drives = 1;
909 }
910
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100911 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
912 MEMTXATTRS_UNSPECIFIED);
913 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200914 return MFI_STAT_OK;
915}
916
917static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
918{
919 uint64_t fw_time;
920 size_t dcmd_size = sizeof(fw_time);
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100921 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200922
923 fw_time = cpu_to_le64(megasas_fw_time());
924
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100925 dma_buf_read(&fw_time, dcmd_size, &residual, &cmd->qsg,
926 MEMTXATTRS_UNSPECIFIED);
927 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200928 return MFI_STAT_OK;
929}
930
931static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
932{
933 uint64_t fw_time;
934
935 /* This is a dummy; setting of firmware time is not allowed */
936 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
937
938 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
939 fw_time = cpu_to_le64(megasas_fw_time());
940 return MFI_STAT_OK;
941}
942
943static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
944{
945 struct mfi_evt_log_state info;
946 size_t dcmd_size = sizeof(info);
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100947 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200948
949 memset(&info, 0, dcmd_size);
950
951 info.newest_seq_num = cpu_to_le32(s->event_count);
952 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
953 info.boot_seq_num = cpu_to_le32(s->boot_event);
954
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100955 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
956 MEMTXATTRS_UNSPECIFIED);
957 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200958 return MFI_STAT_OK;
959}
960
961static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
962{
963 union mfi_evt event;
964
965 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
966 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
967 sizeof(struct mfi_evt_detail));
968 return MFI_STAT_INVALID_PARAMETER;
969 }
970 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
971 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
972 s->event_locale = event.members.locale;
973 s->event_class = event.members.class;
974 s->event_cmd = cmd;
975 /* Decrease busy count; event frame doesn't count here */
976 s->busy--;
977 cmd->iov_size = sizeof(struct mfi_evt_detail);
978 return MFI_STAT_INVALID_STATUS;
979}
980
981static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
982{
983 struct mfi_pd_list info;
984 size_t dcmd_size = sizeof(info);
985 BusChild *kid;
986 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +0100987 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +0200988
989 memset(&info, 0, dcmd_size);
990 offset = 8;
991 dcmd_limit = offset + sizeof(struct mfi_pd_address);
992 if (cmd->iov_size < dcmd_limit) {
993 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
994 dcmd_limit);
995 return MFI_STAT_INVALID_PARAMETER;
996 }
997
998 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +0100999 if (max_pd_disks > MFI_MAX_SYS_PDS) {
1000 max_pd_disks = MFI_MAX_SYS_PDS;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001001 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001002 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
Cao jine1dc6812016-01-06 17:37:46 +08001003 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001004 uint16_t pd_id;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001005
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001006 if (num_pd_disks >= max_pd_disks)
1007 break;
1008
1009 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1010 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001011 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
1012 info.addr[num_pd_disks].encl_index = 0;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001013 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001014 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
1015 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
1016 info.addr[num_pd_disks].sas_addr[0] =
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001017 cpu_to_le64(megasas_get_sata_addr(pd_id));
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001018 num_pd_disks++;
1019 offset += sizeof(struct mfi_pd_address);
1020 }
1021 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
1022 max_pd_disks, offset);
1023
1024 info.size = cpu_to_le32(offset);
1025 info.count = cpu_to_le32(num_pd_disks);
1026
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001027 dma_buf_read(&info, offset, &residual, &cmd->qsg,
1028 MEMTXATTRS_UNSPECIFIED);
1029 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001030 return MFI_STAT_OK;
1031}
1032
1033static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1034{
1035 uint16_t flags;
1036
1037 /* mbox0 contains flags */
1038 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1039 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1040 if (flags == MR_PD_QUERY_TYPE_ALL ||
1041 megasas_is_jbod(s)) {
1042 return megasas_dcmd_pd_get_list(s, cmd);
1043 }
1044
1045 return MFI_STAT_OK;
1046}
1047
1048static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1049 MegasasCmd *cmd)
1050{
1051 struct mfi_pd_info *info = cmd->iov_buf;
1052 size_t dcmd_size = sizeof(struct mfi_pd_info);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001053 uint64_t pd_size;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001054 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001055 uint8_t cmdbuf[6];
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001056 size_t len;
Philippe Mathieu-Daudébfa30f32021-12-31 11:33:29 +01001057 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001058
1059 if (!cmd->iov_buf) {
Markus Armbruster0bd0adb2014-12-04 14:12:44 +01001060 cmd->iov_buf = g_malloc0(dcmd_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001061 info = cmd->iov_buf;
1062 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1063 info->vpd_page83[0] = 0x7f;
1064 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
John Millikinfe9d8922022-08-17 14:34:58 +09001065 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, sizeof(cmdbuf), cmd);
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001066 if (!cmd->req) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001067 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1068 "PD get info std inquiry");
1069 g_free(cmd->iov_buf);
1070 cmd->iov_buf = NULL;
1071 return MFI_STAT_FLASH_ALLOC_FAIL;
1072 }
1073 trace_megasas_dcmd_internal_submit(cmd->index,
1074 "PD get info std inquiry", lun);
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001075 len = scsi_req_enqueue(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001076 if (len > 0) {
1077 cmd->iov_size = len;
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001078 scsi_req_continue(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001079 }
1080 return MFI_STAT_INVALID_STATUS;
1081 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1082 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
John Millikinfe9d8922022-08-17 14:34:58 +09001083 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, sizeof(cmdbuf), cmd);
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001084 if (!cmd->req) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001085 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1086 "PD get info vpd inquiry");
1087 return MFI_STAT_FLASH_ALLOC_FAIL;
1088 }
1089 trace_megasas_dcmd_internal_submit(cmd->index,
1090 "PD get info vpd inquiry", lun);
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001091 len = scsi_req_enqueue(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001092 if (len > 0) {
1093 cmd->iov_size = len;
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001094 scsi_req_continue(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001095 }
1096 return MFI_STAT_INVALID_STATUS;
1097 }
1098 /* Finished, set FW state */
1099 if ((info->inquiry_data[0] >> 5) == 0) {
1100 if (megasas_is_jbod(cmd->state)) {
1101 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1102 } else {
1103 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1104 }
1105 } else {
1106 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1107 }
1108
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001109 info->ref.v.device_id = cpu_to_le16(pd_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001110 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1111 MFI_PD_DDF_TYPE_INTF_SAS);
Markus Armbruster4be74632014-10-07 13:59:18 +02001112 blk_get_geometry(sdev->conf.blk, &pd_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001113 info->raw_size = cpu_to_le64(pd_size);
1114 info->non_coerced_size = cpu_to_le64(pd_size);
1115 info->coerced_size = cpu_to_le64(pd_size);
1116 info->encl_device_id = 0xFFFF;
1117 info->slot_number = (sdev->id & 0xFF);
1118 info->path_info.count = 1;
1119 info->path_info.sas_addr[0] =
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001120 cpu_to_le64(megasas_get_sata_addr(pd_id));
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001121 info->connected_port_bitmap = 0x1;
1122 info->device_speed = 1;
1123 info->link_speed = 1;
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001124 dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
1125 MEMTXATTRS_UNSPECIFIED);
1126 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001127 g_free(cmd->iov_buf);
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001128 cmd->iov_size = dcmd_size - residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001129 cmd->iov_buf = NULL;
1130 return MFI_STAT_OK;
1131}
1132
1133static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1134{
1135 size_t dcmd_size = sizeof(struct mfi_pd_info);
1136 uint16_t pd_id;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001137 uint8_t target_id, lun_id;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001138 SCSIDevice *sdev = NULL;
1139 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1140
1141 if (cmd->iov_size < dcmd_size) {
1142 return MFI_STAT_INVALID_PARAMETER;
1143 }
1144
1145 /* mbox0 has the ID */
1146 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001147 target_id = (pd_id >> 8) & 0xFF;
1148 lun_id = pd_id & 0xFF;
1149 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001150 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1151
1152 if (sdev) {
1153 /* Submit inquiry */
1154 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1155 }
1156
1157 return retval;
1158}
1159
1160static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1161{
1162 struct mfi_ld_list info;
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001163 size_t dcmd_size = sizeof(info);
Philippe Mathieu-Daudébfa30f32021-12-31 11:33:29 +01001164 dma_addr_t residual;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001165 uint32_t num_ld_disks = 0, max_ld_disks;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001166 uint64_t ld_size;
1167 BusChild *kid;
1168
1169 memset(&info, 0, dcmd_size);
Hannes Reineckee74a4312014-10-29 13:00:09 +01001170 if (cmd->iov_size > dcmd_size) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001171 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1172 dcmd_size);
1173 return MFI_STAT_INVALID_PARAMETER;
1174 }
1175
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001176 max_ld_disks = (cmd->iov_size - 8) / 16;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001177 if (megasas_is_jbod(s)) {
1178 max_ld_disks = 0;
1179 }
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001180 if (max_ld_disks > MFI_MAX_LD) {
1181 max_ld_disks = MFI_MAX_LD;
1182 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001183 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
Cao jine1dc6812016-01-06 17:37:46 +08001184 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001185
1186 if (num_ld_disks >= max_ld_disks) {
1187 break;
1188 }
1189 /* Logical device size is in blocks */
Markus Armbruster4be74632014-10-07 13:59:18 +02001190 blk_get_geometry(sdev->conf.blk, &ld_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001191 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1192 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1193 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1194 num_ld_disks++;
1195 }
1196 info.ld_count = cpu_to_le32(num_ld_disks);
1197 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1198
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001199 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1200 MEMTXATTRS_UNSPECIFIED);
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001201 cmd->iov_size = dcmd_size - residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001202 return MFI_STAT_OK;
1203}
1204
Hannes Reinecke34bb4d02014-04-16 16:44:13 +02001205static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1206{
1207 uint16_t flags;
Hannes Reinecked97ae362014-10-29 13:00:05 +01001208 struct mfi_ld_targetid_list info;
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001209 size_t dcmd_size = sizeof(info);
Philippe Mathieu-Daudébfa30f32021-12-31 11:33:29 +01001210 dma_addr_t residual;
Hannes Reinecked97ae362014-10-29 13:00:05 +01001211 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1212 BusChild *kid;
Hannes Reinecke34bb4d02014-04-16 16:44:13 +02001213
1214 /* mbox0 contains flags */
1215 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1216 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
Hannes Reinecked97ae362014-10-29 13:00:05 +01001217 if (flags != MR_LD_QUERY_TYPE_ALL &&
1218 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1219 max_ld_disks = 0;
Hannes Reinecke34bb4d02014-04-16 16:44:13 +02001220 }
1221
Hannes Reinecked97ae362014-10-29 13:00:05 +01001222 memset(&info, 0, dcmd_size);
1223 if (cmd->iov_size < 12) {
1224 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1225 dcmd_size);
1226 return MFI_STAT_INVALID_PARAMETER;
1227 }
1228 dcmd_size = sizeof(uint32_t) * 2 + 3;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001229 max_ld_disks = cmd->iov_size - dcmd_size;
Hannes Reinecked97ae362014-10-29 13:00:05 +01001230 if (megasas_is_jbod(s)) {
1231 max_ld_disks = 0;
1232 }
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001233 if (max_ld_disks > MFI_MAX_LD) {
1234 max_ld_disks = MFI_MAX_LD;
1235 }
Hannes Reinecked97ae362014-10-29 13:00:05 +01001236 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
Cao jine1dc6812016-01-06 17:37:46 +08001237 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
Hannes Reinecked97ae362014-10-29 13:00:05 +01001238
1239 if (num_ld_disks >= max_ld_disks) {
1240 break;
1241 }
1242 info.targetid[num_ld_disks] = sdev->lun;
1243 num_ld_disks++;
1244 dcmd_size++;
1245 }
1246 info.ld_count = cpu_to_le32(num_ld_disks);
1247 info.size = dcmd_size;
1248 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1249
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001250 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1251 MEMTXATTRS_UNSPECIFIED);
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001252 cmd->iov_size = dcmd_size - residual;
Hannes Reinecke34bb4d02014-04-16 16:44:13 +02001253 return MFI_STAT_OK;
1254}
1255
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001256static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1257 MegasasCmd *cmd)
1258{
1259 struct mfi_ld_info *info = cmd->iov_buf;
1260 size_t dcmd_size = sizeof(struct mfi_ld_info);
1261 uint8_t cdb[6];
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001262 ssize_t len;
Philippe Mathieu-Daudébfa30f32021-12-31 11:33:29 +01001263 dma_addr_t residual;
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001264 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001265 uint64_t ld_size;
1266
1267 if (!cmd->iov_buf) {
Markus Armbruster0bd0adb2014-12-04 14:12:44 +01001268 cmd->iov_buf = g_malloc0(dcmd_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001269 info = cmd->iov_buf;
1270 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
John Millikinfe9d8922022-08-17 14:34:58 +09001271 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, sizeof(cdb), cmd);
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001272 if (!cmd->req) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001273 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1274 "LD get info vpd inquiry");
1275 g_free(cmd->iov_buf);
1276 cmd->iov_buf = NULL;
1277 return MFI_STAT_FLASH_ALLOC_FAIL;
1278 }
1279 trace_megasas_dcmd_internal_submit(cmd->index,
1280 "LD get info vpd inquiry", lun);
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001281 len = scsi_req_enqueue(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001282 if (len > 0) {
1283 cmd->iov_size = len;
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001284 scsi_req_continue(cmd->req);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001285 }
1286 return MFI_STAT_INVALID_STATUS;
1287 }
1288
1289 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1290 info->ld_config.properties.ld.v.target_id = lun;
1291 info->ld_config.params.stripe_size = 3;
1292 info->ld_config.params.num_drives = 1;
1293 info->ld_config.params.is_consistent = 1;
1294 /* Logical device size is in blocks */
Markus Armbruster4be74632014-10-07 13:59:18 +02001295 blk_get_geometry(sdev->conf.blk, &ld_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001296 info->size = cpu_to_le64(ld_size);
1297 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1298 info->ld_config.span[0].start_block = 0;
1299 info->ld_config.span[0].num_blocks = info->size;
1300 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1301
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001302 dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
1303 MEMTXATTRS_UNSPECIFIED);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001304 g_free(cmd->iov_buf);
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001305 cmd->iov_size = dcmd_size - residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001306 cmd->iov_buf = NULL;
1307 return MFI_STAT_OK;
1308}
1309
1310static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1311{
1312 struct mfi_ld_info info;
1313 size_t dcmd_size = sizeof(info);
1314 uint16_t ld_id;
1315 uint32_t max_ld_disks = s->fw_luns;
1316 SCSIDevice *sdev = NULL;
1317 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1318
1319 if (cmd->iov_size < dcmd_size) {
1320 return MFI_STAT_INVALID_PARAMETER;
1321 }
1322
1323 /* mbox0 has the ID */
1324 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1325 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1326
1327 if (megasas_is_jbod(s)) {
1328 return MFI_STAT_DEVICE_NOT_FOUND;
1329 }
1330
1331 if (ld_id < max_ld_disks) {
1332 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1333 }
1334
1335 if (sdev) {
1336 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1337 }
1338
1339 return retval;
1340}
1341
1342static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1343{
Prasad J Panditd37af742016-05-25 17:41:44 +05301344 uint8_t data[4096] = { 0 };
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001345 struct mfi_config_data *info;
1346 int num_pd_disks = 0, array_offset, ld_offset;
1347 BusChild *kid;
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001348 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001349
1350 if (cmd->iov_size > 4096) {
1351 return MFI_STAT_INVALID_PARAMETER;
1352 }
1353
1354 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1355 num_pd_disks++;
1356 }
1357 info = (struct mfi_config_data *)&data;
1358 /*
1359 * Array mapping:
1360 * - One array per SCSI device
1361 * - One logical drive per SCSI device
1362 * spanning the entire device
1363 */
1364 info->array_count = num_pd_disks;
1365 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1366 info->log_drv_count = num_pd_disks;
1367 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1368 info->spares_count = 0;
1369 info->spares_size = sizeof(struct mfi_spare);
1370 info->size = sizeof(struct mfi_config_data) + info->array_size +
1371 info->log_drv_size;
1372 if (info->size > 4096) {
1373 return MFI_STAT_INVALID_PARAMETER;
1374 }
1375
1376 array_offset = sizeof(struct mfi_config_data);
1377 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1378
1379 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
Cao jine1dc6812016-01-06 17:37:46 +08001380 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001381 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001382 struct mfi_array *array;
1383 struct mfi_ld_config *ld;
1384 uint64_t pd_size;
1385 int i;
1386
1387 array = (struct mfi_array *)(data + array_offset);
Markus Armbruster4be74632014-10-07 13:59:18 +02001388 blk_get_geometry(sdev->conf.blk, &pd_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001389 array->size = cpu_to_le64(pd_size);
1390 array->num_drives = 1;
1391 array->array_ref = cpu_to_le16(sdev_id);
1392 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1393 array->pd[0].ref.v.seq_num = 0;
1394 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1395 array->pd[0].encl.pd = 0xFF;
1396 array->pd[0].encl.slot = (sdev->id & 0xFF);
1397 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1398 array->pd[i].ref.v.device_id = 0xFFFF;
1399 array->pd[i].ref.v.seq_num = 0;
1400 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1401 array->pd[i].encl.pd = 0xFF;
1402 array->pd[i].encl.slot = 0xFF;
1403 }
1404 array_offset += sizeof(struct mfi_array);
1405 ld = (struct mfi_ld_config *)(data + ld_offset);
1406 memset(ld, 0, sizeof(struct mfi_ld_config));
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001407 ld->properties.ld.v.target_id = sdev->id;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001408 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1409 MR_LD_CACHE_READ_ADAPTIVE;
1410 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1411 MR_LD_CACHE_READ_ADAPTIVE;
1412 ld->params.state = MFI_LD_STATE_OPTIMAL;
1413 ld->params.stripe_size = 3;
1414 ld->params.num_drives = 1;
1415 ld->params.span_depth = 1;
1416 ld->params.is_consistent = 1;
1417 ld->span[0].start_block = 0;
1418 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1419 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1420 ld_offset += sizeof(struct mfi_ld_config);
1421 }
1422
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001423 dma_buf_read(data, info->size, &residual, &cmd->qsg,
1424 MEMTXATTRS_UNSPECIFIED);
1425 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001426 return MFI_STAT_OK;
1427}
1428
1429static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1430{
1431 struct mfi_ctrl_props info;
1432 size_t dcmd_size = sizeof(info);
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001433 dma_addr_t residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001434
1435 memset(&info, 0x0, dcmd_size);
1436 if (cmd->iov_size < dcmd_size) {
1437 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1438 dcmd_size);
1439 return MFI_STAT_INVALID_PARAMETER;
1440 }
1441 info.pred_fail_poll_interval = cpu_to_le16(300);
1442 info.intr_throttle_cnt = cpu_to_le16(16);
1443 info.intr_throttle_timeout = cpu_to_le16(50);
1444 info.rebuild_rate = 30;
1445 info.patrol_read_rate = 30;
1446 info.bgi_rate = 30;
1447 info.cc_rate = 30;
1448 info.recon_rate = 30;
1449 info.cache_flush_interval = 4;
1450 info.spinup_drv_cnt = 2;
1451 info.spinup_delay = 6;
1452 info.ecc_bucket_size = 15;
1453 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1454 info.expose_encl_devices = 1;
1455
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001456 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1457 MEMTXATTRS_UNSPECIFIED);
1458 cmd->iov_size -= residual;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001459 return MFI_STAT_OK;
1460}
1461
1462static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1463{
Markus Armbruster4be74632014-10-07 13:59:18 +02001464 blk_drain_all();
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001465 return MFI_STAT_OK;
1466}
1467
1468static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1469{
1470 s->fw_state = MFI_FWSTATE_READY;
1471 return MFI_STAT_OK;
1472}
1473
Hannes Reinecke200b6962014-10-29 13:00:13 +01001474/* Some implementations use CLUSTER RESET LD to simulate a device reset */
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001475static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1476{
Hannes Reinecke200b6962014-10-29 13:00:13 +01001477 uint16_t target_id;
1478 int i;
1479
1480 /* mbox0 contains the device index */
1481 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1482 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1483 for (i = 0; i < s->fw_cmds; i++) {
1484 MegasasCmd *tmp_cmd = &s->frames[i];
1485 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1486 SCSIDevice *d = tmp_cmd->req->dev;
Peter Maydell4a5fc892022-10-13 17:06:22 +01001487 device_cold_reset(&d->qdev);
Hannes Reinecke200b6962014-10-29 13:00:13 +01001488 }
1489 }
1490 return MFI_STAT_OK;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001491}
1492
1493static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1494{
Hannes Reinecke10d65302012-07-11 13:35:16 +02001495 struct mfi_ctrl_props info;
1496 size_t dcmd_size = sizeof(info);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001497
Hannes Reinecke10d65302012-07-11 13:35:16 +02001498 if (cmd->iov_size < dcmd_size) {
1499 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1500 dcmd_size);
1501 return MFI_STAT_INVALID_PARAMETER;
1502 }
Philippe Mathieu-Daudéf02b6642021-12-16 09:36:38 +01001503 dma_buf_write(&info, dcmd_size, NULL, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
Hannes Reinecke10d65302012-07-11 13:35:16 +02001504 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001505 return MFI_STAT_OK;
1506}
1507
1508static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1509{
1510 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1511 return MFI_STAT_OK;
1512}
1513
1514static const struct dcmd_cmd_tbl_t {
1515 int opcode;
1516 const char *desc;
1517 int (*func)(MegasasState *s, MegasasCmd *cmd);
1518} dcmd_cmd_tbl[] = {
1519 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1520 megasas_dcmd_dummy },
1521 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1522 megasas_ctrl_get_info },
1523 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1524 megasas_dcmd_get_properties },
1525 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1526 megasas_dcmd_set_properties },
1527 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1528 megasas_dcmd_dummy },
1529 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1530 megasas_dcmd_dummy },
1531 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1532 megasas_dcmd_dummy },
1533 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1534 megasas_dcmd_dummy },
1535 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1536 megasas_dcmd_dummy },
1537 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1538 megasas_event_info },
1539 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1540 megasas_dcmd_dummy },
1541 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1542 megasas_event_wait },
1543 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1544 megasas_ctrl_shutdown },
1545 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1546 megasas_dcmd_dummy },
1547 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1548 megasas_dcmd_get_fw_time },
1549 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1550 megasas_dcmd_set_fw_time },
1551 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1552 megasas_dcmd_get_bios_info },
1553 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1554 megasas_dcmd_dummy },
1555 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1556 megasas_mfc_get_defaults },
1557 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1558 megasas_dcmd_dummy },
1559 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1560 megasas_cache_flush },
1561 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1562 megasas_dcmd_pd_get_list },
1563 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1564 megasas_dcmd_pd_list_query },
1565 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1566 megasas_dcmd_pd_get_info },
1567 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1568 megasas_dcmd_dummy },
1569 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1570 megasas_dcmd_dummy },
1571 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1572 megasas_dcmd_dummy },
1573 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1574 megasas_dcmd_dummy },
1575 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1576 megasas_dcmd_ld_get_list},
Hannes Reinecke34bb4d02014-04-16 16:44:13 +02001577 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1578 megasas_dcmd_ld_list_query },
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001579 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1580 megasas_dcmd_ld_get_info },
1581 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1582 megasas_dcmd_dummy },
1583 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1584 megasas_dcmd_dummy },
1585 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1586 megasas_dcmd_dummy },
1587 { MFI_DCMD_CFG_READ, "CFG_READ",
1588 megasas_dcmd_cfg_read },
1589 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1590 megasas_dcmd_dummy },
1591 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1592 megasas_dcmd_dummy },
1593 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1594 megasas_dcmd_dummy },
1595 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1596 megasas_dcmd_dummy },
1597 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1598 megasas_dcmd_dummy },
1599 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1600 megasas_dcmd_dummy },
1601 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1602 megasas_dcmd_dummy },
1603 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1604 megasas_dcmd_dummy },
1605 { MFI_DCMD_CLUSTER, "CLUSTER",
1606 megasas_dcmd_dummy },
1607 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1608 megasas_dcmd_dummy },
1609 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1610 megasas_cluster_reset_ld },
1611 { -1, NULL, NULL }
1612};
1613
1614static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1615{
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001616 int retval = 0;
Paolo Bonzini765a7072017-01-02 11:03:33 +01001617 size_t len;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001618 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1619
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001620 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1621 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
Paolo Bonzini765a7072017-01-02 11:03:33 +01001622 if (megasas_map_dcmd(s, cmd) < 0) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001623 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1624 }
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001625 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001626 cmdptr++;
1627 }
Paolo Bonzini765a7072017-01-02 11:03:33 +01001628 len = cmd->iov_size;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001629 if (cmdptr->opcode == -1) {
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001630 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001631 retval = megasas_dcmd_dummy(s, cmd);
1632 } else {
1633 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1634 retval = cmdptr->func(s, cmd);
1635 }
1636 if (retval != MFI_STAT_INVALID_STATUS) {
1637 megasas_finish_dcmd(cmd, len);
1638 }
1639 return retval;
1640}
1641
1642static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
Philippe Mathieu-Daudébfa30f32021-12-31 11:33:29 +01001643 SCSIRequest *req, dma_addr_t residual)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001644{
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001645 int retval = MFI_STAT_OK;
1646 int lun = req->lun;
1647
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001648 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001649 cmd->iov_size -= residual;
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001650 switch (cmd->dcmd_opcode) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001651 case MFI_DCMD_PD_GET_INFO:
1652 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1653 break;
1654 case MFI_DCMD_LD_GET_INFO:
1655 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1656 break;
1657 default:
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001658 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001659 retval = MFI_STAT_INVALID_DCMD;
1660 break;
1661 }
1662 if (retval != MFI_STAT_INVALID_STATUS) {
1663 megasas_finish_dcmd(cmd, cmd->iov_size);
1664 }
1665 return retval;
1666}
1667
1668static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1669{
1670 int len;
1671
1672 len = scsi_req_enqueue(cmd->req);
1673 if (len < 0) {
1674 len = -len;
1675 }
1676 if (len > 0) {
1677 if (len > cmd->iov_size) {
1678 if (is_write) {
1679 trace_megasas_iov_write_overflow(cmd->index, len,
1680 cmd->iov_size);
1681 } else {
1682 trace_megasas_iov_read_overflow(cmd->index, len,
1683 cmd->iov_size);
1684 }
1685 }
1686 if (len < cmd->iov_size) {
1687 if (is_write) {
1688 trace_megasas_iov_write_underflow(cmd->index, len,
1689 cmd->iov_size);
1690 } else {
1691 trace_megasas_iov_read_underflow(cmd->index, len,
1692 cmd->iov_size);
1693 }
1694 cmd->iov_size = len;
1695 }
1696 scsi_req_continue(cmd->req);
1697 }
1698 return len;
1699}
1700
1701static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001702 int frame_cmd)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001703{
1704 uint8_t *cdb;
Paolo Bonzinib3568072017-06-01 17:25:03 +02001705 int target_id, lun_id, cdb_len;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001706 bool is_write;
1707 struct SCSIDevice *sdev = NULL;
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001708 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001709
1710 cdb = cmd->frame->pass.cdb;
Paolo Bonzinib3568072017-06-01 17:25:03 +02001711 target_id = cmd->frame->header.target_id;
1712 lun_id = cmd->frame->header.lun_id;
1713 cdb_len = cmd->frame->header.cdb_len;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001714
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001715 if (is_logical) {
Paolo Bonzinib3568072017-06-01 17:25:03 +02001716 if (target_id >= MFI_MAX_LD || lun_id != 0) {
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001717 trace_megasas_scsi_target_not_present(
Thomas Huthee760ac2020-06-15 09:26:29 +02001718 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001719 return MFI_STAT_DEVICE_NOT_FOUND;
1720 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001721 }
Paolo Bonzinib3568072017-06-01 17:25:03 +02001722 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01001723
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001724 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
Thomas Huthee760ac2020-06-15 09:26:29 +02001725 trace_megasas_handle_scsi(mfi_frame_desc(frame_cmd), is_logical,
Paolo Bonzinib3568072017-06-01 17:25:03 +02001726 target_id, lun_id, sdev, cmd->iov_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001727
1728 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1729 trace_megasas_scsi_target_not_present(
Thomas Huthee760ac2020-06-15 09:26:29 +02001730 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001731 return MFI_STAT_DEVICE_NOT_FOUND;
1732 }
1733
Paolo Bonzinib3568072017-06-01 17:25:03 +02001734 if (cdb_len > 16) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001735 trace_megasas_scsi_invalid_cdb_len(
Thomas Huthee760ac2020-06-15 09:26:29 +02001736 mfi_frame_desc(frame_cmd), is_logical,
Paolo Bonzinib3568072017-06-01 17:25:03 +02001737 target_id, lun_id, cdb_len);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001738 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1739 cmd->frame->header.scsi_status = CHECK_CONDITION;
1740 s->event_count++;
1741 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1742 }
1743
1744 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1745 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1746 cmd->frame->header.scsi_status = CHECK_CONDITION;
1747 s->event_count++;
1748 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1749 }
1750
John Millikinfe9d8922022-08-17 14:34:58 +09001751 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cdb_len, cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001752 if (!cmd->req) {
1753 trace_megasas_scsi_req_alloc_failed(
Thomas Huthee760ac2020-06-15 09:26:29 +02001754 mfi_frame_desc(frame_cmd), target_id, lun_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001755 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1756 cmd->frame->header.scsi_status = BUSY;
1757 s->event_count++;
1758 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1759 }
1760
1761 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
Hannes Reineckeaaf2a852014-10-29 13:00:14 +01001762 if (cmd->iov_size) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001763 if (is_write) {
Hannes Reineckeaaf2a852014-10-29 13:00:14 +01001764 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001765 } else {
Hannes Reineckeaaf2a852014-10-29 13:00:14 +01001766 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001767 }
1768 } else {
1769 trace_megasas_scsi_nodata(cmd->index);
1770 }
Hannes Reineckeaaf2a852014-10-29 13:00:14 +01001771 megasas_enqueue_req(cmd, is_write);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001772 return MFI_STAT_INVALID_STATUS;
1773}
1774
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001775static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001776{
1777 uint32_t lba_count, lba_start_hi, lba_start_lo;
1778 uint64_t lba_start;
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001779 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001780 uint8_t cdb[16];
1781 int len;
1782 struct SCSIDevice *sdev = NULL;
Paolo Bonzinib3568072017-06-01 17:25:03 +02001783 int target_id, lun_id, cdb_len;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001784
1785 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1786 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1787 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1788 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1789
Paolo Bonzinib3568072017-06-01 17:25:03 +02001790 target_id = cmd->frame->header.target_id;
1791 lun_id = cmd->frame->header.lun_id;
1792 cdb_len = cmd->frame->header.cdb_len;
1793
1794 if (target_id < MFI_MAX_LD && lun_id == 0) {
1795 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001796 }
1797
1798 trace_megasas_handle_io(cmd->index,
Thomas Huthee760ac2020-06-15 09:26:29 +02001799 mfi_frame_desc(frame_cmd), target_id, lun_id,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001800 (unsigned long)lba_start, (unsigned long)lba_count);
1801 if (!sdev) {
1802 trace_megasas_io_target_not_present(cmd->index,
Thomas Huthee760ac2020-06-15 09:26:29 +02001803 mfi_frame_desc(frame_cmd), target_id, lun_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001804 return MFI_STAT_DEVICE_NOT_FOUND;
1805 }
1806
Paolo Bonzinib3568072017-06-01 17:25:03 +02001807 if (cdb_len > 16) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001808 trace_megasas_scsi_invalid_cdb_len(
Thomas Huthee760ac2020-06-15 09:26:29 +02001809 mfi_frame_desc(frame_cmd), 1, target_id, lun_id, cdb_len);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001810 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1811 cmd->frame->header.scsi_status = CHECK_CONDITION;
1812 s->event_count++;
1813 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1814 }
1815
1816 cmd->iov_size = lba_count * sdev->blocksize;
1817 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1818 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1819 cmd->frame->header.scsi_status = CHECK_CONDITION;
1820 s->event_count++;
1821 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1822 }
1823
1824 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1825 cmd->req = scsi_req_new(sdev, cmd->index,
John Millikinfe9d8922022-08-17 14:34:58 +09001826 lun_id, cdb, cdb_len, cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001827 if (!cmd->req) {
1828 trace_megasas_scsi_req_alloc_failed(
Thomas Huthee760ac2020-06-15 09:26:29 +02001829 mfi_frame_desc(frame_cmd), target_id, lun_id);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001830 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1831 cmd->frame->header.scsi_status = BUSY;
1832 s->event_count++;
1833 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1834 }
1835 len = megasas_enqueue_req(cmd, is_write);
1836 if (len > 0) {
1837 if (is_write) {
1838 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1839 } else {
1840 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1841 }
1842 }
1843 return MFI_STAT_INVALID_STATUS;
1844}
1845
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001846static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1847{
1848 MegasasCmd *cmd = req->hba_private;
1849
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001850 if (cmd->dcmd_opcode != -1) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001851 return NULL;
1852 } else {
1853 return &cmd->qsg;
1854 }
1855}
1856
1857static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1858{
1859 MegasasCmd *cmd = req->hba_private;
1860 uint8_t *buf;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001861
1862 trace_megasas_io_complete(cmd->index, len);
1863
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001864 if (cmd->dcmd_opcode != -1) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001865 scsi_req_continue(req);
1866 return;
1867 }
1868
1869 buf = scsi_req_get_buf(req);
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001870 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001871 struct mfi_pd_info *info = cmd->iov_buf;
1872
1873 if (info->inquiry_data[0] == 0x7f) {
1874 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1875 memcpy(info->inquiry_data, buf, len);
1876 } else if (info->vpd_page83[0] == 0x7f) {
1877 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1878 memcpy(info->vpd_page83, buf, len);
1879 }
1880 scsi_req_continue(req);
Paolo Bonzini5104fac2017-06-01 17:18:23 +02001881 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001882 struct mfi_ld_info *info = cmd->iov_buf;
1883
1884 if (cmd->iov_buf) {
1885 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1886 scsi_req_continue(req);
1887 }
1888 }
1889}
1890
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001891static void megasas_command_complete(SCSIRequest *req, size_t residual)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001892{
1893 MegasasCmd *cmd = req->hba_private;
1894 uint8_t cmd_status = MFI_STAT_OK;
1895
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001896 trace_megasas_command_complete(cmd->index, req->status, residual);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001897
Paolo Bonzini9e55d582016-11-10 16:27:51 +01001898 if (req->io_canceled) {
1899 return;
1900 }
1901
Paolo Bonzini87e459a2017-06-01 17:26:14 +02001902 if (cmd->dcmd_opcode != -1) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001903 /*
1904 * Internal command complete
1905 */
Philippe Mathieu-Daudé5f412602021-12-31 11:13:34 +01001906 cmd_status = megasas_finish_internal_dcmd(cmd, req, residual);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001907 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1908 return;
1909 }
1910 } else {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001911 trace_megasas_scsi_complete(cmd->index, req->status,
1912 cmd->iov_size, req->cmd.xfer);
1913 if (req->status != GOOD) {
1914 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1915 }
1916 if (req->status == CHECK_CONDITION) {
1917 megasas_copy_sense(cmd);
1918 }
1919
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001920 cmd->frame->header.scsi_status = req->status;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001921 }
1922 cmd->frame->header.cmd_status = cmd_status;
Paolo Bonzini9e55d582016-11-10 16:27:51 +01001923 megasas_complete_command(cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001924}
1925
Paolo Bonzini9e55d582016-11-10 16:27:51 +01001926static void megasas_command_cancelled(SCSIRequest *req)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001927{
1928 MegasasCmd *cmd = req->hba_private;
1929
Paolo Bonzini9e55d582016-11-10 16:27:51 +01001930 if (!cmd) {
1931 return;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001932 }
Paolo Bonzini9e55d582016-11-10 16:27:51 +01001933 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1934 megasas_complete_command(cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001935}
1936
1937static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1938{
1939 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
Avi Kivitya8170e52012-10-23 12:30:10 +02001940 hwaddr abort_addr, addr_hi, addr_lo;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001941 MegasasCmd *abort_cmd;
1942
1943 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1944 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1945 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1946
1947 abort_cmd = megasas_lookup_frame(s, abort_addr);
1948 if (!abort_cmd) {
1949 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1950 s->event_count++;
1951 return MFI_STAT_OK;
1952 }
1953 if (!megasas_use_queue64(s)) {
1954 abort_ctx &= (uint64_t)0xFFFFFFFF;
1955 }
1956 if (abort_cmd->context != abort_ctx) {
Eric Blaked17e7442017-03-13 14:55:19 -05001957 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1958 abort_cmd->index);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001959 s->event_count++;
1960 return MFI_STAT_ABORT_NOT_POSSIBLE;
1961 }
1962 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1963 megasas_abort_command(abort_cmd);
1964 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1965 s->event_cmd = NULL;
1966 }
1967 s->event_count++;
1968 return MFI_STAT_OK;
1969}
1970
1971static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1972 uint32_t frame_count)
1973{
1974 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1975 uint64_t frame_context;
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001976 int frame_cmd;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001977 MegasasCmd *cmd;
1978
1979 /*
1980 * Always read 64bit context, top bits will be
1981 * masked out if required in megasas_enqueue_frame()
1982 */
Paolo Bonzini16578c62015-03-23 17:15:17 +01001983 frame_context = megasas_frame_get_context(s, frame_addr);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001984
1985 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1986 if (!cmd) {
1987 /* reply queue full */
1988 trace_megasas_frame_busy(frame_addr);
Paolo Bonzini16578c62015-03-23 17:15:17 +01001989 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1990 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001991 megasas_complete_frame(s, frame_context);
1992 s->event_count++;
1993 return;
1994 }
Paolo Bonzini36c327a2017-06-01 17:23:13 +02001995 frame_cmd = cmd->frame->header.frame_cmd;
1996 switch (frame_cmd) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02001997 case MFI_CMD_INIT:
1998 frame_status = megasas_init_firmware(s, cmd);
1999 break;
2000 case MFI_CMD_DCMD:
2001 frame_status = megasas_handle_dcmd(s, cmd);
2002 break;
2003 case MFI_CMD_ABORT:
2004 frame_status = megasas_handle_abort(s, cmd);
2005 break;
2006 case MFI_CMD_PD_SCSI_IO:
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002007 case MFI_CMD_LD_SCSI_IO:
Paolo Bonzini36c327a2017-06-01 17:23:13 +02002008 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002009 break;
2010 case MFI_CMD_LD_READ:
2011 case MFI_CMD_LD_WRITE:
Paolo Bonzini36c327a2017-06-01 17:23:13 +02002012 frame_status = megasas_handle_io(s, cmd, frame_cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002013 break;
2014 default:
Paolo Bonzini36c327a2017-06-01 17:23:13 +02002015 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002016 s->event_count++;
2017 break;
2018 }
2019 if (frame_status != MFI_STAT_INVALID_STATUS) {
Paolo Bonzini421cc3e2016-09-08 17:42:53 +02002020 if (cmd->frame) {
2021 cmd->frame->header.cmd_status = frame_status;
2022 } else {
2023 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
2024 }
Hannes Reinecke6df57182014-10-29 13:00:15 +01002025 megasas_unmap_frame(s, cmd);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002026 megasas_complete_frame(s, cmd->context);
2027 }
2028}
2029
Avi Kivitya8170e52012-10-23 12:30:10 +02002030static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002031 unsigned size)
2032{
2033 MegasasState *s = opaque;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002034 PCIDevice *pci_dev = PCI_DEVICE(s);
Eduardo Habkost2e0aec12020-08-25 15:19:58 -04002035 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002036 uint32_t retval = 0;
2037
2038 switch (addr) {
2039 case MFI_IDB:
2040 retval = 0;
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002041 trace_megasas_mmio_readl("MFI_IDB", retval);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002042 break;
2043 case MFI_OMSG0:
2044 case MFI_OSP0:
Hannes Reineckee23d0492014-10-29 13:00:08 +01002045 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002046 (s->fw_state & MFI_FWSTATE_MASK) |
2047 ((s->fw_sge & 0xff) << 16) |
2048 (s->fw_cmds & 0xFFFF);
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002049 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2050 retval);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002051 break;
2052 case MFI_OSTS:
2053 if (megasas_intr_enabled(s) && s->doorbell) {
Hannes Reineckee23d0492014-10-29 13:00:08 +01002054 retval = base_class->osts;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002055 }
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002056 trace_megasas_mmio_readl("MFI_OSTS", retval);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002057 break;
2058 case MFI_OMSK:
2059 retval = s->intr_mask;
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002060 trace_megasas_mmio_readl("MFI_OMSK", retval);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002061 break;
2062 case MFI_ODCR0:
Hannes Reinecke7957ee72014-10-29 13:00:16 +01002063 retval = s->doorbell ? 1 : 0;
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002064 trace_megasas_mmio_readl("MFI_ODCR0", retval);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002065 break;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002066 case MFI_DIAG:
2067 retval = s->diag;
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002068 trace_megasas_mmio_readl("MFI_DIAG", retval);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002069 break;
2070 case MFI_OSP1:
2071 retval = 15;
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002072 trace_megasas_mmio_readl("MFI_OSP1", retval);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002073 break;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002074 default:
2075 trace_megasas_mmio_invalid_readl(addr);
2076 break;
2077 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002078 return retval;
2079}
2080
Hannes Reineckee23d0492014-10-29 13:00:08 +01002081static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2082
Avi Kivitya8170e52012-10-23 12:30:10 +02002083static void megasas_mmio_write(void *opaque, hwaddr addr,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002084 uint64_t val, unsigned size)
2085{
2086 MegasasState *s = opaque;
Andreas Färber52190c12013-06-30 14:02:53 +02002087 PCIDevice *pci_dev = PCI_DEVICE(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002088 uint64_t frame_addr;
2089 uint32_t frame_count;
2090 int i;
2091
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002092 switch (addr) {
2093 case MFI_IDB:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002094 trace_megasas_mmio_writel("MFI_IDB", val);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002095 if (val & MFI_FWINIT_ABORT) {
2096 /* Abort all pending cmds */
2097 for (i = 0; i < s->fw_cmds; i++) {
2098 megasas_abort_command(&s->frames[i]);
2099 }
2100 }
2101 if (val & MFI_FWINIT_READY) {
2102 /* move to FW READY */
2103 megasas_soft_reset(s);
2104 }
2105 if (val & MFI_FWINIT_MFIMODE) {
2106 /* discard MFIs */
2107 }
Hannes Reineckee23d0492014-10-29 13:00:08 +01002108 if (val & MFI_FWINIT_STOP_ADP) {
2109 /* Terminal error, stop processing */
2110 s->fw_state = MFI_FWSTATE_FAULT;
2111 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002112 break;
2113 case MFI_OMSK:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002114 trace_megasas_mmio_writel("MFI_OMSK", val);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002115 s->intr_mask = val;
Hannes Reinecke4522b692014-04-16 16:44:15 +02002116 if (!megasas_intr_enabled(s) &&
2117 !msi_enabled(pci_dev) &&
2118 !msix_enabled(pci_dev)) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002119 trace_megasas_irq_lower();
Marcel Apfelbaum9e64f8a2013-10-07 10:36:39 +03002120 pci_irq_deassert(pci_dev);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002121 }
2122 if (megasas_intr_enabled(s)) {
Hannes Reinecke4522b692014-04-16 16:44:15 +02002123 if (msix_enabled(pci_dev)) {
2124 trace_megasas_msix_enabled(0);
2125 } else if (msi_enabled(pci_dev)) {
2126 trace_megasas_msi_enabled(0);
2127 } else {
2128 trace_megasas_intr_enabled();
2129 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002130 } else {
2131 trace_megasas_intr_disabled();
Hannes Reineckee23d0492014-10-29 13:00:08 +01002132 megasas_soft_reset(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002133 }
2134 break;
2135 case MFI_ODCR0:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002136 trace_megasas_mmio_writel("MFI_ODCR0", val);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002137 s->doorbell = 0;
Hannes Reinecke7957ee72014-10-29 13:00:16 +01002138 if (megasas_intr_enabled(s)) {
2139 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002140 trace_megasas_irq_lower();
Marcel Apfelbaum9e64f8a2013-10-07 10:36:39 +03002141 pci_irq_deassert(pci_dev);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002142 }
2143 }
2144 break;
2145 case MFI_IQPH:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002146 trace_megasas_mmio_writel("MFI_IQPH", val);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002147 /* Received high 32 bits of a 64 bit MFI frame address */
2148 s->frame_hi = val;
2149 break;
2150 case MFI_IQPL:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002151 trace_megasas_mmio_writel("MFI_IQPL", val);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002152 /* Received low 32 bits of a 64 bit MFI frame address */
Hannes Reineckee23d0492014-10-29 13:00:08 +01002153 /* Fallthrough */
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002154 case MFI_IQP:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002155 if (addr == MFI_IQP) {
2156 trace_megasas_mmio_writel("MFI_IQP", val);
2157 /* Received 64 bit MFI frame address */
2158 s->frame_hi = 0;
2159 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002160 frame_addr = (val & ~0x1F);
2161 /* Add possible 64 bit offset */
2162 frame_addr |= ((uint64_t)s->frame_hi << 32);
2163 s->frame_hi = 0;
2164 frame_count = (val >> 1) & 0xF;
2165 megasas_handle_frame(s, frame_addr, frame_count);
2166 break;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002167 case MFI_SEQ:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002168 trace_megasas_mmio_writel("MFI_SEQ", val);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002169 /* Magic sequence to start ADP reset */
Prasad J Pandit24dfa9f2017-04-24 17:36:34 +05302170 if (adp_reset_seq[s->adp_reset++] == val) {
2171 if (s->adp_reset == 6) {
2172 s->adp_reset = 0;
2173 s->diag = MFI_DIAG_WRITE_ENABLE;
2174 }
Hannes Reineckee23d0492014-10-29 13:00:08 +01002175 } else {
2176 s->adp_reset = 0;
2177 s->diag = 0;
2178 }
Hannes Reineckee23d0492014-10-29 13:00:08 +01002179 break;
2180 case MFI_DIAG:
Hannes Reinecke77bb6b12014-10-29 13:00:10 +01002181 trace_megasas_mmio_writel("MFI_DIAG", val);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002182 /* ADP reset */
2183 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2184 (val & MFI_DIAG_RESET_ADP)) {
2185 s->diag |= MFI_DIAG_RESET_ADP;
2186 megasas_soft_reset(s);
2187 s->adp_reset = 0;
2188 s->diag = 0;
2189 }
2190 break;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002191 default:
2192 trace_megasas_mmio_invalid_writel(addr, val);
2193 break;
2194 }
2195}
2196
2197static const MemoryRegionOps megasas_mmio_ops = {
2198 .read = megasas_mmio_read,
2199 .write = megasas_mmio_write,
2200 .endianness = DEVICE_LITTLE_ENDIAN,
2201 .impl = {
2202 .min_access_size = 8,
2203 .max_access_size = 8,
2204 }
2205};
2206
Avi Kivitya8170e52012-10-23 12:30:10 +02002207static uint64_t megasas_port_read(void *opaque, hwaddr addr,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002208 unsigned size)
2209{
2210 return megasas_mmio_read(opaque, addr & 0xff, size);
2211}
2212
Avi Kivitya8170e52012-10-23 12:30:10 +02002213static void megasas_port_write(void *opaque, hwaddr addr,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002214 uint64_t val, unsigned size)
2215{
2216 megasas_mmio_write(opaque, addr & 0xff, val, size);
2217}
2218
2219static const MemoryRegionOps megasas_port_ops = {
2220 .read = megasas_port_read,
2221 .write = megasas_port_write,
2222 .endianness = DEVICE_LITTLE_ENDIAN,
2223 .impl = {
2224 .min_access_size = 4,
2225 .max_access_size = 4,
2226 }
2227};
2228
Avi Kivitya8170e52012-10-23 12:30:10 +02002229static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002230 unsigned size)
2231{
2232 return 0;
2233}
2234
Salva Peiró55875fc2015-07-27 10:51:52 +02002235static void megasas_queue_write(void *opaque, hwaddr addr,
2236 uint64_t val, unsigned size)
2237{
2238 return;
2239}
2240
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002241static const MemoryRegionOps megasas_queue_ops = {
2242 .read = megasas_queue_read,
Salva Peiró55875fc2015-07-27 10:51:52 +02002243 .write = megasas_queue_write,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002244 .endianness = DEVICE_LITTLE_ENDIAN,
2245 .impl = {
2246 .min_access_size = 8,
2247 .max_access_size = 8,
2248 }
2249};
2250
2251static void megasas_soft_reset(MegasasState *s)
2252{
2253 int i;
2254 MegasasCmd *cmd;
2255
Hannes Reinecke8d72db62014-10-29 13:00:11 +01002256 trace_megasas_reset(s->fw_state);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002257 for (i = 0; i < s->fw_cmds; i++) {
2258 cmd = &s->frames[i];
2259 megasas_abort_command(cmd);
2260 }
Hannes Reinecke8d72db62014-10-29 13:00:11 +01002261 if (s->fw_state == MFI_FWSTATE_READY) {
2262 BusChild *kid;
2263
2264 /*
2265 * The EFI firmware doesn't handle UA,
2266 * so we need to clear the Power On/Reset UA
2267 * after the initial reset.
2268 */
2269 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
Cao jine1dc6812016-01-06 17:37:46 +08002270 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
Hannes Reinecke8d72db62014-10-29 13:00:11 +01002271
2272 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2273 scsi_device_unit_attention_reported(sdev);
2274 }
2275 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002276 megasas_reset_frames(s);
2277 s->reply_queue_len = s->fw_cmds;
2278 s->reply_queue_pa = 0;
2279 s->consumer_pa = 0;
2280 s->producer_pa = 0;
2281 s->fw_state = MFI_FWSTATE_READY;
2282 s->doorbell = 0;
2283 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2284 s->frame_hi = 0;
2285 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2286 s->event_count++;
2287 s->boot_event = s->event_count;
2288}
2289
2290static void megasas_scsi_reset(DeviceState *dev)
2291{
Peter Crosthwaitec79e16a2013-06-24 16:54:15 +10002292 MegasasState *s = MEGASAS(dev);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002293
2294 megasas_soft_reset(s);
2295}
2296
Hannes Reineckee23d0492014-10-29 13:00:08 +01002297static const VMStateDescription vmstate_megasas_gen1 = {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002298 .name = "megasas",
2299 .version_id = 0,
2300 .minimum_version_id = 0,
Juan Quintelad49805a2014-04-16 15:32:32 +02002301 .fields = (VMStateField[]) {
Andreas Färber52190c12013-06-30 14:02:53 +02002302 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
Hannes Reinecke23335f62014-04-16 16:44:14 +02002303 VMSTATE_MSIX(parent_obj, MegasasState),
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002304
Prasad J Pandit2b151292020-05-14 00:55:40 +05302305 VMSTATE_UINT32(fw_state, MegasasState),
2306 VMSTATE_UINT32(intr_mask, MegasasState),
2307 VMSTATE_UINT32(doorbell, MegasasState),
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002308 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2309 VMSTATE_UINT64(consumer_pa, MegasasState),
2310 VMSTATE_UINT64(producer_pa, MegasasState),
2311 VMSTATE_END_OF_LIST()
2312 }
2313};
2314
Hannes Reineckee23d0492014-10-29 13:00:08 +01002315static const VMStateDescription vmstate_megasas_gen2 = {
2316 .name = "megasas-gen2",
2317 .version_id = 0,
2318 .minimum_version_id = 0,
Hannes Reineckee23d0492014-10-29 13:00:08 +01002319 .fields = (VMStateField[]) {
Dr. David Alan Gilbert20daa902016-12-14 19:58:29 +00002320 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
Hannes Reineckee23d0492014-10-29 13:00:08 +01002321 VMSTATE_MSIX(parent_obj, MegasasState),
2322
Prasad J Pandit2b151292020-05-14 00:55:40 +05302323 VMSTATE_UINT32(fw_state, MegasasState),
2324 VMSTATE_UINT32(intr_mask, MegasasState),
2325 VMSTATE_UINT32(doorbell, MegasasState),
Hannes Reineckee23d0492014-10-29 13:00:08 +01002326 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2327 VMSTATE_UINT64(consumer_pa, MegasasState),
2328 VMSTATE_UINT64(producer_pa, MegasasState),
2329 VMSTATE_END_OF_LIST()
2330 }
2331};
2332
Stefan Weil18fc6112012-07-31 07:54:57 +02002333static void megasas_scsi_uninit(PCIDevice *d)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002334{
Peter Crosthwaitec79e16a2013-06-24 16:54:15 +10002335 MegasasState *s = MEGASAS(d);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002336
Hannes Reinecke4522b692014-04-16 16:44:15 +02002337 if (megasas_use_msix(s)) {
2338 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2339 }
Cao jinafea4e12016-06-20 14:13:40 +08002340 msi_uninit(d);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002341}
2342
2343static const struct SCSIBusInfo megasas_scsi_info = {
2344 .tcq = true,
2345 .max_target = MFI_MAX_LD,
2346 .max_lun = 255,
2347
2348 .transfer_data = megasas_xfer_complete,
2349 .get_sg_list = megasas_get_sg_list,
2350 .complete = megasas_command_complete,
Paolo Bonzini9e55d582016-11-10 16:27:51 +01002351 .cancel = megasas_command_cancelled,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002352};
2353
Markus Armbrusterae071cc2015-03-09 19:17:28 +01002354static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002355{
Peter Crosthwaitec79e16a2013-06-24 16:54:15 +10002356 MegasasState *s = MEGASAS(dev);
Eduardo Habkost2e0aec12020-08-25 15:19:58 -04002357 MegasasBaseClass *b = MEGASAS_GET_CLASS(s);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002358 uint8_t *pci_conf;
2359 int i, bar_type;
Cao jin1108b2f2016-06-20 14:13:39 +08002360 Error *err = NULL;
2361 int ret;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002362
Andreas Färber52190c12013-06-30 14:02:53 +02002363 pci_conf = dev->config;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002364
2365 /* PCI latency timer = 0 */
2366 pci_conf[PCI_LATENCY_TIMER] = 0;
2367 /* Interrupt pin 1 */
2368 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2369
Cao jinafea4e12016-06-20 14:13:40 +08002370 if (s->msi != ON_OFF_AUTO_OFF) {
Cao jin1108b2f2016-06-20 14:13:39 +08002371 ret = msi_init(dev, 0x50, 1, true, false, &err);
2372 /* Any error other than -ENOTSUP(board's MSI support is broken)
2373 * is a programming error */
2374 assert(!ret || ret == -ENOTSUP);
2375 if (ret && s->msi == ON_OFF_AUTO_ON) {
2376 /* Can't satisfy user's explicit msi=on request, fail */
2377 error_append_hint(&err, "You have to use msi=auto (default) or "
2378 "msi=off with this machine type.\n");
2379 error_propagate(errp, err);
2380 return;
2381 } else if (ret) {
2382 /* With msi=auto, we fall back to MSI off silently */
2383 s->msi = ON_OFF_AUTO_OFF;
2384 error_free(err);
2385 }
2386 }
2387
Paolo Bonzini29776732013-06-06 21:25:08 -04002388 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002389 "megasas-mmio", 0x4000);
Paolo Bonzini29776732013-06-06 21:25:08 -04002390 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002391 "megasas-io", 256);
Paolo Bonzini29776732013-06-06 21:25:08 -04002392 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002393 "megasas-queue", 0x40000);
2394
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002395 if (megasas_use_msix(s) &&
Hannes Reineckee23d0492014-10-29 13:00:08 +01002396 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
Cao jinee640c62017-01-17 14:18:48 +08002397 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2398 /* TODO: check msix_init's error, and should fail on msix=on */
Cao jinb4b4a572016-06-20 14:13:37 +08002399 s->msix = ON_OFF_AUTO_OFF;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002400 }
Cao jinee640c62017-01-17 14:18:48 +08002401
Hannes Reineckee23d0492014-10-29 13:00:08 +01002402 if (pci_is_express(dev)) {
2403 pcie_endpoint_cap_init(dev, 0xa0);
2404 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002405
2406 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002407 pci_register_bar(dev, b->ioport_bar,
2408 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2409 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
Andreas Färber52190c12013-06-30 14:02:53 +02002410 pci_register_bar(dev, 3, bar_type, &s->queue_io);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002411
2412 if (megasas_use_msix(s)) {
Andreas Färber52190c12013-06-30 14:02:53 +02002413 msix_vector_use(dev, 0);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002414 }
2415
Hannes Reinecke8d72db62014-10-29 13:00:11 +01002416 s->fw_state = MFI_FWSTATE_READY;
Hannes Reinecke76b523d2012-08-01 12:46:50 +02002417 if (!s->sas_addr) {
2418 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2419 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
Philippe Mathieu-Daudéba1da4a2020-10-11 21:50:01 +02002420 s->sas_addr |= pci_dev_bus_num(dev) << 16;
2421 s->sas_addr |= PCI_SLOT(dev->devfn) << 8;
Hannes Reinecke76b523d2012-08-01 12:46:50 +02002422 s->sas_addr |= PCI_FUNC(dev->devfn);
2423 }
Hannes Reineckefb654152012-08-24 12:36:41 +02002424 if (!s->hba_serial) {
Hannes Reinecke23335f62014-04-16 16:44:14 +02002425 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
Hannes Reineckefb654152012-08-24 12:36:41 +02002426 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002427 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2428 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2429 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2430 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2431 } else {
2432 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2433 }
2434 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2435 s->fw_cmds = MEGASAS_MAX_FRAMES;
2436 }
2437 trace_megasas_init(s->fw_sge, s->fw_cmds,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002438 megasas_is_jbod(s) ? "jbod" : "raid");
Hannes Reinecke3f2cd4d2014-10-29 13:00:07 +01002439
2440 if (megasas_is_jbod(s)) {
2441 s->fw_luns = MFI_MAX_SYS_PDS;
2442 } else {
2443 s->fw_luns = MFI_MAX_LD;
2444 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002445 s->producer_pa = 0;
2446 s->consumer_pa = 0;
2447 for (i = 0; i < s->fw_cmds; i++) {
2448 s->frames[i].index = i;
2449 s->frames[i].context = -1;
2450 s->frames[i].pa = 0;
2451 s->frames[i].state = s;
2452 }
2453
Peter Maydell739e95f2021-09-23 13:11:48 +01002454 scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002455}
2456
Hannes Reineckee23d0492014-10-29 13:00:08 +01002457static Property megasas_properties_gen1[] = {
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002458 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2459 MEGASAS_DEFAULT_SGE),
2460 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2461 MEGASAS_DEFAULT_FRAMES),
Hannes Reineckefb654152012-08-24 12:36:41 +02002462 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
Paolo Bonzinic7bcc852014-02-08 11:01:53 +01002463 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
Cao jinb4b4a572016-06-20 14:13:37 +08002464 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2465 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002466 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2467 MEGASAS_FLAG_USE_JBOD, false),
2468 DEFINE_PROP_END_OF_LIST(),
2469};
2470
Hannes Reineckee23d0492014-10-29 13:00:08 +01002471static Property megasas_properties_gen2[] = {
2472 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2473 MEGASAS_DEFAULT_SGE),
2474 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2475 MEGASAS_GEN2_DEFAULT_FRAMES),
2476 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2477 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
Cao jinb4b4a572016-06-20 14:13:37 +08002478 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2479 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
Hannes Reineckee23d0492014-10-29 13:00:08 +01002480 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2481 MEGASAS_FLAG_USE_JBOD, false),
2482 DEFINE_PROP_END_OF_LIST(),
2483};
2484
2485typedef struct MegasasInfo {
2486 const char *name;
2487 const char *desc;
2488 const char *product_name;
2489 const char *product_version;
2490 uint16_t device_id;
2491 uint16_t subsystem_id;
2492 int ioport_bar;
2493 int mmio_bar;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002494 int osts;
2495 const VMStateDescription *vmsd;
2496 Property *props;
Eduardo Habkost71d78762017-09-27 16:56:33 -03002497 InterfaceInfo *interfaces;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002498} MegasasInfo;
2499
2500static struct MegasasInfo megasas_devices[] = {
2501 {
2502 .name = TYPE_MEGASAS_GEN1,
2503 .desc = "LSI MegaRAID SAS 1078",
2504 .product_name = "LSI MegaRAID SAS 8708EM2",
2505 .product_version = MEGASAS_VERSION_GEN1,
2506 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2507 .subsystem_id = 0x1013,
2508 .ioport_bar = 2,
2509 .mmio_bar = 0,
2510 .osts = MFI_1078_RM | 1,
Hannes Reineckee23d0492014-10-29 13:00:08 +01002511 .vmsd = &vmstate_megasas_gen1,
2512 .props = megasas_properties_gen1,
Eduardo Habkostfd3b02c2017-09-27 16:56:34 -03002513 .interfaces = (InterfaceInfo[]) {
2514 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2515 { },
2516 },
Hannes Reineckee23d0492014-10-29 13:00:08 +01002517 },{
2518 .name = TYPE_MEGASAS_GEN2,
2519 .desc = "LSI MegaRAID SAS 2108",
2520 .product_name = "LSI MegaRAID SAS 9260-8i",
2521 .product_version = MEGASAS_VERSION_GEN2,
2522 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2523 .subsystem_id = 0x9261,
2524 .ioport_bar = 0,
2525 .mmio_bar = 1,
2526 .osts = MFI_GEN2_RM,
Hannes Reineckee23d0492014-10-29 13:00:08 +01002527 .vmsd = &vmstate_megasas_gen2,
2528 .props = megasas_properties_gen2,
Eduardo Habkost71d78762017-09-27 16:56:33 -03002529 .interfaces = (InterfaceInfo[]) {
2530 { INTERFACE_PCIE_DEVICE },
2531 { }
2532 },
Hannes Reineckee23d0492014-10-29 13:00:08 +01002533 }
2534};
2535
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002536static void megasas_class_init(ObjectClass *oc, void *data)
2537{
2538 DeviceClass *dc = DEVICE_CLASS(oc);
2539 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
Eduardo Habkost2e0aec12020-08-25 15:19:58 -04002540 MegasasBaseClass *e = MEGASAS_CLASS(oc);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002541 const MegasasInfo *info = data;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002542
Markus Armbrusterae071cc2015-03-09 19:17:28 +01002543 pc->realize = megasas_scsi_realize;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002544 pc->exit = megasas_scsi_uninit;
2545 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002546 pc->device_id = info->device_id;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002547 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002548 pc->subsystem_id = info->subsystem_id;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002549 pc->class_id = PCI_CLASS_STORAGE_RAID;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002550 e->mmio_bar = info->mmio_bar;
2551 e->ioport_bar = info->ioport_bar;
2552 e->osts = info->osts;
2553 e->product_name = info->product_name;
2554 e->product_version = info->product_version;
Marc-André Lureau4f67d302020-01-10 19:30:32 +04002555 device_class_set_props(dc, info->props);
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002556 dc->reset = megasas_scsi_reset;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002557 dc->vmsd = info->vmsd;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +03002558 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002559 dc->desc = info->desc;
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002560}
2561
2562static const TypeInfo megasas_info = {
Hannes Reineckee23d0492014-10-29 13:00:08 +01002563 .name = TYPE_MEGASAS_BASE,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002564 .parent = TYPE_PCI_DEVICE,
2565 .instance_size = sizeof(MegasasState),
Hannes Reineckee23d0492014-10-29 13:00:08 +01002566 .class_size = sizeof(MegasasBaseClass),
2567 .abstract = true,
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002568};
2569
2570static void megasas_register_types(void)
2571{
Hannes Reineckee23d0492014-10-29 13:00:08 +01002572 int i;
2573
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002574 type_register_static(&megasas_info);
Hannes Reineckee23d0492014-10-29 13:00:08 +01002575 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2576 const MegasasInfo *info = &megasas_devices[i];
2577 TypeInfo type_info = {};
2578
2579 type_info.name = info->name;
2580 type_info.parent = TYPE_MEGASAS_BASE;
2581 type_info.class_data = (void *)info;
2582 type_info.class_init = megasas_class_init;
Eduardo Habkost71d78762017-09-27 16:56:33 -03002583 type_info.interfaces = info->interfaces;
Hannes Reineckee23d0492014-10-29 13:00:08 +01002584
2585 type_register(&type_info);
2586 }
Hannes Reineckee8f943c2012-05-29 13:51:17 +02002587}
2588
2589type_init(megasas_register_types)