pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1 | /* |
aurel32 | 1654b2d | 2008-04-11 04:55:07 +0000 | [diff] [blame] | 2 | * Luminary Micro Stellaris peripherals |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 7 | * This code is licensed under the GPL. |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Peter Maydell | 12b1672 | 2015-12-07 16:23:45 +0000 | [diff] [blame] | 10 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 11 | #include "qapi/error.h" |
Zongyuan Li | d0a030d | 2022-03-25 02:15:55 +0800 | [diff] [blame] | 12 | #include "hw/core/split-irq.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 13 | #include "hw/sysbus.h" |
Markus Armbruster | 36aa285 | 2021-11-17 17:33:57 +0100 | [diff] [blame] | 14 | #include "hw/sd/sd.h" |
Alistair Francis | 8fd0671 | 2016-01-21 14:15:03 +0000 | [diff] [blame] | 15 | #include "hw/ssi/ssi.h" |
Peter Maydell | 12ec8bd | 2019-05-23 14:47:43 +0100 | [diff] [blame] | 16 | #include "hw/arm/boot.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 17 | #include "qemu/timer.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 18 | #include "hw/i2c/i2c.h" |
Paolo Bonzini | 1422e32 | 2012-10-24 08:43:34 +0200 | [diff] [blame] | 19 | #include "net/net.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 20 | #include "hw/boards.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 21 | #include "qemu/log.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 22 | #include "exec/address-spaces.h" |
Michael Davidsaver | d69ffb5 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 23 | #include "sysemu/sysemu.h" |
Peter Maydell | f04d446 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 24 | #include "hw/arm/armv7m.h" |
xiaoqiang zhao | f0d1d2c | 2016-06-06 16:59:31 +0100 | [diff] [blame] | 25 | #include "hw/char/pl011.h" |
Peter Maydell | c45460d | 2023-10-30 11:47:57 +0000 | [diff] [blame] | 26 | #include "hw/input/stellaris_gamepad.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 27 | #include "hw/irq.h" |
Michel Heily | 566528f | 2019-03-05 01:16:22 +0200 | [diff] [blame] | 28 | #include "hw/watchdog/cmsdk-apb-watchdog.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 29 | #include "migration/vmstate.h" |
Peter Maydell | aecfbbc | 2017-02-07 18:30:00 +0000 | [diff] [blame] | 30 | #include "hw/misc/unimp.h" |
Peter Maydell | f3eb755 | 2021-08-12 10:33:54 +0100 | [diff] [blame] | 31 | #include "hw/timer/stellaris-gptm.h" |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 32 | #include "hw/qdev-clock.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 33 | #include "qom/object.h" |
Peter Maydell | a75f336 | 2023-10-30 11:48:01 +0000 | [diff] [blame] | 34 | #include "qapi/qmp/qlist.h" |
Peter Maydell | 7c76f39 | 2023-10-30 11:48:02 +0000 | [diff] [blame] | 35 | #include "ui/input.h" |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 36 | |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 37 | #define GPIO_A 0 |
| 38 | #define GPIO_B 1 |
| 39 | #define GPIO_C 2 |
| 40 | #define GPIO_D 3 |
| 41 | #define GPIO_E 4 |
| 42 | #define GPIO_F 5 |
| 43 | #define GPIO_G 6 |
| 44 | |
| 45 | #define BP_OLED_I2C 0x01 |
| 46 | #define BP_OLED_SSI 0x02 |
| 47 | #define BP_GAMEPAD 0x04 |
| 48 | |
Alistair Francis | 8b47b7d | 2015-02-05 13:37:21 +0000 | [diff] [blame] | 49 | #define NUM_IRQ_LINES 64 |
Samuel Tardieu | 4a04655 | 2024-01-06 19:15:03 +0100 | [diff] [blame] | 50 | #define NUM_PRIO_BITS 3 |
Alistair Francis | 8b47b7d | 2015-02-05 13:37:21 +0000 | [diff] [blame] | 51 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 52 | typedef const struct { |
| 53 | const char *name; |
| 54 | uint32_t did0; |
| 55 | uint32_t did1; |
| 56 | uint32_t dc0; |
| 57 | uint32_t dc1; |
| 58 | uint32_t dc2; |
| 59 | uint32_t dc3; |
| 60 | uint32_t dc4; |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 61 | uint32_t peripherals; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 62 | } stellaris_board_info; |
| 63 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 64 | /* System controller. */ |
| 65 | |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 66 | #define TYPE_STELLARIS_SYS "stellaris-sys" |
| 67 | OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) |
| 68 | |
| 69 | struct ssys_state { |
| 70 | SysBusDevice parent_obj; |
| 71 | |
Benoît Canet | 5699301 | 2011-10-17 17:28:29 +0200 | [diff] [blame] | 72 | MemoryRegion iomem; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 73 | uint32_t pborctl; |
| 74 | uint32_t ldopctl; |
| 75 | uint32_t int_status; |
| 76 | uint32_t int_mask; |
| 77 | uint32_t resc; |
| 78 | uint32_t rcc; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 79 | uint32_t rcc2; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 80 | uint32_t rcgc[3]; |
| 81 | uint32_t scgc[3]; |
| 82 | uint32_t dcgc[3]; |
| 83 | uint32_t clkvclr; |
| 84 | uint32_t ldoarst; |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 85 | qemu_irq irq; |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 86 | Clock *sysclk; |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 87 | /* Properties (all read-only registers) */ |
pbrook | eea589c | 2007-11-24 03:13:04 +0000 | [diff] [blame] | 88 | uint32_t user0; |
| 89 | uint32_t user1; |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 90 | uint32_t did0; |
| 91 | uint32_t did1; |
| 92 | uint32_t dc0; |
| 93 | uint32_t dc1; |
| 94 | uint32_t dc2; |
| 95 | uint32_t dc3; |
| 96 | uint32_t dc4; |
| 97 | }; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 98 | |
| 99 | static void ssys_update(ssys_state *s) |
| 100 | { |
| 101 | qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); |
| 102 | } |
| 103 | |
| 104 | static uint32_t pllcfg_sandstorm[16] = { |
| 105 | 0x31c0, /* 1 Mhz */ |
| 106 | 0x1ae0, /* 1.8432 Mhz */ |
| 107 | 0x18c0, /* 2 Mhz */ |
| 108 | 0xd573, /* 2.4576 Mhz */ |
| 109 | 0x37a6, /* 3.57954 Mhz */ |
| 110 | 0x1ae2, /* 3.6864 Mhz */ |
| 111 | 0x0c40, /* 4 Mhz */ |
| 112 | 0x98bc, /* 4.906 Mhz */ |
| 113 | 0x935b, /* 4.9152 Mhz */ |
| 114 | 0x09c0, /* 5 Mhz */ |
| 115 | 0x4dee, /* 5.12 Mhz */ |
| 116 | 0x0c41, /* 6 Mhz */ |
| 117 | 0x75db, /* 6.144 Mhz */ |
| 118 | 0x1ae6, /* 7.3728 Mhz */ |
| 119 | 0x0600, /* 8 Mhz */ |
| 120 | 0x585b /* 8.192 Mhz */ |
| 121 | }; |
| 122 | |
| 123 | static uint32_t pllcfg_fury[16] = { |
| 124 | 0x3200, /* 1 Mhz */ |
| 125 | 0x1b20, /* 1.8432 Mhz */ |
| 126 | 0x1900, /* 2 Mhz */ |
| 127 | 0xf42b, /* 2.4576 Mhz */ |
| 128 | 0x37e3, /* 3.57954 Mhz */ |
| 129 | 0x1b21, /* 3.6864 Mhz */ |
| 130 | 0x0c80, /* 4 Mhz */ |
| 131 | 0x98ee, /* 4.906 Mhz */ |
| 132 | 0xd5b4, /* 4.9152 Mhz */ |
| 133 | 0x0a00, /* 5 Mhz */ |
| 134 | 0x4e27, /* 5.12 Mhz */ |
| 135 | 0x1902, /* 6 Mhz */ |
| 136 | 0xec1c, /* 6.144 Mhz */ |
| 137 | 0x1b23, /* 7.3728 Mhz */ |
| 138 | 0x0640, /* 8 Mhz */ |
| 139 | 0xb11c /* 8.192 Mhz */ |
| 140 | }; |
| 141 | |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 142 | #define DID0_VER_MASK 0x70000000 |
| 143 | #define DID0_VER_0 0x00000000 |
| 144 | #define DID0_VER_1 0x10000000 |
| 145 | |
| 146 | #define DID0_CLASS_MASK 0x00FF0000 |
| 147 | #define DID0_CLASS_SANDSTORM 0x00000000 |
| 148 | #define DID0_CLASS_FURY 0x00010000 |
| 149 | |
| 150 | static int ssys_board_class(const ssys_state *s) |
| 151 | { |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 152 | uint32_t did0 = s->did0; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 153 | switch (did0 & DID0_VER_MASK) { |
| 154 | case DID0_VER_0: |
| 155 | return DID0_CLASS_SANDSTORM; |
| 156 | case DID0_VER_1: |
| 157 | switch (did0 & DID0_CLASS_MASK) { |
| 158 | case DID0_CLASS_SANDSTORM: |
| 159 | case DID0_CLASS_FURY: |
| 160 | return did0 & DID0_CLASS_MASK; |
| 161 | } |
| 162 | /* for unknown classes, fall through */ |
| 163 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 164 | /* This can only happen if the hardwired constant did0 value |
| 165 | * in this board's stellaris_board_info struct is wrong. |
| 166 | */ |
| 167 | g_assert_not_reached(); |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 168 | } |
| 169 | } |
| 170 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 171 | static uint64_t ssys_read(void *opaque, hwaddr offset, |
Benoît Canet | 5699301 | 2011-10-17 17:28:29 +0200 | [diff] [blame] | 172 | unsigned size) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 173 | { |
| 174 | ssys_state *s = (ssys_state *)opaque; |
| 175 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 176 | switch (offset) { |
| 177 | case 0x000: /* DID0 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 178 | return s->did0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 179 | case 0x004: /* DID1 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 180 | return s->did1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 181 | case 0x008: /* DC0 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 182 | return s->dc0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 183 | case 0x010: /* DC1 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 184 | return s->dc1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 185 | case 0x014: /* DC2 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 186 | return s->dc2; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 187 | case 0x018: /* DC3 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 188 | return s->dc3; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 189 | case 0x01c: /* DC4 */ |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 190 | return s->dc4; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 191 | case 0x030: /* PBORCTL */ |
| 192 | return s->pborctl; |
| 193 | case 0x034: /* LDOPCTL */ |
| 194 | return s->ldopctl; |
| 195 | case 0x040: /* SRCR0 */ |
| 196 | return 0; |
| 197 | case 0x044: /* SRCR1 */ |
| 198 | return 0; |
| 199 | case 0x048: /* SRCR2 */ |
| 200 | return 0; |
| 201 | case 0x050: /* RIS */ |
| 202 | return s->int_status; |
| 203 | case 0x054: /* IMC */ |
| 204 | return s->int_mask; |
| 205 | case 0x058: /* MISC */ |
| 206 | return s->int_status & s->int_mask; |
| 207 | case 0x05c: /* RESC */ |
| 208 | return s->resc; |
| 209 | case 0x060: /* RCC */ |
| 210 | return s->rcc; |
| 211 | case 0x064: /* PLLCFG */ |
| 212 | { |
| 213 | int xtal; |
| 214 | xtal = (s->rcc >> 6) & 0xf; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 215 | switch (ssys_board_class(s)) { |
| 216 | case DID0_CLASS_FURY: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 217 | return pllcfg_fury[xtal]; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 218 | case DID0_CLASS_SANDSTORM: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 219 | return pllcfg_sandstorm[xtal]; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 220 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 221 | g_assert_not_reached(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 222 | } |
| 223 | } |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 224 | case 0x070: /* RCC2 */ |
| 225 | return s->rcc2; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 226 | case 0x100: /* RCGC0 */ |
| 227 | return s->rcgc[0]; |
| 228 | case 0x104: /* RCGC1 */ |
| 229 | return s->rcgc[1]; |
| 230 | case 0x108: /* RCGC2 */ |
| 231 | return s->rcgc[2]; |
| 232 | case 0x110: /* SCGC0 */ |
| 233 | return s->scgc[0]; |
| 234 | case 0x114: /* SCGC1 */ |
| 235 | return s->scgc[1]; |
| 236 | case 0x118: /* SCGC2 */ |
| 237 | return s->scgc[2]; |
| 238 | case 0x120: /* DCGC0 */ |
| 239 | return s->dcgc[0]; |
| 240 | case 0x124: /* DCGC1 */ |
| 241 | return s->dcgc[1]; |
| 242 | case 0x128: /* DCGC2 */ |
| 243 | return s->dcgc[2]; |
| 244 | case 0x150: /* CLKVCLR */ |
| 245 | return s->clkvclr; |
| 246 | case 0x160: /* LDOARST */ |
| 247 | return s->ldoarst; |
pbrook | eea589c | 2007-11-24 03:13:04 +0000 | [diff] [blame] | 248 | case 0x1e0: /* USER0 */ |
| 249 | return s->user0; |
| 250 | case 0x1e4: /* USER1 */ |
| 251 | return s->user1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 252 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 253 | qemu_log_mask(LOG_GUEST_ERROR, |
| 254 | "SSYS: read at bad offset 0x%x\n", (int)offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 255 | return 0; |
| 256 | } |
| 257 | } |
| 258 | |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 259 | static bool ssys_use_rcc2(ssys_state *s) |
| 260 | { |
| 261 | return (s->rcc2 >> 31) & 0x1; |
| 262 | } |
| 263 | |
| 264 | /* |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 265 | * Calculate the system clock period. We only want to propagate |
| 266 | * this change to the rest of the system if we're not being called |
| 267 | * from migration post-load. |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 268 | */ |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 269 | static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 270 | { |
Peter Maydell | 683754c | 2021-08-12 10:33:56 +0100 | [diff] [blame] | 271 | int period_ns; |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 272 | /* |
| 273 | * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input |
| 274 | * clock is 200MHz, which is a period of 5 ns. Dividing the clock |
| 275 | * frequency by X is the same as multiplying the period by X. |
| 276 | */ |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 277 | if (ssys_use_rcc2(s)) { |
Peter Maydell | 683754c | 2021-08-12 10:33:56 +0100 | [diff] [blame] | 278 | period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 279 | } else { |
Peter Maydell | 683754c | 2021-08-12 10:33:56 +0100 | [diff] [blame] | 280 | period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 281 | } |
Peter Maydell | 683754c | 2021-08-12 10:33:56 +0100 | [diff] [blame] | 282 | clock_set_ns(s->sysclk, period_ns); |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 283 | if (propagate_clock) { |
| 284 | clock_propagate(s->sysclk); |
| 285 | } |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 286 | } |
| 287 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 288 | static void ssys_write(void *opaque, hwaddr offset, |
Benoît Canet | 5699301 | 2011-10-17 17:28:29 +0200 | [diff] [blame] | 289 | uint64_t value, unsigned size) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 290 | { |
| 291 | ssys_state *s = (ssys_state *)opaque; |
| 292 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 293 | switch (offset) { |
| 294 | case 0x030: /* PBORCTL */ |
| 295 | s->pborctl = value & 0xffff; |
| 296 | break; |
| 297 | case 0x034: /* LDOPCTL */ |
| 298 | s->ldopctl = value & 0x1f; |
| 299 | break; |
| 300 | case 0x040: /* SRCR0 */ |
| 301 | case 0x044: /* SRCR1 */ |
| 302 | case 0x048: /* SRCR2 */ |
Philippe Mathieu-Daudé | 9194524 | 2018-06-26 17:50:41 +0100 | [diff] [blame] | 303 | qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 304 | break; |
| 305 | case 0x054: /* IMC */ |
| 306 | s->int_mask = value & 0x7f; |
| 307 | break; |
| 308 | case 0x058: /* MISC */ |
| 309 | s->int_status &= ~value; |
| 310 | break; |
| 311 | case 0x05c: /* RESC */ |
| 312 | s->resc = value & 0x3f; |
| 313 | break; |
| 314 | case 0x060: /* RCC */ |
| 315 | if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { |
| 316 | /* PLL enable. */ |
| 317 | s->int_status |= (1 << 6); |
| 318 | } |
| 319 | s->rcc = value; |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 320 | ssys_calculate_system_clock(s, true); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 321 | break; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 322 | case 0x070: /* RCC2 */ |
| 323 | if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { |
| 324 | break; |
| 325 | } |
| 326 | |
| 327 | if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { |
| 328 | /* PLL enable. */ |
| 329 | s->int_status |= (1 << 6); |
| 330 | } |
| 331 | s->rcc2 = value; |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 332 | ssys_calculate_system_clock(s, true); |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 333 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 334 | case 0x100: /* RCGC0 */ |
| 335 | s->rcgc[0] = value; |
| 336 | break; |
| 337 | case 0x104: /* RCGC1 */ |
| 338 | s->rcgc[1] = value; |
| 339 | break; |
| 340 | case 0x108: /* RCGC2 */ |
| 341 | s->rcgc[2] = value; |
| 342 | break; |
| 343 | case 0x110: /* SCGC0 */ |
| 344 | s->scgc[0] = value; |
| 345 | break; |
| 346 | case 0x114: /* SCGC1 */ |
| 347 | s->scgc[1] = value; |
| 348 | break; |
| 349 | case 0x118: /* SCGC2 */ |
| 350 | s->scgc[2] = value; |
| 351 | break; |
| 352 | case 0x120: /* DCGC0 */ |
| 353 | s->dcgc[0] = value; |
| 354 | break; |
| 355 | case 0x124: /* DCGC1 */ |
| 356 | s->dcgc[1] = value; |
| 357 | break; |
| 358 | case 0x128: /* DCGC2 */ |
| 359 | s->dcgc[2] = value; |
| 360 | break; |
| 361 | case 0x150: /* CLKVCLR */ |
| 362 | s->clkvclr = value; |
| 363 | break; |
| 364 | case 0x160: /* LDOARST */ |
| 365 | s->ldoarst = value; |
| 366 | break; |
| 367 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 368 | qemu_log_mask(LOG_GUEST_ERROR, |
| 369 | "SSYS: write at bad offset 0x%x\n", (int)offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 370 | } |
| 371 | ssys_update(s); |
| 372 | } |
| 373 | |
Benoît Canet | 5699301 | 2011-10-17 17:28:29 +0200 | [diff] [blame] | 374 | static const MemoryRegionOps ssys_ops = { |
| 375 | .read = ssys_read, |
| 376 | .write = ssys_write, |
| 377 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 378 | }; |
| 379 | |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 380 | static void stellaris_sys_reset_enter(Object *obj, ResetType type) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 381 | { |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 382 | ssys_state *s = STELLARIS_SYS(obj); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 383 | |
| 384 | s->pborctl = 0x7ffd; |
| 385 | s->rcc = 0x078e3ac0; |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 386 | |
| 387 | if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { |
| 388 | s->rcc2 = 0; |
| 389 | } else { |
| 390 | s->rcc2 = 0x07802810; |
| 391 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 392 | s->rcgc[0] = 1; |
| 393 | s->scgc[0] = 1; |
| 394 | s->dcgc[0] = 1; |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | static void stellaris_sys_reset_hold(Object *obj) |
| 398 | { |
| 399 | ssys_state *s = STELLARIS_SYS(obj); |
| 400 | |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 401 | /* OK to propagate clocks from the hold phase */ |
| 402 | ssys_calculate_system_clock(s, true); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 403 | } |
| 404 | |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 405 | static void stellaris_sys_reset_exit(Object *obj) |
| 406 | { |
| 407 | } |
| 408 | |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 409 | static int stellaris_sys_post_load(void *opaque, int version_id) |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 410 | { |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 411 | ssys_state *s = opaque; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 412 | |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 413 | ssys_calculate_system_clock(s, false); |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 418 | static const VMStateDescription vmstate_stellaris_sys = { |
| 419 | .name = "stellaris_sys", |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 420 | .version_id = 2, |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 421 | .minimum_version_id = 1, |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 422 | .post_load = stellaris_sys_post_load, |
Richard Henderson | 607ef57 | 2023-12-21 14:15:59 +1100 | [diff] [blame] | 423 | .fields = (const VMStateField[]) { |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 424 | VMSTATE_UINT32(pborctl, ssys_state), |
| 425 | VMSTATE_UINT32(ldopctl, ssys_state), |
| 426 | VMSTATE_UINT32(int_mask, ssys_state), |
| 427 | VMSTATE_UINT32(int_status, ssys_state), |
| 428 | VMSTATE_UINT32(resc, ssys_state), |
| 429 | VMSTATE_UINT32(rcc, ssys_state), |
Engin AYDOGAN | dc804ab | 2011-08-03 22:15:23 +0100 | [diff] [blame] | 430 | VMSTATE_UINT32_V(rcc2, ssys_state, 2), |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 431 | VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), |
| 432 | VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), |
| 433 | VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), |
| 434 | VMSTATE_UINT32(clkvclr, ssys_state), |
| 435 | VMSTATE_UINT32(ldoarst, ssys_state), |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 436 | /* No field for sysclk -- handled in post-load instead */ |
Juan Quintela | 293c16a | 2010-12-02 03:03:11 +0100 | [diff] [blame] | 437 | VMSTATE_END_OF_LIST() |
| 438 | } |
| 439 | }; |
| 440 | |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 441 | static Property stellaris_sys_properties[] = { |
| 442 | DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), |
| 443 | DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), |
| 444 | DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), |
| 445 | DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), |
| 446 | DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), |
| 447 | DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), |
| 448 | DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), |
| 449 | DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), |
| 450 | DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), |
| 451 | DEFINE_PROP_END_OF_LIST() |
| 452 | }; |
| 453 | |
| 454 | static void stellaris_sys_instance_init(Object *obj) |
| 455 | { |
| 456 | ssys_state *s = STELLARIS_SYS(obj); |
| 457 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); |
| 458 | |
| 459 | memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); |
| 460 | sysbus_init_mmio(sbd, &s->iomem); |
| 461 | sysbus_init_irq(sbd, &s->irq); |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 462 | s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 463 | } |
| 464 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 465 | /* I2C controller. */ |
| 466 | |
Andreas Färber | d94a401 | 2013-07-24 09:08:23 +0200 | [diff] [blame] | 467 | #define TYPE_STELLARIS_I2C "stellaris-i2c" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 468 | OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) |
Andreas Färber | d94a401 | 2013-07-24 09:08:23 +0200 | [diff] [blame] | 469 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 470 | struct stellaris_i2c_state { |
Andreas Färber | d94a401 | 2013-07-24 09:08:23 +0200 | [diff] [blame] | 471 | SysBusDevice parent_obj; |
| 472 | |
Andreas Färber | a5c8285 | 2013-08-03 00:18:51 +0200 | [diff] [blame] | 473 | I2CBus *bus; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 474 | qemu_irq irq; |
Benoît Canet | 8ea72f3 | 2011-10-17 17:28:30 +0200 | [diff] [blame] | 475 | MemoryRegion iomem; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 476 | uint32_t msa; |
| 477 | uint32_t mcs; |
| 478 | uint32_t mdr; |
| 479 | uint32_t mtpr; |
| 480 | uint32_t mimr; |
| 481 | uint32_t mris; |
| 482 | uint32_t mcr; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 483 | }; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 484 | |
| 485 | #define STELLARIS_I2C_MCS_BUSY 0x01 |
| 486 | #define STELLARIS_I2C_MCS_ERROR 0x02 |
| 487 | #define STELLARIS_I2C_MCS_ADRACK 0x04 |
| 488 | #define STELLARIS_I2C_MCS_DATACK 0x08 |
| 489 | #define STELLARIS_I2C_MCS_ARBLST 0x10 |
| 490 | #define STELLARIS_I2C_MCS_IDLE 0x20 |
| 491 | #define STELLARIS_I2C_MCS_BUSBSY 0x40 |
| 492 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 493 | static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, |
Benoît Canet | 8ea72f3 | 2011-10-17 17:28:30 +0200 | [diff] [blame] | 494 | unsigned size) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 495 | { |
| 496 | stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 497 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 498 | switch (offset) { |
| 499 | case 0x00: /* MSA */ |
| 500 | return s->msa; |
| 501 | case 0x04: /* MCS */ |
| 502 | /* We don't emulate timing, so the controller is never busy. */ |
| 503 | return s->mcs | STELLARIS_I2C_MCS_IDLE; |
| 504 | case 0x08: /* MDR */ |
| 505 | return s->mdr; |
| 506 | case 0x0c: /* MTPR */ |
| 507 | return s->mtpr; |
| 508 | case 0x10: /* MIMR */ |
| 509 | return s->mimr; |
| 510 | case 0x14: /* MRIS */ |
| 511 | return s->mris; |
| 512 | case 0x18: /* MMIS */ |
| 513 | return s->mris & s->mimr; |
| 514 | case 0x20: /* MCR */ |
| 515 | return s->mcr; |
| 516 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 517 | qemu_log_mask(LOG_GUEST_ERROR, |
| 518 | "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 519 | return 0; |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | static void stellaris_i2c_update(stellaris_i2c_state *s) |
| 524 | { |
| 525 | int level; |
| 526 | |
| 527 | level = (s->mris & s->mimr) != 0; |
| 528 | qemu_set_irq(s->irq, level); |
| 529 | } |
| 530 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 531 | static void stellaris_i2c_write(void *opaque, hwaddr offset, |
Benoît Canet | 8ea72f3 | 2011-10-17 17:28:30 +0200 | [diff] [blame] | 532 | uint64_t value, unsigned size) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 533 | { |
| 534 | stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 535 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 536 | switch (offset) { |
| 537 | case 0x00: /* MSA */ |
| 538 | s->msa = value & 0xff; |
| 539 | break; |
| 540 | case 0x04: /* MCS */ |
| 541 | if ((s->mcr & 0x10) == 0) { |
| 542 | /* Disabled. Do nothing. */ |
| 543 | break; |
| 544 | } |
| 545 | /* Grab the bus if this is starting a transfer. */ |
| 546 | if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { |
| 547 | if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { |
| 548 | s->mcs |= STELLARIS_I2C_MCS_ARBLST; |
| 549 | } else { |
| 550 | s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; |
| 551 | s->mcs |= STELLARIS_I2C_MCS_BUSBSY; |
| 552 | } |
| 553 | } |
| 554 | /* If we don't have the bus then indicate an error. */ |
| 555 | if (!i2c_bus_busy(s->bus) |
| 556 | || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { |
| 557 | s->mcs |= STELLARIS_I2C_MCS_ERROR; |
| 558 | break; |
| 559 | } |
| 560 | s->mcs &= ~STELLARIS_I2C_MCS_ERROR; |
| 561 | if (value & 1) { |
| 562 | /* Transfer a byte. */ |
| 563 | /* TODO: Handle errors. */ |
| 564 | if (s->msa & 1) { |
| 565 | /* Recv */ |
Corey Minyard | 05f9f17 | 2018-11-20 11:10:58 -0600 | [diff] [blame] | 566 | s->mdr = i2c_recv(s->bus); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 567 | } else { |
| 568 | /* Send */ |
| 569 | i2c_send(s->bus, s->mdr); |
| 570 | } |
| 571 | /* Raise an interrupt. */ |
| 572 | s->mris |= 1; |
| 573 | } |
| 574 | if (value & 4) { |
| 575 | /* Finish transfer. */ |
| 576 | i2c_end_transfer(s->bus); |
| 577 | s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; |
| 578 | } |
| 579 | break; |
| 580 | case 0x08: /* MDR */ |
| 581 | s->mdr = value & 0xff; |
| 582 | break; |
| 583 | case 0x0c: /* MTPR */ |
| 584 | s->mtpr = value & 0xff; |
| 585 | break; |
| 586 | case 0x10: /* MIMR */ |
| 587 | s->mimr = 1; |
| 588 | break; |
| 589 | case 0x1c: /* MICR */ |
| 590 | s->mris &= ~value; |
| 591 | break; |
| 592 | case 0x20: /* MCR */ |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 593 | if (value & 1) { |
Philippe Mathieu-Daudé | 9492e4b | 2018-06-08 13:15:33 +0100 | [diff] [blame] | 594 | qemu_log_mask(LOG_UNIMP, |
| 595 | "stellaris_i2c: Loopback not implemented\n"); |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 596 | } |
| 597 | if (value & 0x20) { |
| 598 | qemu_log_mask(LOG_UNIMP, |
Philippe Mathieu-Daudé | 9492e4b | 2018-06-08 13:15:33 +0100 | [diff] [blame] | 599 | "stellaris_i2c: Slave mode not implemented\n"); |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 600 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 601 | s->mcr = value & 0x31; |
| 602 | break; |
| 603 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 604 | qemu_log_mask(LOG_GUEST_ERROR, |
| 605 | "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 606 | } |
| 607 | stellaris_i2c_update(s); |
| 608 | } |
| 609 | |
| 610 | static void stellaris_i2c_reset(stellaris_i2c_state *s) |
| 611 | { |
| 612 | if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) |
| 613 | i2c_end_transfer(s->bus); |
| 614 | |
| 615 | s->msa = 0; |
| 616 | s->mcs = 0; |
| 617 | s->mdr = 0; |
| 618 | s->mtpr = 1; |
| 619 | s->mimr = 0; |
| 620 | s->mris = 0; |
| 621 | s->mcr = 0; |
| 622 | stellaris_i2c_update(s); |
| 623 | } |
| 624 | |
Benoît Canet | 8ea72f3 | 2011-10-17 17:28:30 +0200 | [diff] [blame] | 625 | static const MemoryRegionOps stellaris_i2c_ops = { |
| 626 | .read = stellaris_i2c_read, |
| 627 | .write = stellaris_i2c_write, |
| 628 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 629 | }; |
| 630 | |
Juan Quintela | ff269cd | 2010-12-02 02:48:43 +0100 | [diff] [blame] | 631 | static const VMStateDescription vmstate_stellaris_i2c = { |
| 632 | .name = "stellaris_i2c", |
| 633 | .version_id = 1, |
| 634 | .minimum_version_id = 1, |
Richard Henderson | 607ef57 | 2023-12-21 14:15:59 +1100 | [diff] [blame] | 635 | .fields = (const VMStateField[]) { |
Juan Quintela | ff269cd | 2010-12-02 02:48:43 +0100 | [diff] [blame] | 636 | VMSTATE_UINT32(msa, stellaris_i2c_state), |
| 637 | VMSTATE_UINT32(mcs, stellaris_i2c_state), |
| 638 | VMSTATE_UINT32(mdr, stellaris_i2c_state), |
| 639 | VMSTATE_UINT32(mtpr, stellaris_i2c_state), |
| 640 | VMSTATE_UINT32(mimr, stellaris_i2c_state), |
| 641 | VMSTATE_UINT32(mris, stellaris_i2c_state), |
| 642 | VMSTATE_UINT32(mcr, stellaris_i2c_state), |
| 643 | VMSTATE_END_OF_LIST() |
| 644 | } |
| 645 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 646 | |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 647 | static void stellaris_i2c_init(Object *obj) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 648 | { |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 649 | DeviceState *dev = DEVICE(obj); |
| 650 | stellaris_i2c_state *s = STELLARIS_I2C(obj); |
| 651 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
Andreas Färber | a5c8285 | 2013-08-03 00:18:51 +0200 | [diff] [blame] | 652 | I2CBus *bus; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 653 | |
Andreas Färber | d94a401 | 2013-07-24 09:08:23 +0200 | [diff] [blame] | 654 | sysbus_init_irq(sbd, &s->irq); |
| 655 | bus = i2c_init_bus(dev, "i2c"); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 656 | s->bus = bus; |
| 657 | |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 658 | memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, |
Benoît Canet | 8ea72f3 | 2011-10-17 17:28:30 +0200 | [diff] [blame] | 659 | "i2c", 0x1000); |
Andreas Färber | d94a401 | 2013-07-24 09:08:23 +0200 | [diff] [blame] | 660 | sysbus_init_mmio(sbd, &s->iomem); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 661 | /* ??? For now we only implement the master interface. */ |
| 662 | stellaris_i2c_reset(s); |
| 663 | } |
| 664 | |
| 665 | /* Analogue to Digital Converter. This is only partially implemented, |
| 666 | enough for applications that use a combined ADC and timer tick. */ |
| 667 | |
| 668 | #define STELLARIS_ADC_EM_CONTROLLER 0 |
| 669 | #define STELLARIS_ADC_EM_COMP 1 |
| 670 | #define STELLARIS_ADC_EM_EXTERNAL 4 |
| 671 | #define STELLARIS_ADC_EM_TIMER 5 |
| 672 | #define STELLARIS_ADC_EM_PWM0 6 |
| 673 | #define STELLARIS_ADC_EM_PWM1 7 |
| 674 | #define STELLARIS_ADC_EM_PWM2 8 |
| 675 | |
| 676 | #define STELLARIS_ADC_FIFO_EMPTY 0x0100 |
| 677 | #define STELLARIS_ADC_FIFO_FULL 0x1000 |
| 678 | |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 679 | #define TYPE_STELLARIS_ADC "stellaris-adc" |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 680 | typedef struct StellarisADCState StellarisADCState; |
| 681 | DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 682 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 683 | struct StellarisADCState { |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 684 | SysBusDevice parent_obj; |
| 685 | |
Benoît Canet | 71a2df0 | 2011-10-17 17:28:31 +0200 | [diff] [blame] | 686 | MemoryRegion iomem; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 687 | uint32_t actss; |
| 688 | uint32_t ris; |
| 689 | uint32_t im; |
| 690 | uint32_t emux; |
| 691 | uint32_t ostat; |
| 692 | uint32_t ustat; |
| 693 | uint32_t sspri; |
| 694 | uint32_t sac; |
| 695 | struct { |
| 696 | uint32_t state; |
| 697 | uint32_t data[16]; |
| 698 | } fifo[4]; |
| 699 | uint32_t ssmux[4]; |
| 700 | uint32_t ssctl[4]; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 701 | uint32_t noise; |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 702 | qemu_irq irq[4]; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 703 | }; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 704 | |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 705 | static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 706 | { |
| 707 | int tail; |
| 708 | |
| 709 | tail = s->fifo[n].state & 0xf; |
| 710 | if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { |
| 711 | s->ustat |= 1 << n; |
| 712 | } else { |
| 713 | s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); |
| 714 | s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; |
| 715 | if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) |
| 716 | s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; |
| 717 | } |
| 718 | return s->fifo[n].data[tail]; |
| 719 | } |
| 720 | |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 721 | static void stellaris_adc_fifo_write(StellarisADCState *s, int n, |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 722 | uint32_t value) |
| 723 | { |
| 724 | int head; |
| 725 | |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 726 | /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry |
| 727 | FIFO fir each sequencer. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 728 | head = (s->fifo[n].state >> 4) & 0xf; |
| 729 | if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { |
| 730 | s->ostat |= 1 << n; |
| 731 | return; |
| 732 | } |
| 733 | s->fifo[n].data[head] = value; |
| 734 | head = (head + 1) & 0xf; |
| 735 | s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; |
| 736 | s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); |
| 737 | if ((s->fifo[n].state & 0xf) == head) |
| 738 | s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; |
| 739 | } |
| 740 | |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 741 | static void stellaris_adc_update(StellarisADCState *s) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 742 | { |
| 743 | int level; |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 744 | int n; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 745 | |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 746 | for (n = 0; n < 4; n++) { |
| 747 | level = (s->ris & s->im & (1 << n)) != 0; |
| 748 | qemu_set_irq(s->irq[n], level); |
| 749 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | static void stellaris_adc_trigger(void *opaque, int irq, int level) |
| 753 | { |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 754 | StellarisADCState *s = opaque; |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 755 | int n; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 756 | |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 757 | for (n = 0; n < 4; n++) { |
| 758 | if ((s->actss & (1 << n)) == 0) { |
| 759 | continue; |
| 760 | } |
| 761 | |
| 762 | if (((s->emux >> (n * 4)) & 0xff) != 5) { |
| 763 | continue; |
| 764 | } |
| 765 | |
| 766 | /* Some applications use the ADC as a random number source, so introduce |
| 767 | some variation into the signal. */ |
| 768 | s->noise = s->noise * 314159 + 1; |
| 769 | /* ??? actual inputs not implemented. Return an arbitrary value. */ |
| 770 | stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); |
| 771 | s->ris |= (1 << n); |
| 772 | stellaris_adc_update(s); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 773 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 774 | } |
| 775 | |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 776 | static void stellaris_adc_reset(StellarisADCState *s) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 777 | { |
| 778 | int n; |
| 779 | |
| 780 | for (n = 0; n < 4; n++) { |
| 781 | s->ssmux[n] = 0; |
| 782 | s->ssctl[n] = 0; |
| 783 | s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; |
| 784 | } |
| 785 | } |
| 786 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 787 | static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, |
Benoît Canet | 71a2df0 | 2011-10-17 17:28:31 +0200 | [diff] [blame] | 788 | unsigned size) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 789 | { |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 790 | StellarisADCState *s = opaque; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 791 | |
| 792 | /* TODO: Implement this. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 793 | if (offset >= 0x40 && offset < 0xc0) { |
| 794 | int n; |
| 795 | n = (offset - 0x40) >> 5; |
| 796 | switch (offset & 0x1f) { |
| 797 | case 0x00: /* SSMUX */ |
| 798 | return s->ssmux[n]; |
| 799 | case 0x04: /* SSCTL */ |
| 800 | return s->ssctl[n]; |
| 801 | case 0x08: /* SSFIFO */ |
| 802 | return stellaris_adc_fifo_read(s, n); |
| 803 | case 0x0c: /* SSFSTAT */ |
| 804 | return s->fifo[n].state; |
| 805 | default: |
| 806 | break; |
| 807 | } |
| 808 | } |
| 809 | switch (offset) { |
| 810 | case 0x00: /* ACTSS */ |
| 811 | return s->actss; |
| 812 | case 0x04: /* RIS */ |
| 813 | return s->ris; |
| 814 | case 0x08: /* IM */ |
| 815 | return s->im; |
| 816 | case 0x0c: /* ISC */ |
| 817 | return s->ris & s->im; |
| 818 | case 0x10: /* OSTAT */ |
| 819 | return s->ostat; |
| 820 | case 0x14: /* EMUX */ |
| 821 | return s->emux; |
| 822 | case 0x18: /* USTAT */ |
| 823 | return s->ustat; |
| 824 | case 0x20: /* SSPRI */ |
| 825 | return s->sspri; |
| 826 | case 0x30: /* SAC */ |
| 827 | return s->sac; |
| 828 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 829 | qemu_log_mask(LOG_GUEST_ERROR, |
| 830 | "stellaris_adc: read at bad offset 0x%x\n", (int)offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 831 | return 0; |
| 832 | } |
| 833 | } |
| 834 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 835 | static void stellaris_adc_write(void *opaque, hwaddr offset, |
Benoît Canet | 71a2df0 | 2011-10-17 17:28:31 +0200 | [diff] [blame] | 836 | uint64_t value, unsigned size) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 837 | { |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 838 | StellarisADCState *s = opaque; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 839 | |
| 840 | /* TODO: Implement this. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 841 | if (offset >= 0x40 && offset < 0xc0) { |
| 842 | int n; |
| 843 | n = (offset - 0x40) >> 5; |
| 844 | switch (offset & 0x1f) { |
| 845 | case 0x00: /* SSMUX */ |
| 846 | s->ssmux[n] = value & 0x33333333; |
| 847 | return; |
| 848 | case 0x04: /* SSCTL */ |
| 849 | if (value != 6) { |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 850 | qemu_log_mask(LOG_UNIMP, |
| 851 | "ADC: Unimplemented sequence %" PRIx64 "\n", |
| 852 | value); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 853 | } |
| 854 | s->ssctl[n] = value; |
| 855 | return; |
| 856 | default: |
| 857 | break; |
| 858 | } |
| 859 | } |
| 860 | switch (offset) { |
| 861 | case 0x00: /* ACTSS */ |
| 862 | s->actss = value & 0xf; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 863 | break; |
| 864 | case 0x08: /* IM */ |
| 865 | s->im = value; |
| 866 | break; |
| 867 | case 0x0c: /* ISC */ |
| 868 | s->ris &= ~value; |
| 869 | break; |
| 870 | case 0x10: /* OSTAT */ |
| 871 | s->ostat &= ~value; |
| 872 | break; |
| 873 | case 0x14: /* EMUX */ |
| 874 | s->emux = value; |
| 875 | break; |
| 876 | case 0x18: /* USTAT */ |
| 877 | s->ustat &= ~value; |
| 878 | break; |
| 879 | case 0x20: /* SSPRI */ |
| 880 | s->sspri = value; |
| 881 | break; |
| 882 | case 0x28: /* PSSI */ |
Philippe Mathieu-Daudé | 9492e4b | 2018-06-08 13:15:33 +0100 | [diff] [blame] | 883 | qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 884 | break; |
| 885 | case 0x30: /* SAC */ |
| 886 | s->sac = value; |
| 887 | break; |
| 888 | default: |
Peter Maydell | df3692e | 2017-04-20 17:32:29 +0100 | [diff] [blame] | 889 | qemu_log_mask(LOG_GUEST_ERROR, |
| 890 | "stellaris_adc: write at bad offset 0x%x\n", (int)offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 891 | } |
| 892 | stellaris_adc_update(s); |
| 893 | } |
| 894 | |
Benoît Canet | 71a2df0 | 2011-10-17 17:28:31 +0200 | [diff] [blame] | 895 | static const MemoryRegionOps stellaris_adc_ops = { |
| 896 | .read = stellaris_adc_read, |
| 897 | .write = stellaris_adc_write, |
| 898 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 899 | }; |
| 900 | |
Juan Quintela | cf1d31d | 2010-12-03 01:27:58 +0100 | [diff] [blame] | 901 | static const VMStateDescription vmstate_stellaris_adc = { |
| 902 | .name = "stellaris_adc", |
| 903 | .version_id = 1, |
| 904 | .minimum_version_id = 1, |
Richard Henderson | 607ef57 | 2023-12-21 14:15:59 +1100 | [diff] [blame] | 905 | .fields = (const VMStateField[]) { |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 906 | VMSTATE_UINT32(actss, StellarisADCState), |
| 907 | VMSTATE_UINT32(ris, StellarisADCState), |
| 908 | VMSTATE_UINT32(im, StellarisADCState), |
| 909 | VMSTATE_UINT32(emux, StellarisADCState), |
| 910 | VMSTATE_UINT32(ostat, StellarisADCState), |
| 911 | VMSTATE_UINT32(ustat, StellarisADCState), |
| 912 | VMSTATE_UINT32(sspri, StellarisADCState), |
| 913 | VMSTATE_UINT32(sac, StellarisADCState), |
| 914 | VMSTATE_UINT32(fifo[0].state, StellarisADCState), |
| 915 | VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), |
| 916 | VMSTATE_UINT32(ssmux[0], StellarisADCState), |
| 917 | VMSTATE_UINT32(ssctl[0], StellarisADCState), |
| 918 | VMSTATE_UINT32(fifo[1].state, StellarisADCState), |
| 919 | VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), |
| 920 | VMSTATE_UINT32(ssmux[1], StellarisADCState), |
| 921 | VMSTATE_UINT32(ssctl[1], StellarisADCState), |
| 922 | VMSTATE_UINT32(fifo[2].state, StellarisADCState), |
| 923 | VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), |
| 924 | VMSTATE_UINT32(ssmux[2], StellarisADCState), |
| 925 | VMSTATE_UINT32(ssctl[2], StellarisADCState), |
| 926 | VMSTATE_UINT32(fifo[3].state, StellarisADCState), |
| 927 | VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), |
| 928 | VMSTATE_UINT32(ssmux[3], StellarisADCState), |
| 929 | VMSTATE_UINT32(ssctl[3], StellarisADCState), |
| 930 | VMSTATE_UINT32(noise, StellarisADCState), |
Juan Quintela | cf1d31d | 2010-12-03 01:27:58 +0100 | [diff] [blame] | 931 | VMSTATE_END_OF_LIST() |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 932 | } |
Juan Quintela | cf1d31d | 2010-12-03 01:27:58 +0100 | [diff] [blame] | 933 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 934 | |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 935 | static void stellaris_adc_init(Object *obj) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 936 | { |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 937 | DeviceState *dev = DEVICE(obj); |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 938 | StellarisADCState *s = STELLARIS_ADC(obj); |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 939 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 940 | int n; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 941 | |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 942 | for (n = 0; n < 4; n++) { |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 943 | sysbus_init_irq(sbd, &s->irq[n]); |
Paul Brook | 2c6554b | 2009-06-02 15:30:27 +0100 | [diff] [blame] | 944 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 945 | |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 946 | memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, |
Benoît Canet | 71a2df0 | 2011-10-17 17:28:31 +0200 | [diff] [blame] | 947 | "adc", 0x1000); |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 948 | sysbus_init_mmio(sbd, &s->iomem); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 949 | stellaris_adc_reset(s); |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 950 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 951 | } |
| 952 | |
| 953 | /* Board init. */ |
| 954 | static stellaris_board_info stellaris_boards[] = { |
| 955 | { "LM3S811EVB", |
| 956 | 0, |
| 957 | 0x0032000e, |
| 958 | 0x001f001f, /* dc0 */ |
| 959 | 0x001132bf, |
| 960 | 0x01071013, |
| 961 | 0x3f0f01ff, |
| 962 | 0x0000001f, |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 963 | BP_OLED_I2C |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 964 | }, |
| 965 | { "LM3S6965EVB", |
| 966 | 0x10010002, |
| 967 | 0x1073402e, |
| 968 | 0x00ff007f, /* dc0 */ |
| 969 | 0x001133ff, |
| 970 | 0x030f5317, |
| 971 | 0x0f0f87ff, |
| 972 | 0x5000007f, |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 973 | BP_OLED_SSI | BP_GAMEPAD |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 974 | } |
| 975 | }; |
| 976 | |
Igor Mammedov | ba1ba5c | 2017-09-13 18:04:57 +0200 | [diff] [blame] | 977 | static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 978 | { |
| 979 | static const int uart_irq[] = {5, 6, 33, 34}; |
| 980 | static const int timer_irq[] = {19, 21, 23, 35}; |
| 981 | static const uint32_t gpio_addr[7] = |
| 982 | { 0x40004000, 0x40005000, 0x40006000, 0x40007000, |
| 983 | 0x40024000, 0x40025000, 0x40026000}; |
| 984 | static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; |
| 985 | |
Peter Maydell | 394c8bb | 2017-02-07 18:30:00 +0000 | [diff] [blame] | 986 | /* Memory map of SoC devices, from |
| 987 | * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) |
| 988 | * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf |
| 989 | * |
Michel Heily | 566528f | 2019-03-05 01:16:22 +0200 | [diff] [blame] | 990 | * 40000000 wdtimer |
Peter Maydell | 394c8bb | 2017-02-07 18:30:00 +0000 | [diff] [blame] | 991 | * 40002000 i2c (unimplemented) |
| 992 | * 40004000 GPIO |
| 993 | * 40005000 GPIO |
| 994 | * 40006000 GPIO |
| 995 | * 40007000 GPIO |
| 996 | * 40008000 SSI |
| 997 | * 4000c000 UART |
| 998 | * 4000d000 UART |
| 999 | * 4000e000 UART |
| 1000 | * 40020000 i2c |
| 1001 | * 40021000 i2c (unimplemented) |
| 1002 | * 40024000 GPIO |
| 1003 | * 40025000 GPIO |
| 1004 | * 40026000 GPIO |
| 1005 | * 40028000 PWM (unimplemented) |
| 1006 | * 4002c000 QEI (unimplemented) |
| 1007 | * 4002d000 QEI (unimplemented) |
| 1008 | * 40030000 gptimer |
| 1009 | * 40031000 gptimer |
| 1010 | * 40032000 gptimer |
| 1011 | * 40033000 gptimer |
| 1012 | * 40038000 ADC |
| 1013 | * 4003c000 analogue comparator (unimplemented) |
| 1014 | * 40048000 ethernet |
| 1015 | * 400fc000 hibernation module (unimplemented) |
| 1016 | * 400fd000 flash memory control (unimplemented) |
| 1017 | * 400fe000 system control |
| 1018 | */ |
| 1019 | |
Michael Davidsaver | 20c59c3 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 1020 | DeviceState *gpio_dev[7], *nvic; |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1021 | qemu_irq gpio_in[7][8]; |
| 1022 | qemu_irq gpio_out[7][8]; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1023 | qemu_irq adc; |
| 1024 | int sram_size; |
| 1025 | int flash_size; |
Andreas Färber | a5c8285 | 2013-08-03 00:18:51 +0200 | [diff] [blame] | 1026 | I2CBus *i2c; |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1027 | DeviceState *dev; |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 1028 | DeviceState *ssys_dev; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1029 | int i; |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1030 | int j; |
Peter Maydell | 8ecda75 | 2021-08-12 10:33:48 +0100 | [diff] [blame] | 1031 | const uint8_t *macaddr; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1032 | |
Alistair Francis | fe6ac44 | 2015-02-05 13:37:21 +0000 | [diff] [blame] | 1033 | MemoryRegion *sram = g_new(MemoryRegion, 1); |
| 1034 | MemoryRegion *flash = g_new(MemoryRegion, 1); |
| 1035 | MemoryRegion *system_memory = get_system_memory(); |
| 1036 | |
| 1037 | flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; |
| 1038 | sram_size = ((board->dc0 >> 18) + 1) * 1024; |
| 1039 | |
| 1040 | /* Flash programming is done via the SCU, so pretend it is ROM. */ |
Philippe Mathieu-Daudé | 1626000 | 2020-02-24 19:50:18 +0100 | [diff] [blame] | 1041 | memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, |
Markus Armbruster | f8ed85a | 2015-09-11 16:51:43 +0200 | [diff] [blame] | 1042 | &error_fatal); |
Alistair Francis | fe6ac44 | 2015-02-05 13:37:21 +0000 | [diff] [blame] | 1043 | memory_region_add_subregion(system_memory, 0, flash); |
| 1044 | |
Peter Maydell | 98a99ce | 2017-07-07 15:42:53 +0100 | [diff] [blame] | 1045 | memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, |
Markus Armbruster | f8ed85a | 2015-09-11 16:51:43 +0200 | [diff] [blame] | 1046 | &error_fatal); |
Alistair Francis | fe6ac44 | 2015-02-05 13:37:21 +0000 | [diff] [blame] | 1047 | memory_region_add_subregion(system_memory, 0x20000000, sram); |
| 1048 | |
Peter Maydell | a861b3e | 2021-08-12 10:33:47 +0100 | [diff] [blame] | 1049 | /* |
| 1050 | * Create the system-registers object early, because we will |
| 1051 | * need its sysclk output. |
| 1052 | */ |
| 1053 | ssys_dev = qdev_new(TYPE_STELLARIS_SYS); |
| 1054 | /* Most devices come preprogrammed with a MAC address in the user data. */ |
| 1055 | macaddr = nd_table[0].macaddr.a; |
| 1056 | qdev_prop_set_uint32(ssys_dev, "user0", |
| 1057 | macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); |
| 1058 | qdev_prop_set_uint32(ssys_dev, "user1", |
| 1059 | macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); |
| 1060 | qdev_prop_set_uint32(ssys_dev, "did0", board->did0); |
| 1061 | qdev_prop_set_uint32(ssys_dev, "did1", board->did1); |
| 1062 | qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); |
| 1063 | qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); |
| 1064 | qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); |
| 1065 | qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); |
| 1066 | qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); |
| 1067 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); |
| 1068 | |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 1069 | nvic = qdev_new(TYPE_ARMV7M); |
Peter Maydell | f04d446 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 1070 | qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); |
Samuel Tardieu | 4a04655 | 2024-01-06 19:15:03 +0100 | [diff] [blame] | 1071 | qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); |
Peter Maydell | f04d446 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 1072 | qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); |
Stefan Hajnoczi | a1c5a06 | 2018-08-16 14:05:28 +0100 | [diff] [blame] | 1073 | qdev_prop_set_bit(nvic, "enable-bitband", true); |
Peter Maydell | 8ecda75 | 2021-08-12 10:33:48 +0100 | [diff] [blame] | 1074 | qdev_connect_clock_in(nvic, "cpuclk", |
| 1075 | qdev_get_clock_out(ssys_dev, "SYSCLK")); |
| 1076 | /* This SoC does not connect the systick reference clock */ |
Markus Armbruster | 5325cc3 | 2020-07-07 18:05:54 +0200 | [diff] [blame] | 1077 | object_property_set_link(OBJECT(nvic), "memory", |
| 1078 | OBJECT(get_system_memory()), &error_abort); |
Peter Maydell | f04d446 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 1079 | /* This will exit with an error if the user passed us a bad cpu_type */ |
Markus Armbruster | 3c6ef47 | 2020-06-10 07:32:34 +0200 | [diff] [blame] | 1080 | sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1081 | |
Peter Maydell | a861b3e | 2021-08-12 10:33:47 +0100 | [diff] [blame] | 1082 | /* Now we can wire up the IRQ and MMIO of the system registers */ |
| 1083 | sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); |
| 1084 | sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); |
| 1085 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1086 | if (board->dc1 & (1 << 16)) { |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 1087 | dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, |
Michael Davidsaver | 20c59c3 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 1088 | qdev_get_gpio_in(nvic, 14), |
| 1089 | qdev_get_gpio_in(nvic, 15), |
| 1090 | qdev_get_gpio_in(nvic, 16), |
| 1091 | qdev_get_gpio_in(nvic, 17), |
| 1092 | NULL); |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1093 | adc = qdev_get_gpio_in(dev, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1094 | } else { |
| 1095 | adc = NULL; |
| 1096 | } |
| 1097 | for (i = 0; i < 4; i++) { |
| 1098 | if (board->dc2 & (0x10000 << i)) { |
Peter Maydell | d18fdd6 | 2021-08-12 10:33:55 +0100 | [diff] [blame] | 1099 | SysBusDevice *sbd; |
| 1100 | |
| 1101 | dev = qdev_new(TYPE_STELLARIS_GPTM); |
| 1102 | sbd = SYS_BUS_DEVICE(dev); |
| 1103 | qdev_connect_clock_in(dev, "clk", |
| 1104 | qdev_get_clock_out(ssys_dev, "SYSCLK")); |
| 1105 | sysbus_realize_and_unref(sbd, &error_fatal); |
| 1106 | sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); |
| 1107 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1108 | /* TODO: This is incorrect, but we get away with it because |
| 1109 | the ADC output is only ever pulsed. */ |
| 1110 | qdev_connect_gpio_out(dev, 0, adc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1111 | } |
| 1112 | } |
| 1113 | |
Michel Heily | 566528f | 2019-03-05 01:16:22 +0200 | [diff] [blame] | 1114 | if (board->dc1 & (1 << 3)) { /* watchdog present */ |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 1115 | dev = qdev_new(TYPE_LUMINARY_WATCHDOG); |
Michel Heily | 566528f | 2019-03-05 01:16:22 +0200 | [diff] [blame] | 1116 | |
Peter Maydell | 1e31d8e | 2021-01-28 11:41:37 +0000 | [diff] [blame] | 1117 | qdev_connect_clock_in(dev, "WDOGCLK", |
| 1118 | qdev_get_clock_out(ssys_dev, "SYSCLK")); |
Michel Heily | 566528f | 2019-03-05 01:16:22 +0200 | [diff] [blame] | 1119 | |
Markus Armbruster | 3c6ef47 | 2020-06-10 07:32:34 +0200 | [diff] [blame] | 1120 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
Michel Heily | 566528f | 2019-03-05 01:16:22 +0200 | [diff] [blame] | 1121 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), |
| 1122 | 0, |
| 1123 | 0x40000000u); |
| 1124 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), |
| 1125 | 0, |
| 1126 | qdev_get_gpio_in(nvic, 18)); |
| 1127 | } |
| 1128 | |
| 1129 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1130 | for (i = 0; i < 7; i++) { |
| 1131 | if (board->dc4 & (1 << i)) { |
Peter Maydell | 7063f49 | 2011-02-21 20:57:51 +0000 | [diff] [blame] | 1132 | gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], |
Michael Davidsaver | 20c59c3 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 1133 | qdev_get_gpio_in(nvic, |
| 1134 | gpio_irq[i])); |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1135 | for (j = 0; j < 8; j++) { |
| 1136 | gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); |
| 1137 | gpio_out[i][j] = NULL; |
| 1138 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | if (board->dc2 & (1 << 12)) { |
Michael Davidsaver | 20c59c3 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 1143 | dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, |
| 1144 | qdev_get_gpio_in(nvic, 8)); |
Andreas Färber | a5c8285 | 2013-08-03 00:18:51 +0200 | [diff] [blame] | 1145 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 1146 | if (board->peripherals & BP_OLED_I2C) { |
Philippe Mathieu-Daudé | 1373b15 | 2020-07-06 00:41:53 +0200 | [diff] [blame] | 1147 | i2c_slave_create_simple(i2c, "ssd0303", 0x3d); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | for (i = 0; i < 4; i++) { |
| 1152 | if (board->dc2 & (1 << i)) { |
Philippe Mathieu-Daudé | b7f9309 | 2023-02-20 12:51:09 +0100 | [diff] [blame] | 1153 | SysBusDevice *sbd; |
| 1154 | |
| 1155 | dev = qdev_new("pl011_luminary"); |
| 1156 | sbd = SYS_BUS_DEVICE(dev); |
| 1157 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
| 1158 | sysbus_realize_and_unref(sbd, &error_fatal); |
| 1159 | sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); |
| 1160 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1161 | } |
| 1162 | } |
| 1163 | if (board->dc2 & (1 << 4)) { |
Michael Davidsaver | 20c59c3 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 1164 | dev = sysbus_create_simple("pl022", 0x40008000, |
| 1165 | qdev_get_gpio_in(nvic, 7)); |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 1166 | if (board->peripherals & BP_OLED_SSI) { |
Paul Brook | 5493e33 | 2009-05-14 22:35:09 +0100 | [diff] [blame] | 1167 | void *bus; |
Peter A. G. Crosthwaite | 8120e71 | 2012-07-31 16:42:04 +1000 | [diff] [blame] | 1168 | DeviceState *sddev; |
| 1169 | DeviceState *ssddev; |
Markus Armbruster | 36aa285 | 2021-11-17 17:33:57 +0100 | [diff] [blame] | 1170 | DriveInfo *dinfo; |
| 1171 | DeviceState *carddev; |
Zongyuan Li | d0a030d | 2022-03-25 02:15:55 +0800 | [diff] [blame] | 1172 | DeviceState *gpio_d_splitter; |
Markus Armbruster | 36aa285 | 2021-11-17 17:33:57 +0100 | [diff] [blame] | 1173 | BlockBackend *blk; |
pbrook | 775616c | 2007-11-24 23:35:08 +0000 | [diff] [blame] | 1174 | |
Peter Maydell | 5092e01 | 2021-07-02 11:40:18 +0100 | [diff] [blame] | 1175 | /* |
| 1176 | * Some boards have both an OLED controller and SD card connected to |
Peter A. G. Crosthwaite | 8120e71 | 2012-07-31 16:42:04 +1000 | [diff] [blame] | 1177 | * the same SSI port, with the SD card chip select connected to a |
| 1178 | * GPIO pin. Technically the OLED chip select is connected to the |
| 1179 | * SSI Fss pin. We do not bother emulating that as both devices |
| 1180 | * should never be selected simultaneously, and our OLED controller |
| 1181 | * ignores stray 0xff commands that occur when deselecting the SD |
| 1182 | * card. |
Peter Maydell | 5092e01 | 2021-07-02 11:40:18 +0100 | [diff] [blame] | 1183 | * |
| 1184 | * The h/w wiring is: |
| 1185 | * - GPIO pin D0 is wired to the active-low SD card chip select |
| 1186 | * - GPIO pin A3 is wired to the active-low OLED chip select |
| 1187 | * - The SoC wiring of the PL061 "auxiliary function" for A3 is |
| 1188 | * SSI0Fss ("frame signal"), which is an output from the SoC's |
| 1189 | * SSI controller. The SSI controller takes SSI0Fss low when it |
| 1190 | * transmits a frame, so it can work as a chip-select signal. |
| 1191 | * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx |
| 1192 | * (the OLED never sends data to the CPU, so no wiring needed) |
| 1193 | * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx |
| 1194 | * and the OLED display-data-in |
| 1195 | * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED |
| 1196 | * serial-clock input |
| 1197 | * So a guest that wants to use the OLED can configure the PL061 |
| 1198 | * to make pins A2, A3, A5 aux-function, so they are connected |
| 1199 | * directly to the SSI controller. When the SSI controller sends |
| 1200 | * data it asserts SSI0Fss which selects the OLED. |
| 1201 | * A guest that wants to use the SD card configures A2, A4 and A5 |
| 1202 | * as aux-function, but leaves A3 as a software-controlled GPIO |
| 1203 | * line. It asserts the SD card chip-select by using the PL061 |
| 1204 | * to control pin D0, and lets the SSI controller handle Clk, Tx |
| 1205 | * and Rx. (The SSI controller asserts Fss during tx cycles as |
| 1206 | * usual, but because A3 is not set to aux-function this is not |
| 1207 | * forwarded to the OLED, and so the OLED stays unselected.) |
| 1208 | * |
| 1209 | * The QEMU implementation instead is: |
| 1210 | * - GPIO pin D0 is wired to the active-low SD card chip select, |
| 1211 | * and also to the OLED chip-select which is implemented |
| 1212 | * as *active-high* |
| 1213 | * - SSI controller signals go to the devices regardless of |
| 1214 | * whether the guest programs A2, A4, A5 as aux-function or not |
| 1215 | * |
| 1216 | * The problem with this implementation is if the guest doesn't |
| 1217 | * care about the SD card and only uses the OLED. In that case it |
| 1218 | * may choose never to do anything with D0 (leaving it in its |
| 1219 | * default floating state, which reliably leaves the card disabled |
| 1220 | * because an SD card has a pullup on CS within the card itself), |
| 1221 | * and only set up A2, A3, A5. This for us would mean the OLED |
| 1222 | * never gets the chip-select assert it needs. We work around |
| 1223 | * this with a manual raise of D0 here (despite board creation |
| 1224 | * code being the wrong place to raise IRQ lines) to put the OLED |
| 1225 | * into an initially selected state. |
| 1226 | * |
| 1227 | * In theory the right way to model this would be: |
| 1228 | * - Implement aux-function support in the PL061, with an |
| 1229 | * extra set of AFIN and AFOUT GPIO lines (set up so that |
| 1230 | * if a GPIO line is in auxfn mode the main GPIO in and out |
| 1231 | * track the AFIN and AFOUT lines) |
| 1232 | * - Wire the AFOUT for D0 up to either a line from the |
| 1233 | * SSI controller that's pulled low around every transmit, |
| 1234 | * or at least to an always-0 line here on the board |
| 1235 | * - Make the ssd0323 OLED controller chipselect active-low |
Peter A. G. Crosthwaite | 8120e71 | 2012-07-31 16:42:04 +1000 | [diff] [blame] | 1236 | */ |
Paul Brook | 5493e33 | 2009-05-14 22:35:09 +0100 | [diff] [blame] | 1237 | bus = qdev_get_child_bus(dev, "ssi"); |
Philippe Mathieu-Daudé | ec7e429 | 2020-10-12 14:49:55 +0200 | [diff] [blame] | 1238 | sddev = ssi_create_peripheral(bus, "ssi-sd"); |
Markus Armbruster | 36aa285 | 2021-11-17 17:33:57 +0100 | [diff] [blame] | 1239 | |
| 1240 | dinfo = drive_get(IF_SD, 0, 0); |
| 1241 | blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; |
Cédric Le Goater | c3287c0 | 2023-07-03 08:00:08 +0200 | [diff] [blame] | 1242 | carddev = qdev_new(TYPE_SD_CARD_SPI); |
Markus Armbruster | 36aa285 | 2021-11-17 17:33:57 +0100 | [diff] [blame] | 1243 | qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); |
Markus Armbruster | 36aa285 | 2021-11-17 17:33:57 +0100 | [diff] [blame] | 1244 | qdev_realize_and_unref(carddev, |
| 1245 | qdev_get_child_bus(sddev, "sd-bus"), |
| 1246 | &error_fatal); |
| 1247 | |
Cédric Le Goater | a617e65 | 2023-06-07 06:39:38 +0200 | [diff] [blame] | 1248 | ssddev = qdev_new("ssd0323"); |
| 1249 | qdev_prop_set_uint8(ssddev, "cs", 1); |
| 1250 | qdev_realize_and_unref(ssddev, bus, &error_fatal); |
Zongyuan Li | d0a030d | 2022-03-25 02:15:55 +0800 | [diff] [blame] | 1251 | |
| 1252 | gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); |
| 1253 | qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); |
| 1254 | qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); |
| 1255 | qdev_connect_gpio_out( |
| 1256 | gpio_d_splitter, 0, |
| 1257 | qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); |
| 1258 | qdev_connect_gpio_out( |
| 1259 | gpio_d_splitter, 1, |
Peter Crosthwaite | de77914 | 2014-05-19 23:31:33 -0700 | [diff] [blame] | 1260 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); |
Zongyuan Li | d0a030d | 2022-03-25 02:15:55 +0800 | [diff] [blame] | 1261 | gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); |
| 1262 | |
Peter Crosthwaite | de77914 | 2014-05-19 23:31:33 -0700 | [diff] [blame] | 1263 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); |
Paul Brook | 5493e33 | 2009-05-14 22:35:09 +0100 | [diff] [blame] | 1264 | |
pbrook | 775616c | 2007-11-24 23:35:08 +0000 | [diff] [blame] | 1265 | /* Make sure the select pin is high. */ |
| 1266 | qemu_irq_raise(gpio_out[GPIO_D][0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1267 | } |
| 1268 | } |
Paul Brook | a558046 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 1269 | if (board->dc4 & (1 << 28)) { |
| 1270 | DeviceState *enet; |
| 1271 | |
| 1272 | qemu_check_nic_model(&nd_table[0], "stellaris"); |
| 1273 | |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 1274 | enet = qdev_new("stellaris_enet"); |
Gerd Hoffmann | 540f006 | 2009-10-21 15:25:39 +0200 | [diff] [blame] | 1275 | qdev_set_nic_properties(enet, &nd_table[0]); |
Markus Armbruster | 3c6ef47 | 2020-06-10 07:32:34 +0200 | [diff] [blame] | 1276 | sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 1277 | sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); |
Michael Davidsaver | 20c59c3 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 1278 | sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); |
Paul Brook | a558046 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 1279 | } |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 1280 | if (board->peripherals & BP_GAMEPAD) { |
Peter Maydell | a75f336 | 2023-10-30 11:48:01 +0000 | [diff] [blame] | 1281 | QList *gpad_keycode_list = qlist_new(); |
Peter Maydell | 7c76f39 | 2023-10-30 11:48:02 +0000 | [diff] [blame] | 1282 | static const int gpad_keycode[5] = { |
| 1283 | Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT, |
| 1284 | Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL, |
| 1285 | }; |
Peter Maydell | a75f336 | 2023-10-30 11:48:01 +0000 | [diff] [blame] | 1286 | DeviceState *gpad; |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 1287 | |
Peter Maydell | a75f336 | 2023-10-30 11:48:01 +0000 | [diff] [blame] | 1288 | gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); |
| 1289 | for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { |
| 1290 | qlist_append_int(gpad_keycode_list, gpad_keycode[i]); |
| 1291 | } |
| 1292 | qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list); |
| 1293 | sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal); |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 1294 | |
Peter Maydell | a75f336 | 2023-10-30 11:48:01 +0000 | [diff] [blame] | 1295 | qdev_connect_gpio_out(gpad, 0, |
| 1296 | qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ |
| 1297 | qdev_connect_gpio_out(gpad, 1, |
| 1298 | qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */ |
| 1299 | qdev_connect_gpio_out(gpad, 2, |
| 1300 | qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */ |
| 1301 | qdev_connect_gpio_out(gpad, 3, |
| 1302 | qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */ |
| 1303 | qdev_connect_gpio_out(gpad, 4, |
| 1304 | qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */ |
pbrook | cf0dbb2 | 2007-11-18 14:36:08 +0000 | [diff] [blame] | 1305 | } |
Paul Brook | 40905a6 | 2009-06-03 15:16:49 +0100 | [diff] [blame] | 1306 | for (i = 0; i < 7; i++) { |
| 1307 | if (board->dc4 & (1 << i)) { |
| 1308 | for (j = 0; j < 8; j++) { |
| 1309 | if (gpio_out[i][j]) { |
| 1310 | qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); |
| 1311 | } |
| 1312 | } |
| 1313 | } |
| 1314 | } |
Peter Maydell | aecfbbc | 2017-02-07 18:30:00 +0000 | [diff] [blame] | 1315 | |
| 1316 | /* Add dummy regions for the devices we don't implement yet, |
| 1317 | * so guest accesses don't cause unlogged crashes. |
| 1318 | */ |
Peter Maydell | aecfbbc | 2017-02-07 18:30:00 +0000 | [diff] [blame] | 1319 | create_unimplemented_device("i2c-0", 0x40002000, 0x1000); |
| 1320 | create_unimplemented_device("i2c-2", 0x40021000, 0x1000); |
| 1321 | create_unimplemented_device("PWM", 0x40028000, 0x1000); |
| 1322 | create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); |
| 1323 | create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); |
| 1324 | create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); |
| 1325 | create_unimplemented_device("hibernation", 0x400fc000, 0x1000); |
| 1326 | create_unimplemented_device("flash-control", 0x400fd000, 0x1000); |
Peter Maydell | f04d446 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 1327 | |
Peter Maydell | 761c532 | 2022-08-23 17:04:17 +0100 | [diff] [blame] | 1328 | armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1329 | } |
| 1330 | |
| 1331 | /* FIXME: Figure out how to generate these from stellaris_boards. */ |
Marcel Apfelbaum | 3ef9622 | 2014-05-07 17:42:57 +0300 | [diff] [blame] | 1332 | static void lm3s811evb_init(MachineState *machine) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1333 | { |
Igor Mammedov | ba1ba5c | 2017-09-13 18:04:57 +0200 | [diff] [blame] | 1334 | stellaris_init(machine, &stellaris_boards[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1335 | } |
| 1336 | |
Marcel Apfelbaum | 3ef9622 | 2014-05-07 17:42:57 +0300 | [diff] [blame] | 1337 | static void lm3s6965evb_init(MachineState *machine) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1338 | { |
Igor Mammedov | ba1ba5c | 2017-09-13 18:04:57 +0200 | [diff] [blame] | 1339 | stellaris_init(machine, &stellaris_boards[1]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1340 | } |
| 1341 | |
Andreas Färber | 8a661ae | 2015-09-19 10:49:44 +0200 | [diff] [blame] | 1342 | static void lm3s811evb_class_init(ObjectClass *oc, void *data) |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 1343 | { |
Andreas Färber | 8a661ae | 2015-09-19 10:49:44 +0200 | [diff] [blame] | 1344 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1345 | |
Philippe Mathieu-Daudé | fd8f71b | 2021-01-31 19:44:49 +0100 | [diff] [blame] | 1346 | mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 1347 | mc->init = lm3s811evb_init; |
Peter Maydell | 4672cbd | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 1348 | mc->ignore_memory_transaction_failures = true; |
Igor Mammedov | ba1ba5c | 2017-09-13 18:04:57 +0200 | [diff] [blame] | 1349 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 1350 | } |
| 1351 | |
Andreas Färber | 8a661ae | 2015-09-19 10:49:44 +0200 | [diff] [blame] | 1352 | static const TypeInfo lm3s811evb_type = { |
| 1353 | .name = MACHINE_TYPE_NAME("lm3s811evb"), |
| 1354 | .parent = TYPE_MACHINE, |
| 1355 | .class_init = lm3s811evb_class_init, |
| 1356 | }; |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 1357 | |
Andreas Färber | 8a661ae | 2015-09-19 10:49:44 +0200 | [diff] [blame] | 1358 | static void lm3s6965evb_class_init(ObjectClass *oc, void *data) |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 1359 | { |
Andreas Färber | 8a661ae | 2015-09-19 10:49:44 +0200 | [diff] [blame] | 1360 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1361 | |
Philippe Mathieu-Daudé | fd8f71b | 2021-01-31 19:44:49 +0100 | [diff] [blame] | 1362 | mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 1363 | mc->init = lm3s6965evb_init; |
Peter Maydell | 4672cbd | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 1364 | mc->ignore_memory_transaction_failures = true; |
Igor Mammedov | ba1ba5c | 2017-09-13 18:04:57 +0200 | [diff] [blame] | 1365 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
Eduardo Habkost | e264d29 | 2015-09-04 15:37:08 -0300 | [diff] [blame] | 1366 | } |
| 1367 | |
Andreas Färber | 8a661ae | 2015-09-19 10:49:44 +0200 | [diff] [blame] | 1368 | static const TypeInfo lm3s6965evb_type = { |
| 1369 | .name = MACHINE_TYPE_NAME("lm3s6965evb"), |
| 1370 | .parent = TYPE_MACHINE, |
| 1371 | .class_init = lm3s6965evb_class_init, |
| 1372 | }; |
| 1373 | |
| 1374 | static void stellaris_machine_init(void) |
| 1375 | { |
| 1376 | type_register_static(&lm3s811evb_type); |
| 1377 | type_register_static(&lm3s6965evb_type); |
| 1378 | } |
| 1379 | |
Eduardo Habkost | 0e6aac8 | 2016-02-16 18:59:04 -0200 | [diff] [blame] | 1380 | type_init(stellaris_machine_init) |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 1381 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1382 | static void stellaris_i2c_class_init(ObjectClass *klass, void *data) |
| 1383 | { |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 1384 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1385 | |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 1386 | dc->vmsd = &vmstate_stellaris_i2c; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1387 | } |
| 1388 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 1389 | static const TypeInfo stellaris_i2c_info = { |
Andreas Färber | d94a401 | 2013-07-24 09:08:23 +0200 | [diff] [blame] | 1390 | .name = TYPE_STELLARIS_I2C, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 1391 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1392 | .instance_size = sizeof(stellaris_i2c_state), |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 1393 | .instance_init = stellaris_i2c_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 1394 | .class_init = stellaris_i2c_class_init, |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1395 | }; |
| 1396 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1397 | static void stellaris_adc_class_init(ObjectClass *klass, void *data) |
| 1398 | { |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 1399 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1400 | |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 1401 | dc->vmsd = &vmstate_stellaris_adc; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1402 | } |
| 1403 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 1404 | static const TypeInfo stellaris_adc_info = { |
Andreas Färber | 7df7f67 | 2013-07-24 09:13:06 +0200 | [diff] [blame] | 1405 | .name = TYPE_STELLARIS_ADC, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 1406 | .parent = TYPE_SYS_BUS_DEVICE, |
Philippe Mathieu-Daudé | d6b109d | 2023-01-09 15:03:00 +0100 | [diff] [blame] | 1407 | .instance_size = sizeof(StellarisADCState), |
xiaoqiang.zhao | 15c4fff | 2016-03-07 15:05:48 +0800 | [diff] [blame] | 1408 | .instance_init = stellaris_adc_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 1409 | .class_init = stellaris_adc_class_init, |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 1410 | }; |
| 1411 | |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 1412 | static void stellaris_sys_class_init(ObjectClass *klass, void *data) |
| 1413 | { |
| 1414 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1415 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 1416 | |
| 1417 | dc->vmsd = &vmstate_stellaris_sys; |
| 1418 | rc->phases.enter = stellaris_sys_reset_enter; |
| 1419 | rc->phases.hold = stellaris_sys_reset_hold; |
| 1420 | rc->phases.exit = stellaris_sys_reset_exit; |
| 1421 | device_class_set_props(dc, stellaris_sys_properties); |
| 1422 | } |
| 1423 | |
| 1424 | static const TypeInfo stellaris_sys_info = { |
| 1425 | .name = TYPE_STELLARIS_SYS, |
| 1426 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1427 | .instance_size = sizeof(ssys_state), |
| 1428 | .instance_init = stellaris_sys_instance_init, |
| 1429 | .class_init = stellaris_sys_class_init, |
| 1430 | }; |
| 1431 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 1432 | static void stellaris_register_types(void) |
Paul Brook | 1de9610 | 2009-05-14 22:35:09 +0100 | [diff] [blame] | 1433 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 1434 | type_register_static(&stellaris_i2c_info); |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 1435 | type_register_static(&stellaris_adc_info); |
Peter Maydell | 4bebb9a | 2021-01-28 11:41:36 +0000 | [diff] [blame] | 1436 | type_register_static(&stellaris_sys_info); |
Paul Brook | 1de9610 | 2009-05-14 22:35:09 +0100 | [diff] [blame] | 1437 | } |
| 1438 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 1439 | type_init(stellaris_register_types) |