bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Crystal CS4231 audio chip emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 24 | |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 25 | #include "sysbus.h" |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 26 | |
| 27 | /* debug CS4231 */ |
| 28 | //#define DEBUG_CS |
| 29 | |
| 30 | /* |
| 31 | * In addition to Crystal CS4231 there is a DMA controller on Sparc. |
| 32 | */ |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 33 | #define CS_SIZE 0x40 |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 34 | #define CS_REGS 16 |
| 35 | #define CS_DREGS 32 |
| 36 | #define CS_MAXDREG (CS_DREGS - 1) |
| 37 | |
| 38 | typedef struct CSState { |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 39 | SysBusDevice busdev; |
| 40 | qemu_irq irq; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 41 | uint32_t regs[CS_REGS]; |
| 42 | uint8_t dregs[CS_DREGS]; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 43 | } CSState; |
| 44 | |
| 45 | #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
| 46 | #define CS_VER 0xa0 |
| 47 | #define CS_CDC_VER 0x8a |
| 48 | |
| 49 | #ifdef DEBUG_CS |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 50 | #define DPRINTF(fmt, ...) \ |
| 51 | do { printf("CS: " fmt , ## __VA_ARGS__); } while (0) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 52 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 53 | #define DPRINTF(fmt, ...) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 54 | #endif |
| 55 | |
Blue Swirl | 82d4c6e | 2009-10-24 16:20:32 +0000 | [diff] [blame] | 56 | static void cs_reset(DeviceState *d) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 57 | { |
Blue Swirl | 82d4c6e | 2009-10-24 16:20:32 +0000 | [diff] [blame] | 58 | CSState *s = container_of(d, CSState, busdev.qdev); |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 59 | |
| 60 | memset(s->regs, 0, CS_REGS * 4); |
| 61 | memset(s->dregs, 0, CS_DREGS); |
| 62 | s->dregs[12] = CS_CDC_VER; |
| 63 | s->dregs[25] = CS_VER; |
| 64 | } |
| 65 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 66 | static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 67 | { |
| 68 | CSState *s = opaque; |
| 69 | uint32_t saddr, ret; |
| 70 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 71 | saddr = addr >> 2; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 72 | switch (saddr) { |
| 73 | case 1: |
| 74 | switch (CS_RAP(s)) { |
| 75 | case 3: // Write only |
| 76 | ret = 0; |
| 77 | break; |
| 78 | default: |
| 79 | ret = s->dregs[CS_RAP(s)]; |
| 80 | break; |
| 81 | } |
| 82 | DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 83 | break; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 84 | default: |
| 85 | ret = s->regs[saddr]; |
| 86 | DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 87 | break; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 88 | } |
| 89 | return ret; |
| 90 | } |
| 91 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 92 | static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 93 | { |
| 94 | CSState *s = opaque; |
| 95 | uint32_t saddr; |
| 96 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 97 | saddr = addr >> 2; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 98 | DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val); |
| 99 | switch (saddr) { |
| 100 | case 1: |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 101 | DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), |
| 102 | s->dregs[CS_RAP(s)], val); |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 103 | switch(CS_RAP(s)) { |
| 104 | case 11: |
| 105 | case 25: // Read only |
| 106 | break; |
| 107 | case 12: |
| 108 | val &= 0x40; |
| 109 | val |= CS_CDC_VER; // Codec version |
| 110 | s->dregs[CS_RAP(s)] = val; |
| 111 | break; |
| 112 | default: |
| 113 | s->dregs[CS_RAP(s)] = val; |
| 114 | break; |
| 115 | } |
| 116 | break; |
| 117 | case 2: // Read only |
| 118 | break; |
| 119 | case 4: |
Blue Swirl | 82d4c6e | 2009-10-24 16:20:32 +0000 | [diff] [blame] | 120 | if (val & 1) { |
| 121 | cs_reset(&s->busdev.qdev); |
| 122 | } |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 123 | val &= 0x7f; |
| 124 | s->regs[saddr] = val; |
| 125 | break; |
| 126 | default: |
| 127 | s->regs[saddr] = val; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 128 | break; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 129 | } |
| 130 | } |
| 131 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 132 | static CPUReadMemoryFunc * const cs_mem_read[3] = { |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 133 | cs_mem_readl, |
| 134 | cs_mem_readl, |
| 135 | cs_mem_readl, |
| 136 | }; |
| 137 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 138 | static CPUWriteMemoryFunc * const cs_mem_write[3] = { |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 139 | cs_mem_writel, |
| 140 | cs_mem_writel, |
| 141 | cs_mem_writel, |
| 142 | }; |
| 143 | |
Blue Swirl | 82d4c6e | 2009-10-24 16:20:32 +0000 | [diff] [blame] | 144 | static const VMStateDescription vmstate_cs4231 = { |
| 145 | .name ="cs4231", |
| 146 | .version_id = 1, |
| 147 | .minimum_version_id = 1, |
| 148 | .minimum_version_id_old = 1, |
| 149 | .fields = (VMStateField []) { |
| 150 | VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS), |
| 151 | VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS), |
| 152 | VMSTATE_END_OF_LIST() |
| 153 | } |
| 154 | }; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 155 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 156 | static int cs4231_init1(SysBusDevice *dev) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 157 | { |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 158 | int io; |
| 159 | CSState *s = FROM_SYSBUS(CSState, dev); |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 160 | |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 161 | io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s); |
| 162 | sysbus_init_mmio(dev, CS_SIZE, io); |
| 163 | sysbus_init_irq(dev, &s->irq); |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 164 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 165 | return 0; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 166 | } |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 167 | |
| 168 | static SysBusDeviceInfo cs4231_info = { |
| 169 | .init = cs4231_init1, |
| 170 | .qdev.name = "SUNW,CS4231", |
| 171 | .qdev.size = sizeof(CSState), |
Blue Swirl | 82d4c6e | 2009-10-24 16:20:32 +0000 | [diff] [blame] | 172 | .qdev.vmsd = &vmstate_cs4231, |
| 173 | .qdev.reset = cs_reset, |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 174 | .qdev.props = (Property[]) { |
Blue Swirl | fa28ec5 | 2009-07-16 13:47:45 +0000 | [diff] [blame] | 175 | {.name = NULL} |
| 176 | } |
| 177 | }; |
| 178 | |
| 179 | static void cs4231_register_devices(void) |
| 180 | { |
| 181 | sysbus_register_withprop(&cs4231_info); |
| 182 | } |
| 183 | |
| 184 | device_init(cs4231_register_devices) |