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bellardb8174932006-09-10 19:25:12 +00001/*
2 * QEMU Crystal CS4231 audio chip emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirlfa28ec52009-07-16 13:47:45 +000024
Blue Swirlfa28ec52009-07-16 13:47:45 +000025#include "sysbus.h"
bellardb8174932006-09-10 19:25:12 +000026
27/* debug CS4231 */
28//#define DEBUG_CS
29
30/*
31 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
32 */
blueswir1e64d7d52008-12-02 17:47:02 +000033#define CS_SIZE 0x40
bellardb8174932006-09-10 19:25:12 +000034#define CS_REGS 16
35#define CS_DREGS 32
36#define CS_MAXDREG (CS_DREGS - 1)
37
38typedef struct CSState {
Blue Swirlfa28ec52009-07-16 13:47:45 +000039 SysBusDevice busdev;
40 qemu_irq irq;
bellardb8174932006-09-10 19:25:12 +000041 uint32_t regs[CS_REGS];
42 uint8_t dregs[CS_DREGS];
bellardb8174932006-09-10 19:25:12 +000043} CSState;
44
45#define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
46#define CS_VER 0xa0
47#define CS_CDC_VER 0x8a
48
49#ifdef DEBUG_CS
Blue Swirl001faf32009-05-13 17:53:17 +000050#define DPRINTF(fmt, ...) \
51 do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
bellardb8174932006-09-10 19:25:12 +000052#else
Blue Swirl001faf32009-05-13 17:53:17 +000053#define DPRINTF(fmt, ...)
bellardb8174932006-09-10 19:25:12 +000054#endif
55
Blue Swirl82d4c6e2009-10-24 16:20:32 +000056static void cs_reset(DeviceState *d)
bellardb8174932006-09-10 19:25:12 +000057{
Blue Swirl82d4c6e2009-10-24 16:20:32 +000058 CSState *s = container_of(d, CSState, busdev.qdev);
bellardb8174932006-09-10 19:25:12 +000059
60 memset(s->regs, 0, CS_REGS * 4);
61 memset(s->dregs, 0, CS_DREGS);
62 s->dregs[12] = CS_CDC_VER;
63 s->dregs[25] = CS_VER;
64}
65
Anthony Liguoric227f092009-10-01 16:12:16 -050066static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
bellardb8174932006-09-10 19:25:12 +000067{
68 CSState *s = opaque;
69 uint32_t saddr, ret;
70
blueswir1e64d7d52008-12-02 17:47:02 +000071 saddr = addr >> 2;
bellardb8174932006-09-10 19:25:12 +000072 switch (saddr) {
73 case 1:
74 switch (CS_RAP(s)) {
75 case 3: // Write only
76 ret = 0;
77 break;
78 default:
79 ret = s->dregs[CS_RAP(s)];
80 break;
81 }
82 DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
blueswir1f930d072007-10-06 11:28:21 +000083 break;
bellardb8174932006-09-10 19:25:12 +000084 default:
85 ret = s->regs[saddr];
86 DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
blueswir1f930d072007-10-06 11:28:21 +000087 break;
bellardb8174932006-09-10 19:25:12 +000088 }
89 return ret;
90}
91
Anthony Liguoric227f092009-10-01 16:12:16 -050092static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
bellardb8174932006-09-10 19:25:12 +000093{
94 CSState *s = opaque;
95 uint32_t saddr;
96
blueswir1e64d7d52008-12-02 17:47:02 +000097 saddr = addr >> 2;
bellardb8174932006-09-10 19:25:12 +000098 DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
99 switch (saddr) {
100 case 1:
blueswir177f193d2008-05-12 16:13:33 +0000101 DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
102 s->dregs[CS_RAP(s)], val);
bellardb8174932006-09-10 19:25:12 +0000103 switch(CS_RAP(s)) {
104 case 11:
105 case 25: // Read only
106 break;
107 case 12:
108 val &= 0x40;
109 val |= CS_CDC_VER; // Codec version
110 s->dregs[CS_RAP(s)] = val;
111 break;
112 default:
113 s->dregs[CS_RAP(s)] = val;
114 break;
115 }
116 break;
117 case 2: // Read only
118 break;
119 case 4:
Blue Swirl82d4c6e2009-10-24 16:20:32 +0000120 if (val & 1) {
121 cs_reset(&s->busdev.qdev);
122 }
bellardb8174932006-09-10 19:25:12 +0000123 val &= 0x7f;
124 s->regs[saddr] = val;
125 break;
126 default:
127 s->regs[saddr] = val;
blueswir1f930d072007-10-06 11:28:21 +0000128 break;
bellardb8174932006-09-10 19:25:12 +0000129 }
130}
131
Blue Swirld60efc62009-08-25 18:29:31 +0000132static CPUReadMemoryFunc * const cs_mem_read[3] = {
bellardb8174932006-09-10 19:25:12 +0000133 cs_mem_readl,
134 cs_mem_readl,
135 cs_mem_readl,
136};
137
Blue Swirld60efc62009-08-25 18:29:31 +0000138static CPUWriteMemoryFunc * const cs_mem_write[3] = {
bellardb8174932006-09-10 19:25:12 +0000139 cs_mem_writel,
140 cs_mem_writel,
141 cs_mem_writel,
142};
143
Blue Swirl82d4c6e2009-10-24 16:20:32 +0000144static const VMStateDescription vmstate_cs4231 = {
145 .name ="cs4231",
146 .version_id = 1,
147 .minimum_version_id = 1,
148 .minimum_version_id_old = 1,
149 .fields = (VMStateField []) {
150 VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
151 VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
152 VMSTATE_END_OF_LIST()
153 }
154};
bellardb8174932006-09-10 19:25:12 +0000155
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200156static int cs4231_init1(SysBusDevice *dev)
bellardb8174932006-09-10 19:25:12 +0000157{
Blue Swirlfa28ec52009-07-16 13:47:45 +0000158 int io;
159 CSState *s = FROM_SYSBUS(CSState, dev);
bellardb8174932006-09-10 19:25:12 +0000160
Blue Swirlfa28ec52009-07-16 13:47:45 +0000161 io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
162 sysbus_init_mmio(dev, CS_SIZE, io);
163 sysbus_init_irq(dev, &s->irq);
bellardb8174932006-09-10 19:25:12 +0000164
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200165 return 0;
bellardb8174932006-09-10 19:25:12 +0000166}
Blue Swirlfa28ec52009-07-16 13:47:45 +0000167
168static SysBusDeviceInfo cs4231_info = {
169 .init = cs4231_init1,
170 .qdev.name = "SUNW,CS4231",
171 .qdev.size = sizeof(CSState),
Blue Swirl82d4c6e2009-10-24 16:20:32 +0000172 .qdev.vmsd = &vmstate_cs4231,
173 .qdev.reset = cs_reset,
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200174 .qdev.props = (Property[]) {
Blue Swirlfa28ec52009-07-16 13:47:45 +0000175 {.name = NULL}
176 }
177};
178
179static void cs4231_register_devices(void)
180{
181 sysbus_register_withprop(&cs4231_info);
182}
183
184device_init(cs4231_register_devices)