bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Crystal CS4231 audio chip emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | #include "vl.h" |
| 25 | |
| 26 | /* debug CS4231 */ |
| 27 | //#define DEBUG_CS |
| 28 | |
| 29 | /* |
| 30 | * In addition to Crystal CS4231 there is a DMA controller on Sparc. |
| 31 | */ |
| 32 | #define CS_MAXADDR 0x3f |
blueswir1 | 5aca8c3 | 2007-05-26 17:39:43 +0000 | [diff] [blame] | 33 | #define CS_SIZE (CS_MAXADDR + 1) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 34 | #define CS_REGS 16 |
| 35 | #define CS_DREGS 32 |
| 36 | #define CS_MAXDREG (CS_DREGS - 1) |
| 37 | |
| 38 | typedef struct CSState { |
| 39 | uint32_t regs[CS_REGS]; |
| 40 | uint8_t dregs[CS_DREGS]; |
| 41 | void *intctl; |
| 42 | } CSState; |
| 43 | |
| 44 | #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
| 45 | #define CS_VER 0xa0 |
| 46 | #define CS_CDC_VER 0x8a |
| 47 | |
| 48 | #ifdef DEBUG_CS |
| 49 | #define DPRINTF(fmt, args...) \ |
| 50 | do { printf("CS: " fmt , ##args); } while (0) |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 51 | #else |
| 52 | #define DPRINTF(fmt, args...) |
| 53 | #endif |
| 54 | |
| 55 | static void cs_reset(void *opaque) |
| 56 | { |
| 57 | CSState *s = opaque; |
| 58 | |
| 59 | memset(s->regs, 0, CS_REGS * 4); |
| 60 | memset(s->dregs, 0, CS_DREGS); |
| 61 | s->dregs[12] = CS_CDC_VER; |
| 62 | s->dregs[25] = CS_VER; |
| 63 | } |
| 64 | |
| 65 | static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
| 66 | { |
| 67 | CSState *s = opaque; |
| 68 | uint32_t saddr, ret; |
| 69 | |
| 70 | saddr = (addr & CS_MAXADDR) >> 2; |
| 71 | switch (saddr) { |
| 72 | case 1: |
| 73 | switch (CS_RAP(s)) { |
| 74 | case 3: // Write only |
| 75 | ret = 0; |
| 76 | break; |
| 77 | default: |
| 78 | ret = s->dregs[CS_RAP(s)]; |
| 79 | break; |
| 80 | } |
| 81 | DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame^] | 82 | break; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 83 | default: |
| 84 | ret = s->regs[saddr]; |
| 85 | DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame^] | 86 | break; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 87 | } |
| 88 | return ret; |
| 89 | } |
| 90 | |
| 91 | static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 92 | { |
| 93 | CSState *s = opaque; |
| 94 | uint32_t saddr; |
| 95 | |
| 96 | saddr = (addr & CS_MAXADDR) >> 2; |
| 97 | DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val); |
| 98 | switch (saddr) { |
| 99 | case 1: |
| 100 | DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val); |
| 101 | switch(CS_RAP(s)) { |
| 102 | case 11: |
| 103 | case 25: // Read only |
| 104 | break; |
| 105 | case 12: |
| 106 | val &= 0x40; |
| 107 | val |= CS_CDC_VER; // Codec version |
| 108 | s->dregs[CS_RAP(s)] = val; |
| 109 | break; |
| 110 | default: |
| 111 | s->dregs[CS_RAP(s)] = val; |
| 112 | break; |
| 113 | } |
| 114 | break; |
| 115 | case 2: // Read only |
| 116 | break; |
| 117 | case 4: |
| 118 | if (val & 1) |
| 119 | cs_reset(s); |
| 120 | val &= 0x7f; |
| 121 | s->regs[saddr] = val; |
| 122 | break; |
| 123 | default: |
| 124 | s->regs[saddr] = val; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame^] | 125 | break; |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 126 | } |
| 127 | } |
| 128 | |
| 129 | static CPUReadMemoryFunc *cs_mem_read[3] = { |
| 130 | cs_mem_readl, |
| 131 | cs_mem_readl, |
| 132 | cs_mem_readl, |
| 133 | }; |
| 134 | |
| 135 | static CPUWriteMemoryFunc *cs_mem_write[3] = { |
| 136 | cs_mem_writel, |
| 137 | cs_mem_writel, |
| 138 | cs_mem_writel, |
| 139 | }; |
| 140 | |
| 141 | static void cs_save(QEMUFile *f, void *opaque) |
| 142 | { |
| 143 | CSState *s = opaque; |
| 144 | unsigned int i; |
| 145 | |
| 146 | for (i = 0; i < CS_REGS; i++) |
| 147 | qemu_put_be32s(f, &s->regs[i]); |
| 148 | |
| 149 | qemu_put_buffer(f, s->dregs, CS_DREGS); |
| 150 | } |
| 151 | |
| 152 | static int cs_load(QEMUFile *f, void *opaque, int version_id) |
| 153 | { |
| 154 | CSState *s = opaque; |
| 155 | unsigned int i; |
| 156 | |
| 157 | if (version_id > 1) |
| 158 | return -EINVAL; |
| 159 | |
| 160 | for (i = 0; i < CS_REGS; i++) |
| 161 | qemu_get_be32s(f, &s->regs[i]); |
| 162 | |
| 163 | qemu_get_buffer(f, s->dregs, CS_DREGS); |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | void cs_init(target_phys_addr_t base, int irq, void *intctl) |
| 168 | { |
| 169 | int cs_io_memory; |
| 170 | CSState *s; |
| 171 | |
| 172 | s = qemu_mallocz(sizeof(CSState)); |
| 173 | if (!s) |
| 174 | return; |
| 175 | |
| 176 | cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s); |
blueswir1 | 5aca8c3 | 2007-05-26 17:39:43 +0000 | [diff] [blame] | 177 | cpu_register_physical_memory(base, CS_SIZE, cs_io_memory); |
bellard | b817493 | 2006-09-10 19:25:12 +0000 | [diff] [blame] | 178 | register_savevm("cs4231", base, 1, cs_save, cs_load, s); |
| 179 | qemu_register_reset(cs_reset, s); |
| 180 | cs_reset(s); |
| 181 | } |