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Michael Clarka7240d12018-03-03 01:31:14 +13001/*
2 * SiFive U series machine interface
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef HW_SIFIVE_U_H
20#define HW_SIFIVE_U_H
21
Markus Armbruster7a5951f2022-12-22 13:08:11 +010022#include "hw/boards.h"
23#include "hw/cpu/cluster.h"
Bin Meng834e0272020-09-01 09:39:11 +080024#include "hw/dma/sifive_pdma.h"
Alistair Francis5a7f76a2018-04-26 13:59:08 -070025#include "hw/net/cadence_gem.h"
Markus Armbrusterec150c72019-08-12 07:23:31 +020026#include "hw/riscv/riscv_hart.h"
Bin Meng20f41c82019-09-06 09:20:02 -070027#include "hw/riscv/sifive_cpu.h"
Bin Meng4921a0c2020-09-03 18:40:15 +080028#include "hw/gpio/sifive_gpio.h"
Bin Meng0fa9e322020-09-03 18:40:14 +080029#include "hw/misc/sifive_u_otp.h"
Bin Meng9fe640a2020-09-03 18:40:13 +080030#include "hw/misc/sifive_u_prci.h"
Bin Meng145b2992021-01-26 14:00:02 +080031#include "hw/ssi/sifive_spi.h"
Alistair Francisea6eaa02021-09-09 13:55:15 +100032#include "hw/timer/sifive_pwm.h"
Alistair Francis5a7f76a2018-04-26 13:59:08 -070033
Alistair Francis23080922018-04-26 11:15:24 -070034#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
35#define RISCV_U_SOC(obj) \
36 OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
37
38typedef struct SiFiveUSoCState {
39 /*< private >*/
Markus Armbruster589b1be2020-06-09 14:23:35 +020040 DeviceState parent_obj;
Alistair Francis23080922018-04-26 11:15:24 -070041
42 /*< public >*/
Bin Mengecdfe392019-09-06 09:20:06 -070043 CPUClusterState e_cluster;
44 CPUClusterState u_cluster;
45 RISCVHartArrayState e_cpus;
46 RISCVHartArrayState u_cpus;
Alistair Francis23080922018-04-26 11:15:24 -070047 DeviceState *plic;
Bin Mengaf14c842019-09-06 09:20:10 -070048 SiFiveUPRCIState prci;
Bin Meng8a88b9f2020-06-08 07:17:36 -070049 SIFIVEGPIOState gpio;
Bin Meng5461c4f2019-09-06 09:20:16 -070050 SiFiveUOTPState otp;
Bin Meng834e0272020-09-01 09:39:11 +080051 SiFivePDMAState dma;
Bin Meng145b2992021-01-26 14:00:02 +080052 SiFiveSPIState spi0;
Bin Meng722f1352021-01-26 14:00:03 +080053 SiFiveSPIState spi2;
Alistair Francis5a7f76a2018-04-26 13:59:08 -070054 CadenceGEMState gem;
Alistair Francisea6eaa02021-09-09 13:55:15 +100055 SiFivePwmState pwm[2];
Alistair Francisfda5b002020-03-02 15:08:51 -080056
57 uint32_t serial;
Alistair Francis099be032020-10-13 17:17:25 -070058 char *cpu_type;
Alistair Francis23080922018-04-26 11:15:24 -070059} SiFiveUSoCState;
60
Alistair Francis687caef2019-10-08 16:32:14 -070061#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
62#define RISCV_U_MACHINE(obj) \
63 OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
64
Michael Clarka7240d12018-03-03 01:31:14 +130065typedef struct SiFiveUState {
66 /*< private >*/
Alistair Francis687caef2019-10-08 16:32:14 -070067 MachineState parent_obj;
Michael Clarka7240d12018-03-03 01:31:14 +130068
69 /*< public >*/
Alistair Francis23080922018-04-26 11:15:24 -070070 SiFiveUSoCState soc;
Bin Mengfc9ec362023-02-28 15:45:22 +080071 int fdt_size;
Alistair Francis687caef2019-10-08 16:32:14 -070072
Alistair Francisfc41ae22019-10-08 16:32:18 -070073 bool start_in_flash;
Bin Mengcfa32632020-06-08 07:17:40 -070074 uint32_t msel;
Bin Meng3ca109c2019-11-16 07:08:50 -080075 uint32_t serial;
Michael Clarka7240d12018-03-03 01:31:14 +130076} SiFiveUState;
77
78enum {
Eduardo Habkost13b8c352020-09-11 13:34:47 -040079 SIFIVE_U_DEV_DEBUG,
80 SIFIVE_U_DEV_MROM,
81 SIFIVE_U_DEV_CLINT,
82 SIFIVE_U_DEV_L2CC,
83 SIFIVE_U_DEV_PDMA,
84 SIFIVE_U_DEV_L2LIM,
85 SIFIVE_U_DEV_PLIC,
86 SIFIVE_U_DEV_PRCI,
87 SIFIVE_U_DEV_UART0,
88 SIFIVE_U_DEV_UART1,
89 SIFIVE_U_DEV_GPIO,
Bin Meng145b2992021-01-26 14:00:02 +080090 SIFIVE_U_DEV_QSPI0,
Bin Meng722f1352021-01-26 14:00:03 +080091 SIFIVE_U_DEV_QSPI2,
Eduardo Habkost13b8c352020-09-11 13:34:47 -040092 SIFIVE_U_DEV_OTP,
93 SIFIVE_U_DEV_DMC,
94 SIFIVE_U_DEV_FLASH0,
95 SIFIVE_U_DEV_DRAM,
96 SIFIVE_U_DEV_GEM,
Alistair Francisea6eaa02021-09-09 13:55:15 +100097 SIFIVE_U_DEV_GEM_MGMT,
98 SIFIVE_U_DEV_PWM0,
99 SIFIVE_U_DEV_PWM1
Michael Clarka7240d12018-03-03 01:31:14 +1300100};
101
102enum {
Bin Meng6eaf9cf2020-07-19 23:49:08 -0700103 SIFIVE_U_L2CC_IRQ0 = 1,
104 SIFIVE_U_L2CC_IRQ1 = 2,
105 SIFIVE_U_L2CC_IRQ2 = 3,
Bin Meng4b55bc22019-09-06 09:20:12 -0700106 SIFIVE_U_UART0_IRQ = 4,
107 SIFIVE_U_UART1_IRQ = 5,
Bin Meng722f1352021-01-26 14:00:03 +0800108 SIFIVE_U_QSPI2_IRQ = 6,
Bin Meng8a88b9f2020-06-08 07:17:36 -0700109 SIFIVE_U_GPIO_IRQ0 = 7,
110 SIFIVE_U_GPIO_IRQ1 = 8,
111 SIFIVE_U_GPIO_IRQ2 = 9,
112 SIFIVE_U_GPIO_IRQ3 = 10,
113 SIFIVE_U_GPIO_IRQ4 = 11,
114 SIFIVE_U_GPIO_IRQ5 = 12,
115 SIFIVE_U_GPIO_IRQ6 = 13,
116 SIFIVE_U_GPIO_IRQ7 = 14,
117 SIFIVE_U_GPIO_IRQ8 = 15,
118 SIFIVE_U_GPIO_IRQ9 = 16,
119 SIFIVE_U_GPIO_IRQ10 = 17,
120 SIFIVE_U_GPIO_IRQ11 = 18,
121 SIFIVE_U_GPIO_IRQ12 = 19,
122 SIFIVE_U_GPIO_IRQ13 = 20,
123 SIFIVE_U_GPIO_IRQ14 = 21,
124 SIFIVE_U_GPIO_IRQ15 = 22,
Bin Meng834e0272020-09-01 09:39:11 +0800125 SIFIVE_U_PDMA_IRQ0 = 23,
126 SIFIVE_U_PDMA_IRQ1 = 24,
127 SIFIVE_U_PDMA_IRQ2 = 25,
128 SIFIVE_U_PDMA_IRQ3 = 26,
129 SIFIVE_U_PDMA_IRQ4 = 27,
130 SIFIVE_U_PDMA_IRQ5 = 28,
131 SIFIVE_U_PDMA_IRQ6 = 29,
132 SIFIVE_U_PDMA_IRQ7 = 30,
Alistair Francisea6eaa02021-09-09 13:55:15 +1000133 SIFIVE_U_PWM0_IRQ0 = 42,
134 SIFIVE_U_PWM0_IRQ1 = 43,
135 SIFIVE_U_PWM0_IRQ2 = 44,
136 SIFIVE_U_PWM0_IRQ3 = 45,
137 SIFIVE_U_PWM1_IRQ0 = 46,
138 SIFIVE_U_PWM1_IRQ1 = 47,
139 SIFIVE_U_PWM1_IRQ2 = 48,
140 SIFIVE_U_PWM1_IRQ3 = 49,
Bin Meng145b2992021-01-26 14:00:02 +0800141 SIFIVE_U_QSPI0_IRQ = 51,
Bin Meng8e3c8862021-01-26 14:00:04 +0800142 SIFIVE_U_GEM_IRQ = 53
Michael Clarka7240d12018-03-03 01:31:14 +1300143};
144
Michael Clark2a8756e2018-03-03 14:30:07 +1300145enum {
Bin Menge1724d02019-09-06 09:20:09 -0700146 SIFIVE_U_HFCLK_FREQ = 33333333,
Bin Meng81e94372019-09-06 09:20:18 -0700147 SIFIVE_U_RTCCLK_FREQ = 1000000
Michael Clark2a8756e2018-03-03 14:30:07 +1300148};
149
Bin Meng17aad9f2020-06-15 17:50:39 -0700150enum {
151 MSEL_MEMMAP_QSPI0_FLASH = 1,
152 MSEL_L2LIM_QSPI0_FLASH = 6,
153 MSEL_L2LIM_QSPI2_SD = 11
154};
155
Bin Mengf3d47d52019-09-06 09:20:05 -0700156#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
Bin Mengecdfe392019-09-06 09:20:06 -0700157#define SIFIVE_U_COMPUTE_CPU_COUNT 4
Bin Mengf3d47d52019-09-06 09:20:05 -0700158
Alistair Francis0feb4a72019-04-04 18:15:23 +0000159#define SIFIVE_U_PLIC_NUM_SOURCES 54
Michael Clarka7240d12018-03-03 01:31:14 +1300160#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
Bin Meng5decd2c2022-12-11 11:08:27 +0800161#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
Michael Clarka7240d12018-03-03 01:31:14 +1300162#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
163#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
164#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
165#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
166#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
167
Michael Clarka7240d12018-03-03 01:31:14 +1300168#endif