Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 1 | /* |
| 2 | * SiFive U series machine interface |
| 3 | * |
| 4 | * Copyright (c) 2017 SiFive, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef HW_SIFIVE_U_H |
| 20 | #define HW_SIFIVE_U_H |
| 21 | |
Markus Armbruster | 7a5951f | 2022-12-22 13:08:11 +0100 | [diff] [blame] | 22 | #include "hw/boards.h" |
| 23 | #include "hw/cpu/cluster.h" |
Bin Meng | 834e027 | 2020-09-01 09:39:11 +0800 | [diff] [blame] | 24 | #include "hw/dma/sifive_pdma.h" |
Alistair Francis | 5a7f76a | 2018-04-26 13:59:08 -0700 | [diff] [blame] | 25 | #include "hw/net/cadence_gem.h" |
Markus Armbruster | ec150c7 | 2019-08-12 07:23:31 +0200 | [diff] [blame] | 26 | #include "hw/riscv/riscv_hart.h" |
Bin Meng | 20f41c8 | 2019-09-06 09:20:02 -0700 | [diff] [blame] | 27 | #include "hw/riscv/sifive_cpu.h" |
Bin Meng | 4921a0c | 2020-09-03 18:40:15 +0800 | [diff] [blame] | 28 | #include "hw/gpio/sifive_gpio.h" |
Bin Meng | 0fa9e32 | 2020-09-03 18:40:14 +0800 | [diff] [blame] | 29 | #include "hw/misc/sifive_u_otp.h" |
Bin Meng | 9fe640a | 2020-09-03 18:40:13 +0800 | [diff] [blame] | 30 | #include "hw/misc/sifive_u_prci.h" |
Bin Meng | 145b299 | 2021-01-26 14:00:02 +0800 | [diff] [blame] | 31 | #include "hw/ssi/sifive_spi.h" |
Alistair Francis | ea6eaa0 | 2021-09-09 13:55:15 +1000 | [diff] [blame] | 32 | #include "hw/timer/sifive_pwm.h" |
Alistair Francis | 5a7f76a | 2018-04-26 13:59:08 -0700 | [diff] [blame] | 33 | |
Alistair Francis | 2308092 | 2018-04-26 11:15:24 -0700 | [diff] [blame] | 34 | #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" |
| 35 | #define RISCV_U_SOC(obj) \ |
| 36 | OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) |
| 37 | |
| 38 | typedef struct SiFiveUSoCState { |
| 39 | /*< private >*/ |
Markus Armbruster | 589b1be | 2020-06-09 14:23:35 +0200 | [diff] [blame] | 40 | DeviceState parent_obj; |
Alistair Francis | 2308092 | 2018-04-26 11:15:24 -0700 | [diff] [blame] | 41 | |
| 42 | /*< public >*/ |
Bin Meng | ecdfe39 | 2019-09-06 09:20:06 -0700 | [diff] [blame] | 43 | CPUClusterState e_cluster; |
| 44 | CPUClusterState u_cluster; |
| 45 | RISCVHartArrayState e_cpus; |
| 46 | RISCVHartArrayState u_cpus; |
Alistair Francis | 2308092 | 2018-04-26 11:15:24 -0700 | [diff] [blame] | 47 | DeviceState *plic; |
Bin Meng | af14c84 | 2019-09-06 09:20:10 -0700 | [diff] [blame] | 48 | SiFiveUPRCIState prci; |
Bin Meng | 8a88b9f | 2020-06-08 07:17:36 -0700 | [diff] [blame] | 49 | SIFIVEGPIOState gpio; |
Bin Meng | 5461c4f | 2019-09-06 09:20:16 -0700 | [diff] [blame] | 50 | SiFiveUOTPState otp; |
Bin Meng | 834e027 | 2020-09-01 09:39:11 +0800 | [diff] [blame] | 51 | SiFivePDMAState dma; |
Bin Meng | 145b299 | 2021-01-26 14:00:02 +0800 | [diff] [blame] | 52 | SiFiveSPIState spi0; |
Bin Meng | 722f135 | 2021-01-26 14:00:03 +0800 | [diff] [blame] | 53 | SiFiveSPIState spi2; |
Alistair Francis | 5a7f76a | 2018-04-26 13:59:08 -0700 | [diff] [blame] | 54 | CadenceGEMState gem; |
Alistair Francis | ea6eaa0 | 2021-09-09 13:55:15 +1000 | [diff] [blame] | 55 | SiFivePwmState pwm[2]; |
Alistair Francis | fda5b00 | 2020-03-02 15:08:51 -0800 | [diff] [blame] | 56 | |
| 57 | uint32_t serial; |
Alistair Francis | 099be03 | 2020-10-13 17:17:25 -0700 | [diff] [blame] | 58 | char *cpu_type; |
Alistair Francis | 2308092 | 2018-04-26 11:15:24 -0700 | [diff] [blame] | 59 | } SiFiveUSoCState; |
| 60 | |
Alistair Francis | 687caef | 2019-10-08 16:32:14 -0700 | [diff] [blame] | 61 | #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") |
| 62 | #define RISCV_U_MACHINE(obj) \ |
| 63 | OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) |
| 64 | |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 65 | typedef struct SiFiveUState { |
| 66 | /*< private >*/ |
Alistair Francis | 687caef | 2019-10-08 16:32:14 -0700 | [diff] [blame] | 67 | MachineState parent_obj; |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 68 | |
| 69 | /*< public >*/ |
Alistair Francis | 2308092 | 2018-04-26 11:15:24 -0700 | [diff] [blame] | 70 | SiFiveUSoCState soc; |
Bin Meng | fc9ec36 | 2023-02-28 15:45:22 +0800 | [diff] [blame] | 71 | int fdt_size; |
Alistair Francis | 687caef | 2019-10-08 16:32:14 -0700 | [diff] [blame] | 72 | |
Alistair Francis | fc41ae2 | 2019-10-08 16:32:18 -0700 | [diff] [blame] | 73 | bool start_in_flash; |
Bin Meng | cfa3263 | 2020-06-08 07:17:40 -0700 | [diff] [blame] | 74 | uint32_t msel; |
Bin Meng | 3ca109c | 2019-11-16 07:08:50 -0800 | [diff] [blame] | 75 | uint32_t serial; |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 76 | } SiFiveUState; |
| 77 | |
| 78 | enum { |
Eduardo Habkost | 13b8c35 | 2020-09-11 13:34:47 -0400 | [diff] [blame] | 79 | SIFIVE_U_DEV_DEBUG, |
| 80 | SIFIVE_U_DEV_MROM, |
| 81 | SIFIVE_U_DEV_CLINT, |
| 82 | SIFIVE_U_DEV_L2CC, |
| 83 | SIFIVE_U_DEV_PDMA, |
| 84 | SIFIVE_U_DEV_L2LIM, |
| 85 | SIFIVE_U_DEV_PLIC, |
| 86 | SIFIVE_U_DEV_PRCI, |
| 87 | SIFIVE_U_DEV_UART0, |
| 88 | SIFIVE_U_DEV_UART1, |
| 89 | SIFIVE_U_DEV_GPIO, |
Bin Meng | 145b299 | 2021-01-26 14:00:02 +0800 | [diff] [blame] | 90 | SIFIVE_U_DEV_QSPI0, |
Bin Meng | 722f135 | 2021-01-26 14:00:03 +0800 | [diff] [blame] | 91 | SIFIVE_U_DEV_QSPI2, |
Eduardo Habkost | 13b8c35 | 2020-09-11 13:34:47 -0400 | [diff] [blame] | 92 | SIFIVE_U_DEV_OTP, |
| 93 | SIFIVE_U_DEV_DMC, |
| 94 | SIFIVE_U_DEV_FLASH0, |
| 95 | SIFIVE_U_DEV_DRAM, |
| 96 | SIFIVE_U_DEV_GEM, |
Alistair Francis | ea6eaa0 | 2021-09-09 13:55:15 +1000 | [diff] [blame] | 97 | SIFIVE_U_DEV_GEM_MGMT, |
| 98 | SIFIVE_U_DEV_PWM0, |
| 99 | SIFIVE_U_DEV_PWM1 |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | enum { |
Bin Meng | 6eaf9cf | 2020-07-19 23:49:08 -0700 | [diff] [blame] | 103 | SIFIVE_U_L2CC_IRQ0 = 1, |
| 104 | SIFIVE_U_L2CC_IRQ1 = 2, |
| 105 | SIFIVE_U_L2CC_IRQ2 = 3, |
Bin Meng | 4b55bc2 | 2019-09-06 09:20:12 -0700 | [diff] [blame] | 106 | SIFIVE_U_UART0_IRQ = 4, |
| 107 | SIFIVE_U_UART1_IRQ = 5, |
Bin Meng | 722f135 | 2021-01-26 14:00:03 +0800 | [diff] [blame] | 108 | SIFIVE_U_QSPI2_IRQ = 6, |
Bin Meng | 8a88b9f | 2020-06-08 07:17:36 -0700 | [diff] [blame] | 109 | SIFIVE_U_GPIO_IRQ0 = 7, |
| 110 | SIFIVE_U_GPIO_IRQ1 = 8, |
| 111 | SIFIVE_U_GPIO_IRQ2 = 9, |
| 112 | SIFIVE_U_GPIO_IRQ3 = 10, |
| 113 | SIFIVE_U_GPIO_IRQ4 = 11, |
| 114 | SIFIVE_U_GPIO_IRQ5 = 12, |
| 115 | SIFIVE_U_GPIO_IRQ6 = 13, |
| 116 | SIFIVE_U_GPIO_IRQ7 = 14, |
| 117 | SIFIVE_U_GPIO_IRQ8 = 15, |
| 118 | SIFIVE_U_GPIO_IRQ9 = 16, |
| 119 | SIFIVE_U_GPIO_IRQ10 = 17, |
| 120 | SIFIVE_U_GPIO_IRQ11 = 18, |
| 121 | SIFIVE_U_GPIO_IRQ12 = 19, |
| 122 | SIFIVE_U_GPIO_IRQ13 = 20, |
| 123 | SIFIVE_U_GPIO_IRQ14 = 21, |
| 124 | SIFIVE_U_GPIO_IRQ15 = 22, |
Bin Meng | 834e027 | 2020-09-01 09:39:11 +0800 | [diff] [blame] | 125 | SIFIVE_U_PDMA_IRQ0 = 23, |
| 126 | SIFIVE_U_PDMA_IRQ1 = 24, |
| 127 | SIFIVE_U_PDMA_IRQ2 = 25, |
| 128 | SIFIVE_U_PDMA_IRQ3 = 26, |
| 129 | SIFIVE_U_PDMA_IRQ4 = 27, |
| 130 | SIFIVE_U_PDMA_IRQ5 = 28, |
| 131 | SIFIVE_U_PDMA_IRQ6 = 29, |
| 132 | SIFIVE_U_PDMA_IRQ7 = 30, |
Alistair Francis | ea6eaa0 | 2021-09-09 13:55:15 +1000 | [diff] [blame] | 133 | SIFIVE_U_PWM0_IRQ0 = 42, |
| 134 | SIFIVE_U_PWM0_IRQ1 = 43, |
| 135 | SIFIVE_U_PWM0_IRQ2 = 44, |
| 136 | SIFIVE_U_PWM0_IRQ3 = 45, |
| 137 | SIFIVE_U_PWM1_IRQ0 = 46, |
| 138 | SIFIVE_U_PWM1_IRQ1 = 47, |
| 139 | SIFIVE_U_PWM1_IRQ2 = 48, |
| 140 | SIFIVE_U_PWM1_IRQ3 = 49, |
Bin Meng | 145b299 | 2021-01-26 14:00:02 +0800 | [diff] [blame] | 141 | SIFIVE_U_QSPI0_IRQ = 51, |
Bin Meng | 8e3c886 | 2021-01-26 14:00:04 +0800 | [diff] [blame] | 142 | SIFIVE_U_GEM_IRQ = 53 |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 143 | }; |
| 144 | |
Michael Clark | 2a8756e | 2018-03-03 14:30:07 +1300 | [diff] [blame] | 145 | enum { |
Bin Meng | e1724d0 | 2019-09-06 09:20:09 -0700 | [diff] [blame] | 146 | SIFIVE_U_HFCLK_FREQ = 33333333, |
Bin Meng | 81e9437 | 2019-09-06 09:20:18 -0700 | [diff] [blame] | 147 | SIFIVE_U_RTCCLK_FREQ = 1000000 |
Michael Clark | 2a8756e | 2018-03-03 14:30:07 +1300 | [diff] [blame] | 148 | }; |
| 149 | |
Bin Meng | 17aad9f | 2020-06-15 17:50:39 -0700 | [diff] [blame] | 150 | enum { |
| 151 | MSEL_MEMMAP_QSPI0_FLASH = 1, |
| 152 | MSEL_L2LIM_QSPI0_FLASH = 6, |
| 153 | MSEL_L2LIM_QSPI2_SD = 11 |
| 154 | }; |
| 155 | |
Bin Meng | f3d47d5 | 2019-09-06 09:20:05 -0700 | [diff] [blame] | 156 | #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 |
Bin Meng | ecdfe39 | 2019-09-06 09:20:06 -0700 | [diff] [blame] | 157 | #define SIFIVE_U_COMPUTE_CPU_COUNT 4 |
Bin Meng | f3d47d5 | 2019-09-06 09:20:05 -0700 | [diff] [blame] | 158 | |
Alistair Francis | 0feb4a7 | 2019-04-04 18:15:23 +0000 | [diff] [blame] | 159 | #define SIFIVE_U_PLIC_NUM_SOURCES 54 |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 160 | #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 |
Bin Meng | 5decd2c | 2022-12-11 11:08:27 +0800 | [diff] [blame] | 161 | #define SIFIVE_U_PLIC_PRIORITY_BASE 0x00 |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 162 | #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 |
| 163 | #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 |
| 164 | #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 |
| 165 | #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 |
| 166 | #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 |
| 167 | |
Michael Clark | a7240d1 | 2018-03-03 01:31:14 +1300 | [diff] [blame] | 168 | #endif |