1. fc9ec36 hw/riscv: Move the dtb load bits outside of create_fdt() by Bin Meng · 2 years ago
  2. 60c7dfa hw/riscv/sifive_u: use 'fdt' from MachineState by Daniel Henrique Barboza · 2 years, 2 months ago
  3. 7a5951f include: Include headers where needed by Markus Armbruster · 2 years, 2 months ago
  4. 5decd2c hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 by Bin Meng · 2 years, 3 months ago
  5. 4e8fb53 hw/riscv: sifive_u: Use the PLIC config helper function by Alistair Francis · 3 years, 4 months ago
  6. ea6eaa0 sifive_u: Connect the SiFive PWM device by Alistair Francis · 3 years, 6 months ago
  7. 8e3c886 hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value by Bin Meng · 4 years, 1 month ago
  8. 722f135 hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card by Bin Meng · 4 years, 1 month ago
  9. 145b299 hw/riscv: sifive_u: Add QSPI0 controller and connect a flash by Bin Meng · 4 years, 1 month ago
  10. 099be03 hw/riscv: sifive_u: Allow specifying the CPU by Alistair Francis · 4 years, 5 months ago
  11. 13b8c35 sifive_u: Rename memmap enum constants by Eduardo Habkost · 4 years, 6 months ago
  12. 4921a0c hw/riscv: Move sifive_gpio model to hw/gpio by Bin Meng · 4 years, 6 months ago
  13. 0fa9e32 hw/riscv: Move sifive_u_otp model to hw/misc by Bin Meng · 4 years, 6 months ago
  14. 9fe640a hw/riscv: Move sifive_u_prci model to hw/misc by Bin Meng · 4 years, 6 months ago
  15. 834e027 hw/riscv: sifive_u: Connect a DMA controller by Bin Meng · 4 years, 6 months ago
  16. 6eaf9cf hw/riscv: sifive_u: Add a dummy L2 cache controller device by Bin Meng · 4 years, 7 months ago
  17. 3eaea6e hw/riscv: sifive_u: Add a dummy DDR memory controller device by Bin Meng · 4 years, 9 months ago
  18. 17aad9f hw/riscv: sifive_u: Support different boot source per MSEL pin state by Bin Meng · 4 years, 9 months ago
  19. cfa3263 hw/riscv: sifive_u: Add a new property msel for MSEL pin state by Bin Meng · 4 years, 9 months ago
  20. 8a88b9f hw/riscv: sifive_u: Hook a GPIO controller by Bin Meng · 4 years, 9 months ago
  21. 589b1be riscv: Fix type of SiFive[EU]SocState, member parent_obj by Markus Armbruster · 4 years, 9 months ago
  22. 3ca109c riscv/sifive_u: Add a serial property to the sifive_u machine by Bin Meng · 5 years ago
  23. fda5b00 riscv/sifive_u: Add a serial property to the sifive_u SoC by Alistair Francis · 5 years ago
  24. fc41ae2 riscv/sifive_u: Add the start-in-flash property by Alistair Francis · 5 years ago
  25. 687caef riscv/sifive_u: Manually define the machine by Alistair Francis · 5 years ago
  26. 1b3a230 riscv/sifive_u: Add QSPI memory region by Alistair Francis · 5 years ago
  27. a6902ef riscv/sifive_u: Add L2-LIM cache memory by Alistair Francis · 5 years ago
  28. 7ae0537 riscv: hw: Drop "clock-frequency" property of cpu nodes by Bin Meng · 5 years ago
  29. 81e9437 riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet by Bin Meng · 5 years ago
  30. 7b6bb66 riscv: sifive_u: Fix broken GEM support by Bin Meng · 5 years ago
  31. 5461c4f riscv: sifive_u: Instantiate OTP memory with a serial number by Bin Meng · 5 years ago
  32. 4b55bc2 riscv: sifive_u: Update UART base addresses and IRQs by Bin Meng · 5 years ago
  33. af14c84 riscv: sifive_u: Add PRCI block to the SoC by Bin Meng · 5 years ago
  34. e1724d0 riscv: sifive_u: Generate hfclk and rtcclk nodes by Bin Meng · 5 years ago
  35. ecdfe39 riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC by Bin Meng · 5 years ago
  36. f3d47d5 riscv: sifive_u: Set the minimum number of cpus to 2 by Bin Meng · 5 years ago
  37. 20f41c8 riscv: Add a sifive_cpu.h to include both E and U cpu type defines by Bin Meng · 5 years ago
  38. ec150c7 include: Make headers more self-contained by Markus Armbruster · 6 years ago
  39. 0feb4a7 riscv: plic: Fix incorrect irq calculation by Alistair Francis · 6 years ago
  40. fe93582 sifive_u: Add clock DT node for GEM ethernet by Anup Patel · 6 years ago
  41. 5a7f76a hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device by Alistair Francis · 7 years ago
  42. 2308092 hw/riscv/sifive_u: Create a SiFive U SoC object by Alistair Francis · 7 years ago
  43. 42b3a4b RISC-V: Remove unused class definitions by Michael Clark · 7 years ago
  44. 2a8756e RISC-V: Replace hardcoded constants with enum values by Michael Clark · 7 years ago
  45. a7240d1 SiFive Freedom U Series RISC-V Machine by Michael Clark · 7 years ago