blob: 3e4da0c47fa16aa5e37ea76d0908a6076ef29b40 [file] [log] [blame]
bellard67e999b2006-09-03 16:09:07 +00001/*
2 * QEMU Sparc32 DMA controller emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +01006 * Modifications:
7 * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
8 *
bellard67e999b2006-09-03 16:09:07 +00009 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
Blue Swirl6f6260c2009-07-15 20:45:19 +000027
Peter Maydell04308912016-01-26 18:17:30 +000028#include "qemu/osdep.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020029#include "hw/irq.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020030#include "hw/qdev-properties.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010031#include "hw/sparc/sparc32_dma.h"
Mark Cave-Ayland1527f482018-01-08 18:16:34 +000032#include "hw/sparc/sun4m_iommu.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010033#include "hw/sysbus.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020034#include "migration/vmstate.h"
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010035#include "sysemu/dma.h"
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +010036#include "qapi/error.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020037#include "qemu/module.h"
Blue Swirl97bf4852010-10-31 09:24:14 +000038#include "trace.h"
bellard67e999b2006-09-03 16:09:07 +000039
40/*
41 * This is the DMA controller part of chip STP2000 (Master I/O), also
42 * produced as NCR89C100. See
43 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
44 * and
45 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
46 */
47
blueswir15aca8c32007-05-26 17:39:43 +000048#define DMA_SIZE (4 * sizeof(uint32_t))
blueswir109723aa2008-12-15 20:24:25 +000049/* We need the mask, because one instance of the device is not page
50 aligned (ledma, start address 0x0010) */
51#define DMA_MASK (DMA_SIZE - 1)
Bob Breuere0087e62010-12-20 11:55:33 -060052/* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
Bob Breuer86d1c382010-12-18 11:09:04 -060053#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
54#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
bellard67e999b2006-09-03 16:09:07 +000055
56#define DMA_VER 0xa0000000
57#define DMA_INTR 1
58#define DMA_INTREN 0x10
59#define DMA_WRITE_MEM 0x100
Blue Swirl73d74342010-09-11 16:38:33 +000060#define DMA_EN 0x200
bellard67e999b2006-09-03 16:09:07 +000061#define DMA_LOADED 0x04000000
blueswir15aca8c32007-05-26 17:39:43 +000062#define DMA_DRAIN_FIFO 0x40
bellard67e999b2006-09-03 16:09:07 +000063#define DMA_RESET 0x80
64
Artyom Tarasenko65899fe2010-05-22 10:38:56 +020065/* XXX SCSI and ethernet should have different read-only bit masks */
66#define DMA_CSR_RO_MASK 0xfe000007
67
Blue Swirl73d74342010-09-11 16:38:33 +000068enum {
69 GPIO_RESET = 0,
70 GPIO_DMA,
bellard67e999b2006-09-03 16:09:07 +000071};
72
bellard9b94dc32006-09-03 19:48:17 +000073/* Note: on sparc, the lance 16 bit bus is swapped */
Avi Kivitya8170e52012-10-23 12:30:10 +020074void ledma_memory_read(void *opaque, hwaddr addr,
bellard9b94dc32006-09-03 19:48:17 +000075 uint8_t *buf, int len, int do_bswap)
bellard67e999b2006-09-03 16:09:07 +000076{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +010077 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010078 IOMMUState *is = (IOMMUState *)s->iommu;
bellard9b94dc32006-09-03 19:48:17 +000079 int i;
bellard67e999b2006-09-03 16:09:07 +000080
blueswir15aca8c32007-05-26 17:39:43 +000081 addr |= s->dmaregs[3];
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +010082 trace_ledma_memory_read(addr, len);
bellard9b94dc32006-09-03 19:48:17 +000083 if (do_bswap) {
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010084 dma_memory_read(&is->iommu_as, addr, buf, len);
bellard9b94dc32006-09-03 19:48:17 +000085 } else {
86 addr &= ~1;
87 len &= ~1;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010088 dma_memory_read(&is->iommu_as, addr, buf, len);
bellard9b94dc32006-09-03 19:48:17 +000089 for(i = 0; i < len; i += 2) {
90 bswap16s((uint16_t *)(buf + i));
91 }
92 }
bellard67e999b2006-09-03 16:09:07 +000093}
94
Avi Kivitya8170e52012-10-23 12:30:10 +020095void ledma_memory_write(void *opaque, hwaddr addr,
bellard9b94dc32006-09-03 19:48:17 +000096 uint8_t *buf, int len, int do_bswap)
bellard67e999b2006-09-03 16:09:07 +000097{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +010098 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010099 IOMMUState *is = (IOMMUState *)s->iommu;
bellard9b94dc32006-09-03 19:48:17 +0000100 int l, i;
101 uint16_t tmp_buf[32];
bellard67e999b2006-09-03 16:09:07 +0000102
blueswir15aca8c32007-05-26 17:39:43 +0000103 addr |= s->dmaregs[3];
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +0100104 trace_ledma_memory_write(addr, len);
bellard9b94dc32006-09-03 19:48:17 +0000105 if (do_bswap) {
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100106 dma_memory_write(&is->iommu_as, addr, buf, len);
bellard9b94dc32006-09-03 19:48:17 +0000107 } else {
108 addr &= ~1;
109 len &= ~1;
110 while (len > 0) {
111 l = len;
112 if (l > sizeof(tmp_buf))
113 l = sizeof(tmp_buf);
114 for(i = 0; i < l; i += 2) {
115 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
116 }
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100117 dma_memory_write(&is->iommu_as, addr, tmp_buf, l);
bellard9b94dc32006-09-03 19:48:17 +0000118 len -= l;
119 buf += l;
120 addr += l;
121 }
122 }
bellard67e999b2006-09-03 16:09:07 +0000123}
124
blueswir170c0de92007-05-27 16:36:10 +0000125static void dma_set_irq(void *opaque, int irq, int level)
bellard67e999b2006-09-03 16:09:07 +0000126{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100127 DMADeviceState *s = opaque;
blueswir170c0de92007-05-27 16:36:10 +0000128 if (level) {
blueswir170c0de92007-05-27 16:36:10 +0000129 s->dmaregs[0] |= DMA_INTR;
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100130 if (s->dmaregs[0] & DMA_INTREN) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000131 trace_sparc32_dma_set_irq_raise();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100132 qemu_irq_raise(s->irq);
133 }
blueswir170c0de92007-05-27 16:36:10 +0000134 } else {
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100135 if (s->dmaregs[0] & DMA_INTR) {
136 s->dmaregs[0] &= ~DMA_INTR;
137 if (s->dmaregs[0] & DMA_INTREN) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000138 trace_sparc32_dma_set_irq_lower();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100139 qemu_irq_lower(s->irq);
140 }
141 }
blueswir170c0de92007-05-27 16:36:10 +0000142 }
bellard67e999b2006-09-03 16:09:07 +0000143}
144
145void espdma_memory_read(void *opaque, uint8_t *buf, int len)
146{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100147 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100148 IOMMUState *is = (IOMMUState *)s->iommu;
bellard67e999b2006-09-03 16:09:07 +0000149
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +0100150 trace_espdma_memory_read(s->dmaregs[1], len);
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100151 dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len);
bellard67e999b2006-09-03 16:09:07 +0000152 s->dmaregs[1] += len;
153}
154
155void espdma_memory_write(void *opaque, uint8_t *buf, int len)
156{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100157 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100158 IOMMUState *is = (IOMMUState *)s->iommu;
bellard67e999b2006-09-03 16:09:07 +0000159
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +0100160 trace_espdma_memory_write(s->dmaregs[1], len);
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100161 dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len);
bellard67e999b2006-09-03 16:09:07 +0000162 s->dmaregs[1] += len;
163}
164
Avi Kivitya8170e52012-10-23 12:30:10 +0200165static uint64_t dma_mem_read(void *opaque, hwaddr addr,
Avi Kivityd6c5f062011-11-14 11:55:27 +0200166 unsigned size)
bellard67e999b2006-09-03 16:09:07 +0000167{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100168 DMADeviceState *s = opaque;
bellard67e999b2006-09-03 16:09:07 +0000169 uint32_t saddr;
170
blueswir109723aa2008-12-15 20:24:25 +0000171 saddr = (addr & DMA_MASK) >> 2;
Blue Swirl97bf4852010-10-31 09:24:14 +0000172 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
bellard67e999b2006-09-03 16:09:07 +0000173 return s->dmaregs[saddr];
174}
175
Avi Kivitya8170e52012-10-23 12:30:10 +0200176static void dma_mem_write(void *opaque, hwaddr addr,
Avi Kivityd6c5f062011-11-14 11:55:27 +0200177 uint64_t val, unsigned size)
bellard67e999b2006-09-03 16:09:07 +0000178{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100179 DMADeviceState *s = opaque;
bellard67e999b2006-09-03 16:09:07 +0000180 uint32_t saddr;
181
blueswir109723aa2008-12-15 20:24:25 +0000182 saddr = (addr & DMA_MASK) >> 2;
Blue Swirl97bf4852010-10-31 09:24:14 +0000183 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
bellard67e999b2006-09-03 16:09:07 +0000184 switch (saddr) {
185 case 0:
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100186 if (val & DMA_INTREN) {
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200187 if (s->dmaregs[0] & DMA_INTR) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000188 trace_sparc32_dma_set_irq_raise();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100189 qemu_irq_raise(s->irq);
190 }
191 } else {
192 if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000193 trace_sparc32_dma_set_irq_lower();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100194 qemu_irq_lower(s->irq);
195 }
pbrookd537cf62007-04-07 18:14:41 +0000196 }
bellard67e999b2006-09-03 16:09:07 +0000197 if (val & DMA_RESET) {
Blue Swirl73d74342010-09-11 16:38:33 +0000198 qemu_irq_raise(s->gpio[GPIO_RESET]);
199 qemu_irq_lower(s->gpio[GPIO_RESET]);
blueswir15aca8c32007-05-26 17:39:43 +0000200 } else if (val & DMA_DRAIN_FIFO) {
201 val &= ~DMA_DRAIN_FIFO;
bellard67e999b2006-09-03 16:09:07 +0000202 } else if (val == 0)
blueswir15aca8c32007-05-26 17:39:43 +0000203 val = DMA_DRAIN_FIFO;
Blue Swirl73d74342010-09-11 16:38:33 +0000204
205 if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000206 trace_sparc32_dma_enable_raise();
Blue Swirl73d74342010-09-11 16:38:33 +0000207 qemu_irq_raise(s->gpio[GPIO_DMA]);
208 } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000209 trace_sparc32_dma_enable_lower();
Blue Swirl73d74342010-09-11 16:38:33 +0000210 qemu_irq_lower(s->gpio[GPIO_DMA]);
211 }
212
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200213 val &= ~DMA_CSR_RO_MASK;
bellard67e999b2006-09-03 16:09:07 +0000214 val |= DMA_VER;
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200215 s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
bellard67e999b2006-09-03 16:09:07 +0000216 break;
217 case 1:
218 s->dmaregs[0] |= DMA_LOADED;
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200219 /* fall through */
bellard67e999b2006-09-03 16:09:07 +0000220 default:
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200221 s->dmaregs[saddr] = val;
bellard67e999b2006-09-03 16:09:07 +0000222 break;
223 }
bellard67e999b2006-09-03 16:09:07 +0000224}
225
Avi Kivityd6c5f062011-11-14 11:55:27 +0200226static const MemoryRegionOps dma_mem_ops = {
227 .read = dma_mem_read,
228 .write = dma_mem_write,
229 .endianness = DEVICE_NATIVE_ENDIAN,
230 .valid = {
231 .min_access_size = 4,
232 .max_access_size = 4,
233 },
bellard67e999b2006-09-03 16:09:07 +0000234};
235
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100236static void sparc32_dma_device_reset(DeviceState *d)
bellard67e999b2006-09-03 16:09:07 +0000237{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100238 DMADeviceState *s = SPARC32_DMA_DEVICE(d);
bellard67e999b2006-09-03 16:09:07 +0000239
blueswir15aca8c32007-05-26 17:39:43 +0000240 memset(s->dmaregs, 0, DMA_SIZE);
bellard67e999b2006-09-03 16:09:07 +0000241 s->dmaregs[0] = DMA_VER;
bellard67e999b2006-09-03 16:09:07 +0000242}
243
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100244static const VMStateDescription vmstate_sparc32_dma_device = {
Blue Swirl75c497d2009-08-28 20:46:15 +0000245 .name ="sparc32_dma",
246 .version_id = 2,
247 .minimum_version_id = 2,
Juan Quintela35d08452014-04-16 16:01:33 +0200248 .fields = (VMStateField[]) {
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100249 VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
Blue Swirl75c497d2009-08-28 20:46:15 +0000250 VMSTATE_END_OF_LIST()
251 }
252};
bellard67e999b2006-09-03 16:09:07 +0000253
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100254static void sparc32_dma_device_init(Object *obj)
Blue Swirl6f6260c2009-07-15 20:45:19 +0000255{
xiaoqiang zhao8c612072017-05-25 21:34:45 +0800256 DeviceState *dev = DEVICE(obj);
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100257 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
xiaoqiang zhao8c612072017-05-25 21:34:45 +0800258 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
bellard67e999b2006-09-03 16:09:07 +0000259
Andreas Färber70cd8d42013-07-26 16:55:59 +0200260 sysbus_init_irq(sbd, &s->irq);
bellard67e999b2006-09-03 16:09:07 +0000261
Andreas Färber70cd8d42013-07-26 16:55:59 +0200262 sysbus_init_mmio(sbd, &s->iomem);
bellard67e999b2006-09-03 16:09:07 +0000263
Mark Cave-Aylandf542ad02017-10-14 13:22:21 +0100264 object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
265 (Object **) &s->iommu,
266 qdev_prop_allow_set_link_before_realize,
267 0, NULL);
268
Andreas Färber70cd8d42013-07-26 16:55:59 +0200269 qdev_init_gpio_in(dev, dma_set_irq, 1);
270 qdev_init_gpio_out(dev, s->gpio, 2);
xiaoqiang zhao8c612072017-05-25 21:34:45 +0800271}
Blue Swirl49ef6c92009-10-24 19:35:32 +0000272
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100273static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
Anthony Liguori999e12b2012-01-24 13:12:29 -0600274{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600275 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600276
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100277 dc->reset = sparc32_dma_device_reset;
278 dc->vmsd = &vmstate_sparc32_dma_device;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600279}
280
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100281static const TypeInfo sparc32_dma_device_info = {
282 .name = TYPE_SPARC32_DMA_DEVICE,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600283 .parent = TYPE_SYS_BUS_DEVICE,
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100284 .abstract = true,
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100285 .instance_size = sizeof(DMADeviceState),
286 .instance_init = sparc32_dma_device_init,
287 .class_init = sparc32_dma_device_class_init,
Blue Swirl6f6260c2009-07-15 20:45:19 +0000288};
289
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100290static void sparc32_espdma_device_init(Object *obj)
291{
292 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
293
294 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
295 "espdma-mmio", DMA_SIZE);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100296}
297
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100298static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
299{
300 DeviceState *d;
301 SysBusESPState *sysbus;
302 ESPState *esp;
303
304 d = qdev_create(NULL, TYPE_ESP);
305 object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);
306 sysbus = ESP_STATE(d);
307 esp = &sysbus->esp;
308 esp->dma_memory_read = espdma_memory_read;
309 esp->dma_memory_write = espdma_memory_write;
310 esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
311 sysbus->it_shift = 2;
312 esp->dma_enabled = 1;
313 qdev_init_nofail(d);
314}
315
316static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
317{
318 DeviceClass *dc = DEVICE_CLASS(klass);
319
320 dc->realize = sparc32_espdma_device_realize;
321}
322
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100323static const TypeInfo sparc32_espdma_device_info = {
324 .name = TYPE_SPARC32_ESPDMA_DEVICE,
325 .parent = TYPE_SPARC32_DMA_DEVICE,
326 .instance_size = sizeof(ESPDMADeviceState),
327 .instance_init = sparc32_espdma_device_init,
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100328 .class_init = sparc32_espdma_device_class_init,
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100329};
330
331static void sparc32_ledma_device_init(Object *obj)
332{
333 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
334
335 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
Mark Cave-Ayland4ca3d362017-10-14 13:22:22 +0100336 "ledma-mmio", DMA_SIZE);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100337}
338
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100339static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
340{
341 DeviceState *d;
342 NICInfo *nd = &nd_table[0];
343
344 qemu_check_nic_model(nd, TYPE_LANCE);
345
346 d = qdev_create(NULL, TYPE_LANCE);
347 object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
348 qdev_set_nic_properties(d, nd);
Marc-André Lureau4cc76282019-10-17 17:31:48 +0200349 object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp);
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100350 qdev_init_nofail(d);
351}
352
353static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
354{
355 DeviceClass *dc = DEVICE_CLASS(klass);
356
357 dc->realize = sparc32_ledma_device_realize;
358}
359
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100360static const TypeInfo sparc32_ledma_device_info = {
361 .name = TYPE_SPARC32_LEDMA_DEVICE,
362 .parent = TYPE_SPARC32_DMA_DEVICE,
363 .instance_size = sizeof(LEDMADeviceState),
364 .instance_init = sparc32_ledma_device_init,
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100365 .class_init = sparc32_ledma_device_class_init,
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100366};
367
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100368static void sparc32_dma_realize(DeviceState *dev, Error **errp)
369{
370 SPARC32DMAState *s = SPARC32_DMA(dev);
371 DeviceState *espdma, *esp, *ledma, *lance;
372 SysBusDevice *sbd;
373 Object *iommu;
374
375 iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
376 if (!iommu) {
377 error_setg(errp, "unable to locate sun4m IOMMU device");
378 return;
379 }
380
381 espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
382 object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
383 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp);
384 qdev_init_nofail(espdma);
385
386 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
387 sbd = SYS_BUS_DEVICE(esp);
388 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
389 qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
390 qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
391
392 sbd = SYS_BUS_DEVICE(espdma);
393 memory_region_add_subregion(&s->dmamem, 0x0,
394 sysbus_mmio_get_region(sbd, 0));
395
396 ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
397 object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
398 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp);
399 qdev_init_nofail(ledma);
400
401 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
402 sbd = SYS_BUS_DEVICE(lance);
403 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
404 qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
405
406 sbd = SYS_BUS_DEVICE(ledma);
407 memory_region_add_subregion(&s->dmamem, 0x10,
408 sysbus_mmio_get_region(sbd, 0));
Mark Cave-Ayland4ca3d362017-10-14 13:22:22 +0100409
410 /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */
411 memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
412 sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
413 memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100414}
415
416static void sparc32_dma_init(Object *obj)
417{
418 SPARC32DMAState *s = SPARC32_DMA(obj);
419 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
420
421 memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
422 sysbus_init_mmio(sbd, &s->dmamem);
423}
424
425static void sparc32_dma_class_init(ObjectClass *klass, void *data)
426{
427 DeviceClass *dc = DEVICE_CLASS(klass);
428
429 dc->realize = sparc32_dma_realize;
430}
431
432static const TypeInfo sparc32_dma_info = {
433 .name = TYPE_SPARC32_DMA,
434 .parent = TYPE_SYS_BUS_DEVICE,
435 .instance_size = sizeof(SPARC32DMAState),
436 .instance_init = sparc32_dma_init,
437 .class_init = sparc32_dma_class_init,
438};
439
440
Andreas Färber83f7d432012-02-09 15:20:55 +0100441static void sparc32_dma_register_types(void)
Blue Swirl6f6260c2009-07-15 20:45:19 +0000442{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100443 type_register_static(&sparc32_dma_device_info);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100444 type_register_static(&sparc32_espdma_device_info);
445 type_register_static(&sparc32_ledma_device_info);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100446 type_register_static(&sparc32_dma_info);
Blue Swirl6f6260c2009-07-15 20:45:19 +0000447}
448
Andreas Färber83f7d432012-02-09 15:20:55 +0100449type_init(sparc32_dma_register_types)