commit 73d7434279e390505164afd02360eebe4b43c7fa
author Blue Swirl <blauwirbel@gmail.com> Sat Sep 11 16:38:33 2010 +0000
committer Blue Swirl <blauwirbel@gmail.com> Sat Sep 11 16:38:33 2010 +0000
tree 309f298ec1dcba9be54fb0604a92811cc3095dbe
parent 24e0e38b83616ee7b540a270d8c4f24edf94f802

ESP: fix ESP DMA access when DMA is not enabled

Sending ESP a command caused it to trigger DMA immediately
even if DMA was not enabled at the DMA controller.

Add a signal from DMA controller to ESP to tell ESP about changes in
DMA enable bit. Also use the correct function for setting up GPIO outputs.

This fixes NetBSD 1.6.1 through 3.0 boot.

Thanks to Artyom Tarasenko for extensive debugging of the problem.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

hw/sparc32_dma.c

diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index b521707..984ffc3 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -58,6 +58,7 @@
 #define DMA_INTR 1
 #define DMA_INTREN 0x10
 #define DMA_WRITE_MEM 0x100
+#define DMA_EN 0x200
 #define DMA_LOADED 0x04000000
 #define DMA_DRAIN_FIFO 0x40
 #define DMA_RESET 0x80
@@ -72,7 +73,12 @@
     uint32_t dmaregs[DMA_REGS];
     qemu_irq irq;
     void *iommu;
-    qemu_irq dev_reset;
+    qemu_irq gpio[2];
+};
+
+enum {
+    GPIO_RESET = 0,
+    GPIO_DMA,
 };
 
 /* Note: on sparc, the lance 16 bit bus is swapped */
@@ -201,12 +207,21 @@
             }
         }
         if (val & DMA_RESET) {
-            qemu_irq_raise(s->dev_reset);
-            qemu_irq_lower(s->dev_reset);
+            qemu_irq_raise(s->gpio[GPIO_RESET]);
+            qemu_irq_lower(s->gpio[GPIO_RESET]);
         } else if (val & DMA_DRAIN_FIFO) {
             val &= ~DMA_DRAIN_FIFO;
         } else if (val == 0)
             val = DMA_DRAIN_FIFO;
+
+        if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
+            DPRINTF("Raise DMA enable\n");
+            qemu_irq_raise(s->gpio[GPIO_DMA]);
+        } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
+            DPRINTF("Lower DMA enable\n");
+            qemu_irq_lower(s->gpio[GPIO_DMA]);
+        }
+
         val &= ~DMA_CSR_RO_MASK;
         val |= DMA_VER;
         s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
@@ -262,7 +277,7 @@
     sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
 
     qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
-    qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
+    qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
 
     return 0;
 }