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pbrook9ee6e8b2007-11-11 00:04:49 +00001/*
2 * ARM Nested Vectored Interrupt Controller
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10007 * This code is licensed under the GPL.
pbrook9ee6e8b2007-11-11 00:04:49 +00008 *
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
11 */
12
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010013#include "hw/sysbus.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010014#include "qemu/timer.h"
Peter Maydellbd2be152013-04-09 15:26:55 +010015#include "hw/arm/arm.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010016#include "exec/address-spaces.h"
Paolo Bonzini47b43a12013-03-18 17:36:02 +010017#include "gic_internal.h"
pbrook9ee6e8b2007-11-11 00:04:49 +000018
19typedef struct {
Peter Maydellfae15282012-10-12 11:54:39 +010020 GICState gic;
pbrook9ee6e8b2007-11-11 00:04:49 +000021 struct {
22 uint32_t control;
23 uint32_t reload;
24 int64_t tick;
25 QEMUTimer *timer;
26 } systick;
Peter Maydell2a29dde2012-05-02 16:49:39 +000027 MemoryRegion sysregmem;
28 MemoryRegion gic_iomem_alias;
29 MemoryRegion container;
Mark Langsdorfa32134a2012-01-17 10:54:07 +000030 uint32_t num_irq;
pbrook9ee6e8b2007-11-11 00:04:49 +000031} nvic_state;
32
Peter Maydell1e8cae42012-05-02 16:49:42 +000033#define TYPE_NVIC "armv7m_nvic"
34/**
35 * NVICClass:
36 * @parent_reset: the parent class' reset handler.
37 *
38 * A model of the v7M NVIC and System Controller
39 */
40typedef struct NVICClass {
41 /*< private >*/
42 ARMGICClass parent_class;
43 /*< public >*/
Peter Maydell53111182013-03-05 00:34:42 +000044 DeviceRealize parent_realize;
Peter Maydell1e8cae42012-05-02 16:49:42 +000045 void (*parent_reset)(DeviceState *dev);
46} NVICClass;
47
48#define NVIC_CLASS(klass) \
49 OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
50#define NVIC_GET_CLASS(obj) \
51 OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
52#define NVIC(obj) \
53 OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
54
Peter Maydell2a29dde2012-05-02 16:49:39 +000055static const uint8_t nvic_id[] = {
56 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
57};
58
pbrook9ee6e8b2007-11-11 00:04:49 +000059/* qemu timers run at 1GHz. We want something closer to 1MHz. */
60#define SYSTICK_SCALE 1000ULL
61
62#define SYSTICK_ENABLE (1 << 0)
63#define SYSTICK_TICKINT (1 << 1)
64#define SYSTICK_CLKSOURCE (1 << 2)
65#define SYSTICK_COUNTFLAG (1 << 16)
66
blueswir17ee930d2008-09-17 19:04:14 +000067int system_clock_scale;
68
pbrooke57ec012007-11-24 03:09:07 +000069/* Conversion factor from qemu timer to SysTick frequencies. */
pbrook9ee6e8b2007-11-11 00:04:49 +000070static inline int64_t systick_scale(nvic_state *s)
71{
72 if (s->systick.control & SYSTICK_CLKSOURCE)
pbrooke57ec012007-11-24 03:09:07 +000073 return system_clock_scale;
pbrook9ee6e8b2007-11-11 00:04:49 +000074 else
75 return 1000;
76}
77
78static void systick_reload(nvic_state *s, int reset)
79{
80 if (reset)
Alex Blighbc72ad62013-08-21 16:03:08 +010081 s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pbrook9ee6e8b2007-11-11 00:04:49 +000082 s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
Alex Blighbc72ad62013-08-21 16:03:08 +010083 timer_mod(s->systick.timer, s->systick.tick);
pbrook9ee6e8b2007-11-11 00:04:49 +000084}
85
86static void systick_timer_tick(void * opaque)
87{
88 nvic_state *s = (nvic_state *)opaque;
89 s->systick.control |= SYSTICK_COUNTFLAG;
90 if (s->systick.control & SYSTICK_TICKINT) {
91 /* Trigger the interrupt. */
92 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
93 }
94 if (s->systick.reload == 0) {
95 s->systick.control &= ~SYSTICK_ENABLE;
96 } else {
97 systick_reload(s, 0);
98 }
99}
100
Peter Maydellaecff692012-04-13 11:39:09 +0000101static void systick_reset(nvic_state *s)
102{
103 s->systick.control = 0;
104 s->systick.reload = 0;
105 s->systick.tick = 0;
Alex Blighbc72ad62013-08-21 16:03:08 +0100106 timer_del(s->systick.timer);
Peter Maydellaecff692012-04-13 11:39:09 +0000107}
108
pbrook9ee6e8b2007-11-11 00:04:49 +0000109/* The external routines use the hardware vector numbering, ie. the first
110 IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
111void armv7m_nvic_set_pending(void *opaque, int irq)
112{
113 nvic_state *s = (nvic_state *)opaque;
114 if (irq >= 16)
115 irq += 16;
Paul Brookfe7e8752009-05-14 22:35:08 +0100116 gic_set_pending_private(&s->gic, 0, irq);
pbrook9ee6e8b2007-11-11 00:04:49 +0000117}
118
119/* Make pending IRQ active. */
120int armv7m_nvic_acknowledge_irq(void *opaque)
121{
122 nvic_state *s = (nvic_state *)opaque;
123 uint32_t irq;
124
Paul Brookfe7e8752009-05-14 22:35:08 +0100125 irq = gic_acknowledge_irq(&s->gic, 0);
pbrook9ee6e8b2007-11-11 00:04:49 +0000126 if (irq == 1023)
Paul Brook2ac71172009-05-08 02:35:15 +0100127 hw_error("Interrupt but no vector\n");
pbrook9ee6e8b2007-11-11 00:04:49 +0000128 if (irq >= 32)
129 irq -= 16;
130 return irq;
131}
132
133void armv7m_nvic_complete_irq(void *opaque, int irq)
134{
135 nvic_state *s = (nvic_state *)opaque;
136 if (irq >= 16)
137 irq += 16;
Paul Brookfe7e8752009-05-14 22:35:08 +0100138 gic_complete_irq(&s->gic, 0, irq);
pbrook9ee6e8b2007-11-11 00:04:49 +0000139}
140
Andre Beckus0e8153d2012-10-30 07:45:07 +0000141static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
pbrook9ee6e8b2007-11-11 00:04:49 +0000142{
Andreas Färber4917cf42013-05-27 05:17:50 +0200143 ARMCPU *cpu;
pbrook9ee6e8b2007-11-11 00:04:49 +0000144 uint32_t val;
145 int irq;
146
147 switch (offset) {
148 case 4: /* Interrupt Control Type. */
Mark Langsdorfa32134a2012-01-17 10:54:07 +0000149 return (s->num_irq / 32) - 1;
pbrook9ee6e8b2007-11-11 00:04:49 +0000150 case 0x10: /* SysTick Control and Status. */
151 val = s->systick.control;
152 s->systick.control &= ~SYSTICK_COUNTFLAG;
153 return val;
154 case 0x14: /* SysTick Reload Value. */
155 return s->systick.reload;
156 case 0x18: /* SysTick Current Value. */
157 {
158 int64_t t;
159 if ((s->systick.control & SYSTICK_ENABLE) == 0)
160 return 0;
Alex Blighbc72ad62013-08-21 16:03:08 +0100161 t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pbrook9ee6e8b2007-11-11 00:04:49 +0000162 if (t >= s->systick.tick)
163 return 0;
164 val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
165 /* The interrupt in triggered when the timer reaches zero.
166 However the counter is not reloaded until the next clock
167 tick. This is a hack to return zero during the first tick. */
168 if (val > s->systick.reload)
169 val = 0;
170 return val;
171 }
172 case 0x1c: /* SysTick Calibration Value. */
173 return 10000;
174 case 0xd00: /* CPUID Base. */
Andreas Färber4917cf42013-05-27 05:17:50 +0200175 cpu = ARM_CPU(current_cpu);
176 return cpu->env.cp15.c0_cpuid;
Peter Maydelle03ba132013-04-09 12:48:19 +0100177 case 0xd04: /* Interrupt Control State. */
pbrook9ee6e8b2007-11-11 00:04:49 +0000178 /* VECTACTIVE */
Paul Brookfe7e8752009-05-14 22:35:08 +0100179 val = s->gic.running_irq[0];
pbrook9ee6e8b2007-11-11 00:04:49 +0000180 if (val == 1023) {
181 val = 0;
182 } else if (val >= 32) {
183 val -= 16;
184 }
185 /* RETTOBASE */
Paul Brookfe7e8752009-05-14 22:35:08 +0100186 if (s->gic.running_irq[0] == 1023
187 || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
pbrook9ee6e8b2007-11-11 00:04:49 +0000188 val |= (1 << 11);
189 }
190 /* VECTPENDING */
Paul Brookfe7e8752009-05-14 22:35:08 +0100191 if (s->gic.current_pending[0] != 1023)
192 val |= (s->gic.current_pending[0] << 12);
pbrook9ee6e8b2007-11-11 00:04:49 +0000193 /* ISRPENDING */
Mark Langsdorfa32134a2012-01-17 10:54:07 +0000194 for (irq = 32; irq < s->num_irq; irq++) {
Paul Brookfe7e8752009-05-14 22:35:08 +0100195 if (s->gic.irq_state[irq].pending) {
pbrook9ee6e8b2007-11-11 00:04:49 +0000196 val |= (1 << 22);
197 break;
198 }
199 }
200 /* PENDSTSET */
Paul Brookfe7e8752009-05-14 22:35:08 +0100201 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
pbrook9ee6e8b2007-11-11 00:04:49 +0000202 val |= (1 << 26);
203 /* PENDSVSET */
Paul Brookfe7e8752009-05-14 22:35:08 +0100204 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
pbrook9ee6e8b2007-11-11 00:04:49 +0000205 val |= (1 << 28);
206 /* NMIPENDSET */
Paul Brookfe7e8752009-05-14 22:35:08 +0100207 if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
pbrook9ee6e8b2007-11-11 00:04:49 +0000208 val |= (1 << 31);
209 return val;
210 case 0xd08: /* Vector Table Offset. */
Andreas Färber4917cf42013-05-27 05:17:50 +0200211 cpu = ARM_CPU(current_cpu);
212 return cpu->env.v7m.vecbase;
pbrook9ee6e8b2007-11-11 00:04:49 +0000213 case 0xd0c: /* Application Interrupt/Reset Control. */
214 return 0xfa05000;
215 case 0xd10: /* System Control. */
216 /* TODO: Implement SLEEPONEXIT. */
217 return 0;
218 case 0xd14: /* Configuration Control. */
219 /* TODO: Implement Configuration Control bits. */
220 return 0;
pbrook9ee6e8b2007-11-11 00:04:49 +0000221 case 0xd24: /* System Handler Status. */
222 val = 0;
Paul Brookfe7e8752009-05-14 22:35:08 +0100223 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
224 if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
225 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
226 if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
227 if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
228 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
229 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
230 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
231 if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
232 if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
233 if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
234 if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
235 if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
236 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
pbrook9ee6e8b2007-11-11 00:04:49 +0000237 return val;
238 case 0xd28: /* Configurable Fault Status. */
239 /* TODO: Implement Fault Status. */
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000240 qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");
pbrook9ee6e8b2007-11-11 00:04:49 +0000241 return 0;
242 case 0xd2c: /* Hard Fault Status. */
243 case 0xd30: /* Debug Fault Status. */
244 case 0xd34: /* Mem Manage Address. */
245 case 0xd38: /* Bus Fault Address. */
246 case 0xd3c: /* Aux Fault Status. */
247 /* TODO: Implement fault status registers. */
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000248 qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");
249 return 0;
pbrook9ee6e8b2007-11-11 00:04:49 +0000250 case 0xd40: /* PFR0. */
251 return 0x00000030;
252 case 0xd44: /* PRF1. */
253 return 0x00000200;
254 case 0xd48: /* DFR0. */
255 return 0x00100000;
256 case 0xd4c: /* AFR0. */
257 return 0x00000000;
258 case 0xd50: /* MMFR0. */
259 return 0x00000030;
260 case 0xd54: /* MMFR1. */
261 return 0x00000000;
262 case 0xd58: /* MMFR2. */
263 return 0x00000000;
264 case 0xd5c: /* MMFR3. */
265 return 0x00000000;
266 case 0xd60: /* ISAR0. */
267 return 0x01141110;
268 case 0xd64: /* ISAR1. */
269 return 0x02111000;
270 case 0xd68: /* ISAR2. */
271 return 0x21112231;
272 case 0xd6c: /* ISAR3. */
273 return 0x01111110;
274 case 0xd70: /* ISAR4. */
275 return 0x01310102;
276 /* TODO: Implement debug registers. */
277 default:
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000278 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
279 return 0;
pbrook9ee6e8b2007-11-11 00:04:49 +0000280 }
281}
282
Andre Beckus0e8153d2012-10-30 07:45:07 +0000283static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
pbrook9ee6e8b2007-11-11 00:04:49 +0000284{
Andreas Färber4917cf42013-05-27 05:17:50 +0200285 ARMCPU *cpu;
pbrook9ee6e8b2007-11-11 00:04:49 +0000286 uint32_t oldval;
287 switch (offset) {
288 case 0x10: /* SysTick Control and Status. */
289 oldval = s->systick.control;
290 s->systick.control &= 0xfffffff8;
291 s->systick.control |= value & 7;
292 if ((oldval ^ value) & SYSTICK_ENABLE) {
Alex Blighbc72ad62013-08-21 16:03:08 +0100293 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pbrook9ee6e8b2007-11-11 00:04:49 +0000294 if (value & SYSTICK_ENABLE) {
295 if (s->systick.tick) {
296 s->systick.tick += now;
Alex Blighbc72ad62013-08-21 16:03:08 +0100297 timer_mod(s->systick.timer, s->systick.tick);
pbrook9ee6e8b2007-11-11 00:04:49 +0000298 } else {
299 systick_reload(s, 1);
300 }
301 } else {
Alex Blighbc72ad62013-08-21 16:03:08 +0100302 timer_del(s->systick.timer);
pbrook9ee6e8b2007-11-11 00:04:49 +0000303 s->systick.tick -= now;
304 if (s->systick.tick < 0)
305 s->systick.tick = 0;
306 }
307 } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
308 /* This is a hack. Force the timer to be reloaded
309 when the reference clock is changed. */
310 systick_reload(s, 1);
311 }
312 break;
313 case 0x14: /* SysTick Reload Value. */
314 s->systick.reload = value;
315 break;
316 case 0x18: /* SysTick Current Value. Writes reload the timer. */
317 systick_reload(s, 1);
318 s->systick.control &= ~SYSTICK_COUNTFLAG;
319 break;
320 case 0xd04: /* Interrupt Control State. */
321 if (value & (1 << 31)) {
322 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
323 }
324 if (value & (1 << 28)) {
325 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
326 } else if (value & (1 << 27)) {
Paul Brookfe7e8752009-05-14 22:35:08 +0100327 s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
328 gic_update(&s->gic);
pbrook9ee6e8b2007-11-11 00:04:49 +0000329 }
330 if (value & (1 << 26)) {
331 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
332 } else if (value & (1 << 25)) {
Paul Brookfe7e8752009-05-14 22:35:08 +0100333 s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
334 gic_update(&s->gic);
pbrook9ee6e8b2007-11-11 00:04:49 +0000335 }
336 break;
337 case 0xd08: /* Vector Table Offset. */
Andreas Färber4917cf42013-05-27 05:17:50 +0200338 cpu = ARM_CPU(current_cpu);
339 cpu->env.v7m.vecbase = value & 0xffffff80;
pbrook9ee6e8b2007-11-11 00:04:49 +0000340 break;
341 case 0xd0c: /* Application Interrupt/Reset Control. */
342 if ((value >> 16) == 0x05fa) {
343 if (value & 2) {
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000344 qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
pbrook9ee6e8b2007-11-11 00:04:49 +0000345 }
346 if (value & 5) {
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000347 qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
pbrook9ee6e8b2007-11-11 00:04:49 +0000348 }
349 }
350 break;
351 case 0xd10: /* System Control. */
352 case 0xd14: /* Configuration Control. */
353 /* TODO: Implement control registers. */
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000354 qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");
355 break;
pbrook9ee6e8b2007-11-11 00:04:49 +0000356 case 0xd24: /* System Handler Control. */
357 /* TODO: Real hardware allows you to set/clear the active bits
358 under some circumstances. We don't implement this. */
Paul Brookfe7e8752009-05-14 22:35:08 +0100359 s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
360 s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
361 s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
pbrook9ee6e8b2007-11-11 00:04:49 +0000362 break;
363 case 0xd28: /* Configurable Fault Status. */
364 case 0xd2c: /* Hard Fault Status. */
365 case 0xd30: /* Debug Fault Status. */
366 case 0xd34: /* Mem Manage Address. */
367 case 0xd38: /* Bus Fault Address. */
368 case 0xd3c: /* Aux Fault Status. */
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000369 qemu_log_mask(LOG_UNIMP,
370 "NVIC: fault status registers unimplemented\n");
371 break;
Peter Maydell2a29dde2012-05-02 16:49:39 +0000372 case 0xf00: /* Software Triggered Interrupt Register */
373 if ((value & 0x1ff) < s->num_irq) {
374 gic_set_pending_private(&s->gic, 0, value & 0x1ff);
375 }
376 break;
pbrook9ee6e8b2007-11-11 00:04:49 +0000377 default:
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000378 qemu_log_mask(LOG_GUEST_ERROR,
379 "NVIC: Bad write offset 0x%x\n", offset);
pbrook9ee6e8b2007-11-11 00:04:49 +0000380 }
381}
382
Avi Kivitya8170e52012-10-23 12:30:10 +0200383static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
Peter Maydell2a29dde2012-05-02 16:49:39 +0000384 unsigned size)
385{
Andre Beckus0e8153d2012-10-30 07:45:07 +0000386 nvic_state *s = (nvic_state *)opaque;
Peter Maydell2a29dde2012-05-02 16:49:39 +0000387 uint32_t offset = addr;
Andre Beckus0e8153d2012-10-30 07:45:07 +0000388 int i;
389 uint32_t val;
390
391 switch (offset) {
392 case 0xd18 ... 0xd23: /* System Handler Priority. */
393 val = 0;
394 for (i = 0; i < size; i++) {
395 val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8);
396 }
397 return val;
398 case 0xfe0 ... 0xfff: /* ID. */
Peter Maydell2a29dde2012-05-02 16:49:39 +0000399 if (offset & 3) {
400 return 0;
401 }
402 return nvic_id[(offset - 0xfe0) >> 2];
403 }
404 if (size == 4) {
Andre Beckus0e8153d2012-10-30 07:45:07 +0000405 return nvic_readl(s, offset);
Peter Maydell2a29dde2012-05-02 16:49:39 +0000406 }
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000407 qemu_log_mask(LOG_GUEST_ERROR,
408 "NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
409 return 0;
Peter Maydell2a29dde2012-05-02 16:49:39 +0000410}
411
Avi Kivitya8170e52012-10-23 12:30:10 +0200412static void nvic_sysreg_write(void *opaque, hwaddr addr,
Peter Maydell2a29dde2012-05-02 16:49:39 +0000413 uint64_t value, unsigned size)
414{
Andre Beckus0e8153d2012-10-30 07:45:07 +0000415 nvic_state *s = (nvic_state *)opaque;
Peter Maydell2a29dde2012-05-02 16:49:39 +0000416 uint32_t offset = addr;
Andre Beckus0e8153d2012-10-30 07:45:07 +0000417 int i;
418
419 switch (offset) {
420 case 0xd18 ... 0xd23: /* System Handler Priority. */
421 for (i = 0; i < size; i++) {
422 s->gic.priority1[(offset - 0xd14) + i][0] =
423 (value >> (i * 8)) & 0xff;
424 }
425 gic_update(&s->gic);
426 return;
427 }
Peter Maydell2a29dde2012-05-02 16:49:39 +0000428 if (size == 4) {
Andre Beckus0e8153d2012-10-30 07:45:07 +0000429 nvic_writel(s, offset, value);
Peter Maydell2a29dde2012-05-02 16:49:39 +0000430 return;
431 }
Peter Maydelle72e3ff2012-10-30 07:45:10 +0000432 qemu_log_mask(LOG_GUEST_ERROR,
433 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
Peter Maydell2a29dde2012-05-02 16:49:39 +0000434}
435
436static const MemoryRegionOps nvic_sysreg_ops = {
437 .read = nvic_sysreg_read,
438 .write = nvic_sysreg_write,
439 .endianness = DEVICE_NATIVE_ENDIAN,
440};
441
Juan Quintela07972262010-12-02 02:17:33 +0100442static const VMStateDescription vmstate_nvic = {
443 .name = "armv7m_nvic",
444 .version_id = 1,
445 .minimum_version_id = 1,
446 .minimum_version_id_old = 1,
447 .fields = (VMStateField[]) {
448 VMSTATE_UINT32(systick.control, nvic_state),
449 VMSTATE_UINT32(systick.reload, nvic_state),
450 VMSTATE_INT64(systick.tick, nvic_state),
451 VMSTATE_TIMER(systick.timer, nvic_state),
452 VMSTATE_END_OF_LIST()
453 }
454};
pbrook23e39292008-07-02 16:48:32 +0000455
Peter Maydellaecff692012-04-13 11:39:09 +0000456static void armv7m_nvic_reset(DeviceState *dev)
457{
Peter Maydell1e8cae42012-05-02 16:49:42 +0000458 nvic_state *s = NVIC(dev);
459 NVICClass *nc = NVIC_GET_CLASS(s);
460 nc->parent_reset(dev);
Peter Maydellb3387ed2012-05-02 16:49:39 +0000461 /* Common GIC reset resets to disabled; the NVIC doesn't have
462 * per-CPU interfaces so mark our non-existent CPU interface
Peter Maydellee3f0952012-12-11 11:30:37 +0000463 * as enabled by default, and with a priority mask which allows
464 * all interrupts through.
Peter Maydellb3387ed2012-05-02 16:49:39 +0000465 */
Peter Maydellc3037772013-04-05 16:17:59 +0100466 s->gic.cpu_enabled[0] = true;
Peter Maydellee3f0952012-12-11 11:30:37 +0000467 s->gic.priority_mask[0] = 0x100;
Peter Maydellb3387ed2012-05-02 16:49:39 +0000468 /* The NVIC as a whole is always enabled. */
Peter Maydellc3037772013-04-05 16:17:59 +0100469 s->gic.enabled = true;
Peter Maydellaecff692012-04-13 11:39:09 +0000470 systick_reset(s);
471}
472
Peter Maydell53111182013-03-05 00:34:42 +0000473static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
pbrook9ee6e8b2007-11-11 00:04:49 +0000474{
Peter Maydell1e8cae42012-05-02 16:49:42 +0000475 nvic_state *s = NVIC(dev);
476 NVICClass *nc = NVIC_GET_CLASS(s);
pbrook9ee6e8b2007-11-11 00:04:49 +0000477
Peter Maydellc48c6522012-05-02 16:49:39 +0000478 /* The NVIC always has only one CPU */
479 s->gic.num_cpu = 1;
Peter Maydell306a5712012-05-02 16:49:40 +0000480 /* Tell the common code we're an NVIC */
481 s->gic.revision = 0xffffffff;
Peter Maydell55e00a12012-08-13 11:04:05 +0100482 s->num_irq = s->gic.num_irq;
Peter Maydell53111182013-03-05 00:34:42 +0000483 nc->parent_realize(dev, errp);
484 if (error_is_set(errp)) {
485 return;
486 }
Peter Maydell2b518c52012-05-02 16:49:41 +0000487 gic_init_irqs_and_distributor(&s->gic, s->num_irq);
Peter Maydell2a29dde2012-05-02 16:49:39 +0000488 /* The NVIC and system controller register area looks like this:
489 * 0..0xff : system control registers, including systick
490 * 0x100..0xcff : GIC-like registers
491 * 0xd00..0xfff : system control registers
492 * We use overlaying to put the GIC like registers
493 * over the top of the system control register region.
494 */
Paolo Bonzini1437c942013-06-06 21:25:08 -0400495 memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
Peter Maydell2a29dde2012-05-02 16:49:39 +0000496 /* The system register region goes at the bottom of the priority
497 * stack as it covers the whole page.
498 */
Paolo Bonzini1437c942013-06-06 21:25:08 -0400499 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
Peter Maydell2a29dde2012-05-02 16:49:39 +0000500 "nvic_sysregs", 0x1000);
501 memory_region_add_subregion(&s->container, 0, &s->sysregmem);
502 /* Alias the GIC region so we can get only the section of it
503 * we need, and layer it on top of the system register region.
504 */
Paolo Bonzini1437c942013-06-06 21:25:08 -0400505 memory_region_init_alias(&s->gic_iomem_alias, OBJECT(s),
506 "nvic-gic", &s->gic.iomem,
Peter Maydell2a29dde2012-05-02 16:49:39 +0000507 0x100, 0xc00);
Meador Inge9892cae2012-09-26 16:46:28 +0100508 memory_region_add_subregion_overlap(&s->container, 0x100,
509 &s->gic_iomem_alias, 1);
Peter Maydell2a29dde2012-05-02 16:49:39 +0000510 /* Map the whole thing into system memory at the location required
511 * by the v7M architecture.
512 */
513 memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
Alex Blighbc72ad62013-08-21 16:03:08 +0100514 s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
pbrook9ee6e8b2007-11-11 00:04:49 +0000515}
Paul Brookfe7e8752009-05-14 22:35:08 +0100516
Peter Maydell55e00a12012-08-13 11:04:05 +0100517static void armv7m_nvic_instance_init(Object *obj)
518{
519 /* We have a different default value for the num-irq property
520 * than our superclass. This function runs after qdev init
521 * has set the defaults from the Property array and before
522 * any user-specified property setting, so just modify the
Peter Maydellfae15282012-10-12 11:54:39 +0100523 * value in the GICState struct.
Peter Maydell55e00a12012-08-13 11:04:05 +0100524 */
Peter Maydellfae15282012-10-12 11:54:39 +0100525 GICState *s = ARM_GIC_COMMON(obj);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600526 /* The ARM v7m may have anything from 0 to 496 external interrupt
527 * IRQ lines. We default to 64. Other boards may differ and should
Peter Maydell55e00a12012-08-13 11:04:05 +0100528 * set the num-irq property appropriately.
Anthony Liguori39bffca2011-12-07 21:34:16 -0600529 */
Peter Maydell55e00a12012-08-13 11:04:05 +0100530 s->num_irq = 64;
531}
Anthony Liguori39bffca2011-12-07 21:34:16 -0600532
Anthony Liguori999e12b2012-01-24 13:12:29 -0600533static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
534{
Peter Maydell1e8cae42012-05-02 16:49:42 +0000535 NVICClass *nc = NVIC_CLASS(klass);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600536 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600537
Peter Maydell1e8cae42012-05-02 16:49:42 +0000538 nc->parent_reset = dc->reset;
Peter Maydell53111182013-03-05 00:34:42 +0000539 nc->parent_realize = dc->realize;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600540 dc->vmsd = &vmstate_nvic;
Peter Maydellaecff692012-04-13 11:39:09 +0000541 dc->reset = armv7m_nvic_reset;
Peter Maydell53111182013-03-05 00:34:42 +0000542 dc->realize = armv7m_nvic_realize;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600543}
544
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100545static const TypeInfo armv7m_nvic_info = {
Peter Maydell1e8cae42012-05-02 16:49:42 +0000546 .name = TYPE_NVIC,
547 .parent = TYPE_ARM_GIC_COMMON,
Peter Maydell55e00a12012-08-13 11:04:05 +0100548 .instance_init = armv7m_nvic_instance_init,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600549 .instance_size = sizeof(nvic_state),
550 .class_init = armv7m_nvic_class_init,
Peter Maydell1e8cae42012-05-02 16:49:42 +0000551 .class_size = sizeof(NVICClass),
Mark Langsdorfa32134a2012-01-17 10:54:07 +0000552};
553
Andreas Färber83f7d432012-02-09 15:20:55 +0100554static void armv7m_nvic_register_types(void)
Paul Brookfe7e8752009-05-14 22:35:08 +0100555{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600556 type_register_static(&armv7m_nvic_info);
Paul Brookfe7e8752009-05-14 22:35:08 +0100557}
558
Andreas Färber83f7d432012-02-09 15:20:55 +0100559type_init(armv7m_nvic_register_types)