commit | ee3f095680e4f578f4f1371a90acc20375b48966 | [log] [tgz] |
---|---|---|
author | Peter Maydell <peter.maydell@linaro.org> | Tue Dec 11 11:30:37 2012 +0000 |
committer | Peter Maydell <peter.maydell@linaro.org> | Tue Dec 11 11:30:37 2012 +0000 |
tree | 84dbe2196110839a10a975a95ffe5c7f6e06b880 | |
parent | cad065f18e1ca7694385f42f560da637d4e651b6 [diff] |
hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>