blob: 943e3301d2092066d43d310fb0e1605cd2bd49f9 [file] [log] [blame]
Andreas Färber8d725fa2011-03-07 01:34:04 +01001/*
2 * QEMU float support
3 *
Peter Maydell16017c42015-01-12 14:38:28 +00004 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 * the SoftFloat-2a license
10 * the BSD license
11 * GPL-v2-or-later
12 *
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
Andreas Färber8d725fa2011-03-07 01:34:04 +010016 */
bellard158142c2005-03-13 16:54:06 +000017
Peter Maydella7d1ac72015-01-12 14:38:25 +000018/*
19===============================================================================
bellard158142c2005-03-13 16:54:06 +000020This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
Peter Maydella7d1ac72015-01-12 14:38:25 +000021Arithmetic Package, Release 2a.
bellard158142c2005-03-13 16:54:06 +000022
23Written by John R. Hauser. This work was made possible in part by the
24International Computer Science Institute, located at Suite 600, 1947 Center
25Street, Berkeley, California 94704. Funding was partially provided by the
26National Science Foundation under grant MIP-9311980. The original version
27of this code was written as part of a project to build a fixed-point vector
28processor in collaboration with the University of California at Berkeley,
29overseen by Profs. Nelson Morgan and John Wawrzynek. More information
Peter Maydella7d1ac72015-01-12 14:38:25 +000030is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
bellard158142c2005-03-13 16:54:06 +000031arithmetic/SoftFloat.html'.
32
Peter Maydella7d1ac72015-01-12 14:38:25 +000033THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
bellard158142c2005-03-13 16:54:06 +000038
39Derivative works are acceptable, even for commercial purposes, so long as
Peter Maydella7d1ac72015-01-12 14:38:25 +000040(1) they include prominent notice that the work is derivative, and (2) they
41include prominent notice akin to these four paragraphs for those parts of
42this code that are retained.
bellard158142c2005-03-13 16:54:06 +000043
Peter Maydella7d1ac72015-01-12 14:38:25 +000044===============================================================================
45*/
bellard158142c2005-03-13 16:54:06 +000046
Peter Maydell16017c42015-01-12 14:38:28 +000047/* BSD licensing:
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
53 *
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
56 *
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 *
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
76 */
77
78/* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
80 */
81
Max Filippovcc43c692020-06-30 19:35:49 -070082/*
83 * Define whether architecture deviates from IEEE in not supporting
Max Filippov213ff4e2012-09-19 04:23:51 +040084 * signaling NaNs (so all NaNs are treated as quiet).
85 */
Max Filippovcc43c692020-06-30 19:35:49 -070086static inline bool no_signaling_nans(float_status *status)
87{
Richard Henderson03385df2018-05-10 14:48:17 -070088#if defined(TARGET_XTENSA)
Max Filippovcc43c692020-06-30 19:35:49 -070089 return status->no_signaling_nans;
90#else
91 return false;
Max Filippov213ff4e2012-09-19 04:23:51 +040092#endif
Max Filippovcc43c692020-06-30 19:35:49 -070093}
Max Filippov213ff4e2012-09-19 04:23:51 +040094
Richard Henderson03385df2018-05-10 14:48:17 -070095/* Define how the architecture discriminates signaling NaNs.
96 * This done with the most significant bit of the fraction.
97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
98 * the msb must be zero. MIPS is (so far) unique in supporting both the
99 * 2008 revision and backward compatibility with their original choice.
100 * Thus for MIPS we must make the choice at runtime.
101 */
Richard Hendersonc1203912020-05-04 19:54:57 -0700102static inline bool snan_bit_is_one(float_status *status)
Richard Henderson03385df2018-05-10 14:48:17 -0700103{
104#if defined(TARGET_MIPS)
105 return status->snan_bit_is_one;
Markus Armbruster43692232021-05-03 10:40:34 +0200106#elif defined(TARGET_HPPA) || defined(TARGET_SH4)
Richard Henderson03385df2018-05-10 14:48:17 -0700107 return 1;
108#else
109 return 0;
110#endif
111}
112
Paolo Bonzini789ec7c2011-07-28 12:10:29 +0200113/*----------------------------------------------------------------------------
Richard Henderson298b4682018-05-10 12:45:29 -0700114| For the deconstructed floating-point with fraction FRAC, return true
115| if the fraction represents a signalling NaN; otherwise false.
116*----------------------------------------------------------------------------*/
117
118static bool parts_is_snan_frac(uint64_t frac, float_status *status)
119{
Max Filippovcc43c692020-06-30 19:35:49 -0700120 if (no_signaling_nans(status)) {
121 return false;
122 } else {
123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
124 return msb == snan_bit_is_one(status);
125 }
Richard Henderson298b4682018-05-10 12:45:29 -0700126}
127
128/*----------------------------------------------------------------------------
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700129| The pattern for a default generated deconstructed floating-point NaN.
130*----------------------------------------------------------------------------*/
131
Richard Henderson0fc07ca2020-10-23 14:00:33 -0700132static void parts64_default_nan(FloatParts64 *p, float_status *status)
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700133{
134 bool sign = 0;
135 uint64_t frac;
136
137#if defined(TARGET_SPARC) || defined(TARGET_M68K)
Richard Henderson8fb3d902018-05-14 13:12:14 -0700138 /* !snan_bit_is_one, set all bits */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
Richard Henderson8fb3d902018-05-14 13:12:14 -0700140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
141 || defined(TARGET_MICROBLAZE)
142 /* !snan_bit_is_one, set sign and msb */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
Richard Henderson8fb3d902018-05-14 13:12:14 -0700144 sign = 1;
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700145#elif defined(TARGET_HPPA)
Richard Henderson8fb3d902018-05-14 13:12:14 -0700146 /* snan_bit_is_one, set msb-1. */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
Taylor Simpsonc0336c82021-04-08 20:07:38 -0500148#elif defined(TARGET_HEXAGON)
149 sign = 1;
150 frac = ~0ULL;
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700151#else
Markus Armbruster43692232021-05-03 10:40:34 +0200152 /*
153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
154 * S390, SH4, TriCore, and Xtensa. Our other supported targets,
155 * CRIS, Nios2, and Tile, do not have floating-point.
Richard Henderson8fb3d902018-05-14 13:12:14 -0700156 */
Richard Henderson03385df2018-05-10 14:48:17 -0700157 if (snan_bit_is_one(status)) {
Richard Henderson8fb3d902018-05-14 13:12:14 -0700158 /* set all bits other than msb */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
160 } else {
Richard Henderson8fb3d902018-05-14 13:12:14 -0700161 /* set msb */
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700163 }
164#endif
165
Richard Henderson0fc07ca2020-10-23 14:00:33 -0700166 *p = (FloatParts64) {
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700167 .cls = float_class_qnan,
168 .sign = sign,
169 .exp = INT_MAX,
170 .frac = frac
171 };
172}
173
Richard Hendersone9034ea2020-10-23 16:37:01 -0700174static void parts128_default_nan(FloatParts128 *p, float_status *status)
175{
176 /*
177 * Extrapolate from the choices made by parts64_default_nan to fill
178 * in the quad-floating format. If the low bit is set, assume we
179 * want to set all non-snan bits.
180 */
181 FloatParts64 p64;
182 parts64_default_nan(&p64, status);
183
184 *p = (FloatParts128) {
185 .cls = float_class_qnan,
186 .sign = p64.sign,
187 .exp = INT_MAX,
188 .frac_hi = p64.frac,
189 .frac_lo = -(p64.frac & 1)
190 };
191}
192
Richard Hendersonf7e598e2018-05-10 13:09:49 -0700193/*----------------------------------------------------------------------------
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700194| Returns a quiet NaN from a signalling NaN for the deconstructed
195| floating-point parts.
196*----------------------------------------------------------------------------*/
197
Richard Henderson92ff4262020-10-23 16:23:06 -0700198static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700199{
Max Filippovcc43c692020-06-30 19:35:49 -0700200 g_assert(!no_signaling_nans(status));
Richard Hendersona777d602020-10-22 09:23:46 -0700201
202 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
Richard Henderson03385df2018-05-10 14:48:17 -0700203 if (snan_bit_is_one(status)) {
Richard Henderson92ff4262020-10-23 16:23:06 -0700204 frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
205 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700206 } else {
Richard Henderson92ff4262020-10-23 16:23:06 -0700207 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700208 }
Richard Henderson92ff4262020-10-23 16:23:06 -0700209 return frac;
210}
211
212static void parts64_silence_nan(FloatParts64 *p, float_status *status)
213{
214 p->frac = parts_silence_nan_frac(p->frac, status);
215 p->cls = float_class_qnan;
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700216}
217
Richard Henderson0018b1f2020-10-23 16:36:19 -0700218static void parts128_silence_nan(FloatParts128 *p, float_status *status)
219{
220 p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
221 p->cls = float_class_qnan;
222}
223
Richard Henderson0bcfbcb2018-05-10 13:32:53 -0700224/*----------------------------------------------------------------------------
Paolo Bonzini789ec7c2011-07-28 12:10:29 +0200225| The pattern for a default generated extended double-precision NaN.
226*----------------------------------------------------------------------------*/
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200227floatx80 floatx80_default_nan(float_status *status)
228{
229 floatx80 r;
Richard Henderson0218a162018-05-14 13:56:44 -0700230
231 /* None of the targets that have snan_bit_is_one use floatx80. */
232 assert(!snan_bit_is_one(status));
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200233#if defined(TARGET_M68K)
Alex Bennéef7e81a92019-08-12 16:04:02 +0100234 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200235 r.high = 0x7FFF;
236#else
Richard Henderson0218a162018-05-14 13:56:44 -0700237 /* X86 */
Alex Bennéef7e81a92019-08-12 16:04:02 +0100238 r.low = UINT64_C(0xC000000000000000);
Richard Henderson0218a162018-05-14 13:56:44 -0700239 r.high = 0xFFFF;
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200240#endif
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200241 return r;
242}
Paolo Bonzini789ec7c2011-07-28 12:10:29 +0200243
244/*----------------------------------------------------------------------------
Laurent Vivier0f605c82018-02-24 21:18:01 +0100245| The pattern for a default generated extended double-precision inf.
246*----------------------------------------------------------------------------*/
247
248#define floatx80_infinity_high 0x7FFF
249#if defined(TARGET_M68K)
Alex Bennéef7e81a92019-08-12 16:04:02 +0100250#define floatx80_infinity_low UINT64_C(0x0000000000000000)
Laurent Vivier0f605c82018-02-24 21:18:01 +0100251#else
Alex Bennéef7e81a92019-08-12 16:04:02 +0100252#define floatx80_infinity_low UINT64_C(0x8000000000000000)
Laurent Vivier0f605c82018-02-24 21:18:01 +0100253#endif
254
255const floatx80 floatx80_infinity
256 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
257
258/*----------------------------------------------------------------------------
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000259| Returns 1 if the half-precision floating-point value `a' is a quiet
260| NaN; otherwise returns 0.
261*----------------------------------------------------------------------------*/
262
Richard Henderson150c7a92020-05-05 12:16:24 -0700263bool float16_is_quiet_nan(float16 a_, float_status *status)
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000264{
Max Filippovcc43c692020-06-30 19:35:49 -0700265 if (no_signaling_nans(status)) {
266 return float16_is_any_nan(a_);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200267 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700268 uint16_t a = float16_val(a_);
269 if (snan_bit_is_one(status)) {
270 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
271 } else {
272
273 return ((a >> 9) & 0x3F) == 0x3F;
274 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200275 }
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000276}
277
278/*----------------------------------------------------------------------------
LIU Zhiwei5ebf5f42020-08-13 15:14:21 +0800279| Returns 1 if the bfloat16 value `a' is a quiet
280| NaN; otherwise returns 0.
281*----------------------------------------------------------------------------*/
282
283bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
284{
285 if (no_signaling_nans(status)) {
286 return bfloat16_is_any_nan(a_);
287 } else {
288 uint16_t a = a_;
289 if (snan_bit_is_one(status)) {
290 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
291 } else {
292 return ((a >> 6) & 0x1FF) == 0x1FF;
293 }
294 }
295}
296
297/*----------------------------------------------------------------------------
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000298| Returns 1 if the half-precision floating-point value `a' is a signaling
299| NaN; otherwise returns 0.
300*----------------------------------------------------------------------------*/
301
Richard Henderson150c7a92020-05-05 12:16:24 -0700302bool float16_is_signaling_nan(float16 a_, float_status *status)
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000303{
Max Filippovcc43c692020-06-30 19:35:49 -0700304 if (no_signaling_nans(status)) {
305 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200306 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700307 uint16_t a = float16_val(a_);
308 if (snan_bit_is_one(status)) {
309 return ((a >> 9) & 0x3F) == 0x3F;
310 } else {
311 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
312 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200313 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700314}
Peter Maydellbb4d4bb2011-02-10 11:28:56 +0000315
316/*----------------------------------------------------------------------------
LIU Zhiwei5ebf5f42020-08-13 15:14:21 +0800317| Returns 1 if the bfloat16 value `a' is a signaling
318| NaN; otherwise returns 0.
319*----------------------------------------------------------------------------*/
320
321bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
322{
323 if (no_signaling_nans(status)) {
324 return 0;
325 } else {
326 uint16_t a = a_;
327 if (snan_bit_is_one(status)) {
328 return ((a >> 6) & 0x1FF) == 0x1FF;
329 } else {
330 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
331 }
332 }
333}
334
335/*----------------------------------------------------------------------------
ths5a6932d2007-11-16 14:57:36 +0000336| Returns 1 if the single-precision floating-point value `a' is a quiet
337| NaN; otherwise returns 0.
bellard158142c2005-03-13 16:54:06 +0000338*----------------------------------------------------------------------------*/
339
Richard Henderson150c7a92020-05-05 12:16:24 -0700340bool float32_is_quiet_nan(float32 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000341{
Max Filippovcc43c692020-06-30 19:35:49 -0700342 if (no_signaling_nans(status)) {
343 return float32_is_any_nan(a_);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200344 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700345 uint32_t a = float32_val(a_);
346 if (snan_bit_is_one(status)) {
347 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
348 } else {
349 return ((uint32_t)(a << 1) >= 0xFF800000);
350 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200351 }
bellard158142c2005-03-13 16:54:06 +0000352}
353
354/*----------------------------------------------------------------------------
355| Returns 1 if the single-precision floating-point value `a' is a signaling
356| NaN; otherwise returns 0.
357*----------------------------------------------------------------------------*/
358
Richard Henderson150c7a92020-05-05 12:16:24 -0700359bool float32_is_signaling_nan(float32 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000360{
Max Filippovcc43c692020-06-30 19:35:49 -0700361 if (no_signaling_nans(status)) {
362 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200363 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700364 uint32_t a = float32_val(a_);
365 if (snan_bit_is_one(status)) {
366 return ((uint32_t)(a << 1) >= 0xFF800000);
367 } else {
368 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
369 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200370 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700371}
bellard158142c2005-03-13 16:54:06 +0000372
373/*----------------------------------------------------------------------------
Peter Maydell354f2112010-12-16 11:51:17 +0000374| Select which NaN to propagate for a two-input operation.
375| IEEE754 doesn't specify all the details of this, so the
376| algorithm is target-specific.
377| The routine is passed various bits of information about the
378| two NaNs and should return 0 to select NaN a and 1 for NaN b.
379| Note that signalling NaNs are always squashed to quiet NaNs
Richard Henderson48853122018-05-10 14:11:15 -0700380| by the caller, by calling floatXX_silence_nan() before
Aurelien Jarno1f398e02011-01-06 15:38:19 +0100381| returning them.
Peter Maydell354f2112010-12-16 11:51:17 +0000382|
383| aIsLargerSignificand is only valid if both a and b are NaNs
384| of some kind, and is true if a has the larger significand,
385| or if both a and b have the same significand but a is
386| positive but b is negative. It is only needed for the x87
387| tie-break rule.
388*----------------------------------------------------------------------------*/
389
Richard Henderson4f251cf2018-05-10 15:21:31 -0700390static int pickNaN(FloatClass a_cls, FloatClass b_cls,
Max Filippov913602e2020-06-30 19:35:57 -0700391 bool aIsLargerSignificand, float_status *status)
Peter Maydell011da612010-12-16 11:51:18 +0000392{
Richard Henderson4f251cf2018-05-10 15:21:31 -0700393#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
Alex Bennée13894522017-07-19 11:49:42 +0100394 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
395 * the first of:
Peter Maydell011da612010-12-16 11:51:18 +0000396 * 1. A if it is signaling
397 * 2. B if it is signaling
398 * 3. A (quiet)
399 * 4. B (quiet)
400 * A signaling NaN is always quietened before returning it.
401 */
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100402 /* According to MIPS specifications, if one of the two operands is
403 * a sNaN, a new qNaN has to be generated. This is done in
Richard Henderson48853122018-05-10 14:11:15 -0700404 * floatXX_silence_nan(). For qNaN inputs the specifications
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100405 * says: "When possible, this QNaN result is one of the operand QNaN
406 * values." In practice it seems that most implementations choose
407 * the first operand if both operands are qNaN. In short this gives
408 * the following rules:
409 * 1. A if it is signaling
410 * 2. B if it is signaling
411 * 3. A (quiet)
412 * 4. B (quiet)
413 * A signaling NaN is always silenced before returning it.
414 */
Richard Henderson4f251cf2018-05-10 15:21:31 -0700415 if (is_snan(a_cls)) {
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100416 return 0;
Richard Henderson4f251cf2018-05-10 15:21:31 -0700417 } else if (is_snan(b_cls)) {
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100418 return 1;
Richard Henderson4f251cf2018-05-10 15:21:31 -0700419 } else if (is_qnan(a_cls)) {
Aurelien Jarno084d19b2011-01-06 15:38:19 +0100420 return 0;
421 } else {
422 return 1;
423 }
Max Filippov913602e2020-06-30 19:35:57 -0700424#elif defined(TARGET_PPC) || defined(TARGET_M68K)
Aurelien Jarnoe024e882011-01-06 15:38:19 +0100425 /* PowerPC propagation rules:
426 * 1. A if it sNaN or qNaN
427 * 2. B if it sNaN or qNaN
428 * A signaling NaN is always silenced before returning it.
429 */
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200430 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
431 * 3.4 FLOATING-POINT INSTRUCTION DETAILS
432 * If either operand, but not both operands, of an operation is a
433 * nonsignaling NaN, then that NaN is returned as the result. If both
434 * operands are nonsignaling NaNs, then the destination operand
435 * nonsignaling NaN is returned as the result.
436 * If either operand to an operation is a signaling NaN (SNaN), then the
437 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
438 * is set in the FPCR ENABLE byte, then the exception is taken and the
439 * destination is not modified. If the SNaN exception enable bit is not
440 * set, setting the SNaN bit in the operand to a one converts the SNaN to
441 * a nonsignaling NaN. The operation then continues as described in the
442 * preceding paragraph for nonsignaling NaNs.
443 */
Richard Henderson4f251cf2018-05-10 15:21:31 -0700444 if (is_nan(a_cls)) {
445 return 0;
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200446 } else {
Richard Henderson4f251cf2018-05-10 15:21:31 -0700447 return 1;
Laurent Viviere5b0cbe2017-06-12 01:16:27 +0200448 }
Max Filippov913602e2020-06-30 19:35:57 -0700449#elif defined(TARGET_XTENSA)
450 /*
451 * Xtensa has two NaN propagation modes.
452 * Which one is active is controlled by float_status::use_first_nan.
453 */
454 if (status->use_first_nan) {
455 if (is_nan(a_cls)) {
456 return 0;
457 } else {
458 return 1;
459 }
460 } else {
461 if (is_nan(b_cls)) {
462 return 1;
463 } else {
464 return 0;
465 }
466 }
Peter Maydell011da612010-12-16 11:51:18 +0000467#else
Peter Maydell354f2112010-12-16 11:51:17 +0000468 /* This implements x87 NaN propagation rules:
469 * SNaN + QNaN => return the QNaN
470 * two SNaNs => return the one with the larger significand, silenced
471 * two QNaNs => return the one with the larger significand
472 * SNaN and a non-NaN => return the SNaN, silenced
473 * QNaN and a non-NaN => return the QNaN
474 *
475 * If we get down to comparing significands and they are the same,
476 * return the NaN with the positive sign bit (if any).
477 */
Richard Henderson4f251cf2018-05-10 15:21:31 -0700478 if (is_snan(a_cls)) {
479 if (is_snan(b_cls)) {
Peter Maydell354f2112010-12-16 11:51:17 +0000480 return aIsLargerSignificand ? 0 : 1;
481 }
Richard Henderson4f251cf2018-05-10 15:21:31 -0700482 return is_qnan(b_cls) ? 1 : 0;
483 } else if (is_qnan(a_cls)) {
484 if (is_snan(b_cls) || !is_qnan(b_cls)) {
Peter Maydell354f2112010-12-16 11:51:17 +0000485 return 0;
Aleksandar Markovica59eaea2016-06-10 11:57:29 +0200486 } else {
Peter Maydell354f2112010-12-16 11:51:17 +0000487 return aIsLargerSignificand ? 0 : 1;
488 }
489 } else {
490 return 1;
491 }
Peter Maydell011da612010-12-16 11:51:18 +0000492#endif
Richard Henderson4f251cf2018-05-10 15:21:31 -0700493}
Peter Maydell354f2112010-12-16 11:51:17 +0000494
495/*----------------------------------------------------------------------------
Peter Maydell369be8f2011-10-19 16:14:06 +0000496| Select which NaN to propagate for a three-input operation.
497| For the moment we assume that no CPU needs the 'larger significand'
498| information.
499| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
500*----------------------------------------------------------------------------*/
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700501static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
502 bool infzero, float_status *status)
Peter Maydell369be8f2011-10-19 16:14:06 +0000503{
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700504#if defined(TARGET_ARM)
Peter Maydell369be8f2011-10-19 16:14:06 +0000505 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
506 * the default NaN
507 */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700508 if (infzero && is_qnan(c_cls)) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100509 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Peter Maydell369be8f2011-10-19 16:14:06 +0000510 return 3;
511 }
512
513 /* This looks different from the ARM ARM pseudocode, because the ARM ARM
514 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
515 */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700516 if (is_snan(c_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000517 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700518 } else if (is_snan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000519 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700520 } else if (is_snan(b_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000521 return 1;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700522 } else if (is_qnan(c_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000523 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700524 } else if (is_qnan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000525 return 0;
526 } else {
527 return 1;
528 }
Aurelien Jarnobbc1ded2012-10-09 21:53:20 +0200529#elif defined(TARGET_MIPS)
Richard Henderson03385df2018-05-10 14:48:17 -0700530 if (snan_bit_is_one(status)) {
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100531 /*
532 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
533 * case sets InvalidOp and returns the default NaN
534 */
535 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100536 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100537 return 3;
538 }
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200539 /* Prefer sNaN over qNaN, in the a, b, c order. */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700540 if (is_snan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200541 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700542 } else if (is_snan(b_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200543 return 1;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700544 } else if (is_snan(c_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200545 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700546 } else if (is_qnan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200547 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700548 } else if (is_qnan(b_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200549 return 1;
550 } else {
551 return 2;
552 }
Aurelien Jarnobbc1ded2012-10-09 21:53:20 +0200553 } else {
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100554 /*
555 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
556 * case sets InvalidOp and returns the input value 'c'
557 */
558 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100559 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Mateja Marjanovic7ca96e12019-03-19 16:21:56 +0100560 return 2;
561 }
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200562 /* Prefer sNaN over qNaN, in the c, a, b order. */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700563 if (is_snan(c_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200564 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700565 } else if (is_snan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200566 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700567 } else if (is_snan(b_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200568 return 1;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700569 } else if (is_qnan(c_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200570 return 2;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700571 } else if (is_qnan(a_cls)) {
Aleksandar Markovicc27644f2016-06-10 11:57:31 +0200572 return 0;
573 } else {
574 return 1;
575 }
Aurelien Jarnobbc1ded2012-10-09 21:53:20 +0200576 }
Peter Maydell369be8f2011-10-19 16:14:06 +0000577#elif defined(TARGET_PPC)
Peter Maydell369be8f2011-10-19 16:14:06 +0000578 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
579 * to return an input NaN if we have one (ie c) rather than generating
580 * a default NaN
581 */
582 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100583 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Peter Maydell369be8f2011-10-19 16:14:06 +0000584 return 2;
585 }
586
587 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
588 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
589 */
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700590 if (is_nan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000591 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700592 } else if (is_nan(c_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000593 return 2;
594 } else {
595 return 1;
596 }
Frank Chang3a7f7752021-04-20 09:31:48 +0800597#elif defined(TARGET_RISCV)
598 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
599 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100600 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Frank Chang3a7f7752021-04-20 09:31:48 +0800601 }
602 return 3; /* default NaN */
Max Filippovfbcc38e2020-07-03 17:02:47 -0700603#elif defined(TARGET_XTENSA)
604 /*
605 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
606 * an input NaN if we have one (ie c).
607 */
608 if (infzero) {
Richard Hendersonbead3c92021-12-17 17:57:14 +0100609 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
Max Filippovfbcc38e2020-07-03 17:02:47 -0700610 return 2;
611 }
612 if (status->use_first_nan) {
613 if (is_nan(a_cls)) {
614 return 0;
615 } else if (is_nan(b_cls)) {
616 return 1;
617 } else {
618 return 2;
619 }
620 } else {
621 if (is_nan(c_cls)) {
622 return 2;
623 } else if (is_nan(b_cls)) {
624 return 1;
625 } else {
626 return 0;
627 }
628 }
Peter Maydell369be8f2011-10-19 16:14:06 +0000629#else
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700630 /* A default implementation: prefer a to b to c.
631 * This is unlikely to actually match any real implementation.
632 */
633 if (is_nan(a_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000634 return 0;
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700635 } else if (is_nan(b_cls)) {
Peter Maydell369be8f2011-10-19 16:14:06 +0000636 return 1;
637 } else {
638 return 2;
639 }
Peter Maydell369be8f2011-10-19 16:14:06 +0000640#endif
Richard Henderson3bd2dec2018-05-10 15:38:08 -0700641}
Peter Maydell369be8f2011-10-19 16:14:06 +0000642
643/*----------------------------------------------------------------------------
ths5a6932d2007-11-16 14:57:36 +0000644| Returns 1 if the double-precision floating-point value `a' is a quiet
645| NaN; otherwise returns 0.
bellard158142c2005-03-13 16:54:06 +0000646*----------------------------------------------------------------------------*/
647
Richard Henderson150c7a92020-05-05 12:16:24 -0700648bool float64_is_quiet_nan(float64 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000649{
Max Filippovcc43c692020-06-30 19:35:49 -0700650 if (no_signaling_nans(status)) {
651 return float64_is_any_nan(a_);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200652 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700653 uint64_t a = float64_val(a_);
654 if (snan_bit_is_one(status)) {
655 return (((a >> 51) & 0xFFF) == 0xFFE)
656 && (a & 0x0007FFFFFFFFFFFFULL);
657 } else {
658 return ((a << 1) >= 0xFFF0000000000000ULL);
659 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200660 }
bellard158142c2005-03-13 16:54:06 +0000661}
662
663/*----------------------------------------------------------------------------
664| Returns 1 if the double-precision floating-point value `a' is a signaling
665| NaN; otherwise returns 0.
666*----------------------------------------------------------------------------*/
667
Richard Henderson150c7a92020-05-05 12:16:24 -0700668bool float64_is_signaling_nan(float64 a_, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000669{
Max Filippovcc43c692020-06-30 19:35:49 -0700670 if (no_signaling_nans(status)) {
671 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200672 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700673 uint64_t a = float64_val(a_);
674 if (snan_bit_is_one(status)) {
675 return ((a << 1) >= 0xFFF0000000000000ULL);
676 } else {
677 return (((a >> 51) & 0xFFF) == 0xFFE)
678 && (a & UINT64_C(0x0007FFFFFFFFFFFF));
679 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200680 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700681}
bellard158142c2005-03-13 16:54:06 +0000682
683/*----------------------------------------------------------------------------
bellard158142c2005-03-13 16:54:06 +0000684| Returns 1 if the extended double-precision floating-point value `a' is a
Aurelien Jarnode4af5f2011-01-17 19:29:33 +0100685| quiet NaN; otherwise returns 0. This slightly differs from the same
686| function for other types as floatx80 has an explicit bit.
bellard158142c2005-03-13 16:54:06 +0000687*----------------------------------------------------------------------------*/
688
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200689int floatx80_is_quiet_nan(floatx80 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000690{
Max Filippovcc43c692020-06-30 19:35:49 -0700691 if (no_signaling_nans(status)) {
692 return floatx80_is_any_nan(a);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200693 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700694 if (snan_bit_is_one(status)) {
695 uint64_t aLow;
696
697 aLow = a.low & ~0x4000000000000000ULL;
698 return ((a.high & 0x7FFF) == 0x7FFF)
699 && (aLow << 1)
700 && (a.low == aLow);
701 } else {
702 return ((a.high & 0x7FFF) == 0x7FFF)
703 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
704 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200705 }
bellard158142c2005-03-13 16:54:06 +0000706}
707
708/*----------------------------------------------------------------------------
709| Returns 1 if the extended double-precision floating-point value `a' is a
Aurelien Jarnode4af5f2011-01-17 19:29:33 +0100710| signaling NaN; otherwise returns 0. This slightly differs from the same
711| function for other types as floatx80 has an explicit bit.
bellard158142c2005-03-13 16:54:06 +0000712*----------------------------------------------------------------------------*/
713
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200714int floatx80_is_signaling_nan(floatx80 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000715{
Max Filippovcc43c692020-06-30 19:35:49 -0700716 if (no_signaling_nans(status)) {
717 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200718 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700719 if (snan_bit_is_one(status)) {
720 return ((a.high & 0x7FFF) == 0x7FFF)
721 && ((a.low << 1) >= 0x8000000000000000ULL);
722 } else {
723 uint64_t aLow;
bellard158142c2005-03-13 16:54:06 +0000724
Max Filippovcc43c692020-06-30 19:35:49 -0700725 aLow = a.low & ~UINT64_C(0x4000000000000000);
726 return ((a.high & 0x7FFF) == 0x7FFF)
727 && (uint64_t)(aLow << 1)
728 && (a.low == aLow);
729 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200730 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700731}
bellard158142c2005-03-13 16:54:06 +0000732
733/*----------------------------------------------------------------------------
Richard Hendersond619bb92018-05-10 11:39:48 -0700734| Returns a quiet NaN from a signalling NaN for the extended double-precision
735| floating point value `a'.
736*----------------------------------------------------------------------------*/
737
738floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
739{
Richard Henderson377ed922018-05-14 14:26:38 -0700740 /* None of the targets that have snan_bit_is_one use floatx80. */
741 assert(!snan_bit_is_one(status));
Alex Bennéef7e81a92019-08-12 16:04:02 +0100742 a.low |= UINT64_C(0xC000000000000000);
Richard Henderson377ed922018-05-14 14:26:38 -0700743 return a;
Richard Hendersond619bb92018-05-10 11:39:48 -0700744}
745
746/*----------------------------------------------------------------------------
bellard158142c2005-03-13 16:54:06 +0000747| Takes two extended double-precision floating-point values `a' and `b', one
748| of which is a NaN, and returns the appropriate NaN result. If either `a' or
749| `b' is a signaling NaN, the invalid exception is raised.
750*----------------------------------------------------------------------------*/
751
Laurent Vivier88857ac2018-02-24 21:17:59 +0100752floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000753{
Richard Hendersonc1203912020-05-04 19:54:57 -0700754 bool aIsLargerSignificand;
Richard Henderson4f251cf2018-05-10 15:21:31 -0700755 FloatClass a_cls, b_cls;
bellard158142c2005-03-13 16:54:06 +0000756
Richard Henderson4f251cf2018-05-10 15:21:31 -0700757 /* This is not complete, but is good enough for pickNaN. */
758 a_cls = (!floatx80_is_any_nan(a)
759 ? float_class_normal
760 : floatx80_is_signaling_nan(a, status)
761 ? float_class_snan
762 : float_class_qnan);
763 b_cls = (!floatx80_is_any_nan(b)
764 ? float_class_normal
765 : floatx80_is_signaling_nan(b, status)
766 ? float_class_snan
767 : float_class_qnan);
Aurelien Jarno1f398e02011-01-06 15:38:19 +0100768
Richard Henderson4f251cf2018-05-10 15:21:31 -0700769 if (is_snan(a_cls) || is_snan(b_cls)) {
Peter Maydellff32e162015-02-02 18:47:16 +0000770 float_raise(float_flag_invalid, status);
771 }
Peter Maydell354f2112010-12-16 11:51:17 +0000772
Peter Maydella2f2d282015-02-02 18:57:35 +0000773 if (status->default_nan_mode) {
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200774 return floatx80_default_nan(status);
Aurelien Jarno10201602011-01-14 20:39:17 +0100775 }
776
Peter Maydell354f2112010-12-16 11:51:17 +0000777 if (a.low < b.low) {
778 aIsLargerSignificand = 0;
779 } else if (b.low < a.low) {
780 aIsLargerSignificand = 1;
781 } else {
782 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
bellard158142c2005-03-13 16:54:06 +0000783 }
Peter Maydell354f2112010-12-16 11:51:17 +0000784
Max Filippov913602e2020-06-30 19:35:57 -0700785 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
Richard Henderson4f251cf2018-05-10 15:21:31 -0700786 if (is_snan(b_cls)) {
Richard Henderson48853122018-05-10 14:11:15 -0700787 return floatx80_silence_nan(b, status);
788 }
789 return b;
Peter Maydell354f2112010-12-16 11:51:17 +0000790 } else {
Richard Henderson4f251cf2018-05-10 15:21:31 -0700791 if (is_snan(a_cls)) {
Richard Henderson48853122018-05-10 14:11:15 -0700792 return floatx80_silence_nan(a, status);
793 }
794 return a;
bellard158142c2005-03-13 16:54:06 +0000795 }
bellard158142c2005-03-13 16:54:06 +0000796}
797
bellard158142c2005-03-13 16:54:06 +0000798/*----------------------------------------------------------------------------
ths5a6932d2007-11-16 14:57:36 +0000799| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
800| NaN; otherwise returns 0.
bellard158142c2005-03-13 16:54:06 +0000801*----------------------------------------------------------------------------*/
802
Richard Henderson150c7a92020-05-05 12:16:24 -0700803bool float128_is_quiet_nan(float128 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000804{
Max Filippovcc43c692020-06-30 19:35:49 -0700805 if (no_signaling_nans(status)) {
806 return float128_is_any_nan(a);
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200807 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700808 if (snan_bit_is_one(status)) {
809 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
810 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
811 } else {
812 return ((a.high << 1) >= 0xFFFF000000000000ULL)
813 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
814 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200815 }
bellard158142c2005-03-13 16:54:06 +0000816}
817
818/*----------------------------------------------------------------------------
819| Returns 1 if the quadruple-precision floating-point value `a' is a
820| signaling NaN; otherwise returns 0.
821*----------------------------------------------------------------------------*/
822
Richard Henderson150c7a92020-05-05 12:16:24 -0700823bool float128_is_signaling_nan(float128 a, float_status *status)
bellard158142c2005-03-13 16:54:06 +0000824{
Max Filippovcc43c692020-06-30 19:35:49 -0700825 if (no_signaling_nans(status)) {
826 return 0;
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200827 } else {
Max Filippovcc43c692020-06-30 19:35:49 -0700828 if (snan_bit_is_one(status)) {
829 return ((a.high << 1) >= 0xFFFF000000000000ULL)
830 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
831 } else {
832 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
833 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
834 }
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200835 }
Richard Hendersonbca52232018-05-10 11:24:13 -0700836}