blob: 0ef13c5e9a8cc2ac826d622da43b3fa072230ba4 [file] [log] [blame]
bellard67e999b2006-09-03 16:09:07 +00001/*
2 * QEMU Sparc32 DMA controller emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +01006 * Modifications:
7 * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
8 *
bellard67e999b2006-09-03 16:09:07 +00009 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
Blue Swirl6f6260c2009-07-15 20:45:19 +000027
Peter Maydell04308912016-01-26 18:17:30 +000028#include "qemu/osdep.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020029#include "hw/irq.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020030#include "hw/qdev-properties.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010031#include "hw/sparc/sparc32_dma.h"
Mark Cave-Ayland1527f482018-01-08 18:16:34 +000032#include "hw/sparc/sun4m_iommu.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010033#include "hw/sysbus.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020034#include "migration/vmstate.h"
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010035#include "sysemu/dma.h"
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +010036#include "qapi/error.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020037#include "qemu/module.h"
Blue Swirl97bf4852010-10-31 09:24:14 +000038#include "trace.h"
bellard67e999b2006-09-03 16:09:07 +000039
40/*
41 * This is the DMA controller part of chip STP2000 (Master I/O), also
42 * produced as NCR89C100. See
43 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
44 * and
45 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
46 */
47
blueswir15aca8c32007-05-26 17:39:43 +000048#define DMA_SIZE (4 * sizeof(uint32_t))
blueswir109723aa2008-12-15 20:24:25 +000049/* We need the mask, because one instance of the device is not page
50 aligned (ledma, start address 0x0010) */
51#define DMA_MASK (DMA_SIZE - 1)
Bob Breuere0087e62010-12-20 11:55:33 -060052/* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
Bob Breuer86d1c382010-12-18 11:09:04 -060053#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
54#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
bellard67e999b2006-09-03 16:09:07 +000055
56#define DMA_VER 0xa0000000
57#define DMA_INTR 1
58#define DMA_INTREN 0x10
59#define DMA_WRITE_MEM 0x100
Blue Swirl73d74342010-09-11 16:38:33 +000060#define DMA_EN 0x200
bellard67e999b2006-09-03 16:09:07 +000061#define DMA_LOADED 0x04000000
blueswir15aca8c32007-05-26 17:39:43 +000062#define DMA_DRAIN_FIFO 0x40
bellard67e999b2006-09-03 16:09:07 +000063#define DMA_RESET 0x80
64
Artyom Tarasenko65899fe2010-05-22 10:38:56 +020065/* XXX SCSI and ethernet should have different read-only bit masks */
66#define DMA_CSR_RO_MASK 0xfe000007
67
Blue Swirl73d74342010-09-11 16:38:33 +000068enum {
69 GPIO_RESET = 0,
70 GPIO_DMA,
bellard67e999b2006-09-03 16:09:07 +000071};
72
bellard9b94dc32006-09-03 19:48:17 +000073/* Note: on sparc, the lance 16 bit bus is swapped */
Avi Kivitya8170e52012-10-23 12:30:10 +020074void ledma_memory_read(void *opaque, hwaddr addr,
bellard9b94dc32006-09-03 19:48:17 +000075 uint8_t *buf, int len, int do_bswap)
bellard67e999b2006-09-03 16:09:07 +000076{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +010077 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010078 IOMMUState *is = (IOMMUState *)s->iommu;
bellard9b94dc32006-09-03 19:48:17 +000079 int i;
bellard67e999b2006-09-03 16:09:07 +000080
blueswir15aca8c32007-05-26 17:39:43 +000081 addr |= s->dmaregs[3];
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +010082 trace_ledma_memory_read(addr, len);
bellard9b94dc32006-09-03 19:48:17 +000083 if (do_bswap) {
Philippe Mathieu-Daudéba06fe82020-09-03 10:08:29 +020084 dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);
bellard9b94dc32006-09-03 19:48:17 +000085 } else {
86 addr &= ~1;
87 len &= ~1;
Philippe Mathieu-Daudéba06fe82020-09-03 10:08:29 +020088 dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);
bellard9b94dc32006-09-03 19:48:17 +000089 for(i = 0; i < len; i += 2) {
90 bswap16s((uint16_t *)(buf + i));
91 }
92 }
bellard67e999b2006-09-03 16:09:07 +000093}
94
Avi Kivitya8170e52012-10-23 12:30:10 +020095void ledma_memory_write(void *opaque, hwaddr addr,
bellard9b94dc32006-09-03 19:48:17 +000096 uint8_t *buf, int len, int do_bswap)
bellard67e999b2006-09-03 16:09:07 +000097{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +010098 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +010099 IOMMUState *is = (IOMMUState *)s->iommu;
bellard9b94dc32006-09-03 19:48:17 +0000100 int l, i;
101 uint16_t tmp_buf[32];
bellard67e999b2006-09-03 16:09:07 +0000102
blueswir15aca8c32007-05-26 17:39:43 +0000103 addr |= s->dmaregs[3];
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +0100104 trace_ledma_memory_write(addr, len);
bellard9b94dc32006-09-03 19:48:17 +0000105 if (do_bswap) {
Philippe Mathieu-Daudéba06fe82020-09-03 10:08:29 +0200106 dma_memory_write(&is->iommu_as, addr, buf, len,
107 MEMTXATTRS_UNSPECIFIED);
bellard9b94dc32006-09-03 19:48:17 +0000108 } else {
109 addr &= ~1;
110 len &= ~1;
111 while (len > 0) {
112 l = len;
113 if (l > sizeof(tmp_buf))
114 l = sizeof(tmp_buf);
115 for(i = 0; i < l; i += 2) {
116 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
117 }
Philippe Mathieu-Daudéba06fe82020-09-03 10:08:29 +0200118 dma_memory_write(&is->iommu_as, addr, tmp_buf, l,
119 MEMTXATTRS_UNSPECIFIED);
bellard9b94dc32006-09-03 19:48:17 +0000120 len -= l;
121 buf += l;
122 addr += l;
123 }
124 }
bellard67e999b2006-09-03 16:09:07 +0000125}
126
blueswir170c0de92007-05-27 16:36:10 +0000127static void dma_set_irq(void *opaque, int irq, int level)
bellard67e999b2006-09-03 16:09:07 +0000128{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100129 DMADeviceState *s = opaque;
blueswir170c0de92007-05-27 16:36:10 +0000130 if (level) {
blueswir170c0de92007-05-27 16:36:10 +0000131 s->dmaregs[0] |= DMA_INTR;
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100132 if (s->dmaregs[0] & DMA_INTREN) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000133 trace_sparc32_dma_set_irq_raise();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100134 qemu_irq_raise(s->irq);
135 }
blueswir170c0de92007-05-27 16:36:10 +0000136 } else {
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100137 if (s->dmaregs[0] & DMA_INTR) {
138 s->dmaregs[0] &= ~DMA_INTR;
139 if (s->dmaregs[0] & DMA_INTREN) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000140 trace_sparc32_dma_set_irq_lower();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100141 qemu_irq_lower(s->irq);
142 }
143 }
blueswir170c0de92007-05-27 16:36:10 +0000144 }
bellard67e999b2006-09-03 16:09:07 +0000145}
146
147void espdma_memory_read(void *opaque, uint8_t *buf, int len)
148{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100149 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100150 IOMMUState *is = (IOMMUState *)s->iommu;
bellard67e999b2006-09-03 16:09:07 +0000151
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +0100152 trace_espdma_memory_read(s->dmaregs[1], len);
Philippe Mathieu-Daudéba06fe82020-09-03 10:08:29 +0200153 dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len,
154 MEMTXATTRS_UNSPECIFIED);
bellard67e999b2006-09-03 16:09:07 +0000155 s->dmaregs[1] += len;
156}
157
158void espdma_memory_write(void *opaque, uint8_t *buf, int len)
159{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100160 DMADeviceState *s = opaque;
Mark Cave-Aylandc413e9a2017-10-27 13:09:03 +0100161 IOMMUState *is = (IOMMUState *)s->iommu;
bellard67e999b2006-09-03 16:09:07 +0000162
Mark Cave-Ayland331b7fc2017-10-14 13:22:22 +0100163 trace_espdma_memory_write(s->dmaregs[1], len);
Philippe Mathieu-Daudéba06fe82020-09-03 10:08:29 +0200164 dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len,
165 MEMTXATTRS_UNSPECIFIED);
bellard67e999b2006-09-03 16:09:07 +0000166 s->dmaregs[1] += len;
167}
168
Avi Kivitya8170e52012-10-23 12:30:10 +0200169static uint64_t dma_mem_read(void *opaque, hwaddr addr,
Avi Kivityd6c5f062011-11-14 11:55:27 +0200170 unsigned size)
bellard67e999b2006-09-03 16:09:07 +0000171{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100172 DMADeviceState *s = opaque;
bellard67e999b2006-09-03 16:09:07 +0000173 uint32_t saddr;
174
blueswir109723aa2008-12-15 20:24:25 +0000175 saddr = (addr & DMA_MASK) >> 2;
Blue Swirl97bf4852010-10-31 09:24:14 +0000176 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
bellard67e999b2006-09-03 16:09:07 +0000177 return s->dmaregs[saddr];
178}
179
Avi Kivitya8170e52012-10-23 12:30:10 +0200180static void dma_mem_write(void *opaque, hwaddr addr,
Avi Kivityd6c5f062011-11-14 11:55:27 +0200181 uint64_t val, unsigned size)
bellard67e999b2006-09-03 16:09:07 +0000182{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100183 DMADeviceState *s = opaque;
bellard67e999b2006-09-03 16:09:07 +0000184 uint32_t saddr;
185
blueswir109723aa2008-12-15 20:24:25 +0000186 saddr = (addr & DMA_MASK) >> 2;
Blue Swirl97bf4852010-10-31 09:24:14 +0000187 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
bellard67e999b2006-09-03 16:09:07 +0000188 switch (saddr) {
189 case 0:
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100190 if (val & DMA_INTREN) {
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200191 if (s->dmaregs[0] & DMA_INTR) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000192 trace_sparc32_dma_set_irq_raise();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100193 qemu_irq_raise(s->irq);
194 }
195 } else {
196 if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000197 trace_sparc32_dma_set_irq_lower();
Artyom Tarasenko6f57bbf2010-02-15 18:39:50 +0100198 qemu_irq_lower(s->irq);
199 }
pbrookd537cf62007-04-07 18:14:41 +0000200 }
bellard67e999b2006-09-03 16:09:07 +0000201 if (val & DMA_RESET) {
Blue Swirl73d74342010-09-11 16:38:33 +0000202 qemu_irq_raise(s->gpio[GPIO_RESET]);
203 qemu_irq_lower(s->gpio[GPIO_RESET]);
blueswir15aca8c32007-05-26 17:39:43 +0000204 } else if (val & DMA_DRAIN_FIFO) {
205 val &= ~DMA_DRAIN_FIFO;
bellard67e999b2006-09-03 16:09:07 +0000206 } else if (val == 0)
blueswir15aca8c32007-05-26 17:39:43 +0000207 val = DMA_DRAIN_FIFO;
Blue Swirl73d74342010-09-11 16:38:33 +0000208
209 if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000210 trace_sparc32_dma_enable_raise();
Blue Swirl73d74342010-09-11 16:38:33 +0000211 qemu_irq_raise(s->gpio[GPIO_DMA]);
212 } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000213 trace_sparc32_dma_enable_lower();
Blue Swirl73d74342010-09-11 16:38:33 +0000214 qemu_irq_lower(s->gpio[GPIO_DMA]);
215 }
216
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200217 val &= ~DMA_CSR_RO_MASK;
bellard67e999b2006-09-03 16:09:07 +0000218 val |= DMA_VER;
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200219 s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
bellard67e999b2006-09-03 16:09:07 +0000220 break;
221 case 1:
222 s->dmaregs[0] |= DMA_LOADED;
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200223 /* fall through */
bellard67e999b2006-09-03 16:09:07 +0000224 default:
Artyom Tarasenko65899fe2010-05-22 10:38:56 +0200225 s->dmaregs[saddr] = val;
bellard67e999b2006-09-03 16:09:07 +0000226 break;
227 }
bellard67e999b2006-09-03 16:09:07 +0000228}
229
Avi Kivityd6c5f062011-11-14 11:55:27 +0200230static const MemoryRegionOps dma_mem_ops = {
231 .read = dma_mem_read,
232 .write = dma_mem_write,
233 .endianness = DEVICE_NATIVE_ENDIAN,
234 .valid = {
235 .min_access_size = 4,
236 .max_access_size = 4,
237 },
bellard67e999b2006-09-03 16:09:07 +0000238};
239
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100240static void sparc32_dma_device_reset(DeviceState *d)
bellard67e999b2006-09-03 16:09:07 +0000241{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100242 DMADeviceState *s = SPARC32_DMA_DEVICE(d);
bellard67e999b2006-09-03 16:09:07 +0000243
blueswir15aca8c32007-05-26 17:39:43 +0000244 memset(s->dmaregs, 0, DMA_SIZE);
bellard67e999b2006-09-03 16:09:07 +0000245 s->dmaregs[0] = DMA_VER;
bellard67e999b2006-09-03 16:09:07 +0000246}
247
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100248static const VMStateDescription vmstate_sparc32_dma_device = {
Blue Swirl75c497d2009-08-28 20:46:15 +0000249 .name ="sparc32_dma",
250 .version_id = 2,
251 .minimum_version_id = 2,
Juan Quintela35d08452014-04-16 16:01:33 +0200252 .fields = (VMStateField[]) {
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100253 VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
Blue Swirl75c497d2009-08-28 20:46:15 +0000254 VMSTATE_END_OF_LIST()
255 }
256};
bellard67e999b2006-09-03 16:09:07 +0000257
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100258static void sparc32_dma_device_init(Object *obj)
Blue Swirl6f6260c2009-07-15 20:45:19 +0000259{
xiaoqiang zhao8c612072017-05-25 21:34:45 +0800260 DeviceState *dev = DEVICE(obj);
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100261 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
xiaoqiang zhao8c612072017-05-25 21:34:45 +0800262 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
bellard67e999b2006-09-03 16:09:07 +0000263
Andreas Färber70cd8d42013-07-26 16:55:59 +0200264 sysbus_init_irq(sbd, &s->irq);
bellard67e999b2006-09-03 16:09:07 +0000265
Andreas Färber70cd8d42013-07-26 16:55:59 +0200266 sysbus_init_mmio(sbd, &s->iomem);
bellard67e999b2006-09-03 16:09:07 +0000267
Mark Cave-Aylandf542ad02017-10-14 13:22:21 +0100268 object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
269 (Object **) &s->iommu,
270 qdev_prop_allow_set_link_before_realize,
Markus Armbrusterd2623122020-05-05 17:29:22 +0200271 0);
Mark Cave-Aylandf542ad02017-10-14 13:22:21 +0100272
Andreas Färber70cd8d42013-07-26 16:55:59 +0200273 qdev_init_gpio_in(dev, dma_set_irq, 1);
274 qdev_init_gpio_out(dev, s->gpio, 2);
xiaoqiang zhao8c612072017-05-25 21:34:45 +0800275}
Blue Swirl49ef6c92009-10-24 19:35:32 +0000276
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100277static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
Anthony Liguori999e12b2012-01-24 13:12:29 -0600278{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600279 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600280
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100281 dc->reset = sparc32_dma_device_reset;
282 dc->vmsd = &vmstate_sparc32_dma_device;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600283}
284
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100285static const TypeInfo sparc32_dma_device_info = {
286 .name = TYPE_SPARC32_DMA_DEVICE,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600287 .parent = TYPE_SYS_BUS_DEVICE,
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100288 .abstract = true,
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100289 .instance_size = sizeof(DMADeviceState),
290 .instance_init = sparc32_dma_device_init,
291 .class_init = sparc32_dma_device_class_init,
Blue Swirl6f6260c2009-07-15 20:45:19 +0000292};
293
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100294static void sparc32_espdma_device_init(Object *obj)
295{
296 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
Mark Cave-Aylandd19265e2020-09-26 15:02:13 +0100297 ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100298
299 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
300 "espdma-mmio", DMA_SIZE);
Mark Cave-Aylandd19265e2020-09-26 15:02:13 +0100301
Mark Cave-Ayland84fbefe2021-03-04 22:10:23 +0000302 object_initialize_child(obj, "esp", &es->esp, TYPE_SYSBUS_ESP);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100303}
304
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100305static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
306{
Mark Cave-Aylandd19265e2020-09-26 15:02:13 +0100307 ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev);
Mark Cave-Ayland84fbefe2021-03-04 22:10:23 +0000308 SysBusESPState *sysbus = SYSBUS_ESP(&es->esp);
Mark Cave-Aylandd19265e2020-09-26 15:02:13 +0100309 ESPState *esp = &sysbus->esp;
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100310
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100311 esp->dma_memory_read = espdma_memory_read;
312 esp->dma_memory_write = espdma_memory_write;
313 esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
314 sysbus->it_shift = 2;
315 esp->dma_enabled = 1;
Mark Cave-Aylandd19265e2020-09-26 15:02:13 +0100316 sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal);
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100317}
318
319static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
320{
321 DeviceClass *dc = DEVICE_CLASS(klass);
322
323 dc->realize = sparc32_espdma_device_realize;
324}
325
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100326static const TypeInfo sparc32_espdma_device_info = {
327 .name = TYPE_SPARC32_ESPDMA_DEVICE,
328 .parent = TYPE_SPARC32_DMA_DEVICE,
329 .instance_size = sizeof(ESPDMADeviceState),
330 .instance_init = sparc32_espdma_device_init,
Mark Cave-Ayland7f773ff2017-10-14 13:22:22 +0100331 .class_init = sparc32_espdma_device_class_init,
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100332};
333
334static void sparc32_ledma_device_init(Object *obj)
335{
336 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
Mark Cave-Aylandbce83ed2020-09-26 15:02:12 +0100337 LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100338
339 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
Mark Cave-Ayland4ca3d362017-10-14 13:22:22 +0100340 "ledma-mmio", DMA_SIZE);
Mark Cave-Aylandbce83ed2020-09-26 15:02:12 +0100341
342 object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100343}
344
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100345static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
346{
Mark Cave-Aylandbce83ed2020-09-26 15:02:12 +0100347 LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev);
348 SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance);
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100349
Mark Cave-Aylandbce83ed2020-09-26 15:02:12 +0100350 object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort);
351 sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal);
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100352}
353
354static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
355{
356 DeviceClass *dc = DEVICE_CLASS(klass);
357
358 dc->realize = sparc32_ledma_device_realize;
359}
360
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100361static const TypeInfo sparc32_ledma_device_info = {
362 .name = TYPE_SPARC32_LEDMA_DEVICE,
363 .parent = TYPE_SPARC32_DMA_DEVICE,
364 .instance_size = sizeof(LEDMADeviceState),
365 .instance_init = sparc32_ledma_device_init,
Mark Cave-Aylande6ca02a2017-10-14 13:22:22 +0100366 .class_init = sparc32_ledma_device_class_init,
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100367};
368
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100369static void sparc32_dma_realize(DeviceState *dev, Error **errp)
370{
371 SPARC32DMAState *s = SPARC32_DMA(dev);
372 DeviceState *espdma, *esp, *ledma, *lance;
373 SysBusDevice *sbd;
374 Object *iommu;
375
376 iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
377 if (!iommu) {
378 error_setg(errp, "unable to locate sun4m IOMMU device");
379 return;
380 }
381
Mark Cave-Ayland1f10fd52020-09-26 15:02:11 +0100382 espdma = DEVICE(&s->espdma);
Markus Armbruster5325cc32020-07-07 18:05:54 +0200383 object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort);
Mark Cave-Ayland1f10fd52020-09-26 15:02:11 +0100384 sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100385
386 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
387 sbd = SYS_BUS_DEVICE(esp);
388 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
389 qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
390 qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
391
392 sbd = SYS_BUS_DEVICE(espdma);
393 memory_region_add_subregion(&s->dmamem, 0x0,
394 sysbus_mmio_get_region(sbd, 0));
395
Mark Cave-Ayland1f10fd52020-09-26 15:02:11 +0100396 ledma = DEVICE(&s->ledma);
Markus Armbruster5325cc32020-07-07 18:05:54 +0200397 object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort);
Mark Cave-Ayland1f10fd52020-09-26 15:02:11 +0100398 sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100399
400 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
401 sbd = SYS_BUS_DEVICE(lance);
402 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
403 qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
404
405 sbd = SYS_BUS_DEVICE(ledma);
406 memory_region_add_subregion(&s->dmamem, 0x10,
407 sysbus_mmio_get_region(sbd, 0));
Mark Cave-Ayland4ca3d362017-10-14 13:22:22 +0100408
409 /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */
410 memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
411 sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
412 memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100413}
414
415static void sparc32_dma_init(Object *obj)
416{
417 SPARC32DMAState *s = SPARC32_DMA(obj);
418 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
419
420 memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
421 sysbus_init_mmio(sbd, &s->dmamem);
Mark Cave-Ayland1f10fd52020-09-26 15:02:11 +0100422
423 object_initialize_child(obj, "espdma", &s->espdma,
424 TYPE_SPARC32_ESPDMA_DEVICE);
425 object_initialize_child(obj, "ledma", &s->ledma,
426 TYPE_SPARC32_LEDMA_DEVICE);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100427}
428
429static void sparc32_dma_class_init(ObjectClass *klass, void *data)
430{
431 DeviceClass *dc = DEVICE_CLASS(klass);
432
433 dc->realize = sparc32_dma_realize;
434}
435
436static const TypeInfo sparc32_dma_info = {
437 .name = TYPE_SPARC32_DMA,
438 .parent = TYPE_SYS_BUS_DEVICE,
439 .instance_size = sizeof(SPARC32DMAState),
440 .instance_init = sparc32_dma_init,
441 .class_init = sparc32_dma_class_init,
442};
443
444
Andreas Färber83f7d432012-02-09 15:20:55 +0100445static void sparc32_dma_register_types(void)
Blue Swirl6f6260c2009-07-15 20:45:19 +0000446{
Mark Cave-Ayland6a1f53f2017-10-14 13:22:21 +0100447 type_register_static(&sparc32_dma_device_info);
Mark Cave-Ayland52d39e52017-10-14 13:22:21 +0100448 type_register_static(&sparc32_espdma_device_info);
449 type_register_static(&sparc32_ledma_device_info);
Mark Cave-Ayland6aa62ed2017-10-14 13:22:22 +0100450 type_register_static(&sparc32_dma_info);
Blue Swirl6f6260c2009-07-15 20:45:19 +0000451}
452
Andreas Färber83f7d432012-02-09 15:20:55 +0100453type_init(sparc32_dma_register_types)