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aurel324ce7ff62008-04-07 19:47:14 +00001/*
2 * QEMU MIPS Jazz support
3 *
4 * Copyright (c) 2007-2008 Hervé Poussineau
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
Peter Maydellc6848222016-01-18 17:35:00 +000025#include "qemu/osdep.h"
Markus Armbrustera8d25322019-05-23 16:35:08 +020026#include "qemu-common.h"
Paolo Bonzini2c65db52020-10-28 07:36:57 -040027#include "qemu/datadir.h"
Philippe Mathieu-Daudé79b99fe2020-10-12 11:57:59 +020028#include "hw/clock.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010029#include "hw/mips/mips.h"
30#include "hw/mips/cpudevs.h"
Paolo Bonzini852c27e2019-12-12 17:15:43 +010031#include "hw/intc/i8259.h"
Philippe Mathieu-Daudé55f613a2018-03-08 23:39:23 +010032#include "hw/dma/i8257.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010033#include "hw/char/serial.h"
Philippe Mathieu-Daudébb3d5ea2018-03-08 23:39:22 +010034#include "hw/char/parallel.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010035#include "hw/isa/isa.h"
36#include "hw/block/fdc.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010037#include "sysemu/sysemu.h"
38#include "sysemu/arch_init.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010039#include "hw/boards.h"
Paolo Bonzini1422e322012-10-24 08:43:34 +020040#include "net/net.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010041#include "hw/scsi/esp.h"
42#include "hw/mips/bios.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010043#include "hw/loader.h"
Philippe Mathieu-Daudébcdb9062019-10-04 01:03:53 +020044#include "hw/rtc/mc146818rtc.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010045#include "hw/timer/i8254.h"
Philippe Mathieu-Daudé866e2b32017-10-17 13:44:21 -030046#include "hw/display/vga.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010047#include "hw/audio/pcspk.h"
Philippe Mathieu-Daudé47973a22018-03-08 23:39:24 +010048#include "hw/input/i8042.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010049#include "hw/sysbus.h"
Andreas Färber38c88942013-07-29 16:05:32 +020050#include "sysemu/qtest.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020051#include "sysemu/reset.h"
Markus Armbrustere688df62018-02-01 12:18:31 +010052#include "qapi/error.h"
Aurelien Jarno2e985fe2013-08-03 16:03:18 +020053#include "qemu/error-report.h"
Veronia Bahaaf348b6d2016-03-20 19:16:19 +020054#include "qemu/help_option.h"
Claudio Fontana78271682021-02-04 17:39:23 +010055#ifdef CONFIG_TCG
56#include "hw/core/tcg-cpu-ops.h"
57#endif /* CONFIG_TCG */
aurel324ce7ff62008-04-07 19:47:14 +000058
Filip Bozuta68fa5f52019-12-06 14:58:03 +010059enum jazz_model_e {
aurel324ce7ff62008-04-07 19:47:14 +000060 JAZZ_MAGNUM,
aurel32c1711482008-04-08 19:51:06 +000061 JAZZ_PICA61,
aurel324ce7ff62008-04-07 19:47:14 +000062};
63
64static void main_cpu_reset(void *opaque)
65{
Andreas Färberf37f4352012-05-05 14:06:50 +020066 MIPSCPU *cpu = opaque;
67
68 cpu_reset(CPU(cpu));
aurel324ce7ff62008-04-07 19:47:14 +000069}
70
Avi Kivitya8170e52012-10-23 12:30:10 +020071static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
aurel324ce7ff62008-04-07 19:47:14 +000072{
Hervé Poussineau5c63bcf2015-02-01 09:12:52 +010073 uint8_t val;
Peter Maydell5c9eb022015-04-26 16:49:24 +010074 address_space_read(&address_space_memory, 0x90000071,
75 MEMTXATTRS_UNSPECIFIED, &val, 1);
Hervé Poussineau5c63bcf2015-02-01 09:12:52 +010076 return val;
aurel324ce7ff62008-04-07 19:47:14 +000077}
78
Avi Kivitya8170e52012-10-23 12:30:10 +020079static void rtc_write(void *opaque, hwaddr addr,
Avi Kivity60581b32011-08-08 21:59:19 +030080 uint64_t val, unsigned size)
aurel324ce7ff62008-04-07 19:47:14 +000081{
Hervé Poussineau5c63bcf2015-02-01 09:12:52 +010082 uint8_t buf = val & 0xff;
Peter Maydell5c9eb022015-04-26 16:49:24 +010083 address_space_write(&address_space_memory, 0x90000071,
84 MEMTXATTRS_UNSPECIFIED, &buf, 1);
aurel324ce7ff62008-04-07 19:47:14 +000085}
86
Avi Kivity60581b32011-08-08 21:59:19 +030087static const MemoryRegionOps rtc_ops = {
88 .read = rtc_read,
89 .write = rtc_write,
90 .endianness = DEVICE_NATIVE_ENDIAN,
aurel324ce7ff62008-04-07 19:47:14 +000091};
92
Avi Kivitya8170e52012-10-23 12:30:10 +020093static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
Avi Kivity60581b32011-08-08 21:59:19 +030094 unsigned size)
95{
Filip Bozuta68fa5f52019-12-06 14:58:03 +010096 /*
97 * Nothing to do. That is only to ensure that
98 * the current DMA acknowledge cycle is completed.
99 */
Avi Kivity60581b32011-08-08 21:59:19 +0300100 return 0xff;
101}
aurel324ce7ff62008-04-07 19:47:14 +0000102
Avi Kivitya8170e52012-10-23 12:30:10 +0200103static void dma_dummy_write(void *opaque, hwaddr addr,
Avi Kivity60581b32011-08-08 21:59:19 +0300104 uint64_t val, unsigned size)
aurel32c6945b12009-01-01 13:03:36 +0000105{
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100106 /*
107 * Nothing to do. That is only to ensure that
108 * the current DMA acknowledge cycle is completed.
109 */
aurel32c6945b12009-01-01 13:03:36 +0000110}
111
Avi Kivity60581b32011-08-08 21:59:19 +0300112static const MemoryRegionOps dma_dummy_ops = {
113 .read = dma_dummy_read,
114 .write = dma_dummy_write,
115 .endianness = DEVICE_NATIVE_ENDIAN,
aurel32c6945b12009-01-01 13:03:36 +0000116};
117
aurel324ce7ff62008-04-07 19:47:14 +0000118#define MAGNUM_BIOS_SIZE_MAX 0x7e000
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100119#define MAGNUM_BIOS_SIZE \
120 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
Claudio Fontanacbc183d2021-02-04 17:39:18 +0100121
Hervé Poussineauf33772c2015-02-01 09:12:51 +0100122static void mips_jazz_init(MachineState *machine,
Richard Hendersonc2d0d012011-08-10 15:28:11 -0700123 enum jazz_model_e jazz_model)
aurel324ce7ff62008-04-07 19:47:14 +0000124{
Hervé Poussineauf33772c2015-02-01 09:12:51 +0100125 MemoryRegion *address_space = get_system_memory();
Paul Brook5cea8592009-05-30 00:52:44 +0100126 char *filename;
aurel324ce7ff62008-04-07 19:47:14 +0000127 int bios_size, n;
Philippe Mathieu-Daudé79b99fe2020-10-12 11:57:59 +0200128 Clock *cpuclk;
Andreas Färber6bd8da62012-05-05 14:05:42 +0200129 MIPSCPU *cpu;
Richard Henderson3803b6b2021-02-27 12:44:00 -0800130 MIPSCPUClass *mcc;
Andreas Färber61c56c82012-03-14 01:38:23 +0100131 CPUMIPSState *env;
Hervé Poussineaud791d602015-06-03 22:45:41 +0200132 qemu_irq *i8259;
aurel32c6945b12009-01-01 13:03:36 +0000133 rc4030_dma *dmas;
Alexey Kardashevskiy3df9d742017-07-11 13:56:19 +1000134 IOMMUMemoryRegion *rc4030_dma_mr;
Hervé Poussineau5c63bcf2015-02-01 09:12:52 +0100135 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
136 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
Avi Kivity60581b32011-08-08 21:59:19 +0300137 MemoryRegion *rtc = g_new(MemoryRegion, 1);
Richard Hendersondbff76a2011-08-10 15:28:17 -0700138 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
Avi Kivity60581b32011-08-08 21:59:19 +0300139 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
aurel32a65f56e2009-04-15 14:57:54 +0000140 NICInfo *nd;
Hervé Poussineaud791d602015-06-03 22:45:41 +0200141 DeviceState *dev, *rc4030;
Hervé Poussineaucd3e2402011-07-18 23:34:22 +0200142 SysBusDevice *sysbus;
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100143 ISABus *isa_bus;
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000144 ISADevice *pit;
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200145 DriveInfo *fds[MAX_FD];
Avi Kivity60581b32011-08-08 21:59:19 +0300146 MemoryRegion *bios = g_new(MemoryRegion, 1);
147 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
Mark Cave-Ayland09eb69a2018-06-13 10:47:26 +0100148 SysBusESPState *sysbus_esp;
Thomas Huth148b2ba2018-03-07 10:24:04 +0100149 ESPState *esp;
Philippe Mathieu-Daudé79b99fe2020-10-12 11:57:59 +0200150 static const struct {
151 unsigned freq_hz;
152 unsigned pll_mult;
153 } ext_clk[] = {
154 [JAZZ_MAGNUM] = {50000000, 2},
155 [JAZZ_PICA61] = {33333333, 4},
156 };
aurel324ce7ff62008-04-07 19:47:14 +0000157
Igor Mammedov7c3dd4c2020-02-19 11:09:28 -0500158 if (machine->ram_size > 256 * MiB) {
159 error_report("RAM size more than 256Mb is not supported");
160 exit(EXIT_FAILURE);
161 }
162
Philippe Mathieu-Daudé79b99fe2020-10-12 11:57:59 +0200163 cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
164 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz
165 * ext_clk[jazz_model].pll_mult);
166
aurel324ce7ff62008-04-07 19:47:14 +0000167 /* init CPUs */
Philippe Mathieu-Daudé79b99fe2020-10-12 11:57:59 +0200168 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
Andreas Färber6bd8da62012-05-05 14:05:42 +0200169 env = &cpu->env;
Andreas Färberf37f4352012-05-05 14:06:50 +0200170 qemu_register_reset(main_cpu_reset, cpu);
aurel324ce7ff62008-04-07 19:47:14 +0000171
Peter Maydell8d2b8712019-08-02 17:04:56 +0100172 /*
173 * Chipset returns 0 in invalid reads and do not raise data exceptions.
Hervé Poussineau54e75552013-11-04 23:26:17 +0100174 * However, we can't simply add a global memory region to catch
Peter Maydell8d2b8712019-08-02 17:04:56 +0100175 * everything, as this would make all accesses including instruction
176 * accesses be ignored and not raise exceptions.
Peter Maydell8d2b8712019-08-02 17:04:56 +0100177 *
178 * NOTE: this behaviour of raising exceptions for bad instruction
179 * fetches but not bad data accesses was added in commit 54e755588cf1e9
180 * to restore behaviour broken by c658b94f6e8c206, but it is not clear
181 * whether the real hardware behaves this way. It is possible that
182 * real hardware ignores bad instruction fetches as well -- if so then
183 * we could replace this hijacking of CPU methods with a simple global
184 * memory region that catches all memory accesses, as we do on Malta.
185 */
Richard Henderson3803b6b2021-02-27 12:44:00 -0800186 mcc = MIPS_CPU_GET_CLASS(cpu);
187 mcc->no_data_aborts = true;
Hervé Poussineau54e75552013-11-04 23:26:17 +0100188
aurel324ce7ff62008-04-07 19:47:14 +0000189 /* allocate RAM */
Igor Mammedov2a9bded2020-02-19 11:09:27 -0500190 memory_region_add_subregion(address_space, 0, machine->ram);
pbrookdcac9672009-04-09 20:05:49 +0000191
Philippe Mathieu-Daudé3fab7f22020-02-24 21:55:08 +0100192 memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +0200193 &error_fatal);
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400194 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
Avi Kivity60581b32011-08-08 21:59:19 +0300195 0, MAGNUM_BIOS_SIZE);
196 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
197 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
aurel324ce7ff62008-04-07 19:47:14 +0000198
199 /* load the BIOS image. */
Paolo Bonzini59588be2020-10-26 10:30:21 -0400200 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
Paul Brook5cea8592009-05-30 00:52:44 +0100201 if (filename) {
202 bios_size = load_image_targphys(filename, 0xfff00000LL,
203 MAGNUM_BIOS_SIZE);
Anthony Liguori7267c092011-08-20 22:09:37 -0500204 g_free(filename);
Paul Brook5cea8592009-05-30 00:52:44 +0100205 } else {
206 bios_size = -1;
207 }
Pavel Dovgalyuka4374f82020-07-21 09:15:05 +0300208 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE)
Paolo Bonzini59588be2020-10-26 10:30:21 -0400209 && machine->firmware && !qtest_enabled()) {
210 error_report("Could not load MIPS bios '%s'", machine->firmware);
Aurelien Jarno2e985fe2013-08-03 16:03:18 +0200211 exit(1);
aurel324ce7ff62008-04-07 19:47:14 +0000212 }
213
aurel324ce7ff62008-04-07 19:47:14 +0000214 /* Init CPU internal devices */
Paolo Bonzini5a975d42016-03-15 14:32:19 +0100215 cpu_mips_irq_init_cpu(cpu);
216 cpu_mips_clock_init(cpu);
aurel324ce7ff62008-04-07 19:47:14 +0000217
218 /* Chipset */
Hervé Poussineaud791d602015-06-03 22:45:41 +0200219 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
220 sysbus = SYS_BUS_DEVICE(rc4030);
221 sysbus_connect_irq(sysbus, 0, env->irq[6]);
222 sysbus_connect_irq(sysbus, 1, env->irq[3]);
223 memory_region_add_subregion(address_space, 0x80000000,
224 sysbus_mmio_get_region(sysbus, 0));
225 memory_region_add_subregion(address_space, 0xf0000000,
226 sysbus_mmio_get_region(sysbus, 1));
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100227 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops,
228 NULL, "dummy_dma", 0x1000);
Avi Kivity60581b32011-08-08 21:59:19 +0300229 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
aurel324ce7ff62008-04-07 19:47:14 +0000230
Hervé Poussineau5c63bcf2015-02-01 09:12:52 +0100231 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
232 memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
233 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
234 memory_region_add_subregion(address_space, 0x90000000, isa_io);
235 memory_region_add_subregion(address_space, 0x91000000, isa_mem);
Markus Armbrusterd10e5432015-12-17 17:35:18 +0100236 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
Hervé Poussineau5c63bcf2015-02-01 09:12:52 +0100237
aurel324ce7ff62008-04-07 19:47:14 +0000238 /* ISA devices */
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100239 i8259 = i8259_init(isa_bus, env->irq[4]);
240 isa_bus_irqs(isa_bus, i8259);
Philippe Mathieu-Daudé55f613a2018-03-08 23:39:23 +0100241 i8257_dma_init(isa_bus, 0);
Philippe Mathieu-Daudéacf695e2017-10-17 13:44:15 -0300242 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
Gerd Hoffmann525d6542020-07-02 15:25:20 +0200243 pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);
aurel324ce7ff62008-04-07 19:47:14 +0000244
aurel324ce7ff62008-04-07 19:47:14 +0000245 /* Video card */
246 switch (jazz_model) {
247 case JAZZ_MAGNUM:
Markus Armbruster3e80f692020-06-10 07:31:58 +0200248 dev = qdev_new("sysbus-g364");
Andreas Färber1356b982013-01-20 02:47:33 +0100249 sysbus = SYS_BUS_DEVICE(dev);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200250 sysbus_realize_and_unref(sysbus, &error_fatal);
Hervé Poussineau97a3f6f2011-08-26 21:20:12 +0200251 sysbus_mmio_map(sysbus, 0, 0x60080000);
252 sysbus_mmio_map(sysbus, 1, 0x40000000);
Hervé Poussineaud791d602015-06-03 22:45:41 +0200253 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
Hervé Poussineau97a3f6f2011-08-26 21:20:12 +0200254 {
255 /* Simple ROM, so user doesn't have to provide one */
Avi Kivity60581b32011-08-08 21:59:19 +0300256 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
Philippe Mathieu-Daudé3fab7f22020-02-24 21:55:08 +0100257 memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000,
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +0200258 &error_fatal);
Avi Kivity60581b32011-08-08 21:59:19 +0300259 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
260 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
Hervé Poussineau97a3f6f2011-08-26 21:20:12 +0200261 rom[0] = 0x10; /* Mips G364 */
262 }
aurel324ce7ff62008-04-07 19:47:14 +0000263 break;
aurel32c1711482008-04-08 19:51:06 +0000264 case JAZZ_PICA61:
Avi Kivitybe20f9e2011-08-15 17:17:37 +0300265 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
aurel32c1711482008-04-08 19:51:06 +0000266 break;
aurel324ce7ff62008-04-07 19:47:14 +0000267 default:
268 break;
269 }
270
271 /* Network controller */
aurel32a65f56e2009-04-15 14:57:54 +0000272 for (n = 0; n < nb_nics; n++) {
273 nd = &nd_table[n];
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100274 if (!nd->model) {
Anthony Liguori7267c092011-08-20 22:09:37 -0500275 nd->model = g_strdup("dp83932");
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100276 }
aurel32a65f56e2009-04-15 14:57:54 +0000277 if (strcmp(nd->model, "dp83932") == 0) {
Hervé Poussineau104655a2015-06-03 22:45:45 +0200278 qemu_check_nic_model(nd, "dp83932");
279
Markus Armbruster3e80f692020-06-10 07:31:58 +0200280 dev = qdev_new("dp8393x");
Hervé Poussineau104655a2015-06-03 22:45:45 +0200281 qdev_set_nic_properties(dev, nd);
282 qdev_prop_set_uint8(dev, "it_shift", 2);
Markus Armbruster5325cc32020-07-07 18:05:54 +0200283 object_property_set_link(OBJECT(dev), "dma_mr",
284 OBJECT(rc4030_dma_mr), &error_abort);
Hervé Poussineau104655a2015-06-03 22:45:45 +0200285 sysbus = SYS_BUS_DEVICE(dev);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200286 sysbus_realize_and_unref(sysbus, &error_fatal);
Hervé Poussineau104655a2015-06-03 22:45:45 +0200287 sysbus_mmio_map(sysbus, 0, 0x80001000);
Hervé Poussineau89ae0ff2015-06-03 22:45:46 +0200288 sysbus_mmio_map(sysbus, 1, 0x8000b000);
Hervé Poussineau104655a2015-06-03 22:45:45 +0200289 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
aurel32a65f56e2009-04-15 14:57:54 +0000290 break;
Peter Maydellc8057f92012-08-02 13:45:54 +0100291 } else if (is_help_option(nd->model)) {
Alistair Francisbd6e1d82018-02-03 09:43:06 +0100292 error_report("Supported NICs: dp83932");
aurel32a65f56e2009-04-15 14:57:54 +0000293 exit(1);
294 } else {
Alistair Francisbd6e1d82018-02-03 09:43:06 +0100295 error_report("Unsupported NIC: %s", nd->model);
aurel32a65f56e2009-04-15 14:57:54 +0000296 exit(1);
297 }
298 }
aurel324ce7ff62008-04-07 19:47:14 +0000299
300 /* SCSI adapter */
Mark Cave-Ayland84fbefe2021-03-04 22:10:23 +0000301 dev = qdev_new(TYPE_SYSBUS_ESP);
302 sysbus_esp = SYSBUS_ESP(dev);
Mark Cave-Ayland09eb69a2018-06-13 10:47:26 +0100303 esp = &sysbus_esp->esp;
304 esp->dma_memory_read = rc4030_dma_read;
305 esp->dma_memory_write = rc4030_dma_write;
306 esp->dma_opaque = dmas[0];
307 sysbus_esp->it_shift = 0;
308 /* XXX for now until rc4030 has been changed to use DMA enable signal */
309 esp->dma_enabled = 1;
Mark Cave-Ayland09eb69a2018-06-13 10:47:26 +0100310
311 sysbus = SYS_BUS_DEVICE(dev);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200312 sysbus_realize_and_unref(sysbus, &error_fatal);
Mark Cave-Ayland09eb69a2018-06-13 10:47:26 +0100313 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
314 sysbus_mmio_map(sysbus, 0, 0x80002000);
315
Thomas Huth148b2ba2018-03-07 10:24:04 +0100316 scsi_bus_legacy_handle_cmdline(&esp->bus);
aurel324ce7ff62008-04-07 19:47:14 +0000317
318 /* Floppy */
aurel324ce7ff62008-04-07 19:47:14 +0000319 for (n = 0; n < MAX_FD; n++) {
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200320 fds[n] = drive_get(IF_FLOPPY, 0, n);
aurel324ce7ff62008-04-07 19:47:14 +0000321 }
Hervé Poussineau020e2982016-02-03 11:28:57 -0500322 /* FIXME: we should enable DMA with a custom IsaDma device */
323 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
aurel324ce7ff62008-04-07 19:47:14 +0000324
325 /* Real time clock */
Philippe Mathieu-Daudé6c646a12017-10-17 13:44:16 -0300326 mc146818_rtc_init(isa_bus, 1980, NULL);
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400327 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
Avi Kivity60581b32011-08-08 21:59:19 +0300328 memory_region_add_subregion(address_space, 0x80004000, rtc);
aurel324ce7ff62008-04-07 19:47:14 +0000329
330 /* Keyboard (i8042) */
Hervé Poussineaud791d602015-06-03 22:45:41 +0200331 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
332 i8042, 0x1000, 0x1);
Richard Hendersondbff76a2011-08-10 15:28:17 -0700333 memory_region_add_subregion(address_space, 0x80005000, i8042);
aurel324ce7ff62008-04-07 19:47:14 +0000334
335 /* Serial ports */
Peter Maydell9bca0ed2018-04-20 15:52:43 +0100336 if (serial_hd(0)) {
Hervé Poussineaud791d602015-06-03 22:45:41 +0200337 serial_mm_init(address_space, 0x80006000, 0,
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100338 qdev_get_gpio_in(rc4030, 8), 8000000 / 16,
Peter Maydell9bca0ed2018-04-20 15:52:43 +0100339 serial_hd(0), DEVICE_NATIVE_ENDIAN);
Blue Swirl2d483772010-03-21 19:47:11 +0000340 }
Peter Maydell9bca0ed2018-04-20 15:52:43 +0100341 if (serial_hd(1)) {
Hervé Poussineaud791d602015-06-03 22:45:41 +0200342 serial_mm_init(address_space, 0x80007000, 0,
Filip Bozuta68fa5f52019-12-06 14:58:03 +0100343 qdev_get_gpio_in(rc4030, 9), 8000000 / 16,
Peter Maydell9bca0ed2018-04-20 15:52:43 +0100344 serial_hd(1), DEVICE_NATIVE_ENDIAN);
Blue Swirl2d483772010-03-21 19:47:11 +0000345 }
aurel324ce7ff62008-04-07 19:47:14 +0000346
347 /* Parallel port */
348 if (parallel_hds[0])
Hervé Poussineaud791d602015-06-03 22:45:41 +0200349 parallel_mm_init(address_space, 0x80008000, 0,
350 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
aurel324ce7ff62008-04-07 19:47:14 +0000351
aurel324ce7ff62008-04-07 19:47:14 +0000352 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
aurel324ce7ff62008-04-07 19:47:14 +0000353
Hervé Poussineaucd3e2402011-07-18 23:34:22 +0200354 /* NVRAM */
Markus Armbruster3e80f692020-06-10 07:31:58 +0200355 dev = qdev_new("ds1225y");
Andreas Färber1356b982013-01-20 02:47:33 +0100356 sysbus = SYS_BUS_DEVICE(dev);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200357 sysbus_realize_and_unref(sysbus, &error_fatal);
Hervé Poussineaucd3e2402011-07-18 23:34:22 +0200358 sysbus_mmio_map(sysbus, 0, 0x80009000);
aurel324ce7ff62008-04-07 19:47:14 +0000359
360 /* LED indicator */
Hervé Poussineaub39506e2012-02-17 20:27:16 +0100361 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
Paolo Bonzini0287d892019-10-01 15:36:25 +0200362
363 g_free(dmas);
aurel324ce7ff62008-04-07 19:47:14 +0000364}
365
366static
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300367void mips_magnum_init(MachineState *machine)
aurel324ce7ff62008-04-07 19:47:14 +0000368{
Hervé Poussineauf33772c2015-02-01 09:12:51 +0100369 mips_jazz_init(machine, JAZZ_MAGNUM);
aurel324ce7ff62008-04-07 19:47:14 +0000370}
371
aurel32c1711482008-04-08 19:51:06 +0000372static
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300373void mips_pica61_init(MachineState *machine)
aurel32c1711482008-04-08 19:51:06 +0000374{
Hervé Poussineauf33772c2015-02-01 09:12:51 +0100375 mips_jazz_init(machine, JAZZ_PICA61);
aurel32c1711482008-04-08 19:51:06 +0000376}
377
Andreas Färber8a661ae2015-09-19 10:49:44 +0200378static void mips_magnum_class_init(ObjectClass *oc, void *data)
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500379{
Andreas Färber8a661ae2015-09-19 10:49:44 +0200380 MachineClass *mc = MACHINE_CLASS(oc);
381
Eduardo Habkoste264d292015-09-04 15:37:08 -0300382 mc->desc = "MIPS Magnum";
383 mc->init = mips_magnum_init;
384 mc->block_default_type = IF_SCSI;
Igor Mammedov3469e652017-10-05 15:51:12 +0200385 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
Igor Mammedov2a9bded2020-02-19 11:09:27 -0500386 mc->default_ram_id = "mips_jazz.ram";
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500387}
388
Andreas Färber8a661ae2015-09-19 10:49:44 +0200389static const TypeInfo mips_magnum_type = {
390 .name = MACHINE_TYPE_NAME("magnum"),
391 .parent = TYPE_MACHINE,
392 .class_init = mips_magnum_class_init,
393};
Eduardo Habkoste264d292015-09-04 15:37:08 -0300394
Andreas Färber8a661ae2015-09-19 10:49:44 +0200395static void mips_pica61_class_init(ObjectClass *oc, void *data)
Eduardo Habkoste264d292015-09-04 15:37:08 -0300396{
Andreas Färber8a661ae2015-09-19 10:49:44 +0200397 MachineClass *mc = MACHINE_CLASS(oc);
398
Eduardo Habkoste264d292015-09-04 15:37:08 -0300399 mc->desc = "Acer Pica 61";
400 mc->init = mips_pica61_init;
401 mc->block_default_type = IF_SCSI;
Igor Mammedov3469e652017-10-05 15:51:12 +0200402 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
Igor Mammedov2a9bded2020-02-19 11:09:27 -0500403 mc->default_ram_id = "mips_jazz.ram";
Eduardo Habkoste264d292015-09-04 15:37:08 -0300404}
405
Andreas Färber8a661ae2015-09-19 10:49:44 +0200406static const TypeInfo mips_pica61_type = {
407 .name = MACHINE_TYPE_NAME("pica61"),
408 .parent = TYPE_MACHINE,
409 .class_init = mips_pica61_class_init,
410};
411
412static void mips_jazz_machine_init(void)
413{
414 type_register_static(&mips_magnum_type);
415 type_register_static(&mips_pica61_type);
416}
417
Eduardo Habkost0e6aac82016-02-16 18:59:04 -0200418type_init(mips_jazz_machine_init)