blob: 08351354ed38bd53c369714cf9123ddcf80d2467 [file] [log] [blame]
bellardd4e81642003-05-25 16:46:15 +00001/*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
bellardb346ff42003-06-15 20:05:50 +000021/* allow to see translation results - the slowdown should be negligible, so we leave it */
22#define DEBUG_DISAS
23
bellard33417e72003-08-10 21:47:01 +000024#ifndef glue
25#define xglue(x, y) x ## y
26#define glue(x, y) xglue(x, y)
27#define stringify(s) tostring(s)
28#define tostring(s) #s
29#endif
30
bellardc98baaa2005-07-02 13:31:24 +000031#if __GNUC__ < 3
bellard33417e72003-08-10 21:47:01 +000032#define __builtin_expect(x, n) (x)
33#endif
34
bellarde2222c32003-08-10 23:39:03 +000035#ifdef __i386__
36#define REGPARM(n) __attribute((regparm(n)))
37#else
38#define REGPARM(n)
39#endif
40
bellardb346ff42003-06-15 20:05:50 +000041/* is_jmp field values */
42#define DISAS_NEXT 0 /* next instruction can be analyzed */
43#define DISAS_JUMP 1 /* only pc was modified dynamically */
44#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
45#define DISAS_TB_JUMP 3 /* only pc was modified statically */
46
47struct TranslationBlock;
48
49/* XXX: make safe guess about sizes */
50#define MAX_OP_PER_INSTR 32
51#define OPC_BUF_SIZE 512
52#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
53
54#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
55
56extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
57extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
bellardc27004e2005-01-03 23:35:10 +000058extern long gen_labels[OPC_BUF_SIZE];
59extern int nb_gen_labels;
60extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
61extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
bellard66e85a22003-06-24 13:28:12 +000062extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
bellardb346ff42003-06-15 20:05:50 +000063extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
bellardc3278b72005-03-20 12:43:29 +000064extern target_ulong gen_opc_jump_pc[2];
bellardb346ff42003-06-15 20:05:50 +000065
bellard9886cc12004-01-04 23:53:54 +000066typedef void (GenOpFunc)(void);
67typedef void (GenOpFunc1)(long);
68typedef void (GenOpFunc2)(long, long);
69typedef void (GenOpFunc3)(long, long, long);
70
bellardb346ff42003-06-15 20:05:50 +000071#if defined(TARGET_I386)
72
bellard33417e72003-08-10 21:47:01 +000073void optimize_flags_init(void);
bellardd4e81642003-05-25 16:46:15 +000074
bellardb346ff42003-06-15 20:05:50 +000075#endif
76
77extern FILE *logfile;
78extern int loglevel;
79
bellard4c3a88a2003-07-26 12:06:08 +000080int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
81int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
bellardb346ff42003-06-15 20:05:50 +000082void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
bellard4c3a88a2003-07-26 12:06:08 +000083int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
bellardb346ff42003-06-15 20:05:50 +000084 int max_code_size, int *gen_code_size_ptr);
bellard66e85a22003-06-24 13:28:12 +000085int cpu_restore_state(struct TranslationBlock *tb,
bellard58fe2f12004-02-16 22:11:32 +000086 CPUState *env, unsigned long searched_pc,
87 void *puc);
88int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
89 int max_code_size, int *gen_code_size_ptr);
90int cpu_restore_state_copy(struct TranslationBlock *tb,
91 CPUState *env, unsigned long searched_pc,
92 void *puc);
bellard2e126692004-04-25 21:28:44 +000093void cpu_resume_from_signal(CPUState *env1, void *puc);
bellard6a00d602005-11-21 23:25:50 +000094void cpu_exec_init(CPUState *env);
bellard2e126692004-04-25 21:28:44 +000095int page_unprotect(unsigned long address, unsigned long pc, void *puc);
96void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
97 int is_cpu_write_access);
bellard4390df52004-01-04 18:03:10 +000098void tb_invalidate_page_range(target_ulong start, target_ulong end);
bellard2e126692004-04-25 21:28:44 +000099void tlb_flush_page(CPUState *env, target_ulong addr);
bellardee8b7022004-02-03 23:35:10 +0000100void tlb_flush(CPUState *env, int flush_global);
bellard84b7b8e2005-11-28 21:19:04 +0000101int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
102 target_phys_addr_t paddr, int prot,
103 int is_user, int is_softmmu);
104static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
105 target_phys_addr_t paddr, int prot,
106 int is_user, int is_softmmu)
107{
108 if (prot & PAGE_READ)
109 prot |= PAGE_EXEC;
110 return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
111}
bellardd4e81642003-05-25 16:46:15 +0000112
113#define CODE_GEN_MAX_SIZE 65536
114#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
115
bellard4390df52004-01-04 18:03:10 +0000116#define CODE_GEN_PHYS_HASH_BITS 15
117#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
118
bellardd4e81642003-05-25 16:46:15 +0000119/* maximum total translate dcode allocated */
bellard4390df52004-01-04 18:03:10 +0000120
121/* NOTE: the translated code area cannot be too big because on some
bellardc4c7e3e2004-01-18 21:50:28 +0000122 archs the range of "fast" function calls is limited. Here is a
bellard4390df52004-01-04 18:03:10 +0000123 summary of the ranges:
124
125 i386 : signed 32 bits
126 arm : signed 26 bits
127 ppc : signed 24 bits
128 sparc : signed 32 bits
129 alpha : signed 23 bits
130*/
131
132#if defined(__alpha__)
133#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
bellardb8076a72005-04-07 22:20:31 +0000134#elif defined(__ia64)
135#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
bellard4390df52004-01-04 18:03:10 +0000136#elif defined(__powerpc__)
bellardc4c7e3e2004-01-18 21:50:28 +0000137#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
bellard4390df52004-01-04 18:03:10 +0000138#else
bellardc98baaa2005-07-02 13:31:24 +0000139#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
bellard4390df52004-01-04 18:03:10 +0000140#endif
141
bellardd4e81642003-05-25 16:46:15 +0000142//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
143
bellard4390df52004-01-04 18:03:10 +0000144/* estimated block size for TB allocation */
145/* XXX: use a per code average code fragment size and modulate it
146 according to the host CPU */
147#if defined(CONFIG_SOFTMMU)
148#define CODE_GEN_AVG_BLOCK_SIZE 128
149#else
150#define CODE_GEN_AVG_BLOCK_SIZE 64
151#endif
152
153#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
154
155#if defined(__powerpc__)
156#define USE_DIRECT_JUMP
157#endif
bellard67b915a2004-03-31 23:37:16 +0000158#if defined(__i386__) && !defined(_WIN32)
bellardd4e81642003-05-25 16:46:15 +0000159#define USE_DIRECT_JUMP
160#endif
161
162typedef struct TranslationBlock {
bellard2e126692004-04-25 21:28:44 +0000163 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
164 target_ulong cs_base; /* CS base for this block */
bellardd4e81642003-05-25 16:46:15 +0000165 unsigned int flags; /* flags defining in which context the code was generated */
166 uint16_t size; /* size of target code for this block (1 <=
167 size <= TARGET_PAGE_SIZE) */
bellard58fe2f12004-02-16 22:11:32 +0000168 uint16_t cflags; /* compile flags */
bellardbf088062004-02-25 23:33:36 +0000169#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
170#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
171#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
bellard2e126692004-04-25 21:28:44 +0000172#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
bellard58fe2f12004-02-16 22:11:32 +0000173
bellardd4e81642003-05-25 16:46:15 +0000174 uint8_t *tc_ptr; /* pointer to the translated code */
bellard4390df52004-01-04 18:03:10 +0000175 /* next matching tb for physical address. */
176 struct TranslationBlock *phys_hash_next;
177 /* first and second physical page containing code. The lower bit
178 of the pointer tells the index in page_next[] */
179 struct TranslationBlock *page_next[2];
180 target_ulong page_addr[2];
181
bellardd4e81642003-05-25 16:46:15 +0000182 /* the following data are used to directly call another TB from
183 the code of this one. */
184 uint16_t tb_next_offset[2]; /* offset of original jump target */
185#ifdef USE_DIRECT_JUMP
bellard4cbb86e2003-09-17 22:53:29 +0000186 uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
bellardd4e81642003-05-25 16:46:15 +0000187#else
bellard95f76522003-06-05 00:54:44 +0000188 uint32_t tb_next[2]; /* address of jump generated code */
bellardd4e81642003-05-25 16:46:15 +0000189#endif
190 /* list of TBs jumping to this one. This is a circular list using
191 the two least significant bits of the pointers to tell what is
192 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
193 jmp_first */
194 struct TranslationBlock *jmp_next[2];
195 struct TranslationBlock *jmp_first;
196} TranslationBlock;
197
bellard8a40a182005-11-20 10:35:40 +0000198static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
bellardd4e81642003-05-25 16:46:15 +0000199{
bellard8a40a182005-11-20 10:35:40 +0000200 return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
bellardd4e81642003-05-25 16:46:15 +0000201}
202
bellard4390df52004-01-04 18:03:10 +0000203static inline unsigned int tb_phys_hash_func(unsigned long pc)
204{
205 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
206}
207
bellardc27004e2005-01-03 23:35:10 +0000208TranslationBlock *tb_alloc(target_ulong pc);
bellard01243112004-01-04 15:48:17 +0000209void tb_flush(CPUState *env);
bellard4390df52004-01-04 18:03:10 +0000210void tb_link_phys(TranslationBlock *tb,
211 target_ulong phys_pc, target_ulong phys_page2);
bellardd4e81642003-05-25 16:46:15 +0000212
bellard4390df52004-01-04 18:03:10 +0000213extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
bellardd4e81642003-05-25 16:46:15 +0000214
215extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
216extern uint8_t *code_gen_ptr;
217
bellard4390df52004-01-04 18:03:10 +0000218#if defined(USE_DIRECT_JUMP)
219
220#if defined(__powerpc__)
bellard4cbb86e2003-09-17 22:53:29 +0000221static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
bellardd4e81642003-05-25 16:46:15 +0000222{
223 uint32_t val, *ptr;
bellardd4e81642003-05-25 16:46:15 +0000224
225 /* patch the branch destination */
bellard4cbb86e2003-09-17 22:53:29 +0000226 ptr = (uint32_t *)jmp_addr;
bellardd4e81642003-05-25 16:46:15 +0000227 val = *ptr;
bellard4cbb86e2003-09-17 22:53:29 +0000228 val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
bellardd4e81642003-05-25 16:46:15 +0000229 *ptr = val;
230 /* flush icache */
231 asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
232 asm volatile ("sync" : : : "memory");
233 asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
234 asm volatile ("sync" : : : "memory");
235 asm volatile ("isync" : : : "memory");
236}
bellard4390df52004-01-04 18:03:10 +0000237#elif defined(__i386__)
238static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
239{
240 /* patch the branch destination */
241 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
242 /* no need to flush icache explicitely */
243}
244#endif
bellardd4e81642003-05-25 16:46:15 +0000245
bellard4cbb86e2003-09-17 22:53:29 +0000246static inline void tb_set_jmp_target(TranslationBlock *tb,
247 int n, unsigned long addr)
248{
249 unsigned long offset;
250
251 offset = tb->tb_jmp_offset[n];
252 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
253 offset = tb->tb_jmp_offset[n + 2];
254 if (offset != 0xffff)
255 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
256}
257
bellardd4e81642003-05-25 16:46:15 +0000258#else
259
260/* set the jump target */
261static inline void tb_set_jmp_target(TranslationBlock *tb,
262 int n, unsigned long addr)
263{
bellard95f76522003-06-05 00:54:44 +0000264 tb->tb_next[n] = addr;
bellardd4e81642003-05-25 16:46:15 +0000265}
266
267#endif
268
269static inline void tb_add_jump(TranslationBlock *tb, int n,
270 TranslationBlock *tb_next)
271{
bellardcf256292003-05-25 19:20:31 +0000272 /* NOTE: this test is only needed for thread safety */
273 if (!tb->jmp_next[n]) {
274 /* patch the native jump address */
275 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
276
277 /* add in TB jmp circular list */
278 tb->jmp_next[n] = tb_next->jmp_first;
279 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
280 }
bellardd4e81642003-05-25 16:46:15 +0000281}
282
bellarda513fe12003-05-27 23:29:48 +0000283TranslationBlock *tb_find_pc(unsigned long pc_ptr);
284
bellardd4e81642003-05-25 16:46:15 +0000285#ifndef offsetof
286#define offsetof(type, field) ((size_t) &((type *)0)->field)
287#endif
288
bellardd549f7d2004-07-05 21:47:44 +0000289#if defined(_WIN32)
290#define ASM_DATA_SECTION ".section \".data\"\n"
291#define ASM_PREVIOUS_SECTION ".section .text\n"
292#elif defined(__APPLE__)
293#define ASM_DATA_SECTION ".data\n"
294#define ASM_PREVIOUS_SECTION ".text\n"
bellardd549f7d2004-07-05 21:47:44 +0000295#else
296#define ASM_DATA_SECTION ".section \".data\"\n"
297#define ASM_PREVIOUS_SECTION ".previous\n"
bellardd549f7d2004-07-05 21:47:44 +0000298#endif
299
bellard75913b72005-08-21 15:19:36 +0000300#define ASM_OP_LABEL_NAME(n, opname) \
301 ASM_NAME(__op_label) #n "." ASM_NAME(opname)
302
bellardb346ff42003-06-15 20:05:50 +0000303#if defined(__powerpc__)
304
bellard4390df52004-01-04 18:03:10 +0000305/* we patch the jump instruction directly */
bellardae063a62005-01-09 00:07:04 +0000306#define GOTO_TB(opname, tbparam, n)\
bellardb346ff42003-06-15 20:05:50 +0000307do {\
bellardd549f7d2004-07-05 21:47:44 +0000308 asm volatile (ASM_DATA_SECTION\
bellard75913b72005-08-21 15:19:36 +0000309 ASM_OP_LABEL_NAME(n, opname) ":\n"\
bellard9257a9e2003-08-11 22:21:18 +0000310 ".long 1f\n"\
bellardd549f7d2004-07-05 21:47:44 +0000311 ASM_PREVIOUS_SECTION \
312 "b " ASM_NAME(__op_jmp) #n "\n"\
bellard9257a9e2003-08-11 22:21:18 +0000313 "1:\n");\
bellard4390df52004-01-04 18:03:10 +0000314} while (0)
315
316#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
317
318/* we patch the jump instruction directly */
bellardae063a62005-01-09 00:07:04 +0000319#define GOTO_TB(opname, tbparam, n)\
bellardc27004e2005-01-03 23:35:10 +0000320do {\
321 asm volatile (".section .data\n"\
bellard75913b72005-08-21 15:19:36 +0000322 ASM_OP_LABEL_NAME(n, opname) ":\n"\
bellardc27004e2005-01-03 23:35:10 +0000323 ".long 1f\n"\
324 ASM_PREVIOUS_SECTION \
325 "jmp " ASM_NAME(__op_jmp) #n "\n"\
326 "1:\n");\
327} while (0)
328
bellardb346ff42003-06-15 20:05:50 +0000329#else
330
331/* jump to next block operations (more portable code, does not need
332 cache flushing, but slower because of indirect jump) */
bellardae063a62005-01-09 00:07:04 +0000333#define GOTO_TB(opname, tbparam, n)\
bellardb346ff42003-06-15 20:05:50 +0000334do {\
bellard2f62b392003-06-30 23:18:59 +0000335 static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
bellard75913b72005-08-21 15:19:36 +0000336 static void __attribute__((unused)) *__op_label ## n \
337 __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
bellardb346ff42003-06-15 20:05:50 +0000338 goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
bellardae063a62005-01-09 00:07:04 +0000339label ## n: ;\
340dummy_label ## n: ;\
bellard4cbb86e2003-09-17 22:53:29 +0000341} while (0)
342
bellardb346ff42003-06-15 20:05:50 +0000343#endif
344
bellard33417e72003-08-10 21:47:01 +0000345extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
346extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
bellarda4193c82004-06-03 14:01:43 +0000347extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
bellard33417e72003-08-10 21:47:01 +0000348
bellardd4e81642003-05-25 16:46:15 +0000349#ifdef __powerpc__
350static inline int testandset (int *p)
351{
352 int ret;
353 __asm__ __volatile__ (
bellard02e1ec92004-07-10 15:15:39 +0000354 "0: lwarx %0,0,%1\n"
355 " xor. %0,%3,%0\n"
356 " bne 1f\n"
357 " stwcx. %2,0,%1\n"
358 " bne- 0b\n"
bellardd4e81642003-05-25 16:46:15 +0000359 "1: "
360 : "=&r" (ret)
361 : "r" (p), "r" (1), "r" (0)
362 : "cr0", "memory");
363 return ret;
364}
365#endif
366
367#ifdef __i386__
368static inline int testandset (int *p)
369{
bellard4955a2c2005-02-07 14:09:05 +0000370 long int readval = 0;
bellardd4e81642003-05-25 16:46:15 +0000371
bellard4955a2c2005-02-07 14:09:05 +0000372 __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
373 : "+m" (*p), "+a" (readval)
374 : "r" (1)
375 : "cc");
376 return readval;
bellardd4e81642003-05-25 16:46:15 +0000377}
378#endif
379
bellardbc51c5c2004-03-17 23:46:04 +0000380#ifdef __x86_64__
381static inline int testandset (int *p)
382{
bellard4955a2c2005-02-07 14:09:05 +0000383 long int readval = 0;
bellardbc51c5c2004-03-17 23:46:04 +0000384
bellard4955a2c2005-02-07 14:09:05 +0000385 __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
386 : "+m" (*p), "+a" (readval)
387 : "r" (1)
388 : "cc");
389 return readval;
bellardbc51c5c2004-03-17 23:46:04 +0000390}
391#endif
392
bellardd4e81642003-05-25 16:46:15 +0000393#ifdef __s390__
394static inline int testandset (int *p)
395{
396 int ret;
397
398 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
399 " jl 0b"
400 : "=&d" (ret)
401 : "r" (1), "a" (p), "0" (*p)
402 : "cc", "memory" );
403 return ret;
404}
405#endif
406
407#ifdef __alpha__
bellard2f87c602003-06-02 20:38:09 +0000408static inline int testandset (int *p)
bellardd4e81642003-05-25 16:46:15 +0000409{
410 int ret;
411 unsigned long one;
412
413 __asm__ __volatile__ ("0: mov 1,%2\n"
414 " ldl_l %0,%1\n"
415 " stl_c %2,%1\n"
416 " beq %2,1f\n"
417 ".subsection 2\n"
418 "1: br 0b\n"
419 ".previous"
420 : "=r" (ret), "=m" (*p), "=r" (one)
421 : "m" (*p));
422 return ret;
423}
424#endif
425
426#ifdef __sparc__
427static inline int testandset (int *p)
428{
429 int ret;
430
431 __asm__ __volatile__("ldstub [%1], %0"
432 : "=r" (ret)
433 : "r" (p)
434 : "memory");
435
436 return (ret ? 1 : 0);
437}
438#endif
439
bellarda95c6792003-06-09 15:29:55 +0000440#ifdef __arm__
441static inline int testandset (int *spinlock)
442{
443 register unsigned int ret;
444 __asm__ __volatile__("swp %0, %1, [%2]"
445 : "=r"(ret)
446 : "0"(1), "r"(spinlock));
447
448 return ret;
449}
450#endif
451
bellard38e584a2003-08-10 22:14:22 +0000452#ifdef __mc68000
453static inline int testandset (int *p)
454{
455 char ret;
456 __asm__ __volatile__("tas %1; sne %0"
457 : "=r" (ret)
458 : "m" (p)
459 : "cc","memory");
bellard4955a2c2005-02-07 14:09:05 +0000460 return ret;
bellard38e584a2003-08-10 22:14:22 +0000461}
462#endif
463
bellardb8076a72005-04-07 22:20:31 +0000464#ifdef __ia64
465#include <ia64intrin.h>
466
467static inline int testandset (int *p)
468{
469 return __sync_lock_test_and_set (p, 1);
470}
471#endif
472
bellardd4e81642003-05-25 16:46:15 +0000473typedef int spinlock_t;
474
475#define SPIN_LOCK_UNLOCKED 0
476
bellardaebcb602003-10-30 01:08:17 +0000477#if defined(CONFIG_USER_ONLY)
bellardd4e81642003-05-25 16:46:15 +0000478static inline void spin_lock(spinlock_t *lock)
479{
480 while (testandset(lock));
481}
482
483static inline void spin_unlock(spinlock_t *lock)
484{
485 *lock = 0;
486}
487
488static inline int spin_trylock(spinlock_t *lock)
489{
490 return !testandset(lock);
491}
bellard3c1cf9f2003-07-07 11:30:47 +0000492#else
493static inline void spin_lock(spinlock_t *lock)
494{
495}
496
497static inline void spin_unlock(spinlock_t *lock)
498{
499}
500
501static inline int spin_trylock(spinlock_t *lock)
502{
503 return 1;
504}
505#endif
bellardd4e81642003-05-25 16:46:15 +0000506
507extern spinlock_t tb_lock;
508
bellard36bdbe52003-11-19 22:12:02 +0000509extern int tb_invalidated_flag;
bellard6e59c1d2003-10-27 21:24:54 +0000510
bellarde95c8d52004-09-30 22:22:08 +0000511#if !defined(CONFIG_USER_ONLY)
bellard6e59c1d2003-10-27 21:24:54 +0000512
bellardc27004e2005-01-03 23:35:10 +0000513void tlb_fill(target_ulong addr, int is_write, int is_user,
bellard6e59c1d2003-10-27 21:24:54 +0000514 void *retaddr);
515
516#define ACCESS_TYPE 3
517#define MEMSUFFIX _code
518#define env cpu_single_env
519
520#define DATA_SIZE 1
521#include "softmmu_header.h"
522
523#define DATA_SIZE 2
524#include "softmmu_header.h"
525
526#define DATA_SIZE 4
527#include "softmmu_header.h"
528
bellardc27004e2005-01-03 23:35:10 +0000529#define DATA_SIZE 8
530#include "softmmu_header.h"
531
bellard6e59c1d2003-10-27 21:24:54 +0000532#undef ACCESS_TYPE
533#undef MEMSUFFIX
534#undef env
535
536#endif
bellard4390df52004-01-04 18:03:10 +0000537
538#if defined(CONFIG_USER_ONLY)
539static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
540{
541 return addr;
542}
543#else
544/* NOTE: this function can trigger an exception */
bellard1ccde1c2004-02-06 19:46:14 +0000545/* NOTE2: the returned address is not exactly the physical address: it
546 is the offset relative to phys_ram_base */
bellard4390df52004-01-04 18:03:10 +0000547static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
548{
bellardc27004e2005-01-03 23:35:10 +0000549 int is_user, index, pd;
bellard4390df52004-01-04 18:03:10 +0000550
551 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard3f5dcc32004-01-18 22:44:01 +0000552#if defined(TARGET_I386)
bellard4390df52004-01-04 18:03:10 +0000553 is_user = ((env->hflags & HF_CPL_MASK) == 3);
bellard3f5dcc32004-01-18 22:44:01 +0000554#elif defined (TARGET_PPC)
555 is_user = msr_pr;
bellard6af0bf92005-07-02 14:58:51 +0000556#elif defined (TARGET_MIPS)
557 is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
bellarde95c8d52004-09-30 22:22:08 +0000558#elif defined (TARGET_SPARC)
559 is_user = (env->psrs == 0);
bellardb5ff1b32005-11-26 10:38:39 +0000560#elif defined (TARGET_ARM)
561 is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
bellard3f5dcc32004-01-18 22:44:01 +0000562#else
bellardb5ff1b32005-11-26 10:38:39 +0000563#error unimplemented CPU
bellard3f5dcc32004-01-18 22:44:01 +0000564#endif
bellard84b7b8e2005-11-28 21:19:04 +0000565 if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
bellard4390df52004-01-04 18:03:10 +0000566 (addr & TARGET_PAGE_MASK), 0)) {
bellardc27004e2005-01-03 23:35:10 +0000567 ldub_code(addr);
568 }
bellard84b7b8e2005-11-28 21:19:04 +0000569 pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
bellardc27004e2005-01-03 23:35:10 +0000570 if (pd > IO_MEM_ROM) {
571 cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
bellard4390df52004-01-04 18:03:10 +0000572 }
bellard84b7b8e2005-11-28 21:19:04 +0000573 return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
bellard4390df52004-01-04 18:03:10 +0000574}
575#endif
bellard9df217a2005-02-10 22:05:51 +0000576
577
578#ifdef USE_KQEMU
bellard9df217a2005-02-10 22:05:51 +0000579int kqemu_init(CPUState *env);
580int kqemu_cpu_exec(CPUState *env);
581void kqemu_flush_page(CPUState *env, target_ulong addr);
582void kqemu_flush(CPUState *env, int global);
bellard4b7df222005-08-21 09:37:35 +0000583void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
bellarda332e112005-09-03 17:55:47 +0000584void kqemu_cpu_interrupt(CPUState *env);
bellard9df217a2005-02-10 22:05:51 +0000585
586static inline int kqemu_is_ok(CPUState *env)
587{
588 return(env->kqemu_enabled &&
589 (env->hflags & HF_CPL_MASK) == 3 &&
590 (env->eflags & IOPL_MASK) != IOPL_MASK &&
591 (env->cr[0] & CR0_PE_MASK) &&
592 (env->eflags & IF_MASK) &&
bellardde758152005-09-04 16:54:47 +0000593 !(env->eflags & VM_MASK));
bellard9df217a2005-02-10 22:05:51 +0000594}
595
596#endif