bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * internal execution defines for qemu |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
| 22 | #define DEBUG_DISAS |
| 23 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 24 | #ifndef glue |
| 25 | #define xglue(x, y) x ## y |
| 26 | #define glue(x, y) xglue(x, y) |
| 27 | #define stringify(s) tostring(s) |
| 28 | #define tostring(s) #s |
| 29 | #endif |
| 30 | |
bellard | c98baaa | 2005-07-02 13:31:24 +0000 | [diff] [blame] | 31 | #if __GNUC__ < 3 |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 32 | #define __builtin_expect(x, n) (x) |
| 33 | #endif |
| 34 | |
bellard | e2222c3 | 2003-08-10 23:39:03 +0000 | [diff] [blame] | 35 | #ifdef __i386__ |
| 36 | #define REGPARM(n) __attribute((regparm(n))) |
| 37 | #else |
| 38 | #define REGPARM(n) |
| 39 | #endif |
| 40 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 41 | /* is_jmp field values */ |
| 42 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
| 43 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
| 44 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
| 45 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
| 46 | |
| 47 | struct TranslationBlock; |
| 48 | |
| 49 | /* XXX: make safe guess about sizes */ |
| 50 | #define MAX_OP_PER_INSTR 32 |
| 51 | #define OPC_BUF_SIZE 512 |
| 52 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) |
| 53 | |
| 54 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
| 55 | |
| 56 | extern uint16_t gen_opc_buf[OPC_BUF_SIZE]; |
| 57 | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE]; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 58 | extern long gen_labels[OPC_BUF_SIZE]; |
| 59 | extern int nb_gen_labels; |
| 60 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; |
| 61 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 62 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 63 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
bellard | c3278b7 | 2005-03-20 12:43:29 +0000 | [diff] [blame] | 64 | extern target_ulong gen_opc_jump_pc[2]; |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 65 | |
bellard | 9886cc1 | 2004-01-04 23:53:54 +0000 | [diff] [blame] | 66 | typedef void (GenOpFunc)(void); |
| 67 | typedef void (GenOpFunc1)(long); |
| 68 | typedef void (GenOpFunc2)(long, long); |
| 69 | typedef void (GenOpFunc3)(long, long, long); |
| 70 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 71 | #if defined(TARGET_I386) |
| 72 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 73 | void optimize_flags_init(void); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 74 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 75 | #endif |
| 76 | |
| 77 | extern FILE *logfile; |
| 78 | extern int loglevel; |
| 79 | |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 80 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
| 81 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 82 | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 83 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 84 | int max_code_size, int *gen_code_size_ptr); |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 85 | int cpu_restore_state(struct TranslationBlock *tb, |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 86 | CPUState *env, unsigned long searched_pc, |
| 87 | void *puc); |
| 88 | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
| 89 | int max_code_size, int *gen_code_size_ptr); |
| 90 | int cpu_restore_state_copy(struct TranslationBlock *tb, |
| 91 | CPUState *env, unsigned long searched_pc, |
| 92 | void *puc); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 93 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 94 | void cpu_exec_init(CPUState *env); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 95 | int page_unprotect(unsigned long address, unsigned long pc, void *puc); |
| 96 | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, |
| 97 | int is_cpu_write_access); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 98 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 99 | void tlb_flush_page(CPUState *env, target_ulong addr); |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 100 | void tlb_flush(CPUState *env, int flush_global); |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 101 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
| 102 | target_phys_addr_t paddr, int prot, |
| 103 | int is_user, int is_softmmu); |
| 104 | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
| 105 | target_phys_addr_t paddr, int prot, |
| 106 | int is_user, int is_softmmu) |
| 107 | { |
| 108 | if (prot & PAGE_READ) |
| 109 | prot |= PAGE_EXEC; |
| 110 | return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu); |
| 111 | } |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 112 | |
| 113 | #define CODE_GEN_MAX_SIZE 65536 |
| 114 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
| 115 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 116 | #define CODE_GEN_PHYS_HASH_BITS 15 |
| 117 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
| 118 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 119 | /* maximum total translate dcode allocated */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 120 | |
| 121 | /* NOTE: the translated code area cannot be too big because on some |
bellard | c4c7e3e | 2004-01-18 21:50:28 +0000 | [diff] [blame] | 122 | archs the range of "fast" function calls is limited. Here is a |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 123 | summary of the ranges: |
| 124 | |
| 125 | i386 : signed 32 bits |
| 126 | arm : signed 26 bits |
| 127 | ppc : signed 24 bits |
| 128 | sparc : signed 32 bits |
| 129 | alpha : signed 23 bits |
| 130 | */ |
| 131 | |
| 132 | #if defined(__alpha__) |
| 133 | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 134 | #elif defined(__ia64) |
| 135 | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 136 | #elif defined(__powerpc__) |
bellard | c4c7e3e | 2004-01-18 21:50:28 +0000 | [diff] [blame] | 137 | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 138 | #else |
bellard | c98baaa | 2005-07-02 13:31:24 +0000 | [diff] [blame] | 139 | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 140 | #endif |
| 141 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 142 | //#define CODE_GEN_BUFFER_SIZE (128 * 1024) |
| 143 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 144 | /* estimated block size for TB allocation */ |
| 145 | /* XXX: use a per code average code fragment size and modulate it |
| 146 | according to the host CPU */ |
| 147 | #if defined(CONFIG_SOFTMMU) |
| 148 | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
| 149 | #else |
| 150 | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
| 151 | #endif |
| 152 | |
| 153 | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE) |
| 154 | |
| 155 | #if defined(__powerpc__) |
| 156 | #define USE_DIRECT_JUMP |
| 157 | #endif |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 158 | #if defined(__i386__) && !defined(_WIN32) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 159 | #define USE_DIRECT_JUMP |
| 160 | #endif |
| 161 | |
| 162 | typedef struct TranslationBlock { |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 163 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
| 164 | target_ulong cs_base; /* CS base for this block */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 165 | unsigned int flags; /* flags defining in which context the code was generated */ |
| 166 | uint16_t size; /* size of target code for this block (1 <= |
| 167 | size <= TARGET_PAGE_SIZE) */ |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 168 | uint16_t cflags; /* compile flags */ |
bellard | bf08806 | 2004-02-25 23:33:36 +0000 | [diff] [blame] | 169 | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
| 170 | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
| 171 | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 172 | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 173 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 174 | uint8_t *tc_ptr; /* pointer to the translated code */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 175 | /* next matching tb for physical address. */ |
| 176 | struct TranslationBlock *phys_hash_next; |
| 177 | /* first and second physical page containing code. The lower bit |
| 178 | of the pointer tells the index in page_next[] */ |
| 179 | struct TranslationBlock *page_next[2]; |
| 180 | target_ulong page_addr[2]; |
| 181 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 182 | /* the following data are used to directly call another TB from |
| 183 | the code of this one. */ |
| 184 | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
| 185 | #ifdef USE_DIRECT_JUMP |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 186 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 187 | #else |
bellard | 95f7652 | 2003-06-05 00:54:44 +0000 | [diff] [blame] | 188 | uint32_t tb_next[2]; /* address of jump generated code */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 189 | #endif |
| 190 | /* list of TBs jumping to this one. This is a circular list using |
| 191 | the two least significant bits of the pointers to tell what is |
| 192 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = |
| 193 | jmp_first */ |
| 194 | struct TranslationBlock *jmp_next[2]; |
| 195 | struct TranslationBlock *jmp_first; |
| 196 | } TranslationBlock; |
| 197 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 198 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 199 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 200 | return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 201 | } |
| 202 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 203 | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
| 204 | { |
| 205 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
| 206 | } |
| 207 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 208 | TranslationBlock *tb_alloc(target_ulong pc); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 209 | void tb_flush(CPUState *env); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 210 | void tb_link_phys(TranslationBlock *tb, |
| 211 | target_ulong phys_pc, target_ulong phys_page2); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 212 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 213 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 214 | |
| 215 | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; |
| 216 | extern uint8_t *code_gen_ptr; |
| 217 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 218 | #if defined(USE_DIRECT_JUMP) |
| 219 | |
| 220 | #if defined(__powerpc__) |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 221 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 222 | { |
| 223 | uint32_t val, *ptr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 224 | |
| 225 | /* patch the branch destination */ |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 226 | ptr = (uint32_t *)jmp_addr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 227 | val = *ptr; |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 228 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 229 | *ptr = val; |
| 230 | /* flush icache */ |
| 231 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
| 232 | asm volatile ("sync" : : : "memory"); |
| 233 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
| 234 | asm volatile ("sync" : : : "memory"); |
| 235 | asm volatile ("isync" : : : "memory"); |
| 236 | } |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 237 | #elif defined(__i386__) |
| 238 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
| 239 | { |
| 240 | /* patch the branch destination */ |
| 241 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); |
| 242 | /* no need to flush icache explicitely */ |
| 243 | } |
| 244 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 245 | |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 246 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
| 247 | int n, unsigned long addr) |
| 248 | { |
| 249 | unsigned long offset; |
| 250 | |
| 251 | offset = tb->tb_jmp_offset[n]; |
| 252 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
| 253 | offset = tb->tb_jmp_offset[n + 2]; |
| 254 | if (offset != 0xffff) |
| 255 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
| 256 | } |
| 257 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 258 | #else |
| 259 | |
| 260 | /* set the jump target */ |
| 261 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
| 262 | int n, unsigned long addr) |
| 263 | { |
bellard | 95f7652 | 2003-06-05 00:54:44 +0000 | [diff] [blame] | 264 | tb->tb_next[n] = addr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | #endif |
| 268 | |
| 269 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
| 270 | TranslationBlock *tb_next) |
| 271 | { |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 272 | /* NOTE: this test is only needed for thread safety */ |
| 273 | if (!tb->jmp_next[n]) { |
| 274 | /* patch the native jump address */ |
| 275 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
| 276 | |
| 277 | /* add in TB jmp circular list */ |
| 278 | tb->jmp_next[n] = tb_next->jmp_first; |
| 279 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); |
| 280 | } |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 281 | } |
| 282 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 283 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
| 284 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 285 | #ifndef offsetof |
| 286 | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
| 287 | #endif |
| 288 | |
bellard | d549f7d | 2004-07-05 21:47:44 +0000 | [diff] [blame] | 289 | #if defined(_WIN32) |
| 290 | #define ASM_DATA_SECTION ".section \".data\"\n" |
| 291 | #define ASM_PREVIOUS_SECTION ".section .text\n" |
| 292 | #elif defined(__APPLE__) |
| 293 | #define ASM_DATA_SECTION ".data\n" |
| 294 | #define ASM_PREVIOUS_SECTION ".text\n" |
bellard | d549f7d | 2004-07-05 21:47:44 +0000 | [diff] [blame] | 295 | #else |
| 296 | #define ASM_DATA_SECTION ".section \".data\"\n" |
| 297 | #define ASM_PREVIOUS_SECTION ".previous\n" |
bellard | d549f7d | 2004-07-05 21:47:44 +0000 | [diff] [blame] | 298 | #endif |
| 299 | |
bellard | 75913b7 | 2005-08-21 15:19:36 +0000 | [diff] [blame] | 300 | #define ASM_OP_LABEL_NAME(n, opname) \ |
| 301 | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
| 302 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 303 | #if defined(__powerpc__) |
| 304 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 305 | /* we patch the jump instruction directly */ |
bellard | ae063a6 | 2005-01-09 00:07:04 +0000 | [diff] [blame] | 306 | #define GOTO_TB(opname, tbparam, n)\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 307 | do {\ |
bellard | d549f7d | 2004-07-05 21:47:44 +0000 | [diff] [blame] | 308 | asm volatile (ASM_DATA_SECTION\ |
bellard | 75913b7 | 2005-08-21 15:19:36 +0000 | [diff] [blame] | 309 | ASM_OP_LABEL_NAME(n, opname) ":\n"\ |
bellard | 9257a9e | 2003-08-11 22:21:18 +0000 | [diff] [blame] | 310 | ".long 1f\n"\ |
bellard | d549f7d | 2004-07-05 21:47:44 +0000 | [diff] [blame] | 311 | ASM_PREVIOUS_SECTION \ |
| 312 | "b " ASM_NAME(__op_jmp) #n "\n"\ |
bellard | 9257a9e | 2003-08-11 22:21:18 +0000 | [diff] [blame] | 313 | "1:\n");\ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 314 | } while (0) |
| 315 | |
| 316 | #elif defined(__i386__) && defined(USE_DIRECT_JUMP) |
| 317 | |
| 318 | /* we patch the jump instruction directly */ |
bellard | ae063a6 | 2005-01-09 00:07:04 +0000 | [diff] [blame] | 319 | #define GOTO_TB(opname, tbparam, n)\ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 320 | do {\ |
| 321 | asm volatile (".section .data\n"\ |
bellard | 75913b7 | 2005-08-21 15:19:36 +0000 | [diff] [blame] | 322 | ASM_OP_LABEL_NAME(n, opname) ":\n"\ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 323 | ".long 1f\n"\ |
| 324 | ASM_PREVIOUS_SECTION \ |
| 325 | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
| 326 | "1:\n");\ |
| 327 | } while (0) |
| 328 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 329 | #else |
| 330 | |
| 331 | /* jump to next block operations (more portable code, does not need |
| 332 | cache flushing, but slower because of indirect jump) */ |
bellard | ae063a6 | 2005-01-09 00:07:04 +0000 | [diff] [blame] | 333 | #define GOTO_TB(opname, tbparam, n)\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 334 | do {\ |
bellard | 2f62b39 | 2003-06-30 23:18:59 +0000 | [diff] [blame] | 335 | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
bellard | 75913b7 | 2005-08-21 15:19:36 +0000 | [diff] [blame] | 336 | static void __attribute__((unused)) *__op_label ## n \ |
| 337 | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 338 | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
bellard | ae063a6 | 2005-01-09 00:07:04 +0000 | [diff] [blame] | 339 | label ## n: ;\ |
| 340 | dummy_label ## n: ;\ |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 341 | } while (0) |
| 342 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 343 | #endif |
| 344 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 345 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
| 346 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 347 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 348 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 349 | #ifdef __powerpc__ |
| 350 | static inline int testandset (int *p) |
| 351 | { |
| 352 | int ret; |
| 353 | __asm__ __volatile__ ( |
bellard | 02e1ec9 | 2004-07-10 15:15:39 +0000 | [diff] [blame] | 354 | "0: lwarx %0,0,%1\n" |
| 355 | " xor. %0,%3,%0\n" |
| 356 | " bne 1f\n" |
| 357 | " stwcx. %2,0,%1\n" |
| 358 | " bne- 0b\n" |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 359 | "1: " |
| 360 | : "=&r" (ret) |
| 361 | : "r" (p), "r" (1), "r" (0) |
| 362 | : "cr0", "memory"); |
| 363 | return ret; |
| 364 | } |
| 365 | #endif |
| 366 | |
| 367 | #ifdef __i386__ |
| 368 | static inline int testandset (int *p) |
| 369 | { |
bellard | 4955a2c | 2005-02-07 14:09:05 +0000 | [diff] [blame] | 370 | long int readval = 0; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 371 | |
bellard | 4955a2c | 2005-02-07 14:09:05 +0000 | [diff] [blame] | 372 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
| 373 | : "+m" (*p), "+a" (readval) |
| 374 | : "r" (1) |
| 375 | : "cc"); |
| 376 | return readval; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 377 | } |
| 378 | #endif |
| 379 | |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 380 | #ifdef __x86_64__ |
| 381 | static inline int testandset (int *p) |
| 382 | { |
bellard | 4955a2c | 2005-02-07 14:09:05 +0000 | [diff] [blame] | 383 | long int readval = 0; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 384 | |
bellard | 4955a2c | 2005-02-07 14:09:05 +0000 | [diff] [blame] | 385 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
| 386 | : "+m" (*p), "+a" (readval) |
| 387 | : "r" (1) |
| 388 | : "cc"); |
| 389 | return readval; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 390 | } |
| 391 | #endif |
| 392 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 393 | #ifdef __s390__ |
| 394 | static inline int testandset (int *p) |
| 395 | { |
| 396 | int ret; |
| 397 | |
| 398 | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n" |
| 399 | " jl 0b" |
| 400 | : "=&d" (ret) |
| 401 | : "r" (1), "a" (p), "0" (*p) |
| 402 | : "cc", "memory" ); |
| 403 | return ret; |
| 404 | } |
| 405 | #endif |
| 406 | |
| 407 | #ifdef __alpha__ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 408 | static inline int testandset (int *p) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 409 | { |
| 410 | int ret; |
| 411 | unsigned long one; |
| 412 | |
| 413 | __asm__ __volatile__ ("0: mov 1,%2\n" |
| 414 | " ldl_l %0,%1\n" |
| 415 | " stl_c %2,%1\n" |
| 416 | " beq %2,1f\n" |
| 417 | ".subsection 2\n" |
| 418 | "1: br 0b\n" |
| 419 | ".previous" |
| 420 | : "=r" (ret), "=m" (*p), "=r" (one) |
| 421 | : "m" (*p)); |
| 422 | return ret; |
| 423 | } |
| 424 | #endif |
| 425 | |
| 426 | #ifdef __sparc__ |
| 427 | static inline int testandset (int *p) |
| 428 | { |
| 429 | int ret; |
| 430 | |
| 431 | __asm__ __volatile__("ldstub [%1], %0" |
| 432 | : "=r" (ret) |
| 433 | : "r" (p) |
| 434 | : "memory"); |
| 435 | |
| 436 | return (ret ? 1 : 0); |
| 437 | } |
| 438 | #endif |
| 439 | |
bellard | a95c679 | 2003-06-09 15:29:55 +0000 | [diff] [blame] | 440 | #ifdef __arm__ |
| 441 | static inline int testandset (int *spinlock) |
| 442 | { |
| 443 | register unsigned int ret; |
| 444 | __asm__ __volatile__("swp %0, %1, [%2]" |
| 445 | : "=r"(ret) |
| 446 | : "0"(1), "r"(spinlock)); |
| 447 | |
| 448 | return ret; |
| 449 | } |
| 450 | #endif |
| 451 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 452 | #ifdef __mc68000 |
| 453 | static inline int testandset (int *p) |
| 454 | { |
| 455 | char ret; |
| 456 | __asm__ __volatile__("tas %1; sne %0" |
| 457 | : "=r" (ret) |
| 458 | : "m" (p) |
| 459 | : "cc","memory"); |
bellard | 4955a2c | 2005-02-07 14:09:05 +0000 | [diff] [blame] | 460 | return ret; |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 461 | } |
| 462 | #endif |
| 463 | |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 464 | #ifdef __ia64 |
| 465 | #include <ia64intrin.h> |
| 466 | |
| 467 | static inline int testandset (int *p) |
| 468 | { |
| 469 | return __sync_lock_test_and_set (p, 1); |
| 470 | } |
| 471 | #endif |
| 472 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 473 | typedef int spinlock_t; |
| 474 | |
| 475 | #define SPIN_LOCK_UNLOCKED 0 |
| 476 | |
bellard | aebcb60 | 2003-10-30 01:08:17 +0000 | [diff] [blame] | 477 | #if defined(CONFIG_USER_ONLY) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 478 | static inline void spin_lock(spinlock_t *lock) |
| 479 | { |
| 480 | while (testandset(lock)); |
| 481 | } |
| 482 | |
| 483 | static inline void spin_unlock(spinlock_t *lock) |
| 484 | { |
| 485 | *lock = 0; |
| 486 | } |
| 487 | |
| 488 | static inline int spin_trylock(spinlock_t *lock) |
| 489 | { |
| 490 | return !testandset(lock); |
| 491 | } |
bellard | 3c1cf9f | 2003-07-07 11:30:47 +0000 | [diff] [blame] | 492 | #else |
| 493 | static inline void spin_lock(spinlock_t *lock) |
| 494 | { |
| 495 | } |
| 496 | |
| 497 | static inline void spin_unlock(spinlock_t *lock) |
| 498 | { |
| 499 | } |
| 500 | |
| 501 | static inline int spin_trylock(spinlock_t *lock) |
| 502 | { |
| 503 | return 1; |
| 504 | } |
| 505 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 506 | |
| 507 | extern spinlock_t tb_lock; |
| 508 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 509 | extern int tb_invalidated_flag; |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 510 | |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 511 | #if !defined(CONFIG_USER_ONLY) |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 512 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 513 | void tlb_fill(target_ulong addr, int is_write, int is_user, |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 514 | void *retaddr); |
| 515 | |
| 516 | #define ACCESS_TYPE 3 |
| 517 | #define MEMSUFFIX _code |
| 518 | #define env cpu_single_env |
| 519 | |
| 520 | #define DATA_SIZE 1 |
| 521 | #include "softmmu_header.h" |
| 522 | |
| 523 | #define DATA_SIZE 2 |
| 524 | #include "softmmu_header.h" |
| 525 | |
| 526 | #define DATA_SIZE 4 |
| 527 | #include "softmmu_header.h" |
| 528 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 529 | #define DATA_SIZE 8 |
| 530 | #include "softmmu_header.h" |
| 531 | |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 532 | #undef ACCESS_TYPE |
| 533 | #undef MEMSUFFIX |
| 534 | #undef env |
| 535 | |
| 536 | #endif |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 537 | |
| 538 | #if defined(CONFIG_USER_ONLY) |
| 539 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 540 | { |
| 541 | return addr; |
| 542 | } |
| 543 | #else |
| 544 | /* NOTE: this function can trigger an exception */ |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 545 | /* NOTE2: the returned address is not exactly the physical address: it |
| 546 | is the offset relative to phys_ram_base */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 547 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 548 | { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 549 | int is_user, index, pd; |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 550 | |
| 551 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
bellard | 3f5dcc3 | 2004-01-18 22:44:01 +0000 | [diff] [blame] | 552 | #if defined(TARGET_I386) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 553 | is_user = ((env->hflags & HF_CPL_MASK) == 3); |
bellard | 3f5dcc3 | 2004-01-18 22:44:01 +0000 | [diff] [blame] | 554 | #elif defined (TARGET_PPC) |
| 555 | is_user = msr_pr; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 556 | #elif defined (TARGET_MIPS) |
| 557 | is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 558 | #elif defined (TARGET_SPARC) |
| 559 | is_user = (env->psrs == 0); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 560 | #elif defined (TARGET_ARM) |
| 561 | is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); |
bellard | 3f5dcc3 | 2004-01-18 22:44:01 +0000 | [diff] [blame] | 562 | #else |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 563 | #error unimplemented CPU |
bellard | 3f5dcc3 | 2004-01-18 22:44:01 +0000 | [diff] [blame] | 564 | #endif |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 565 | if (__builtin_expect(env->tlb_table[is_user][index].addr_code != |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 566 | (addr & TARGET_PAGE_MASK), 0)) { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 567 | ldub_code(addr); |
| 568 | } |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 569 | pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 570 | if (pd > IO_MEM_ROM) { |
| 571 | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 572 | } |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 573 | return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base; |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 574 | } |
| 575 | #endif |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 576 | |
| 577 | |
| 578 | #ifdef USE_KQEMU |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 579 | int kqemu_init(CPUState *env); |
| 580 | int kqemu_cpu_exec(CPUState *env); |
| 581 | void kqemu_flush_page(CPUState *env, target_ulong addr); |
| 582 | void kqemu_flush(CPUState *env, int global); |
bellard | 4b7df22 | 2005-08-21 09:37:35 +0000 | [diff] [blame] | 583 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr); |
bellard | a332e11 | 2005-09-03 17:55:47 +0000 | [diff] [blame] | 584 | void kqemu_cpu_interrupt(CPUState *env); |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 585 | |
| 586 | static inline int kqemu_is_ok(CPUState *env) |
| 587 | { |
| 588 | return(env->kqemu_enabled && |
| 589 | (env->hflags & HF_CPL_MASK) == 3 && |
| 590 | (env->eflags & IOPL_MASK) != IOPL_MASK && |
| 591 | (env->cr[0] & CR0_PE_MASK) && |
| 592 | (env->eflags & IF_MASK) && |
bellard | de75815 | 2005-09-04 16:54:47 +0000 | [diff] [blame] | 593 | !(env->eflags & VM_MASK)); |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | #endif |