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bellardd4e81642003-05-25 16:46:15 +00001/*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
bellardb346ff42003-06-15 20:05:50 +000021/* allow to see translation results - the slowdown should be negligible, so we leave it */
22#define DEBUG_DISAS
23
24/* is_jmp field values */
25#define DISAS_NEXT 0 /* next instruction can be analyzed */
26#define DISAS_JUMP 1 /* only pc was modified dynamically */
27#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
28#define DISAS_TB_JUMP 3 /* only pc was modified statically */
29
30struct TranslationBlock;
31
32/* XXX: make safe guess about sizes */
33#define MAX_OP_PER_INSTR 32
34#define OPC_BUF_SIZE 512
35#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
36
37#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
38
39extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
40extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
41extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
bellard66e85a22003-06-24 13:28:12 +000042extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
bellardb346ff42003-06-15 20:05:50 +000043extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
44
45#if defined(TARGET_I386)
46
bellardd4e81642003-05-25 16:46:15 +000047#define GEN_FLAG_CODE32_SHIFT 0
48#define GEN_FLAG_ADDSEG_SHIFT 1
49#define GEN_FLAG_SS32_SHIFT 2
50#define GEN_FLAG_VM_SHIFT 3
51#define GEN_FLAG_ST_SHIFT 4
bellardcf256292003-05-25 19:20:31 +000052#define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */
53#define GEN_FLAG_CPL_SHIFT 9
54#define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */
bellardd4e81642003-05-25 16:46:15 +000055
bellardb346ff42003-06-15 20:05:50 +000056#endif
57
58extern FILE *logfile;
59extern int loglevel;
60
bellard66e85a22003-06-24 13:28:12 +000061int gen_intermediate_code(struct TranslationBlock *tb);
62int gen_intermediate_code_pc(struct TranslationBlock *tb);
bellardb346ff42003-06-15 20:05:50 +000063void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
64int cpu_gen_code(struct TranslationBlock *tb,
65 int max_code_size, int *gen_code_size_ptr);
bellard66e85a22003-06-24 13:28:12 +000066int cpu_restore_state(struct TranslationBlock *tb,
67 CPUState *env, unsigned long searched_pc);
bellardb346ff42003-06-15 20:05:50 +000068void cpu_exec_init(void);
bellardd4e81642003-05-25 16:46:15 +000069int page_unprotect(unsigned long address);
bellard66e85a22003-06-24 13:28:12 +000070void page_unmap(void);
bellardd4e81642003-05-25 16:46:15 +000071
72#define CODE_GEN_MAX_SIZE 65536
73#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
74
75#define CODE_GEN_HASH_BITS 15
76#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
77
78/* maximum total translate dcode allocated */
79#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
80//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
81
82#if defined(__powerpc__)
83#define USE_DIRECT_JUMP
84#endif
85
86typedef struct TranslationBlock {
87 unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
88 unsigned long cs_base; /* CS base for this block */
89 unsigned int flags; /* flags defining in which context the code was generated */
90 uint16_t size; /* size of target code for this block (1 <=
91 size <= TARGET_PAGE_SIZE) */
92 uint8_t *tc_ptr; /* pointer to the translated code */
93 struct TranslationBlock *hash_next; /* next matching block */
94 struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
95 /* the following data are used to directly call another TB from
96 the code of this one. */
97 uint16_t tb_next_offset[2]; /* offset of original jump target */
98#ifdef USE_DIRECT_JUMP
99 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
100#else
bellard95f76522003-06-05 00:54:44 +0000101 uint32_t tb_next[2]; /* address of jump generated code */
bellardd4e81642003-05-25 16:46:15 +0000102#endif
103 /* list of TBs jumping to this one. This is a circular list using
104 the two least significant bits of the pointers to tell what is
105 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
106 jmp_first */
107 struct TranslationBlock *jmp_next[2];
108 struct TranslationBlock *jmp_first;
109} TranslationBlock;
110
111static inline unsigned int tb_hash_func(unsigned long pc)
112{
113 return pc & (CODE_GEN_HASH_SIZE - 1);
114}
115
116TranslationBlock *tb_alloc(unsigned long pc);
117void tb_flush(void);
118void tb_link(TranslationBlock *tb);
119
120extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
121
122extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
123extern uint8_t *code_gen_ptr;
124
125/* find a translation block in the translation cache. If not found,
126 return NULL and the pointer to the last element of the list in pptb */
127static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
128 unsigned long pc,
129 unsigned long cs_base,
130 unsigned int flags)
131{
132 TranslationBlock **ptb, *tb;
133 unsigned int h;
134
135 h = tb_hash_func(pc);
136 ptb = &tb_hash[h];
137 for(;;) {
138 tb = *ptb;
139 if (!tb)
140 break;
141 if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
142 return tb;
143 ptb = &tb->hash_next;
144 }
145 *pptb = ptb;
146 return NULL;
147}
148
149#if defined(__powerpc__)
150
151static inline void tb_set_jmp_target(TranslationBlock *tb,
152 int n, unsigned long addr)
153{
154 uint32_t val, *ptr;
155 unsigned long offset;
156
157 offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]);
158
159 /* patch the branch destination */
160 ptr = (uint32_t *)offset;
161 val = *ptr;
162 val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc);
163 *ptr = val;
164 /* flush icache */
165 asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
166 asm volatile ("sync" : : : "memory");
167 asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
168 asm volatile ("sync" : : : "memory");
169 asm volatile ("isync" : : : "memory");
170}
171
172#else
173
174/* set the jump target */
175static inline void tb_set_jmp_target(TranslationBlock *tb,
176 int n, unsigned long addr)
177{
bellard95f76522003-06-05 00:54:44 +0000178 tb->tb_next[n] = addr;
bellardd4e81642003-05-25 16:46:15 +0000179}
180
181#endif
182
183static inline void tb_add_jump(TranslationBlock *tb, int n,
184 TranslationBlock *tb_next)
185{
bellardcf256292003-05-25 19:20:31 +0000186 /* NOTE: this test is only needed for thread safety */
187 if (!tb->jmp_next[n]) {
188 /* patch the native jump address */
189 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
190
191 /* add in TB jmp circular list */
192 tb->jmp_next[n] = tb_next->jmp_first;
193 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
194 }
bellardd4e81642003-05-25 16:46:15 +0000195}
196
bellarda513fe12003-05-27 23:29:48 +0000197TranslationBlock *tb_find_pc(unsigned long pc_ptr);
198
bellardd4e81642003-05-25 16:46:15 +0000199#ifndef offsetof
200#define offsetof(type, field) ((size_t) &((type *)0)->field)
201#endif
202
bellardb346ff42003-06-15 20:05:50 +0000203#if defined(__powerpc__)
204
205/* on PowerPC we patch the jump instruction directly */
206#define JUMP_TB(tbparam, n, eip)\
207do {\
208 static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
209 asm volatile ("b %0" : : "i" (&__op_jmp ## n));\
210label ## n:\
211 T0 = (long)(tbparam) + (n);\
212 EIP = eip;\
213} while (0)
214
215#else
216
217/* jump to next block operations (more portable code, does not need
218 cache flushing, but slower because of indirect jump) */
219#define JUMP_TB(tbparam, n, eip)\
220do {\
221 static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
222 goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
223label ## n:\
224 T0 = (long)(tbparam) + (n);\
225 EIP = eip;\
226} while (0)
227
228#endif
229
bellardd4e81642003-05-25 16:46:15 +0000230#ifdef __powerpc__
231static inline int testandset (int *p)
232{
233 int ret;
234 __asm__ __volatile__ (
235 "0: lwarx %0,0,%1 ;"
236 " xor. %0,%3,%0;"
237 " bne 1f;"
238 " stwcx. %2,0,%1;"
239 " bne- 0b;"
240 "1: "
241 : "=&r" (ret)
242 : "r" (p), "r" (1), "r" (0)
243 : "cr0", "memory");
244 return ret;
245}
246#endif
247
248#ifdef __i386__
249static inline int testandset (int *p)
250{
251 char ret;
252 long int readval;
253
254 __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
255 : "=q" (ret), "=m" (*p), "=a" (readval)
256 : "r" (1), "m" (*p), "a" (0)
257 : "memory");
258 return ret;
259}
260#endif
261
262#ifdef __s390__
263static inline int testandset (int *p)
264{
265 int ret;
266
267 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
268 " jl 0b"
269 : "=&d" (ret)
270 : "r" (1), "a" (p), "0" (*p)
271 : "cc", "memory" );
272 return ret;
273}
274#endif
275
276#ifdef __alpha__
bellard2f87c602003-06-02 20:38:09 +0000277static inline int testandset (int *p)
bellardd4e81642003-05-25 16:46:15 +0000278{
279 int ret;
280 unsigned long one;
281
282 __asm__ __volatile__ ("0: mov 1,%2\n"
283 " ldl_l %0,%1\n"
284 " stl_c %2,%1\n"
285 " beq %2,1f\n"
286 ".subsection 2\n"
287 "1: br 0b\n"
288 ".previous"
289 : "=r" (ret), "=m" (*p), "=r" (one)
290 : "m" (*p));
291 return ret;
292}
293#endif
294
295#ifdef __sparc__
296static inline int testandset (int *p)
297{
298 int ret;
299
300 __asm__ __volatile__("ldstub [%1], %0"
301 : "=r" (ret)
302 : "r" (p)
303 : "memory");
304
305 return (ret ? 1 : 0);
306}
307#endif
308
bellarda95c6792003-06-09 15:29:55 +0000309#ifdef __arm__
310static inline int testandset (int *spinlock)
311{
312 register unsigned int ret;
313 __asm__ __volatile__("swp %0, %1, [%2]"
314 : "=r"(ret)
315 : "0"(1), "r"(spinlock));
316
317 return ret;
318}
319#endif
320
bellardd4e81642003-05-25 16:46:15 +0000321typedef int spinlock_t;
322
323#define SPIN_LOCK_UNLOCKED 0
324
325static inline void spin_lock(spinlock_t *lock)
326{
327 while (testandset(lock));
328}
329
330static inline void spin_unlock(spinlock_t *lock)
331{
332 *lock = 0;
333}
334
335static inline int spin_trylock(spinlock_t *lock)
336{
337 return !testandset(lock);
338}
339
340extern spinlock_t tb_lock;
341