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Aurelien Jarnoafa05232009-10-17 14:17:47 +02001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
Markus Armbruster14e54f82016-06-29 11:14:47 +020026
27#ifndef MIPS_TCG_TARGET_H
28#define MIPS_TCG_TARGET_H
Aurelien Jarnoafa05232009-10-17 14:17:47 +020029
Jin Guojie999b9412017-01-05 12:57:54 +080030#if _MIPS_SIM == _ABIO32
31# define TCG_TARGET_REG_BITS 32
32#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
33# define TCG_TARGET_REG_BITS 64
34#else
35# error "Unknown ABI"
36#endif
37
Richard Hendersonae0218e2014-04-25 19:22:44 +000038#define TCG_TARGET_INSN_UNIT_SIZE 4
Paolo Bonzini006f8632015-05-05 09:18:22 +020039#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
Aurelien Jarnoafa05232009-10-17 14:17:47 +020040#define TCG_TARGET_NB_REGS 32
41
Richard Henderson771142c2011-11-09 08:03:33 +000042typedef enum {
Aurelien Jarnoafa05232009-10-17 14:17:47 +020043 TCG_REG_ZERO = 0,
44 TCG_REG_AT,
45 TCG_REG_V0,
46 TCG_REG_V1,
47 TCG_REG_A0,
48 TCG_REG_A1,
49 TCG_REG_A2,
50 TCG_REG_A3,
51 TCG_REG_T0,
52 TCG_REG_T1,
53 TCG_REG_T2,
54 TCG_REG_T3,
55 TCG_REG_T4,
56 TCG_REG_T5,
57 TCG_REG_T6,
58 TCG_REG_T7,
59 TCG_REG_S0,
60 TCG_REG_S1,
61 TCG_REG_S2,
62 TCG_REG_S3,
63 TCG_REG_S4,
64 TCG_REG_S5,
65 TCG_REG_S6,
66 TCG_REG_S7,
67 TCG_REG_T8,
68 TCG_REG_T9,
69 TCG_REG_K0,
70 TCG_REG_K1,
71 TCG_REG_GP,
72 TCG_REG_SP,
Richard Henderson41883902014-04-15 09:03:59 -070073 TCG_REG_S8,
Aurelien Jarnoafa05232009-10-17 14:17:47 +020074 TCG_REG_RA,
Richard Henderson41883902014-04-15 09:03:59 -070075
76 TCG_REG_CALL_STACK = TCG_REG_SP,
77 TCG_AREG0 = TCG_REG_S0,
Richard Henderson771142c2011-11-09 08:03:33 +000078} TCGReg;
Aurelien Jarnoafa05232009-10-17 14:17:47 +020079
Aurelien Jarnoafa05232009-10-17 14:17:47 +020080/* used for function call generation */
Jin Guojie999b9412017-01-05 12:57:54 +080081#define TCG_TARGET_STACK_ALIGN 16
82#if _MIPS_SIM == _ABIO32
83# define TCG_TARGET_CALL_STACK_OFFSET 16
84#else
85# define TCG_TARGET_CALL_STACK_OFFSET 0
86#endif
87#define TCG_TARGET_CALL_ALIGN_ARGS 1
Aurelien Jarnoafa05232009-10-17 14:17:47 +020088
Aurelien Jarno988902f2013-08-15 17:57:59 +020089/* MOVN/MOVZ instructions detection */
90#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
91 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
92 defined(_MIPS_ARCH_MIPS4)
93#define use_movnz_instructions 1
94#else
95extern bool use_movnz_instructions;
96#endif
97
98/* MIPS32 instruction set detection */
99#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
100#define use_mips32_instructions 1
101#else
102extern bool use_mips32_instructions;
103#endif
104
105/* MIPS32R2 instruction set detection */
106#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
107#define use_mips32r2_instructions 1
108#else
109extern bool use_mips32r2_instructions;
110#endif
111
James Hogance14bd42015-10-02 13:24:14 +0100112/* MIPS32R6 instruction set detection */
113#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
114#define use_mips32r6_instructions 1
115#else
116#define use_mips32r6_instructions 0
117#endif
118
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200119/* optional instructions */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700120#define TCG_TARGET_HAS_div_i32 1
Richard Hendersonca675f42013-03-11 22:41:47 -0700121#define TCG_TARGET_HAS_rem_i32 1
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700122#define TCG_TARGET_HAS_not_i32 1
123#define TCG_TARGET_HAS_nor_i32 1
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700124#define TCG_TARGET_HAS_andc_i32 0
125#define TCG_TARGET_HAS_orc_i32 0
126#define TCG_TARGET_HAS_eqv_i32 0
127#define TCG_TARGET_HAS_nand_i32 0
James Hoganbc6d0c22015-10-02 13:24:16 +0100128#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
129#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
Richard Henderson3c9a8f12013-08-14 14:41:43 -0700130#define TCG_TARGET_HAS_muluh_i32 1
131#define TCG_TARGET_HAS_mulsh_i32 1
Jin Guojiebb08afe2017-01-05 12:57:46 +0800132#define TCG_TARGET_HAS_bswap32_i32 1
Aurelien Jarno5786e062017-04-30 16:52:52 +0200133#define TCG_TARGET_HAS_goto_ptr 1
Richard Hendersona8583392017-07-31 22:02:31 -0700134#define TCG_TARGET_HAS_direct_jump 1
Aurelien Jarno7d7c4932012-09-21 18:20:26 +0200135
Jin Guojie0119b192017-01-05 12:57:48 +0800136#if TCG_TARGET_REG_BITS == 64
137#define TCG_TARGET_HAS_add2_i32 0
138#define TCG_TARGET_HAS_sub2_i32 0
139#define TCG_TARGET_HAS_extrl_i64_i32 1
140#define TCG_TARGET_HAS_extrh_i64_i32 1
141#define TCG_TARGET_HAS_div_i64 1
142#define TCG_TARGET_HAS_rem_i64 1
143#define TCG_TARGET_HAS_not_i64 1
144#define TCG_TARGET_HAS_nor_i64 1
145#define TCG_TARGET_HAS_andc_i64 0
146#define TCG_TARGET_HAS_orc_i64 0
147#define TCG_TARGET_HAS_eqv_i64 0
148#define TCG_TARGET_HAS_nand_i64 0
149#define TCG_TARGET_HAS_add2_i64 0
150#define TCG_TARGET_HAS_sub2_i64 0
151#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
152#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
153#define TCG_TARGET_HAS_muluh_i64 1
154#define TCG_TARGET_HAS_mulsh_i64 1
155#define TCG_TARGET_HAS_ext32s_i64 1
156#define TCG_TARGET_HAS_ext32u_i64 1
157#endif
158
Aurelien Jarno988902f2013-08-15 17:57:59 +0200159/* optional instructions detected at runtime */
160#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
161#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
Aurelien Jarno988902f2013-08-15 17:57:59 +0200162#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
Richard Hendersonbefbb3c2016-10-14 15:50:25 -0500163#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500164#define TCG_TARGET_HAS_sextract_i32 0
Aurelien Jarno3207bf22013-08-15 17:57:59 +0200165#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
166#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
Aurelien Jarno988902f2013-08-15 17:57:59 +0200167#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
Richard Henderson2a1d9d42016-11-16 15:34:03 +0100168#define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions
169#define TCG_TARGET_HAS_ctz_i32 0
Richard Hendersona768e4e2016-11-21 11:13:39 +0100170#define TCG_TARGET_HAS_ctpop_i32 0
Aurelien Jarnoc1cf85c2012-09-21 18:20:26 +0200171
Jin Guojie0119b192017-01-05 12:57:48 +0800172#if TCG_TARGET_REG_BITS == 64
173#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions
174#define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions
175#define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions
176#define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions
177#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
Richard Hendersonbefbb3c2016-10-14 15:50:25 -0500178#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
179#define TCG_TARGET_HAS_sextract_i64 0
Jin Guojie0119b192017-01-05 12:57:48 +0800180#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
181#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
182#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
Richard Henderson2a1d9d42016-11-16 15:34:03 +0100183#define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions
184#define TCG_TARGET_HAS_ctz_i64 0
Richard Hendersona768e4e2016-11-21 11:13:39 +0100185#define TCG_TARGET_HAS_ctpop_i64 0
Jin Guojie0119b192017-01-05 12:57:48 +0800186#endif
187
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200188/* optional instructions automatically implemented */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700189#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
190#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
191#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200192
Jin Guojie0119b192017-01-05 12:57:48 +0800193#if TCG_TARGET_REG_BITS == 64
194#define TCG_TARGET_HAS_neg_i64 0 /* sub rd, zero, rt */
195#define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
196#define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
197#endif
198
Brad03938c12011-05-25 23:06:00 -0400199#ifdef __OpenBSD__
200#include <machine/sysarch.h>
201#else
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200202#include <sys/cachectl.h>
Brad03938c12011-05-25 23:06:00 -0400203#endif
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200204
Richard Hendersona8583392017-07-31 22:02:31 -0700205#define TCG_TARGET_DEFAULT_MO (0)
206
Richard Hendersonb93949e2013-08-20 14:22:50 -0700207static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200208{
209 cacheflush ((void *)start, stop-start, ICACHE);
210}
Paolo Bonzinicb9c3772012-12-06 12:15:58 +0100211
Richard Hendersona8583392017-07-31 22:02:31 -0700212void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
Pranith Kumar71650df2017-08-29 02:33:11 -0400213
Richard Henderson659ef5c2017-07-30 12:30:41 -0700214#ifdef CONFIG_SOFTMMU
215#define TCG_TARGET_NEED_LDST_LABELS
216#endif
217
Paolo Bonzinicb9c3772012-12-06 12:15:58 +0100218#endif