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bellard2c0262a2003-09-30 20:34:21 +00001/*
2 * i386 virtual CPU header
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard2c0262a2003-09-30 20:34:21 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard2c0262a2003-09-30 20:34:21 +000018 */
19#ifndef CPU_I386_H
20#define CPU_I386_H
21
bellard14ce26e2005-01-03 23:50:08 +000022#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020023#include "qemu-common.h"
bellard14ce26e2005-01-03 23:50:08 +000024
25#ifdef TARGET_X86_64
26#define TARGET_LONG_BITS 64
27#else
bellard3cf1e032004-01-24 15:19:09 +000028#define TARGET_LONG_BITS 32
bellard14ce26e2005-01-03 23:50:08 +000029#endif
bellard3cf1e032004-01-24 15:19:09 +000030
bellardd720b932004-04-25 17:57:43 +000031/* target supports implicit self modifying code */
32#define TARGET_HAS_SMC
33/* support for self modifying code even if the modified instruction is
34 close to the modifying instruction */
35#define TARGET_HAS_PRECISE_SMC
36
bellard1fddef42005-04-17 19:16:13 +000037#define TARGET_HAS_ICE 1
38
ths9042c0e2006-12-23 14:18:40 +000039#ifdef TARGET_X86_64
40#define ELF_MACHINE EM_X86_64
41#else
42#define ELF_MACHINE EM_386
43#endif
44
pbrookc2764712009-03-07 15:24:59 +000045#define CPUState struct CPUX86State
46
bellard2c0262a2003-09-30 20:34:21 +000047#include "cpu-defs.h"
48
bellard7a0e1f42005-03-13 17:01:47 +000049#include "softfloat.h"
50
bellard2c0262a2003-09-30 20:34:21 +000051#define R_EAX 0
52#define R_ECX 1
53#define R_EDX 2
54#define R_EBX 3
55#define R_ESP 4
56#define R_EBP 5
57#define R_ESI 6
58#define R_EDI 7
59
60#define R_AL 0
61#define R_CL 1
62#define R_DL 2
63#define R_BL 3
64#define R_AH 4
65#define R_CH 5
66#define R_DH 6
67#define R_BH 7
68
69#define R_ES 0
70#define R_CS 1
71#define R_SS 2
72#define R_DS 3
73#define R_FS 4
74#define R_GS 5
75
76/* segment descriptor fields */
77#define DESC_G_MASK (1 << 23)
78#define DESC_B_SHIFT 22
79#define DESC_B_MASK (1 << DESC_B_SHIFT)
bellard14ce26e2005-01-03 23:50:08 +000080#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
81#define DESC_L_MASK (1 << DESC_L_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +000082#define DESC_AVL_MASK (1 << 20)
83#define DESC_P_MASK (1 << 15)
84#define DESC_DPL_SHIFT 13
aliguoria3867ed2009-04-18 15:36:11 +000085#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +000086#define DESC_S_MASK (1 << 12)
87#define DESC_TYPE_SHIFT 8
aliguoria3867ed2009-04-18 15:36:11 +000088#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +000089#define DESC_A_MASK (1 << 8)
90
bellarde670b892003-11-12 23:23:42 +000091#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
92#define DESC_C_MASK (1 << 10) /* code: conforming */
93#define DESC_R_MASK (1 << 9) /* code: readable */
bellard2c0262a2003-09-30 20:34:21 +000094
bellarde670b892003-11-12 23:23:42 +000095#define DESC_E_MASK (1 << 10) /* data: expansion direction */
96#define DESC_W_MASK (1 << 9) /* data: writable */
97
98#define DESC_TSS_BUSY_MASK (1 << 9)
bellard2c0262a2003-09-30 20:34:21 +000099
100/* eflags masks */
101#define CC_C 0x0001
102#define CC_P 0x0004
103#define CC_A 0x0010
104#define CC_Z 0x0040
105#define CC_S 0x0080
106#define CC_O 0x0800
107
108#define TF_SHIFT 8
109#define IOPL_SHIFT 12
110#define VM_SHIFT 17
111
112#define TF_MASK 0x00000100
113#define IF_MASK 0x00000200
114#define DF_MASK 0x00000400
115#define IOPL_MASK 0x00003000
116#define NT_MASK 0x00004000
117#define RF_MASK 0x00010000
118#define VM_MASK 0x00020000
ths5fafdf22007-09-16 21:08:06 +0000119#define AC_MASK 0x00040000
bellard2c0262a2003-09-30 20:34:21 +0000120#define VIF_MASK 0x00080000
121#define VIP_MASK 0x00100000
122#define ID_MASK 0x00200000
123
thsaa1f17c2007-07-11 22:48:58 +0000124/* hidden flags - used internally by qemu to represent additional cpu
bellard33c263d2008-06-04 17:39:33 +0000125 states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
126 redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
127 position to ease oring with eflags. */
bellard2c0262a2003-09-30 20:34:21 +0000128/* current cpl */
129#define HF_CPL_SHIFT 0
130/* true if soft mmu is being used */
131#define HF_SOFTMMU_SHIFT 2
132/* true if hardware interrupts must be disabled for next instruction */
133#define HF_INHIBIT_IRQ_SHIFT 3
134/* 16 or 32 segments */
135#define HF_CS32_SHIFT 4
136#define HF_SS32_SHIFT 5
bellarddc196a52004-06-13 13:26:14 +0000137/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
bellard2c0262a2003-09-30 20:34:21 +0000138#define HF_ADDSEG_SHIFT 6
bellard65262d52004-01-04 17:20:53 +0000139/* copy of CR0.PE (protected mode) */
140#define HF_PE_SHIFT 7
141#define HF_TF_SHIFT 8 /* must be same as eflags */
bellard7eee2a52004-02-25 23:17:58 +0000142#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
143#define HF_EM_SHIFT 10
144#define HF_TS_SHIFT 11
bellard65262d52004-01-04 17:20:53 +0000145#define HF_IOPL_SHIFT 12 /* must be same as eflags */
bellard14ce26e2005-01-03 23:50:08 +0000146#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
147#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
Jan Kiszkaa2397802009-05-10 22:30:53 +0200148#define HF_RF_SHIFT 16 /* must be same as eflags */
bellard65262d52004-01-04 17:20:53 +0000149#define HF_VM_SHIFT 17 /* must be same as eflags */
bellard3b21e032006-09-24 18:41:56 +0000150#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
bellarddb620f42008-06-04 17:02:19 +0000151#define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
152#define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
Jan Kiszkaa2397802009-05-10 22:30:53 +0200153#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
bellard2c0262a2003-09-30 20:34:21 +0000154
155#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
156#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
157#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
158#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
159#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
160#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
bellard65262d52004-01-04 17:20:53 +0000161#define HF_PE_MASK (1 << HF_PE_SHIFT)
bellard58fe2f12004-02-16 22:11:32 +0000162#define HF_TF_MASK (1 << HF_TF_SHIFT)
bellard7eee2a52004-02-25 23:17:58 +0000163#define HF_MP_MASK (1 << HF_MP_SHIFT)
164#define HF_EM_MASK (1 << HF_EM_SHIFT)
165#define HF_TS_MASK (1 << HF_TS_SHIFT)
aliguori0650f1a2008-11-05 15:28:47 +0000166#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
bellard14ce26e2005-01-03 23:50:08 +0000167#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
168#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
Jan Kiszkaa2397802009-05-10 22:30:53 +0200169#define HF_RF_MASK (1 << HF_RF_SHIFT)
aliguori0650f1a2008-11-05 15:28:47 +0000170#define HF_VM_MASK (1 << HF_VM_SHIFT)
bellard3b21e032006-09-24 18:41:56 +0000171#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
bellard872929a2008-05-28 16:16:54 +0000172#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
173#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
Jan Kiszkaa2397802009-05-10 22:30:53 +0200174#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
bellard2c0262a2003-09-30 20:34:21 +0000175
bellarddb620f42008-06-04 17:02:19 +0000176/* hflags2 */
177
178#define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
179#define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
180#define HF2_NMI_SHIFT 2 /* CPU serving NMI */
181#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
182
183#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
184#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
185#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
186#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
187
aliguori0650f1a2008-11-05 15:28:47 +0000188#define CR0_PE_SHIFT 0
189#define CR0_MP_SHIFT 1
190
bellard2c0262a2003-09-30 20:34:21 +0000191#define CR0_PE_MASK (1 << 0)
bellard7eee2a52004-02-25 23:17:58 +0000192#define CR0_MP_MASK (1 << 1)
193#define CR0_EM_MASK (1 << 2)
bellard2c0262a2003-09-30 20:34:21 +0000194#define CR0_TS_MASK (1 << 3)
bellard2ee73ac2004-05-08 21:08:41 +0000195#define CR0_ET_MASK (1 << 4)
bellard7eee2a52004-02-25 23:17:58 +0000196#define CR0_NE_MASK (1 << 5)
bellard2c0262a2003-09-30 20:34:21 +0000197#define CR0_WP_MASK (1 << 16)
198#define CR0_AM_MASK (1 << 18)
199#define CR0_PG_MASK (1 << 31)
200
201#define CR4_VME_MASK (1 << 0)
202#define CR4_PVI_MASK (1 << 1)
203#define CR4_TSD_MASK (1 << 2)
204#define CR4_DE_MASK (1 << 3)
205#define CR4_PSE_MASK (1 << 4)
bellard64a595f2004-02-03 23:27:13 +0000206#define CR4_PAE_MASK (1 << 5)
Huang Ying79c4f6b2009-06-23 10:05:14 +0800207#define CR4_MCE_MASK (1 << 6)
bellard64a595f2004-02-03 23:27:13 +0000208#define CR4_PGE_MASK (1 << 7)
bellard14ce26e2005-01-03 23:50:08 +0000209#define CR4_PCE_MASK (1 << 8)
aliguori0650f1a2008-11-05 15:28:47 +0000210#define CR4_OSFXSR_SHIFT 9
211#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
bellard14ce26e2005-01-03 23:50:08 +0000212#define CR4_OSXMMEXCPT_MASK (1 << 10)
bellard2c0262a2003-09-30 20:34:21 +0000213
aliguori01df0402008-11-18 21:08:15 +0000214#define DR6_BD (1 << 13)
215#define DR6_BS (1 << 14)
216#define DR6_BT (1 << 15)
217#define DR6_FIXED_1 0xffff0ff0
218
219#define DR7_GD (1 << 13)
220#define DR7_TYPE_SHIFT 16
221#define DR7_LEN_SHIFT 18
222#define DR7_FIXED_1 0x00000400
223
bellard2c0262a2003-09-30 20:34:21 +0000224#define PG_PRESENT_BIT 0
225#define PG_RW_BIT 1
226#define PG_USER_BIT 2
227#define PG_PWT_BIT 3
228#define PG_PCD_BIT 4
229#define PG_ACCESSED_BIT 5
230#define PG_DIRTY_BIT 6
231#define PG_PSE_BIT 7
232#define PG_GLOBAL_BIT 8
bellard5cf38392005-11-28 21:02:43 +0000233#define PG_NX_BIT 63
bellard2c0262a2003-09-30 20:34:21 +0000234
235#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
236#define PG_RW_MASK (1 << PG_RW_BIT)
237#define PG_USER_MASK (1 << PG_USER_BIT)
238#define PG_PWT_MASK (1 << PG_PWT_BIT)
239#define PG_PCD_MASK (1 << PG_PCD_BIT)
240#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
241#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
242#define PG_PSE_MASK (1 << PG_PSE_BIT)
243#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
bellard5cf38392005-11-28 21:02:43 +0000244#define PG_NX_MASK (1LL << PG_NX_BIT)
bellard2c0262a2003-09-30 20:34:21 +0000245
246#define PG_ERROR_W_BIT 1
247
248#define PG_ERROR_P_MASK 0x01
249#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
250#define PG_ERROR_U_MASK 0x04
251#define PG_ERROR_RSVD_MASK 0x08
bellard5cf38392005-11-28 21:02:43 +0000252#define PG_ERROR_I_D_MASK 0x10
bellard2c0262a2003-09-30 20:34:21 +0000253
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300254#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
255#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800256
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300257#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
Huang Ying79c4f6b2009-06-23 10:05:14 +0800258#define MCE_BANKS_DEF 10
259
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300260#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
261#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
Anthony Liguorie6a05752009-07-10 13:39:34 -0500262#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800263
Anthony Liguorie6a05752009-07-10 13:39:34 -0500264#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
265#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
266#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
Marcelo Tosattic0532a72010-10-11 15:31:21 -0300267#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
268#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
269#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
270#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
271#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
272#define MCI_STATUS_AR (1ULL<<55) /* Action required */
273
274/* MISC register defines */
275#define MCM_ADDR_SEGOFF 0 /* segment offset */
276#define MCM_ADDR_LINEAR 1 /* linear address */
277#define MCM_ADDR_PHYS 2 /* physical address */
278#define MCM_ADDR_MEM 3 /* memory address */
279#define MCM_ADDR_GENERIC 7 /* generic */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800280
aliguori0650f1a2008-11-05 15:28:47 +0000281#define MSR_IA32_TSC 0x10
bellard2c0262a2003-09-30 20:34:21 +0000282#define MSR_IA32_APICBASE 0x1b
283#define MSR_IA32_APICBASE_BSP (1<<8)
284#define MSR_IA32_APICBASE_ENABLE (1<<11)
285#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
286
aliguoridd5e3b12009-01-29 17:02:17 +0000287#define MSR_MTRRcap 0xfe
288#define MSR_MTRRcap_VCNT 8
289#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
290#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
291
bellard2c0262a2003-09-30 20:34:21 +0000292#define MSR_IA32_SYSENTER_CS 0x174
293#define MSR_IA32_SYSENTER_ESP 0x175
294#define MSR_IA32_SYSENTER_EIP 0x176
295
bellard8f091a52005-07-23 17:41:26 +0000296#define MSR_MCG_CAP 0x179
297#define MSR_MCG_STATUS 0x17a
298#define MSR_MCG_CTL 0x17b
299
balroge737b322008-09-25 18:11:30 +0000300#define MSR_IA32_PERF_STATUS 0x198
301
aliguori165d9b82009-01-26 17:53:04 +0000302#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
303#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
304
305#define MSR_MTRRfix64K_00000 0x250
306#define MSR_MTRRfix16K_80000 0x258
307#define MSR_MTRRfix16K_A0000 0x259
308#define MSR_MTRRfix4K_C0000 0x268
309#define MSR_MTRRfix4K_C8000 0x269
310#define MSR_MTRRfix4K_D0000 0x26a
311#define MSR_MTRRfix4K_D8000 0x26b
312#define MSR_MTRRfix4K_E0000 0x26c
313#define MSR_MTRRfix4K_E8000 0x26d
314#define MSR_MTRRfix4K_F0000 0x26e
315#define MSR_MTRRfix4K_F8000 0x26f
316
bellard8f091a52005-07-23 17:41:26 +0000317#define MSR_PAT 0x277
318
aliguori165d9b82009-01-26 17:53:04 +0000319#define MSR_MTRRdefType 0x2ff
320
Huang Ying79c4f6b2009-06-23 10:05:14 +0800321#define MSR_MC0_CTL 0x400
322#define MSR_MC0_STATUS 0x401
323#define MSR_MC0_ADDR 0x402
324#define MSR_MC0_MISC 0x403
325
bellard14ce26e2005-01-03 23:50:08 +0000326#define MSR_EFER 0xc0000080
327
328#define MSR_EFER_SCE (1 << 0)
329#define MSR_EFER_LME (1 << 8)
330#define MSR_EFER_LMA (1 << 10)
331#define MSR_EFER_NXE (1 << 11)
bellard872929a2008-05-28 16:16:54 +0000332#define MSR_EFER_SVME (1 << 12)
bellard14ce26e2005-01-03 23:50:08 +0000333#define MSR_EFER_FFXSR (1 << 14)
334
335#define MSR_STAR 0xc0000081
336#define MSR_LSTAR 0xc0000082
337#define MSR_CSTAR 0xc0000083
338#define MSR_FMASK 0xc0000084
339#define MSR_FSBASE 0xc0000100
340#define MSR_GSBASE 0xc0000101
341#define MSR_KERNELGSBASE 0xc0000102
Andre Przywara1b050072009-09-19 00:30:49 +0200342#define MSR_TSC_AUX 0xc0000103
bellard14ce26e2005-01-03 23:50:08 +0000343
ths0573fbf2007-09-23 15:28:04 +0000344#define MSR_VM_HSAVE_PA 0xc0010117
345
bellard14ce26e2005-01-03 23:50:08 +0000346/* cpuid_features bits */
347#define CPUID_FP87 (1 << 0)
348#define CPUID_VME (1 << 1)
349#define CPUID_DE (1 << 2)
350#define CPUID_PSE (1 << 3)
351#define CPUID_TSC (1 << 4)
352#define CPUID_MSR (1 << 5)
353#define CPUID_PAE (1 << 6)
354#define CPUID_MCE (1 << 7)
355#define CPUID_CX8 (1 << 8)
356#define CPUID_APIC (1 << 9)
357#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
358#define CPUID_MTRR (1 << 12)
359#define CPUID_PGE (1 << 13)
360#define CPUID_MCA (1 << 14)
361#define CPUID_CMOV (1 << 15)
bellard8f091a52005-07-23 17:41:26 +0000362#define CPUID_PAT (1 << 16)
bellard8988ae82006-09-27 19:54:02 +0000363#define CPUID_PSE36 (1 << 17)
bellarda049de62007-11-08 13:28:47 +0000364#define CPUID_PN (1 << 18)
bellard8f091a52005-07-23 17:41:26 +0000365#define CPUID_CLFLUSH (1 << 19)
bellarda049de62007-11-08 13:28:47 +0000366#define CPUID_DTS (1 << 21)
367#define CPUID_ACPI (1 << 22)
bellard14ce26e2005-01-03 23:50:08 +0000368#define CPUID_MMX (1 << 23)
369#define CPUID_FXSR (1 << 24)
370#define CPUID_SSE (1 << 25)
371#define CPUID_SSE2 (1 << 26)
bellarda049de62007-11-08 13:28:47 +0000372#define CPUID_SS (1 << 27)
373#define CPUID_HT (1 << 28)
374#define CPUID_TM (1 << 29)
375#define CPUID_IA64 (1 << 30)
376#define CPUID_PBE (1 << 31)
bellard14ce26e2005-01-03 23:50:08 +0000377
bellard465e9832006-04-23 21:54:01 +0000378#define CPUID_EXT_SSE3 (1 << 0)
pbrook558fa832008-09-29 13:55:36 +0000379#define CPUID_EXT_DTES64 (1 << 2)
bellard9df217a2005-02-10 22:05:51 +0000380#define CPUID_EXT_MONITOR (1 << 3)
bellarda049de62007-11-08 13:28:47 +0000381#define CPUID_EXT_DSCPL (1 << 4)
382#define CPUID_EXT_VMX (1 << 5)
383#define CPUID_EXT_SMX (1 << 6)
384#define CPUID_EXT_EST (1 << 7)
385#define CPUID_EXT_TM2 (1 << 8)
386#define CPUID_EXT_SSSE3 (1 << 9)
387#define CPUID_EXT_CID (1 << 10)
bellard9df217a2005-02-10 22:05:51 +0000388#define CPUID_EXT_CX16 (1 << 13)
bellarda049de62007-11-08 13:28:47 +0000389#define CPUID_EXT_XTPR (1 << 14)
pbrook558fa832008-09-29 13:55:36 +0000390#define CPUID_EXT_PDCM (1 << 15)
391#define CPUID_EXT_DCA (1 << 18)
392#define CPUID_EXT_SSE41 (1 << 19)
393#define CPUID_EXT_SSE42 (1 << 20)
394#define CPUID_EXT_X2APIC (1 << 21)
395#define CPUID_EXT_MOVBE (1 << 22)
396#define CPUID_EXT_POPCNT (1 << 23)
397#define CPUID_EXT_XSAVE (1 << 26)
398#define CPUID_EXT_OSXSAVE (1 << 27)
Andre Przywara6c0d7ee2009-06-25 00:08:04 +0200399#define CPUID_EXT_HYPERVISOR (1 << 31)
bellard9df217a2005-02-10 22:05:51 +0000400
401#define CPUID_EXT2_SYSCALL (1 << 11)
bellarda049de62007-11-08 13:28:47 +0000402#define CPUID_EXT2_MP (1 << 19)
bellard9df217a2005-02-10 22:05:51 +0000403#define CPUID_EXT2_NX (1 << 20)
bellarda049de62007-11-08 13:28:47 +0000404#define CPUID_EXT2_MMXEXT (1 << 22)
bellard8d9bfc22005-04-23 17:46:55 +0000405#define CPUID_EXT2_FFXSR (1 << 25)
bellarda049de62007-11-08 13:28:47 +0000406#define CPUID_EXT2_PDPE1GB (1 << 26)
407#define CPUID_EXT2_RDTSCP (1 << 27)
bellard9df217a2005-02-10 22:05:51 +0000408#define CPUID_EXT2_LM (1 << 29)
bellarda049de62007-11-08 13:28:47 +0000409#define CPUID_EXT2_3DNOWEXT (1 << 30)
410#define CPUID_EXT2_3DNOW (1 << 31)
bellard9df217a2005-02-10 22:05:51 +0000411
bellarda049de62007-11-08 13:28:47 +0000412#define CPUID_EXT3_LAHF_LM (1 << 0)
413#define CPUID_EXT3_CMP_LEG (1 << 1)
ths0573fbf2007-09-23 15:28:04 +0000414#define CPUID_EXT3_SVM (1 << 2)
bellarda049de62007-11-08 13:28:47 +0000415#define CPUID_EXT3_EXTAPIC (1 << 3)
416#define CPUID_EXT3_CR8LEG (1 << 4)
417#define CPUID_EXT3_ABM (1 << 5)
418#define CPUID_EXT3_SSE4A (1 << 6)
419#define CPUID_EXT3_MISALIGNSSE (1 << 7)
420#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
421#define CPUID_EXT3_OSVW (1 << 9)
422#define CPUID_EXT3_IBS (1 << 10)
bellard872929a2008-05-28 16:16:54 +0000423#define CPUID_EXT3_SKINIT (1 << 12)
ths0573fbf2007-09-23 15:28:04 +0000424
Joerg Roedel296acb62010-09-27 15:16:17 +0200425#define CPUID_SVM_NPT (1 << 0)
426#define CPUID_SVM_LBRV (1 << 1)
427#define CPUID_SVM_SVMLOCK (1 << 2)
428#define CPUID_SVM_NRIPSAVE (1 << 3)
429#define CPUID_SVM_TSCSCALE (1 << 4)
430#define CPUID_SVM_VMCBCLEAN (1 << 5)
431#define CPUID_SVM_FLUSHASID (1 << 6)
432#define CPUID_SVM_DECODEASSIST (1 << 7)
433#define CPUID_SVM_PAUSEFILTER (1 << 10)
434#define CPUID_SVM_PFTHRESHOLD (1 << 12)
435
balrogc5096da2008-09-25 18:08:05 +0000436#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
437#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
438#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
439
440#define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
brillywu@viatech.com.cnb3baa152011-06-01 09:59:52 +0800441#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
balrogc5096da2008-09-25 18:08:05 +0000442#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
443
brillywu@viatech.com.cnb3baa152011-06-01 09:59:52 +0800444#define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */
445#define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */
446#define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */
447
balroge737b322008-09-25 18:11:30 +0000448#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
balroga876e282008-09-26 21:03:37 +0000449#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
balroge737b322008-09-25 18:11:30 +0000450
bellard2c0262a2003-09-30 20:34:21 +0000451#define EXCP00_DIVZ 0
aliguori01df0402008-11-18 21:08:15 +0000452#define EXCP01_DB 1
bellard2c0262a2003-09-30 20:34:21 +0000453#define EXCP02_NMI 2
454#define EXCP03_INT3 3
455#define EXCP04_INTO 4
456#define EXCP05_BOUND 5
457#define EXCP06_ILLOP 6
458#define EXCP07_PREX 7
459#define EXCP08_DBLE 8
460#define EXCP09_XERR 9
461#define EXCP0A_TSS 10
462#define EXCP0B_NOSEG 11
463#define EXCP0C_STACK 12
464#define EXCP0D_GPF 13
465#define EXCP0E_PAGE 14
466#define EXCP10_COPR 16
467#define EXCP11_ALGN 17
468#define EXCP12_MCHK 18
469
bellardd2fd1af2007-11-14 18:08:56 +0000470#define EXCP_SYSCALL 0x100 /* only happens in user only emulation
471 for syscall instruction */
472
Richard Henderson00a152b2011-05-04 13:34:30 -0700473/* i386-specific interrupt pending bits. */
474#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
Richard Henderson85097db2011-05-04 13:34:31 -0700475#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
Richard Henderson00a152b2011-05-04 13:34:30 -0700476#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
477#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
478#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
479#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
480
481
bellard2c0262a2003-09-30 20:34:21 +0000482enum {
483 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
ths1235fc02008-06-03 19:51:57 +0000484 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
bellardd36cd602003-12-02 22:01:31 +0000485
486 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
487 CC_OP_MULW,
488 CC_OP_MULL,
bellard14ce26e2005-01-03 23:50:08 +0000489 CC_OP_MULQ,
bellard2c0262a2003-09-30 20:34:21 +0000490
491 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
492 CC_OP_ADDW,
493 CC_OP_ADDL,
bellard14ce26e2005-01-03 23:50:08 +0000494 CC_OP_ADDQ,
bellard2c0262a2003-09-30 20:34:21 +0000495
496 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
497 CC_OP_ADCW,
498 CC_OP_ADCL,
bellard14ce26e2005-01-03 23:50:08 +0000499 CC_OP_ADCQ,
bellard2c0262a2003-09-30 20:34:21 +0000500
501 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
502 CC_OP_SUBW,
503 CC_OP_SUBL,
bellard14ce26e2005-01-03 23:50:08 +0000504 CC_OP_SUBQ,
bellard2c0262a2003-09-30 20:34:21 +0000505
506 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
507 CC_OP_SBBW,
508 CC_OP_SBBL,
bellard14ce26e2005-01-03 23:50:08 +0000509 CC_OP_SBBQ,
bellard2c0262a2003-09-30 20:34:21 +0000510
511 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
512 CC_OP_LOGICW,
513 CC_OP_LOGICL,
bellard14ce26e2005-01-03 23:50:08 +0000514 CC_OP_LOGICQ,
bellard2c0262a2003-09-30 20:34:21 +0000515
516 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
517 CC_OP_INCW,
518 CC_OP_INCL,
bellard14ce26e2005-01-03 23:50:08 +0000519 CC_OP_INCQ,
bellard2c0262a2003-09-30 20:34:21 +0000520
521 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
522 CC_OP_DECW,
523 CC_OP_DECL,
bellard14ce26e2005-01-03 23:50:08 +0000524 CC_OP_DECQ,
bellard2c0262a2003-09-30 20:34:21 +0000525
bellard6b652792004-07-12 20:33:47 +0000526 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
bellard2c0262a2003-09-30 20:34:21 +0000527 CC_OP_SHLW,
528 CC_OP_SHLL,
bellard14ce26e2005-01-03 23:50:08 +0000529 CC_OP_SHLQ,
bellard2c0262a2003-09-30 20:34:21 +0000530
531 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
532 CC_OP_SARW,
533 CC_OP_SARL,
bellard14ce26e2005-01-03 23:50:08 +0000534 CC_OP_SARQ,
bellard2c0262a2003-09-30 20:34:21 +0000535
536 CC_OP_NB,
537};
538
bellard2c0262a2003-09-30 20:34:21 +0000539typedef struct SegmentCache {
540 uint32_t selector;
bellard14ce26e2005-01-03 23:50:08 +0000541 target_ulong base;
bellard2c0262a2003-09-30 20:34:21 +0000542 uint32_t limit;
543 uint32_t flags;
544} SegmentCache;
545
bellard826461b2005-01-06 20:44:11 +0000546typedef union {
bellard664e0f12005-01-08 18:58:29 +0000547 uint8_t _b[16];
548 uint16_t _w[8];
549 uint32_t _l[4];
550 uint64_t _q[2];
bellard7a0e1f42005-03-13 17:01:47 +0000551 float32 _s[4];
552 float64 _d[2];
bellard14ce26e2005-01-03 23:50:08 +0000553} XMMReg;
554
bellard826461b2005-01-06 20:44:11 +0000555typedef union {
556 uint8_t _b[8];
aurel32a35f3ec2008-04-08 19:51:29 +0000557 uint16_t _w[4];
558 uint32_t _l[2];
559 float32 _s[2];
bellard826461b2005-01-06 20:44:11 +0000560 uint64_t q;
561} MMXReg;
562
Juan Quintelae2542fe2009-07-27 16:13:06 +0200563#ifdef HOST_WORDS_BIGENDIAN
bellard826461b2005-01-06 20:44:11 +0000564#define XMM_B(n) _b[15 - (n)]
565#define XMM_W(n) _w[7 - (n)]
566#define XMM_L(n) _l[3 - (n)]
bellard664e0f12005-01-08 18:58:29 +0000567#define XMM_S(n) _s[3 - (n)]
bellard826461b2005-01-06 20:44:11 +0000568#define XMM_Q(n) _q[1 - (n)]
bellard664e0f12005-01-08 18:58:29 +0000569#define XMM_D(n) _d[1 - (n)]
bellard826461b2005-01-06 20:44:11 +0000570
571#define MMX_B(n) _b[7 - (n)]
572#define MMX_W(n) _w[3 - (n)]
573#define MMX_L(n) _l[1 - (n)]
aurel32a35f3ec2008-04-08 19:51:29 +0000574#define MMX_S(n) _s[1 - (n)]
bellard826461b2005-01-06 20:44:11 +0000575#else
576#define XMM_B(n) _b[n]
577#define XMM_W(n) _w[n]
578#define XMM_L(n) _l[n]
bellard664e0f12005-01-08 18:58:29 +0000579#define XMM_S(n) _s[n]
bellard826461b2005-01-06 20:44:11 +0000580#define XMM_Q(n) _q[n]
bellard664e0f12005-01-08 18:58:29 +0000581#define XMM_D(n) _d[n]
bellard826461b2005-01-06 20:44:11 +0000582
583#define MMX_B(n) _b[n]
584#define MMX_W(n) _w[n]
585#define MMX_L(n) _l[n]
aurel32a35f3ec2008-04-08 19:51:29 +0000586#define MMX_S(n) _s[n]
bellard826461b2005-01-06 20:44:11 +0000587#endif
bellard664e0f12005-01-08 18:58:29 +0000588#define MMX_Q(n) q
bellard826461b2005-01-06 20:44:11 +0000589
Juan Quintelaacc68832009-09-29 22:48:58 +0200590typedef union {
Aurelien Jarnoc31da132011-05-15 14:09:18 +0200591 floatx80 d __attribute__((aligned(16)));
Juan Quintelaacc68832009-09-29 22:48:58 +0200592 MMXReg mmx;
593} FPReg;
594
Juan Quintelac1a54d52009-09-29 22:48:59 +0200595typedef struct {
596 uint64_t base;
597 uint64_t mask;
598} MTRRVar;
599
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200600#define CPU_NB_REGS64 16
601#define CPU_NB_REGS32 8
602
bellard14ce26e2005-01-03 23:50:08 +0000603#ifdef TARGET_X86_64
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200604#define CPU_NB_REGS CPU_NB_REGS64
bellard14ce26e2005-01-03 23:50:08 +0000605#else
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200606#define CPU_NB_REGS CPU_NB_REGS32
bellard14ce26e2005-01-03 23:50:08 +0000607#endif
608
j_mayer6ebbf392007-10-14 07:07:08 +0000609#define NB_MMU_MODES 2
610
bellard2c0262a2003-09-30 20:34:21 +0000611typedef struct CPUX86State {
612 /* standard registers */
bellard14ce26e2005-01-03 23:50:08 +0000613 target_ulong regs[CPU_NB_REGS];
614 target_ulong eip;
615 target_ulong eflags; /* eflags register. During CPU emulation, CC
bellard2c0262a2003-09-30 20:34:21 +0000616 flags and DF are set to zero because they are
617 stored elsewhere */
618
619 /* emulator internal eflags handling */
bellard14ce26e2005-01-03 23:50:08 +0000620 target_ulong cc_src;
621 target_ulong cc_dst;
bellard2c0262a2003-09-30 20:34:21 +0000622 uint32_t cc_op;
623 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
bellarddb620f42008-06-04 17:02:19 +0000624 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
625 are known at translation time. */
626 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
bellard2c0262a2003-09-30 20:34:21 +0000627
bellard9df217a2005-02-10 22:05:51 +0000628 /* segments */
629 SegmentCache segs[6]; /* selector values */
630 SegmentCache ldt;
631 SegmentCache tr;
632 SegmentCache gdt; /* only base and limit are used */
633 SegmentCache idt; /* only base and limit are used */
634
bellarddb620f42008-06-04 17:02:19 +0000635 target_ulong cr[5]; /* NOTE: cr1 is unused */
Juan Quintela5ee0ffa2009-09-29 22:48:49 +0200636 int32_t a20_mask;
bellard9df217a2005-02-10 22:05:51 +0000637
bellard2c0262a2003-09-30 20:34:21 +0000638 /* FPU state */
639 unsigned int fpstt; /* top of stack index */
Juan Quintela67b8f412009-09-29 22:48:51 +0200640 uint16_t fpus;
Juan Quintelaeb831622009-09-29 22:48:50 +0200641 uint16_t fpuc;
bellard2c0262a2003-09-30 20:34:21 +0000642 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
Juan Quintelaacc68832009-09-29 22:48:58 +0200643 FPReg fpregs[8];
Jan Kiszka42cc8fa2011-06-15 15:17:26 +0200644 /* KVM-only so far */
645 uint16_t fpop;
646 uint64_t fpip;
647 uint64_t fpdp;
bellard2c0262a2003-09-30 20:34:21 +0000648
649 /* emulator internal variables */
bellard7a0e1f42005-03-13 17:01:47 +0000650 float_status fp_status;
Aurelien Jarnoc31da132011-05-15 14:09:18 +0200651 floatx80 ft0;
ths3b46e622007-09-17 08:09:54 +0000652
aurel32a35f3ec2008-04-08 19:51:29 +0000653 float_status mmx_status; /* for 3DNow! float ops */
bellard7a0e1f42005-03-13 17:01:47 +0000654 float_status sse_status;
bellard664e0f12005-01-08 18:58:29 +0000655 uint32_t mxcsr;
bellard14ce26e2005-01-03 23:50:08 +0000656 XMMReg xmm_regs[CPU_NB_REGS];
657 XMMReg xmm_t0;
bellard664e0f12005-01-08 18:58:29 +0000658 MMXReg mmx_t0;
bellard1e4840b2008-05-25 17:26:41 +0000659 target_ulong cc_tmp; /* temporary for rcr/rcl */
bellard14ce26e2005-01-03 23:50:08 +0000660
bellard2c0262a2003-09-30 20:34:21 +0000661 /* sysenter registers */
662 uint32_t sysenter_cs;
balrog2436b612008-09-25 18:16:18 +0000663 target_ulong sysenter_esp;
664 target_ulong sysenter_eip;
bellard8d9bfc22005-04-23 17:46:55 +0000665 uint64_t efer;
666 uint64_t star;
ths0573fbf2007-09-23 15:28:04 +0000667
bellard5cc1d1e2008-06-04 18:29:25 +0000668 uint64_t vm_hsave;
669 uint64_t vm_vmcb;
bellard33c263d2008-06-04 17:39:33 +0000670 uint64_t tsc_offset;
ths0573fbf2007-09-23 15:28:04 +0000671 uint64_t intercept;
672 uint16_t intercept_cr_read;
673 uint16_t intercept_cr_write;
674 uint16_t intercept_dr_read;
675 uint16_t intercept_dr_write;
676 uint32_t intercept_exceptions;
bellarddb620f42008-06-04 17:02:19 +0000677 uint8_t v_tpr;
ths0573fbf2007-09-23 15:28:04 +0000678
bellard14ce26e2005-01-03 23:50:08 +0000679#ifdef TARGET_X86_64
bellard14ce26e2005-01-03 23:50:08 +0000680 target_ulong lstar;
681 target_ulong cstar;
682 target_ulong fmask;
683 target_ulong kernelgsbase;
684#endif
Glauber Costa1a036752009-10-22 10:26:56 -0200685 uint64_t system_time_msr;
686 uint64_t wall_clock_msr;
Gleb Natapovf6584ee2010-10-24 14:27:55 +0200687 uint64_t async_pf_en_msr;
bellard58fe2f12004-02-16 22:11:32 +0000688
aliguori7ba1e612008-11-05 16:04:33 +0000689 uint64_t tsc;
690
Jan Kiszka18559232011-03-02 08:56:07 +0100691 uint64_t mcg_status;
692
bellard2c0262a2003-09-30 20:34:21 +0000693 /* exception/interrupt handling */
bellard2c0262a2003-09-30 20:34:21 +0000694 int error_code;
695 int exception_is_int;
bellard826461b2005-01-06 20:44:11 +0000696 target_ulong exception_next_eip;
bellard14ce26e2005-01-03 23:50:08 +0000697 target_ulong dr[8]; /* debug registers */
aliguori01df0402008-11-18 21:08:15 +0000698 union {
699 CPUBreakpoint *cpu_breakpoint[4];
700 CPUWatchpoint *cpu_watchpoint[4];
701 }; /* break/watchpoints for dr[0..3] */
bellard3b21e032006-09-24 18:41:56 +0000702 uint32_t smbase;
ths678dde12007-03-31 20:28:52 +0000703 int old_exception; /* exception in flight */
bellard2c0262a2003-09-30 20:34:21 +0000704
Jan Kiszkad8f771d2011-01-21 21:48:21 +0100705 /* KVM states, automatically cleared on reset */
706 uint8_t nmi_injected;
707 uint8_t nmi_pending;
708
bellarda316d332005-11-20 10:32:34 +0000709 CPU_COMMON
bellard2c0262a2003-09-30 20:34:21 +0000710
Jan Kiszkaebda3772011-03-15 12:26:21 +0100711 uint64_t pat;
712
bellard14ce26e2005-01-03 23:50:08 +0000713 /* processor features (e.g. for CPUID insn) */
bellard8d9bfc22005-04-23 17:46:55 +0000714 uint32_t cpuid_level;
bellard14ce26e2005-01-03 23:50:08 +0000715 uint32_t cpuid_vendor1;
716 uint32_t cpuid_vendor2;
717 uint32_t cpuid_vendor3;
718 uint32_t cpuid_version;
719 uint32_t cpuid_features;
bellard9df217a2005-02-10 22:05:51 +0000720 uint32_t cpuid_ext_features;
bellard8d9bfc22005-04-23 17:46:55 +0000721 uint32_t cpuid_xlevel;
722 uint32_t cpuid_model[12];
723 uint32_t cpuid_ext2_features;
ths0573fbf2007-09-23 15:28:04 +0000724 uint32_t cpuid_ext3_features;
thseae76292007-04-03 16:38:34 +0000725 uint32_t cpuid_apic_id;
Andre Przywaraef768132009-06-06 01:03:29 +0200726 int cpuid_vendor_override;
brillywu@viatech.com.cnb3baa152011-06-01 09:59:52 +0800727 /* Store the results of Centaur's CPUID instructions */
728 uint32_t cpuid_xlevel2;
729 uint32_t cpuid_ext4_features;
ths3b46e622007-09-17 08:09:54 +0000730
aliguori165d9b82009-01-26 17:53:04 +0000731 /* MTRRs */
732 uint64_t mtrr_fixed[11];
733 uint64_t mtrr_deftype;
Juan Quintelac1a54d52009-09-29 22:48:59 +0200734 MTRRVar mtrr_var[8];
aliguori165d9b82009-01-26 17:53:04 +0000735
aliguori7ba1e612008-11-05 16:04:33 +0000736 /* For KVM */
Jan Kiszkaf8d926e2009-05-02 02:18:38 +0200737 uint32_t mp_state;
Jan Kiszka31827372009-12-14 12:26:17 +0100738 int32_t exception_injected;
Jan Kiszka0e607a82009-11-06 19:39:24 +0100739 int32_t interrupt_injected;
Jan Kiszkaa0fb0022009-11-25 00:33:03 +0100740 uint8_t soft_interrupt;
Jan Kiszkaa0fb0022009-11-25 00:33:03 +0100741 uint8_t has_error_code;
742 uint32_t sipi_vector;
Gleb Natapovbb0300d2010-01-13 15:25:06 +0200743 uint32_t cpuid_kvm_features;
Joerg Roedel296acb62010-09-27 15:16:17 +0200744 uint32_t cpuid_svm_features;
Glauber Costab8cc45d2011-02-03 14:19:53 -0500745 bool tsc_valid;
Gleb Natapovbb0300d2010-01-13 15:25:06 +0200746
bellard14ce26e2005-01-03 23:50:08 +0000747 /* in order to simplify APIC support, we leave this pointer to the
748 user */
Blue Swirl92a16d72010-06-19 07:47:42 +0000749 struct DeviceState *apic_state;
Huang Ying79c4f6b2009-06-23 10:05:14 +0800750
Andreas Färberac6c4122010-12-19 17:22:41 +0100751 uint64_t mcg_cap;
Andreas Färberac6c4122010-12-19 17:22:41 +0100752 uint64_t mcg_ctl;
753 uint64_t mce_banks[MCE_BANKS_DEF*4];
Andre Przywara1b050072009-09-19 00:30:49 +0200754
755 uint64_t tsc_aux;
Aurelien Jarno5a2d0e52009-10-05 22:41:04 +0200756
757 /* vmstate */
758 uint16_t fpus_vmstate;
759 uint16_t fptag_vmstate;
760 uint16_t fpregs_format_vmstate;
Sheng Yangf1665b22010-06-17 17:53:07 +0800761
762 uint64_t xstate_bv;
763 XMMReg ymmh_regs[CPU_NB_REGS];
764
765 uint64_t xcr0;
bellard2c0262a2003-09-30 20:34:21 +0000766} CPUX86State;
767
bellardaaed9092007-11-10 15:15:54 +0000768CPUX86State *cpu_x86_init(const char *cpu_model);
bellard2c0262a2003-09-30 20:34:21 +0000769int cpu_x86_exec(CPUX86State *s);
770void cpu_x86_close(CPUX86State *s);
Stefan Weil9a78eea2010-10-22 23:03:33 +0200771void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg);
john cooperb5ec5ce2010-02-20 11:14:59 -0600772void x86_cpudef_setup(void);
Jin Dongming2bd3e042010-12-10 17:21:14 +0900773int cpu_x86_support_mca_broadcast(CPUState *env);
john cooperb5ec5ce2010-02-20 11:14:59 -0600774
bellardd720b932004-04-25 17:57:43 +0000775int cpu_get_pic_interrupt(CPUX86State *s);
bellard2ee73ac2004-05-08 21:08:41 +0000776/* MSDOS compatibility mode FPU exception support */
777void cpu_set_ferr(CPUX86State *s);
bellard2c0262a2003-09-30 20:34:21 +0000778
779/* this function must always be used to load data in the segment
780 cache: it synchronizes the hflags with the segment cache values */
ths5fafdf22007-09-16 21:08:06 +0000781static inline void cpu_x86_load_seg_cache(CPUX86State *env,
bellard2c0262a2003-09-30 20:34:21 +0000782 int seg_reg, unsigned int selector,
bellard8988ae82006-09-27 19:54:02 +0000783 target_ulong base,
ths5fafdf22007-09-16 21:08:06 +0000784 unsigned int limit,
bellard2c0262a2003-09-30 20:34:21 +0000785 unsigned int flags)
786{
787 SegmentCache *sc;
788 unsigned int new_hflags;
ths3b46e622007-09-17 08:09:54 +0000789
bellard2c0262a2003-09-30 20:34:21 +0000790 sc = &env->segs[seg_reg];
791 sc->selector = selector;
792 sc->base = base;
793 sc->limit = limit;
794 sc->flags = flags;
795
796 /* update the hidden flags */
bellard14ce26e2005-01-03 23:50:08 +0000797 {
798 if (seg_reg == R_CS) {
799#ifdef TARGET_X86_64
800 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
801 /* long mode */
802 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
803 env->hflags &= ~(HF_ADDSEG_MASK);
ths5fafdf22007-09-16 21:08:06 +0000804 } else
bellard14ce26e2005-01-03 23:50:08 +0000805#endif
806 {
807 /* legacy / compatibility case */
808 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
809 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
810 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
811 new_hflags;
812 }
813 }
814 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
815 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
816 if (env->hflags & HF_CS64_MASK) {
817 /* zero base assumed for DS, ES and SS in long mode */
ths5fafdf22007-09-16 21:08:06 +0000818 } else if (!(env->cr[0] & CR0_PE_MASK) ||
bellard735a8fd2005-01-12 22:36:43 +0000819 (env->eflags & VM_MASK) ||
820 !(env->hflags & HF_CS32_MASK)) {
bellard14ce26e2005-01-03 23:50:08 +0000821 /* XXX: try to avoid this test. The problem comes from the
822 fact that is real mode or vm86 mode we only modify the
823 'base' and 'selector' fields of the segment cache to go
824 faster. A solution may be to force addseg to one in
825 translate-i386.c. */
826 new_hflags |= HF_ADDSEG_MASK;
827 } else {
ths5fafdf22007-09-16 21:08:06 +0000828 new_hflags |= ((env->segs[R_DS].base |
bellard735a8fd2005-01-12 22:36:43 +0000829 env->segs[R_ES].base |
ths5fafdf22007-09-16 21:08:06 +0000830 env->segs[R_SS].base) != 0) <<
bellard14ce26e2005-01-03 23:50:08 +0000831 HF_ADDSEG_SHIFT;
832 }
ths5fafdf22007-09-16 21:08:06 +0000833 env->hflags = (env->hflags &
bellard14ce26e2005-01-03 23:50:08 +0000834 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
bellard2c0262a2003-09-30 20:34:21 +0000835 }
bellard2c0262a2003-09-30 20:34:21 +0000836}
837
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300838static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
839 int sipi_vector)
840{
841 env->eip = 0;
842 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
843 sipi_vector << 12,
844 env->segs[R_CS].limit,
845 env->segs[R_CS].flags);
846 env->halted = 0;
847}
848
Jan Kiszka84273172009-06-27 09:53:51 +0200849int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
850 target_ulong *base, unsigned int *limit,
851 unsigned int *flags);
852
bellard2c0262a2003-09-30 20:34:21 +0000853/* wrapper, just in case memory mappings must be changed */
854static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
855{
856#if HF_CPL_MASK == 3
857 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
858#else
859#error HF_CPL_MASK is hardcoded
860#endif
861}
862
blueswir1d9957a82008-12-13 11:49:17 +0000863/* op_helper.c */
bellard1f1af9f2004-03-31 18:56:43 +0000864/* used for debug or cpu save/restore */
Aurelien Jarnoc31da132011-05-15 14:09:18 +0200865void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
866floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
bellard1f1af9f2004-03-31 18:56:43 +0000867
blueswir1d9957a82008-12-13 11:49:17 +0000868/* cpu-exec.c */
bellard2c0262a2003-09-30 20:34:21 +0000869/* the following helpers are only usable in user mode simulation as
870 they can trigger unexpected exceptions */
871void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
bellard6f12a2a2007-11-11 22:16:56 +0000872void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
873void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
bellard2c0262a2003-09-30 20:34:21 +0000874
875/* you can call this signal handler from your SIGBUS and SIGSEGV
876 signal handlers to inform the virtual CPU of exceptions. non zero
877 is returned if the signal was handled by the virtual CPU. */
ths5fafdf22007-09-16 21:08:06 +0000878int cpu_x86_signal_handler(int host_signum, void *pinfo,
bellard2c0262a2003-09-30 20:34:21 +0000879 void *puc);
blueswir1d9957a82008-12-13 11:49:17 +0000880
Andre Przywarac6dc6f62010-03-11 14:38:55 +0100881/* cpuid.c */
882void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
883 uint32_t *eax, uint32_t *ebx,
884 uint32_t *ecx, uint32_t *edx);
885int cpu_x86_register (CPUX86State *env, const char *cpu_model);
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300886void cpu_clear_apic_feature(CPUX86State *env);
Jan Kiszkabb44e0d2011-01-21 21:48:07 +0100887void host_cpuid(uint32_t function, uint32_t count,
888 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
Andre Przywarac6dc6f62010-03-11 14:38:55 +0100889
blueswir1d9957a82008-12-13 11:49:17 +0000890/* helper.c */
891int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
892 int is_write, int mmu_idx, int is_softmmu);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700893#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
bellard461c0472003-11-04 23:34:23 +0000894void cpu_x86_set_a20(CPUX86State *env, int a20_state);
bellard2c0262a2003-09-30 20:34:21 +0000895
blueswir1d9957a82008-12-13 11:49:17 +0000896static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
897{
898 return (dr7 >> (index * 2)) & 3;
899}
bellard28ab0e22004-05-20 14:02:14 +0000900
blueswir1d9957a82008-12-13 11:49:17 +0000901static inline int hw_breakpoint_type(unsigned long dr7, int index)
902{
Jan Kiszkad46272c2009-12-14 12:26:27 +0100903 return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
blueswir1d9957a82008-12-13 11:49:17 +0000904}
905
906static inline int hw_breakpoint_len(unsigned long dr7, int index)
907{
Jan Kiszkad46272c2009-12-14 12:26:27 +0100908 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
blueswir1d9957a82008-12-13 11:49:17 +0000909 return (len == 2) ? 8 : len + 1;
910}
911
912void hw_breakpoint_insert(CPUX86State *env, int index);
913void hw_breakpoint_remove(CPUX86State *env, int index);
914int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
915
916/* will be suppressed */
917void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
918void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
919void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
920
blueswir1d9957a82008-12-13 11:49:17 +0000921/* hw/pc.c */
bellard3b21e032006-09-24 18:41:56 +0000922void cpu_smm_update(CPUX86State *env);
blueswir1d9957a82008-12-13 11:49:17 +0000923uint64_t cpu_get_tsc(CPUX86State *env);
aliguori6fd805e2008-11-05 15:34:06 +0000924
bellard2c0262a2003-09-30 20:34:21 +0000925/* used to debug */
926#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
927#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
bellard2c0262a2003-09-30 20:34:21 +0000928
bellard2c0262a2003-09-30 20:34:21 +0000929#define TARGET_PAGE_BITS 12
ths9467d442007-06-03 21:02:38 +0000930
Richard Henderson52705892010-03-10 14:33:23 -0800931#ifdef TARGET_X86_64
932#define TARGET_PHYS_ADDR_SPACE_BITS 52
933/* ??? This is really 48 bits, sign-extended, but the only thing
934 accessible to userland with bit 48 set is the VSYSCALL, and that
935 is handled via other mechanisms. */
936#define TARGET_VIRT_ADDR_SPACE_BITS 47
937#else
938#define TARGET_PHYS_ADDR_SPACE_BITS 36
939#define TARGET_VIRT_ADDR_SPACE_BITS 32
940#endif
941
ths9467d442007-06-03 21:02:38 +0000942#define cpu_init cpu_x86_init
943#define cpu_exec cpu_x86_exec
944#define cpu_gen_code cpu_x86_gen_code
945#define cpu_signal_handler cpu_x86_signal_handler
john cooperb5ec5ce2010-02-20 11:14:59 -0600946#define cpu_list_id x86_cpu_list
947#define cpudef_setup x86_cpudef_setup
ths9467d442007-06-03 21:02:38 +0000948
Sheng Yangf1665b22010-06-17 17:53:07 +0800949#define CPU_SAVE_VERSION 12
pbrookb3c77242008-06-30 16:31:04 +0000950
j_mayer6ebbf392007-10-14 07:07:08 +0000951/* MMU modes definitions */
952#define MMU_MODE0_SUFFIX _kernel
953#define MMU_MODE1_SUFFIX _user
954#define MMU_USER_IDX 1
955static inline int cpu_mmu_index (CPUState *env)
956{
957 return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
958}
959
Blue Swirlf081c762011-05-21 07:10:23 +0000960#undef EAX
961#define EAX (env->regs[R_EAX])
962#undef ECX
963#define ECX (env->regs[R_ECX])
964#undef EDX
965#define EDX (env->regs[R_EDX])
966#undef EBX
967#define EBX (env->regs[R_EBX])
968#undef ESP
969#define ESP (env->regs[R_ESP])
970#undef EBP
971#define EBP (env->regs[R_EBP])
972#undef ESI
973#define ESI (env->regs[R_ESI])
974#undef EDI
975#define EDI (env->regs[R_EDI])
976#undef EIP
977#define EIP (env->eip)
978#define DF (env->df)
979
980#define CC_SRC (env->cc_src)
981#define CC_DST (env->cc_dst)
982#define CC_OP (env->cc_op)
983
984/* float macros */
985#define FT0 (env->ft0)
986#define ST0 (env->fpregs[env->fpstt].d)
987#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
988#define ST1 ST(1)
989
blueswir1d9957a82008-12-13 11:49:17 +0000990/* translate.c */
bellard26a5f132008-05-28 12:30:31 +0000991void optimize_flags_init(void);
992
bellardb6abf972008-05-17 12:44:31 +0000993typedef struct CCTable {
994 int (*compute_all)(void); /* return all the flags */
995 int (*compute_c)(void); /* return the C flag */
996} CCTable;
997
pbrook6e68e072008-05-30 17:22:15 +0000998#if defined(CONFIG_USER_ONLY)
999static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
1000{
pbrookf8ed7072008-05-30 17:54:15 +00001001 if (newsp)
pbrook6e68e072008-05-30 17:22:15 +00001002 env->regs[R_ESP] = newsp;
1003 env->regs[R_EAX] = 0;
1004}
1005#endif
1006
bellard2c0262a2003-09-30 20:34:21 +00001007#include "cpu-all.h"
ths0573fbf2007-09-23 15:28:04 +00001008#include "svm.h"
1009
Blue Swirl0e26b7b2010-06-19 10:42:34 +03001010#if !defined(CONFIG_USER_ONLY)
1011#include "hw/apic.h"
1012#endif
1013
Blue Swirlf081c762011-05-21 07:10:23 +00001014static inline bool cpu_has_work(CPUState *env)
1015{
1016 return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1017 (env->eflags & IF_MASK)) ||
1018 (env->interrupt_request & (CPU_INTERRUPT_NMI |
1019 CPU_INTERRUPT_INIT |
1020 CPU_INTERRUPT_SIPI |
1021 CPU_INTERRUPT_MCE));
1022}
1023
1024#include "exec-all.h"
1025
1026static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
1027{
1028 env->eip = tb->pc - tb->cs_base;
1029}
1030
aliguori6b917542008-11-18 19:46:41 +00001031static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1032 target_ulong *cs_base, int *flags)
1033{
1034 *cs_base = env->segs[R_CS].base;
1035 *pc = *cs_base + env->eip;
Jan Kiszkaa2397802009-05-10 22:30:53 +02001036 *flags = env->hflags |
1037 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
aliguori6b917542008-11-18 19:46:41 +00001038}
1039
Gleb Natapovb09ea7d2009-06-17 23:26:59 +03001040void do_cpu_init(CPUState *env);
1041void do_cpu_sipi(CPUState *env);
Jan Kiszka2fa11da2011-03-02 08:56:08 +01001042
Jan Kiszka747461c2011-03-02 08:56:10 +01001043#define MCE_INJECT_BROADCAST 1
1044#define MCE_INJECT_UNCOND_AO 2
1045
Jan Kiszka316378e2011-03-02 08:56:09 +01001046void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
1047 uint64_t status, uint64_t mcg_status, uint64_t addr,
Jan Kiszka747461c2011-03-02 08:56:10 +01001048 uint64_t misc, int flags);
Jan Kiszka2fa11da2011-03-02 08:56:08 +01001049
Blue Swirle694d4e2011-05-16 19:38:48 +00001050/* op_helper.c */
1051void do_interrupt(CPUState *env);
1052void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw);
1053
1054void do_smm_enter(CPUState *env1);
1055
1056void svm_check_intercept(CPUState *env1, uint32_t type);
1057
1058uint32_t cpu_cc_compute_all(CPUState *env1, int op);
1059
bellard2c0262a2003-09-30 20:34:21 +00001060#endif /* CPU_I386_H */