aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * DMA helper functions |
| 3 | * |
Philippe Mathieu-Daudé | 9c211ad | 2020-10-23 17:19:16 +0200 | [diff] [blame] | 4 | * Copyright (c) 2009, 2020 Red Hat |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 5 | * |
| 6 | * This work is licensed under the terms of the GNU General Public License |
| 7 | * (GNU GPL), version 2 or later. |
| 8 | */ |
| 9 | |
| 10 | #ifndef DMA_H |
| 11 | #define DMA_H |
| 12 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 13 | #include "exec/memory.h" |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 14 | #include "exec/address-spaces.h" |
Paolo Bonzini | 737e150 | 2012-12-17 18:19:44 +0100 | [diff] [blame] | 15 | #include "block/block.h" |
Benoît Canet | 5e5a94b | 2014-09-05 15:46:16 +0200 | [diff] [blame] | 16 | #include "block/accounting.h" |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 17 | |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 18 | typedef struct ScatterGatherEntry ScatterGatherEntry; |
| 19 | |
David Gibson | 43cf8ae | 2012-03-27 13:42:23 +1100 | [diff] [blame] | 20 | typedef enum { |
| 21 | DMA_DIRECTION_TO_DEVICE = 0, |
| 22 | DMA_DIRECTION_FROM_DEVICE = 1, |
| 23 | } DMADirection; |
| 24 | |
Paolo Bonzini | fead0c2 | 2011-11-09 16:58:30 +0100 | [diff] [blame] | 25 | struct QEMUSGList { |
| 26 | ScatterGatherEntry *sg; |
| 27 | int nsg; |
| 28 | int nalloc; |
| 29 | size_t size; |
Paolo Bonzini | f487b67 | 2013-06-03 14:17:19 +0200 | [diff] [blame] | 30 | DeviceState *dev; |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 31 | AddressSpace *as; |
Paolo Bonzini | fead0c2 | 2011-11-09 16:58:30 +0100 | [diff] [blame] | 32 | }; |
| 33 | |
Avi Kivity | 4be403c | 2012-10-04 12:36:04 +0200 | [diff] [blame] | 34 | #ifndef CONFIG_USER_ONLY |
David Gibson | d9d1055 | 2011-10-31 17:06:45 +1100 | [diff] [blame] | 35 | |
David Gibson | e5332e6 | 2012-06-27 14:50:43 +1000 | [diff] [blame] | 36 | /* |
| 37 | * When an IOMMU is present, bus addresses become distinct from |
| 38 | * CPU/memory physical addresses and may be a different size. Because |
| 39 | * the IOVA size depends more on the bus than on the platform, we more |
| 40 | * or less have to treat these as 64-bit always to cover all (or at |
| 41 | * least most) cases. |
| 42 | */ |
| 43 | typedef uint64_t dma_addr_t; |
| 44 | |
| 45 | #define DMA_ADDR_BITS 64 |
| 46 | #define DMA_ADDR_FMT "%" PRIx64 |
| 47 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 48 | static inline void dma_barrier(AddressSpace *as, DMADirection dir) |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 49 | { |
| 50 | /* |
| 51 | * This is called before DMA read and write operations |
| 52 | * unless the _relaxed form is used and is responsible |
| 53 | * for providing some sane ordering of accesses vs |
| 54 | * concurrently running VCPUs. |
| 55 | * |
| 56 | * Users of map(), unmap() or lower level st/ld_* |
| 57 | * operations are responsible for providing their own |
| 58 | * ordering via barriers. |
| 59 | * |
| 60 | * This primitive implementation does a simple smp_mb() |
| 61 | * before each operation which provides pretty much full |
| 62 | * ordering. |
| 63 | * |
| 64 | * A smarter implementation can be devised if needed to |
| 65 | * use lighter barriers based on the direction of the |
| 66 | * transfer, the DMA context, etc... |
| 67 | */ |
Paolo Bonzini | 77ac58d | 2014-09-17 12:21:29 +0200 | [diff] [blame] | 68 | smp_mb(); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 69 | } |
| 70 | |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 71 | /* Checks that the given range of addresses is valid for DMA. This is |
| 72 | * useful for certain cases, but usually you should just use |
| 73 | * dma_memory_{read,write}() and check for errors */ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 74 | static inline bool dma_memory_valid(AddressSpace *as, |
David Gibson | e5332e6 | 2012-06-27 14:50:43 +1000 | [diff] [blame] | 75 | dma_addr_t addr, dma_addr_t len, |
Philippe Mathieu-Daudé | 7ccb391 | 2020-09-03 09:28:49 +0200 | [diff] [blame] | 76 | DMADirection dir, MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 77 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 78 | return address_space_access_valid(as, addr, len, |
Peter Maydell | fddffa4 | 2018-05-31 14:50:52 +0100 | [diff] [blame] | 79 | dir == DMA_DIRECTION_FROM_DEVICE, |
Philippe Mathieu-Daudé | 7ccb391 | 2020-09-03 09:28:49 +0200 | [diff] [blame] | 80 | attrs); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 81 | } |
| 82 | |
Philippe Mathieu-Daudé | 9989bcd | 2020-10-23 17:19:18 +0200 | [diff] [blame] | 83 | static inline MemTxResult dma_memory_rw_relaxed(AddressSpace *as, |
| 84 | dma_addr_t addr, |
| 85 | void *buf, dma_addr_t len, |
Philippe Mathieu-Daudé | 4afd0f2 | 2020-09-03 09:30:10 +0200 | [diff] [blame] | 86 | DMADirection dir, |
| 87 | MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 88 | { |
Philippe Mathieu-Daudé | 4afd0f2 | 2020-09-03 09:30:10 +0200 | [diff] [blame] | 89 | return address_space_rw(as, addr, attrs, |
Philippe Mathieu-Daudé | 9989bcd | 2020-10-23 17:19:18 +0200 | [diff] [blame] | 90 | buf, len, dir == DMA_DIRECTION_FROM_DEVICE); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 91 | } |
| 92 | |
Philippe Mathieu-Daudé | b1f5130 | 2020-10-23 17:19:19 +0200 | [diff] [blame] | 93 | static inline MemTxResult dma_memory_read_relaxed(AddressSpace *as, |
| 94 | dma_addr_t addr, |
| 95 | void *buf, dma_addr_t len) |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 96 | { |
Philippe Mathieu-Daudé | 4afd0f2 | 2020-09-03 09:30:10 +0200 | [diff] [blame] | 97 | return dma_memory_rw_relaxed(as, addr, buf, len, |
| 98 | DMA_DIRECTION_TO_DEVICE, |
| 99 | MEMTXATTRS_UNSPECIFIED); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 100 | } |
| 101 | |
Philippe Mathieu-Daudé | 77c71d1 | 2020-10-23 17:19:20 +0200 | [diff] [blame] | 102 | static inline MemTxResult dma_memory_write_relaxed(AddressSpace *as, |
| 103 | dma_addr_t addr, |
| 104 | const void *buf, |
| 105 | dma_addr_t len) |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 106 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 107 | return dma_memory_rw_relaxed(as, addr, (void *)buf, len, |
Philippe Mathieu-Daudé | 4afd0f2 | 2020-09-03 09:30:10 +0200 | [diff] [blame] | 108 | DMA_DIRECTION_FROM_DEVICE, |
| 109 | MEMTXATTRS_UNSPECIFIED); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 110 | } |
| 111 | |
Philippe Mathieu-Daudé | 9989bcd | 2020-10-23 17:19:18 +0200 | [diff] [blame] | 112 | /** |
| 113 | * dma_memory_rw: Read from or write to an address space from DMA controller. |
| 114 | * |
| 115 | * Return a MemTxResult indicating whether the operation succeeded |
| 116 | * or failed (eg unassigned memory, device rejected the transaction, |
| 117 | * IOMMU fault). |
| 118 | * |
| 119 | * @as: #AddressSpace to be accessed |
| 120 | * @addr: address within that address space |
| 121 | * @buf: buffer with the data transferred |
| 122 | * @len: the number of bytes to read or write |
| 123 | * @dir: indicates the transfer direction |
Philippe Mathieu-Daudé | 23faf56 | 2020-09-03 09:37:43 +0200 | [diff] [blame] | 124 | * @attrs: memory transaction attributes |
Philippe Mathieu-Daudé | 9989bcd | 2020-10-23 17:19:18 +0200 | [diff] [blame] | 125 | */ |
| 126 | static inline MemTxResult dma_memory_rw(AddressSpace *as, dma_addr_t addr, |
| 127 | void *buf, dma_addr_t len, |
Philippe Mathieu-Daudé | 23faf56 | 2020-09-03 09:37:43 +0200 | [diff] [blame] | 128 | DMADirection dir, MemTxAttrs attrs) |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 129 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 130 | dma_barrier(as, dir); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 131 | |
Philippe Mathieu-Daudé | 23faf56 | 2020-09-03 09:37:43 +0200 | [diff] [blame] | 132 | return dma_memory_rw_relaxed(as, addr, buf, len, dir, attrs); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 133 | } |
| 134 | |
Philippe Mathieu-Daudé | b1f5130 | 2020-10-23 17:19:19 +0200 | [diff] [blame] | 135 | /** |
| 136 | * dma_memory_read: Read from an address space from DMA controller. |
| 137 | * |
| 138 | * Return a MemTxResult indicating whether the operation succeeded |
| 139 | * or failed (eg unassigned memory, device rejected the transaction, |
| 140 | * IOMMU fault). Called within RCU critical section. |
| 141 | * |
| 142 | * @as: #AddressSpace to be accessed |
| 143 | * @addr: address within that address space |
| 144 | * @buf: buffer with the data transferred |
| 145 | * @len: length of the data transferred |
Philippe Mathieu-Daudé | ba06fe8 | 2020-09-03 10:08:29 +0200 | [diff] [blame] | 146 | * @attrs: memory transaction attributes |
Philippe Mathieu-Daudé | b1f5130 | 2020-10-23 17:19:19 +0200 | [diff] [blame] | 147 | */ |
| 148 | static inline MemTxResult dma_memory_read(AddressSpace *as, dma_addr_t addr, |
Philippe Mathieu-Daudé | ba06fe8 | 2020-09-03 10:08:29 +0200 | [diff] [blame] | 149 | void *buf, dma_addr_t len, |
| 150 | MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 151 | { |
Philippe Mathieu-Daudé | 23faf56 | 2020-09-03 09:37:43 +0200 | [diff] [blame] | 152 | return dma_memory_rw(as, addr, buf, len, |
Philippe Mathieu-Daudé | ba06fe8 | 2020-09-03 10:08:29 +0200 | [diff] [blame] | 153 | DMA_DIRECTION_TO_DEVICE, attrs); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 154 | } |
| 155 | |
Philippe Mathieu-Daudé | 77c71d1 | 2020-10-23 17:19:20 +0200 | [diff] [blame] | 156 | /** |
| 157 | * address_space_write: Write to address space from DMA controller. |
| 158 | * |
| 159 | * Return a MemTxResult indicating whether the operation succeeded |
| 160 | * or failed (eg unassigned memory, device rejected the transaction, |
| 161 | * IOMMU fault). |
| 162 | * |
| 163 | * @as: #AddressSpace to be accessed |
| 164 | * @addr: address within that address space |
| 165 | * @buf: buffer with the data transferred |
| 166 | * @len: the number of bytes to write |
Philippe Mathieu-Daudé | ba06fe8 | 2020-09-03 10:08:29 +0200 | [diff] [blame] | 167 | * @attrs: memory transaction attributes |
Philippe Mathieu-Daudé | 77c71d1 | 2020-10-23 17:19:20 +0200 | [diff] [blame] | 168 | */ |
| 169 | static inline MemTxResult dma_memory_write(AddressSpace *as, dma_addr_t addr, |
Philippe Mathieu-Daudé | ba06fe8 | 2020-09-03 10:08:29 +0200 | [diff] [blame] | 170 | const void *buf, dma_addr_t len, |
| 171 | MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 172 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 173 | return dma_memory_rw(as, addr, (void *)buf, len, |
Philippe Mathieu-Daudé | ba06fe8 | 2020-09-03 10:08:29 +0200 | [diff] [blame] | 174 | DMA_DIRECTION_FROM_DEVICE, attrs); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 175 | } |
| 176 | |
Philippe Mathieu-Daudé | bb755f5 | 2020-10-23 17:19:17 +0200 | [diff] [blame] | 177 | /** |
| 178 | * dma_memory_set: Fill memory with a constant byte from DMA controller. |
| 179 | * |
| 180 | * Return a MemTxResult indicating whether the operation succeeded |
| 181 | * or failed (eg unassigned memory, device rejected the transaction, |
| 182 | * IOMMU fault). |
| 183 | * |
| 184 | * @as: #AddressSpace to be accessed |
| 185 | * @addr: address within that address space |
| 186 | * @c: constant byte to fill the memory |
| 187 | * @len: the number of bytes to fill with the constant byte |
Philippe Mathieu-Daudé | 7a36e42 | 2020-09-03 10:28:32 +0200 | [diff] [blame] | 188 | * @attrs: memory transaction attributes |
Philippe Mathieu-Daudé | bb755f5 | 2020-10-23 17:19:17 +0200 | [diff] [blame] | 189 | */ |
| 190 | MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t addr, |
Philippe Mathieu-Daudé | 7a36e42 | 2020-09-03 10:28:32 +0200 | [diff] [blame] | 191 | uint8_t c, dma_addr_t len, MemTxAttrs attrs); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 192 | |
Philippe Mathieu-Daudé | 9c211ad | 2020-10-23 17:19:16 +0200 | [diff] [blame] | 193 | /** |
| 194 | * address_space_map: Map a physical memory region into a host virtual address. |
| 195 | * |
| 196 | * May map a subset of the requested range, given by and returned in @plen. |
| 197 | * May return %NULL and set *@plen to zero(0), if resources needed to perform |
| 198 | * the mapping are exhausted. |
| 199 | * Use only for reads OR writes - not for read-modify-write operations. |
| 200 | * |
| 201 | * @as: #AddressSpace to be accessed |
| 202 | * @addr: address within that address space |
| 203 | * @len: pointer to length of buffer; updated on return |
| 204 | * @dir: indicates the transfer direction |
Philippe Mathieu-Daudé | a1d4b0a | 2020-09-03 11:00:47 +0200 | [diff] [blame] | 205 | * @attrs: memory attributes |
Philippe Mathieu-Daudé | 9c211ad | 2020-10-23 17:19:16 +0200 | [diff] [blame] | 206 | */ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 207 | static inline void *dma_memory_map(AddressSpace *as, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 208 | dma_addr_t addr, dma_addr_t *len, |
Philippe Mathieu-Daudé | a1d4b0a | 2020-09-03 11:00:47 +0200 | [diff] [blame] | 209 | DMADirection dir, MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 210 | { |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 211 | hwaddr xlen = *len; |
| 212 | void *p; |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 213 | |
Peter Maydell | f26404f | 2018-05-31 14:50:52 +0100 | [diff] [blame] | 214 | p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE, |
Philippe Mathieu-Daudé | a1d4b0a | 2020-09-03 11:00:47 +0200 | [diff] [blame] | 215 | attrs); |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 216 | *len = xlen; |
| 217 | return p; |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 218 | } |
| 219 | |
Philippe Mathieu-Daudé | 9c211ad | 2020-10-23 17:19:16 +0200 | [diff] [blame] | 220 | /** |
| 221 | * address_space_unmap: Unmaps a memory region previously mapped |
| 222 | * by dma_memory_map() |
| 223 | * |
| 224 | * Will also mark the memory as dirty if @dir == %DMA_DIRECTION_FROM_DEVICE. |
| 225 | * @access_len gives the amount of memory that was actually read or written |
| 226 | * by the caller. |
| 227 | * |
| 228 | * @as: #AddressSpace used |
| 229 | * @buffer: host pointer as returned by address_space_map() |
| 230 | * @len: buffer length as returned by address_space_map() |
| 231 | * @dir: indicates the transfer direction |
| 232 | * @access_len: amount of data actually transferred |
| 233 | */ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 234 | static inline void dma_memory_unmap(AddressSpace *as, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 235 | void *buffer, dma_addr_t len, |
| 236 | DMADirection dir, dma_addr_t access_len) |
| 237 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 238 | address_space_unmap(as, buffer, (hwaddr)len, |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 239 | dir == DMA_DIRECTION_FROM_DEVICE, access_len); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 240 | } |
| 241 | |
| 242 | #define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \ |
Philippe Mathieu-Daudé | cd1db8d | 2021-12-17 22:31:11 +0100 | [diff] [blame] | 243 | static inline MemTxResult ld##_lname##_##_end##_dma(AddressSpace *as, \ |
| 244 | dma_addr_t addr, \ |
| 245 | uint##_bits##_t *pval, \ |
| 246 | MemTxAttrs attrs) \ |
| 247 | { \ |
| 248 | MemTxResult res = dma_memory_read(as, addr, pval, (_bits) / 8, attrs); \ |
| 249 | _end##_bits##_to_cpus(pval); \ |
| 250 | return res; \ |
| 251 | } \ |
Philippe Mathieu-Daudé | 24aed6b | 2021-12-17 23:56:14 +0100 | [diff] [blame] | 252 | static inline MemTxResult st##_sname##_##_end##_dma(AddressSpace *as, \ |
| 253 | dma_addr_t addr, \ |
| 254 | uint##_bits##_t val, \ |
| 255 | MemTxAttrs attrs) \ |
| 256 | { \ |
| 257 | val = cpu_to_##_end##_bits(val); \ |
| 258 | return dma_memory_write(as, addr, &val, (_bits) / 8, attrs); \ |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 259 | } |
| 260 | |
Philippe Mathieu-Daudé | cd1db8d | 2021-12-17 22:31:11 +0100 | [diff] [blame] | 261 | static inline MemTxResult ldub_dma(AddressSpace *as, dma_addr_t addr, |
| 262 | uint8_t *val, MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 263 | { |
Philippe Mathieu-Daudé | cd1db8d | 2021-12-17 22:31:11 +0100 | [diff] [blame] | 264 | return dma_memory_read(as, addr, val, 1, attrs); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 265 | } |
| 266 | |
Philippe Mathieu-Daudé | 24aed6b | 2021-12-17 23:56:14 +0100 | [diff] [blame] | 267 | static inline MemTxResult stb_dma(AddressSpace *as, dma_addr_t addr, |
| 268 | uint8_t val, MemTxAttrs attrs) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 269 | { |
Philippe Mathieu-Daudé | 24aed6b | 2021-12-17 23:56:14 +0100 | [diff] [blame] | 270 | return dma_memory_write(as, addr, &val, 1, attrs); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | DEFINE_LDST_DMA(uw, w, 16, le); |
| 274 | DEFINE_LDST_DMA(l, l, 32, le); |
| 275 | DEFINE_LDST_DMA(q, q, 64, le); |
| 276 | DEFINE_LDST_DMA(uw, w, 16, be); |
| 277 | DEFINE_LDST_DMA(l, l, 32, be); |
| 278 | DEFINE_LDST_DMA(q, q, 64, be); |
| 279 | |
| 280 | #undef DEFINE_LDST_DMA |
| 281 | |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 282 | struct ScatterGatherEntry { |
David Gibson | d323118 | 2011-10-31 17:06:46 +1100 | [diff] [blame] | 283 | dma_addr_t base; |
| 284 | dma_addr_t len; |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 285 | }; |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 286 | |
Paolo Bonzini | f487b67 | 2013-06-03 14:17:19 +0200 | [diff] [blame] | 287 | void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint, |
| 288 | AddressSpace *as); |
David Gibson | d323118 | 2011-10-31 17:06:46 +1100 | [diff] [blame] | 289 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len); |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 290 | void qemu_sglist_destroy(QEMUSGList *qsg); |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 291 | #endif |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 292 | |
Paolo Bonzini | 8a8e63e | 2016-05-23 14:54:06 +0200 | [diff] [blame] | 293 | typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov, |
| 294 | BlockCompletionFunc *cb, void *cb_opaque, |
| 295 | void *opaque); |
Christoph Hellwig | cb144cc | 2011-05-19 10:57:59 +0200 | [diff] [blame] | 296 | |
Paolo Bonzini | 8a8e63e | 2016-05-23 14:54:06 +0200 | [diff] [blame] | 297 | BlockAIOCB *dma_blk_io(AioContext *ctx, |
Mark Cave-Ayland | 99868af | 2016-10-27 16:29:13 -0400 | [diff] [blame] | 298 | QEMUSGList *sg, uint64_t offset, uint32_t align, |
Paolo Bonzini | 8a8e63e | 2016-05-23 14:54:06 +0200 | [diff] [blame] | 299 | DMAIOFunc *io_func, void *io_func_opaque, |
| 300 | BlockCompletionFunc *cb, void *opaque, DMADirection dir); |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 301 | BlockAIOCB *dma_blk_read(BlockBackend *blk, |
Mark Cave-Ayland | 99868af | 2016-10-27 16:29:13 -0400 | [diff] [blame] | 302 | QEMUSGList *sg, uint64_t offset, uint32_t align, |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 303 | BlockCompletionFunc *cb, void *opaque); |
| 304 | BlockAIOCB *dma_blk_write(BlockBackend *blk, |
Mark Cave-Ayland | 99868af | 2016-10-27 16:29:13 -0400 | [diff] [blame] | 305 | QEMUSGList *sg, uint64_t offset, uint32_t align, |
Markus Armbruster | 097310b | 2014-10-07 13:59:15 +0200 | [diff] [blame] | 306 | BlockCompletionFunc *cb, void *opaque); |
Philippe Mathieu-Daudé | 1e5a3f8 | 2021-12-15 23:29:52 +0100 | [diff] [blame] | 307 | uint64_t dma_buf_read(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs attrs); |
Philippe Mathieu-Daudé | 392e48a | 2021-12-15 23:02:21 +0100 | [diff] [blame] | 308 | uint64_t dma_buf_write(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs attrs); |
Paolo Bonzini | 8171ee3 | 2011-07-06 08:02:14 +0200 | [diff] [blame] | 309 | |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 310 | void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie, |
Paolo Bonzini | 84a6935 | 2011-09-05 14:20:29 +0200 | [diff] [blame] | 311 | QEMUSGList *sg, enum BlockAcctType type); |
| 312 | |
Eric Auger | f14fb6c | 2021-03-09 11:27:37 +0100 | [diff] [blame] | 313 | /** |
| 314 | * dma_aligned_pow2_mask: Return the address bit mask of the largest |
| 315 | * power of 2 size less or equal than @end - @start + 1, aligned with @start, |
| 316 | * and bounded by 1 << @max_addr_bits bits. |
| 317 | * |
| 318 | * @start: range start address |
| 319 | * @end: range end address (greater than @start) |
| 320 | * @max_addr_bits: max address bits (<= 64) |
| 321 | */ |
| 322 | uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end, |
| 323 | int max_addr_bits); |
| 324 | |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 325 | #endif |