aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * DMA helper functions |
| 3 | * |
| 4 | * Copyright (c) 2009 Red Hat |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU General Public License |
| 7 | * (GNU GPL), version 2 or later. |
| 8 | */ |
| 9 | |
| 10 | #ifndef DMA_H |
| 11 | #define DMA_H |
| 12 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 13 | #include "exec/memory.h" |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 14 | #include "exec/address-spaces.h" |
Paul Brook | 1ad2134 | 2009-05-19 16:17:58 +0100 | [diff] [blame] | 15 | #include "hw/hw.h" |
Paolo Bonzini | 737e150 | 2012-12-17 18:19:44 +0100 | [diff] [blame] | 16 | #include "block/block.h" |
BenoƮt Canet | 5e5a94b | 2014-09-05 15:46:16 +0200 | [diff] [blame] | 17 | #include "block/accounting.h" |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 18 | |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 19 | typedef struct ScatterGatherEntry ScatterGatherEntry; |
| 20 | |
David Gibson | 43cf8ae | 2012-03-27 13:42:23 +1100 | [diff] [blame] | 21 | typedef enum { |
| 22 | DMA_DIRECTION_TO_DEVICE = 0, |
| 23 | DMA_DIRECTION_FROM_DEVICE = 1, |
| 24 | } DMADirection; |
| 25 | |
Paolo Bonzini | fead0c2 | 2011-11-09 16:58:30 +0100 | [diff] [blame] | 26 | struct QEMUSGList { |
| 27 | ScatterGatherEntry *sg; |
| 28 | int nsg; |
| 29 | int nalloc; |
| 30 | size_t size; |
Paolo Bonzini | f487b67 | 2013-06-03 14:17:19 +0200 | [diff] [blame] | 31 | DeviceState *dev; |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 32 | AddressSpace *as; |
Paolo Bonzini | fead0c2 | 2011-11-09 16:58:30 +0100 | [diff] [blame] | 33 | }; |
| 34 | |
Avi Kivity | 4be403c | 2012-10-04 12:36:04 +0200 | [diff] [blame] | 35 | #ifndef CONFIG_USER_ONLY |
David Gibson | d9d1055 | 2011-10-31 17:06:45 +1100 | [diff] [blame] | 36 | |
David Gibson | e5332e6 | 2012-06-27 14:50:43 +1000 | [diff] [blame] | 37 | /* |
| 38 | * When an IOMMU is present, bus addresses become distinct from |
| 39 | * CPU/memory physical addresses and may be a different size. Because |
| 40 | * the IOVA size depends more on the bus than on the platform, we more |
| 41 | * or less have to treat these as 64-bit always to cover all (or at |
| 42 | * least most) cases. |
| 43 | */ |
| 44 | typedef uint64_t dma_addr_t; |
| 45 | |
| 46 | #define DMA_ADDR_BITS 64 |
| 47 | #define DMA_ADDR_FMT "%" PRIx64 |
| 48 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 49 | static inline void dma_barrier(AddressSpace *as, DMADirection dir) |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 50 | { |
| 51 | /* |
| 52 | * This is called before DMA read and write operations |
| 53 | * unless the _relaxed form is used and is responsible |
| 54 | * for providing some sane ordering of accesses vs |
| 55 | * concurrently running VCPUs. |
| 56 | * |
| 57 | * Users of map(), unmap() or lower level st/ld_* |
| 58 | * operations are responsible for providing their own |
| 59 | * ordering via barriers. |
| 60 | * |
| 61 | * This primitive implementation does a simple smp_mb() |
| 62 | * before each operation which provides pretty much full |
| 63 | * ordering. |
| 64 | * |
| 65 | * A smarter implementation can be devised if needed to |
| 66 | * use lighter barriers based on the direction of the |
| 67 | * transfer, the DMA context, etc... |
| 68 | */ |
Paolo Bonzini | 77ac58d | 2014-09-17 12:21:29 +0200 | [diff] [blame] | 69 | smp_mb(); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 70 | } |
| 71 | |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 72 | /* Checks that the given range of addresses is valid for DMA. This is |
| 73 | * useful for certain cases, but usually you should just use |
| 74 | * dma_memory_{read,write}() and check for errors */ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 75 | static inline bool dma_memory_valid(AddressSpace *as, |
David Gibson | e5332e6 | 2012-06-27 14:50:43 +1000 | [diff] [blame] | 76 | dma_addr_t addr, dma_addr_t len, |
| 77 | DMADirection dir) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 78 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 79 | return address_space_access_valid(as, addr, len, |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 80 | dir == DMA_DIRECTION_FROM_DEVICE); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 81 | } |
| 82 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 83 | static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 84 | void *buf, dma_addr_t len, |
| 85 | DMADirection dir) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 86 | { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 87 | return (bool)address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, |
| 88 | buf, len, dir == DMA_DIRECTION_FROM_DEVICE); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 89 | } |
| 90 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 91 | static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr, |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 92 | void *buf, dma_addr_t len) |
| 93 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 94 | return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 95 | } |
| 96 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 97 | static inline int dma_memory_write_relaxed(AddressSpace *as, dma_addr_t addr, |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 98 | const void *buf, dma_addr_t len) |
| 99 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 100 | return dma_memory_rw_relaxed(as, addr, (void *)buf, len, |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 101 | DMA_DIRECTION_FROM_DEVICE); |
| 102 | } |
| 103 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 104 | static inline int dma_memory_rw(AddressSpace *as, dma_addr_t addr, |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 105 | void *buf, dma_addr_t len, |
| 106 | DMADirection dir) |
| 107 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 108 | dma_barrier(as, dir); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 109 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 110 | return dma_memory_rw_relaxed(as, addr, buf, len, dir); |
Benjamin Herrenschmidt | 7a0bac4 | 2012-06-27 14:50:47 +1000 | [diff] [blame] | 111 | } |
| 112 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 113 | static inline int dma_memory_read(AddressSpace *as, dma_addr_t addr, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 114 | void *buf, dma_addr_t len) |
| 115 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 116 | return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 117 | } |
| 118 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 119 | static inline int dma_memory_write(AddressSpace *as, dma_addr_t addr, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 120 | const void *buf, dma_addr_t len) |
| 121 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 122 | return dma_memory_rw(as, addr, (void *)buf, len, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 123 | DMA_DIRECTION_FROM_DEVICE); |
| 124 | } |
| 125 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 126 | int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 127 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 128 | static inline void *dma_memory_map(AddressSpace *as, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 129 | dma_addr_t addr, dma_addr_t *len, |
| 130 | DMADirection dir) |
| 131 | { |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 132 | hwaddr xlen = *len; |
| 133 | void *p; |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 134 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 135 | p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE); |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 136 | *len = xlen; |
| 137 | return p; |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 138 | } |
| 139 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 140 | static inline void dma_memory_unmap(AddressSpace *as, |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 141 | void *buffer, dma_addr_t len, |
| 142 | DMADirection dir, dma_addr_t access_len) |
| 143 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 144 | address_space_unmap(as, buffer, (hwaddr)len, |
Paolo Bonzini | 24addbc | 2013-04-10 17:49:04 +0200 | [diff] [blame] | 145 | dir == DMA_DIRECTION_FROM_DEVICE, access_len); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | #define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 149 | static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \ |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 150 | dma_addr_t addr) \ |
| 151 | { \ |
| 152 | uint##_bits##_t val; \ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 153 | dma_memory_read(as, addr, &val, (_bits) / 8); \ |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 154 | return _end##_bits##_to_cpu(val); \ |
| 155 | } \ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 156 | static inline void st##_sname##_##_end##_dma(AddressSpace *as, \ |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 157 | dma_addr_t addr, \ |
| 158 | uint##_bits##_t val) \ |
| 159 | { \ |
| 160 | val = cpu_to_##_end##_bits(val); \ |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 161 | dma_memory_write(as, addr, &val, (_bits) / 8); \ |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 162 | } |
| 163 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 164 | static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 165 | { |
| 166 | uint8_t val; |
| 167 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 168 | dma_memory_read(as, addr, &val, 1); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 169 | return val; |
| 170 | } |
| 171 | |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 172 | static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val) |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 173 | { |
Paolo Bonzini | df32fd1 | 2013-04-10 18:15:49 +0200 | [diff] [blame] | 174 | dma_memory_write(as, addr, &val, 1); |
David Gibson | d86a77f | 2012-06-27 14:50:38 +1000 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | DEFINE_LDST_DMA(uw, w, 16, le); |
| 178 | DEFINE_LDST_DMA(l, l, 32, le); |
| 179 | DEFINE_LDST_DMA(q, q, 64, le); |
| 180 | DEFINE_LDST_DMA(uw, w, 16, be); |
| 181 | DEFINE_LDST_DMA(l, l, 32, be); |
| 182 | DEFINE_LDST_DMA(q, q, 64, be); |
| 183 | |
| 184 | #undef DEFINE_LDST_DMA |
| 185 | |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 186 | struct ScatterGatherEntry { |
David Gibson | d323118 | 2011-10-31 17:06:46 +1100 | [diff] [blame] | 187 | dma_addr_t base; |
| 188 | dma_addr_t len; |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 189 | }; |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 190 | |
Paolo Bonzini | f487b67 | 2013-06-03 14:17:19 +0200 | [diff] [blame] | 191 | void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint, |
| 192 | AddressSpace *as); |
David Gibson | d323118 | 2011-10-31 17:06:46 +1100 | [diff] [blame] | 193 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len); |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 194 | void qemu_sglist_destroy(QEMUSGList *qsg); |
Paolo Bonzini | 10dc8ae | 2011-09-16 16:40:01 +0200 | [diff] [blame] | 195 | #endif |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 196 | |
Paolo Bonzini | 8a8e63e | 2016-05-23 14:54:06 +0200 | [diff] [blame^] | 197 | typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov, |
| 198 | BlockCompletionFunc *cb, void *cb_opaque, |
| 199 | void *opaque); |
Christoph Hellwig | cb144cc | 2011-05-19 10:57:59 +0200 | [diff] [blame] | 200 | |
Paolo Bonzini | 8a8e63e | 2016-05-23 14:54:06 +0200 | [diff] [blame^] | 201 | BlockAIOCB *dma_blk_io(AioContext *ctx, |
Paolo Bonzini | cbe0ed6 | 2016-05-23 14:54:05 +0200 | [diff] [blame] | 202 | QEMUSGList *sg, uint64_t offset, |
Paolo Bonzini | 8a8e63e | 2016-05-23 14:54:06 +0200 | [diff] [blame^] | 203 | DMAIOFunc *io_func, void *io_func_opaque, |
| 204 | BlockCompletionFunc *cb, void *opaque, DMADirection dir); |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 205 | BlockAIOCB *dma_blk_read(BlockBackend *blk, |
Paolo Bonzini | cbe0ed6 | 2016-05-23 14:54:05 +0200 | [diff] [blame] | 206 | QEMUSGList *sg, uint64_t offset, |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 207 | BlockCompletionFunc *cb, void *opaque); |
| 208 | BlockAIOCB *dma_blk_write(BlockBackend *blk, |
Paolo Bonzini | cbe0ed6 | 2016-05-23 14:54:05 +0200 | [diff] [blame] | 209 | QEMUSGList *sg, uint64_t offset, |
Markus Armbruster | 097310b | 2014-10-07 13:59:15 +0200 | [diff] [blame] | 210 | BlockCompletionFunc *cb, void *opaque); |
Paolo Bonzini | 8171ee3 | 2011-07-06 08:02:14 +0200 | [diff] [blame] | 211 | uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg); |
| 212 | uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg); |
| 213 | |
Markus Armbruster | 4be7463 | 2014-10-07 13:59:18 +0200 | [diff] [blame] | 214 | void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie, |
Paolo Bonzini | 84a6935 | 2011-09-05 14:20:29 +0200 | [diff] [blame] | 215 | QEMUSGList *sg, enum BlockAcctType type); |
| 216 | |
aliguori | 244ab90 | 2009-02-05 21:23:50 +0000 | [diff] [blame] | 217 | #endif |