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aliguori244ab902009-02-05 21:23:50 +00001/*
2 * DMA helper functions
3 *
4 * Copyright (c) 2009 Red Hat
5 *
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
9
10#ifndef DMA_H
11#define DMA_H
12
Paolo Bonzini022c62c2012-12-17 18:19:49 +010013#include "exec/memory.h"
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020014#include "exec/address-spaces.h"
Paul Brook1ad21342009-05-19 16:17:58 +010015#include "hw/hw.h"
Paolo Bonzini737e1502012-12-17 18:19:44 +010016#include "block/block.h"
BenoƮt Canet5e5a94b2014-09-05 15:46:16 +020017#include "block/accounting.h"
aliguori244ab902009-02-05 21:23:50 +000018
Paolo Bonzini10dc8ae2011-09-16 16:40:01 +020019typedef struct ScatterGatherEntry ScatterGatherEntry;
20
David Gibson43cf8ae2012-03-27 13:42:23 +110021typedef enum {
22 DMA_DIRECTION_TO_DEVICE = 0,
23 DMA_DIRECTION_FROM_DEVICE = 1,
24} DMADirection;
25
Paolo Bonzinifead0c22011-11-09 16:58:30 +010026struct QEMUSGList {
27 ScatterGatherEntry *sg;
28 int nsg;
29 int nalloc;
30 size_t size;
Paolo Bonzinif487b672013-06-03 14:17:19 +020031 DeviceState *dev;
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020032 AddressSpace *as;
Paolo Bonzinifead0c22011-11-09 16:58:30 +010033};
34
Avi Kivity4be403c2012-10-04 12:36:04 +020035#ifndef CONFIG_USER_ONLY
David Gibsond9d10552011-10-31 17:06:45 +110036
David Gibsone5332e62012-06-27 14:50:43 +100037/*
38 * When an IOMMU is present, bus addresses become distinct from
39 * CPU/memory physical addresses and may be a different size. Because
40 * the IOVA size depends more on the bus than on the platform, we more
41 * or less have to treat these as 64-bit always to cover all (or at
42 * least most) cases.
43 */
44typedef uint64_t dma_addr_t;
45
46#define DMA_ADDR_BITS 64
47#define DMA_ADDR_FMT "%" PRIx64
48
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020049static inline void dma_barrier(AddressSpace *as, DMADirection dir)
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100050{
51 /*
52 * This is called before DMA read and write operations
53 * unless the _relaxed form is used and is responsible
54 * for providing some sane ordering of accesses vs
55 * concurrently running VCPUs.
56 *
57 * Users of map(), unmap() or lower level st/ld_*
58 * operations are responsible for providing their own
59 * ordering via barriers.
60 *
61 * This primitive implementation does a simple smp_mb()
62 * before each operation which provides pretty much full
63 * ordering.
64 *
65 * A smarter implementation can be devised if needed to
66 * use lighter barriers based on the direction of the
67 * transfer, the DMA context, etc...
68 */
Paolo Bonzini77ac58d2014-09-17 12:21:29 +020069 smp_mb();
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100070}
71
David Gibsond86a77f2012-06-27 14:50:38 +100072/* Checks that the given range of addresses is valid for DMA. This is
73 * useful for certain cases, but usually you should just use
74 * dma_memory_{read,write}() and check for errors */
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020075static inline bool dma_memory_valid(AddressSpace *as,
David Gibsone5332e62012-06-27 14:50:43 +100076 dma_addr_t addr, dma_addr_t len,
77 DMADirection dir)
David Gibsond86a77f2012-06-27 14:50:38 +100078{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020079 return address_space_access_valid(as, addr, len,
Paolo Bonzini24addbc2013-04-10 17:49:04 +020080 dir == DMA_DIRECTION_FROM_DEVICE);
David Gibsond86a77f2012-06-27 14:50:38 +100081}
82
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020083static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100084 void *buf, dma_addr_t len,
85 DMADirection dir)
David Gibsond86a77f2012-06-27 14:50:38 +100086{
Peter Maydell5c9eb022015-04-26 16:49:24 +010087 return (bool)address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
88 buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
David Gibsond86a77f2012-06-27 14:50:38 +100089}
90
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020091static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr,
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100092 void *buf, dma_addr_t len)
93{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020094 return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100095}
96
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020097static inline int dma_memory_write_relaxed(AddressSpace *as, dma_addr_t addr,
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100098 const void *buf, dma_addr_t len)
99{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200100 return dma_memory_rw_relaxed(as, addr, (void *)buf, len,
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +1000101 DMA_DIRECTION_FROM_DEVICE);
102}
103
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200104static inline int dma_memory_rw(AddressSpace *as, dma_addr_t addr,
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +1000105 void *buf, dma_addr_t len,
106 DMADirection dir)
107{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200108 dma_barrier(as, dir);
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +1000109
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200110 return dma_memory_rw_relaxed(as, addr, buf, len, dir);
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +1000111}
112
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200113static inline int dma_memory_read(AddressSpace *as, dma_addr_t addr,
David Gibsond86a77f2012-06-27 14:50:38 +1000114 void *buf, dma_addr_t len)
115{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200116 return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
David Gibsond86a77f2012-06-27 14:50:38 +1000117}
118
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200119static inline int dma_memory_write(AddressSpace *as, dma_addr_t addr,
David Gibsond86a77f2012-06-27 14:50:38 +1000120 const void *buf, dma_addr_t len)
121{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200122 return dma_memory_rw(as, addr, (void *)buf, len,
David Gibsond86a77f2012-06-27 14:50:38 +1000123 DMA_DIRECTION_FROM_DEVICE);
124}
125
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200126int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len);
David Gibsond86a77f2012-06-27 14:50:38 +1000127
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200128static inline void *dma_memory_map(AddressSpace *as,
David Gibsond86a77f2012-06-27 14:50:38 +1000129 dma_addr_t addr, dma_addr_t *len,
130 DMADirection dir)
131{
Paolo Bonzini24addbc2013-04-10 17:49:04 +0200132 hwaddr xlen = *len;
133 void *p;
David Gibsond86a77f2012-06-27 14:50:38 +1000134
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200135 p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
Paolo Bonzini24addbc2013-04-10 17:49:04 +0200136 *len = xlen;
137 return p;
David Gibsond86a77f2012-06-27 14:50:38 +1000138}
139
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200140static inline void dma_memory_unmap(AddressSpace *as,
David Gibsond86a77f2012-06-27 14:50:38 +1000141 void *buffer, dma_addr_t len,
142 DMADirection dir, dma_addr_t access_len)
143{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200144 address_space_unmap(as, buffer, (hwaddr)len,
Paolo Bonzini24addbc2013-04-10 17:49:04 +0200145 dir == DMA_DIRECTION_FROM_DEVICE, access_len);
David Gibsond86a77f2012-06-27 14:50:38 +1000146}
147
148#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200149 static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \
David Gibsond86a77f2012-06-27 14:50:38 +1000150 dma_addr_t addr) \
151 { \
152 uint##_bits##_t val; \
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200153 dma_memory_read(as, addr, &val, (_bits) / 8); \
David Gibsond86a77f2012-06-27 14:50:38 +1000154 return _end##_bits##_to_cpu(val); \
155 } \
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200156 static inline void st##_sname##_##_end##_dma(AddressSpace *as, \
David Gibsond86a77f2012-06-27 14:50:38 +1000157 dma_addr_t addr, \
158 uint##_bits##_t val) \
159 { \
160 val = cpu_to_##_end##_bits(val); \
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200161 dma_memory_write(as, addr, &val, (_bits) / 8); \
David Gibsond86a77f2012-06-27 14:50:38 +1000162 }
163
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200164static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr)
David Gibsond86a77f2012-06-27 14:50:38 +1000165{
166 uint8_t val;
167
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200168 dma_memory_read(as, addr, &val, 1);
David Gibsond86a77f2012-06-27 14:50:38 +1000169 return val;
170}
171
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200172static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val)
David Gibsond86a77f2012-06-27 14:50:38 +1000173{
Paolo Bonzinidf32fd12013-04-10 18:15:49 +0200174 dma_memory_write(as, addr, &val, 1);
David Gibsond86a77f2012-06-27 14:50:38 +1000175}
176
177DEFINE_LDST_DMA(uw, w, 16, le);
178DEFINE_LDST_DMA(l, l, 32, le);
179DEFINE_LDST_DMA(q, q, 64, le);
180DEFINE_LDST_DMA(uw, w, 16, be);
181DEFINE_LDST_DMA(l, l, 32, be);
182DEFINE_LDST_DMA(q, q, 64, be);
183
184#undef DEFINE_LDST_DMA
185
Paolo Bonzini10dc8ae2011-09-16 16:40:01 +0200186struct ScatterGatherEntry {
David Gibsond3231182011-10-31 17:06:46 +1100187 dma_addr_t base;
188 dma_addr_t len;
Paolo Bonzini10dc8ae2011-09-16 16:40:01 +0200189};
aliguori244ab902009-02-05 21:23:50 +0000190
Paolo Bonzinif487b672013-06-03 14:17:19 +0200191void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
192 AddressSpace *as);
David Gibsond3231182011-10-31 17:06:46 +1100193void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
aliguori244ab902009-02-05 21:23:50 +0000194void qemu_sglist_destroy(QEMUSGList *qsg);
Paolo Bonzini10dc8ae2011-09-16 16:40:01 +0200195#endif
aliguori244ab902009-02-05 21:23:50 +0000196
Paolo Bonzini8a8e63e2016-05-23 14:54:06 +0200197typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov,
198 BlockCompletionFunc *cb, void *cb_opaque,
199 void *opaque);
Christoph Hellwigcb144cc2011-05-19 10:57:59 +0200200
Paolo Bonzini8a8e63e2016-05-23 14:54:06 +0200201BlockAIOCB *dma_blk_io(AioContext *ctx,
Paolo Bonzinicbe0ed62016-05-23 14:54:05 +0200202 QEMUSGList *sg, uint64_t offset,
Paolo Bonzini8a8e63e2016-05-23 14:54:06 +0200203 DMAIOFunc *io_func, void *io_func_opaque,
204 BlockCompletionFunc *cb, void *opaque, DMADirection dir);
Markus Armbruster4be74632014-10-07 13:59:18 +0200205BlockAIOCB *dma_blk_read(BlockBackend *blk,
Paolo Bonzinicbe0ed62016-05-23 14:54:05 +0200206 QEMUSGList *sg, uint64_t offset,
Markus Armbruster4be74632014-10-07 13:59:18 +0200207 BlockCompletionFunc *cb, void *opaque);
208BlockAIOCB *dma_blk_write(BlockBackend *blk,
Paolo Bonzinicbe0ed62016-05-23 14:54:05 +0200209 QEMUSGList *sg, uint64_t offset,
Markus Armbruster097310b2014-10-07 13:59:15 +0200210 BlockCompletionFunc *cb, void *opaque);
Paolo Bonzini8171ee32011-07-06 08:02:14 +0200211uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg);
212uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
213
Markus Armbruster4be74632014-10-07 13:59:18 +0200214void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
Paolo Bonzini84a69352011-09-05 14:20:29 +0200215 QEMUSGList *sg, enum BlockAcctType type);
216
aliguori244ab902009-02-05 21:23:50 +0000217#endif