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balrogc1713132007-04-30 01:26:42 +00001/*
2 * Intel XScale PXA255/270 GPIO controller emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
Peter Maydell12b16722015-12-07 16:23:45 +000010#include "qemu/osdep.h"
Paolo Bonzini33c11872016-03-15 16:58:45 +010011#include "cpu.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010012#include "hw/hw.h"
13#include "hw/sysbus.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010014#include "hw/arm/pxa.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +010015#include "qemu/log.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020016#include "qemu/module.h"
balrogc1713132007-04-30 01:26:42 +000017
18#define PXA2XX_GPIO_BANKS 4
19
Andreas Färber922bb312013-07-24 02:03:39 +020020#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
21#define PXA2XX_GPIO(obj) \
22 OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
23
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030024typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
Paul Brookbc24a222009-05-10 01:44:56 +010025struct PXA2xxGPIOInfo {
Andreas Färber922bb312013-07-24 02:03:39 +020026 /*< private >*/
27 SysBusDevice parent_obj;
28 /*< public >*/
29
Benoît Canet55a8b802011-10-30 14:50:11 +010030 MemoryRegion iomem;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030031 qemu_irq irq0, irq1, irqX;
balrogc1713132007-04-30 01:26:42 +000032 int lines;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030033 int ncpu;
Andreas Färber95d42bb2012-05-04 00:23:14 +020034 ARMCPU *cpu;
balrogc1713132007-04-30 01:26:42 +000035
36 /* XXX: GNU C vectors are more suitable */
37 uint32_t ilevel[PXA2XX_GPIO_BANKS];
38 uint32_t olevel[PXA2XX_GPIO_BANKS];
39 uint32_t dir[PXA2XX_GPIO_BANKS];
40 uint32_t rising[PXA2XX_GPIO_BANKS];
41 uint32_t falling[PXA2XX_GPIO_BANKS];
42 uint32_t status[PXA2XX_GPIO_BANKS];
43 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
44
45 uint32_t prev_level[PXA2XX_GPIO_BANKS];
balrog38641a52007-11-17 14:07:13 +000046 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
47 qemu_irq read_notify;
balrogc1713132007-04-30 01:26:42 +000048};
49
50static struct {
51 enum {
52 GPIO_NONE,
53 GPLR,
54 GPSR,
55 GPCR,
56 GPDR,
57 GRER,
58 GFER,
59 GEDR,
60 GAFR_L,
61 GAFR_U,
62 } reg;
63 int bank;
64} pxa2xx_gpio_regs[0x200] = {
65 [0 ... 0x1ff] = { GPIO_NONE, 0 },
66#define PXA2XX_REG(reg, a0, a1, a2, a3) \
ths5fafdf22007-09-16 21:08:06 +000067 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
balrogc1713132007-04-30 01:26:42 +000068
69 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
70 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
71 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
72 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
73 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
74 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
75 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
76 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
77 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
78};
79
Paul Brookbc24a222009-05-10 01:44:56 +010080static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
balrogc1713132007-04-30 01:26:42 +000081{
82 if (s->status[0] & (1 << 0))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030083 qemu_irq_raise(s->irq0);
balrogc1713132007-04-30 01:26:42 +000084 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030085 qemu_irq_lower(s->irq0);
balrogc1713132007-04-30 01:26:42 +000086
87 if (s->status[0] & (1 << 1))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030088 qemu_irq_raise(s->irq1);
balrogc1713132007-04-30 01:26:42 +000089 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030090 qemu_irq_lower(s->irq1);
balrogc1713132007-04-30 01:26:42 +000091
92 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030093 qemu_irq_raise(s->irqX);
balrogc1713132007-04-30 01:26:42 +000094 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030095 qemu_irq_lower(s->irqX);
balrogc1713132007-04-30 01:26:42 +000096}
97
98/* Bitmap of pins used as standby and sleep wake-up sources. */
balrog38641a52007-11-17 14:07:13 +000099static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
balrogc1713132007-04-30 01:26:42 +0000100 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
101};
102
balrog38641a52007-11-17 14:07:13 +0000103static void pxa2xx_gpio_set(void *opaque, int line, int level)
balrogc1713132007-04-30 01:26:42 +0000104{
Paul Brookbc24a222009-05-10 01:44:56 +0100105 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
Andreas Färber259186a2013-01-17 18:51:17 +0100106 CPUState *cpu = CPU(s->cpu);
balrogc1713132007-04-30 01:26:42 +0000107 int bank;
108 uint32_t mask;
109
110 if (line >= s->lines) {
Alistair Francisa89f3642017-11-08 14:56:31 -0800111 printf("%s: No GPIO pin %i\n", __func__, line);
balrogc1713132007-04-30 01:26:42 +0000112 return;
113 }
114
115 bank = line >> 5;
Peter Maydell43a32ed2014-03-10 14:56:29 +0000116 mask = 1U << (line & 31);
balrogc1713132007-04-30 01:26:42 +0000117
118 if (level) {
119 s->status[bank] |= s->rising[bank] & mask &
120 ~s->ilevel[bank] & ~s->dir[bank];
121 s->ilevel[bank] |= mask;
122 } else {
123 s->status[bank] |= s->falling[bank] & mask &
124 s->ilevel[bank] & ~s->dir[bank];
125 s->ilevel[bank] &= ~mask;
126 }
127
128 if (s->status[bank] & mask)
129 pxa2xx_gpio_irq_update(s);
130
131 /* Wake-up GPIOs */
Andreas Färber259186a2013-01-17 18:51:17 +0100132 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
Andreas Färberc3affe52013-01-18 15:03:43 +0100133 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
Andreas Färber95d42bb2012-05-04 00:23:14 +0200134 }
balrogc1713132007-04-30 01:26:42 +0000135}
136
Paul Brookbc24a222009-05-10 01:44:56 +0100137static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
balrogc1713132007-04-30 01:26:42 +0000138 uint32_t level, diff;
139 int i, bit, line;
140 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
141 level = s->olevel[i] & s->dir[i];
142
143 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
Stefan Hajnoczi786a4ea2015-03-23 15:29:26 +0000144 bit = ctz32(diff);
balrogc1713132007-04-30 01:26:42 +0000145 line = bit + 32 * i;
balrog38641a52007-11-17 14:07:13 +0000146 qemu_set_irq(s->handler[line], (level >> bit) & 1);
balrogc1713132007-04-30 01:26:42 +0000147 }
148
149 s->prev_level[i] = level;
150 }
151}
152
Avi Kivitya8170e52012-10-23 12:30:10 +0200153static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100154 unsigned size)
balrogc1713132007-04-30 01:26:42 +0000155{
Paul Brookbc24a222009-05-10 01:44:56 +0100156 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000157 uint32_t ret;
158 int bank;
balrogc1713132007-04-30 01:26:42 +0000159 if (offset >= 0x200)
160 return 0;
161
162 bank = pxa2xx_gpio_regs[offset].bank;
163 switch (pxa2xx_gpio_regs[offset].reg) {
164 case GPDR: /* GPIO Pin-Direction registers */
165 return s->dir[bank];
166
balrog2b76bdc2007-10-04 19:41:17 +0000167 case GPSR: /* GPIO Pin-Output Set registers */
Peter Maydellab7a0f02014-06-29 18:38:40 +0100168 qemu_log_mask(LOG_GUEST_ERROR,
169 "pxa2xx GPIO: read from write only register GPSR\n");
170 return 0;
balrog2b76bdc2007-10-04 19:41:17 +0000171
balroge1dad5a2007-11-17 18:43:47 +0000172 case GPCR: /* GPIO Pin-Output Clear registers */
Peter Maydellab7a0f02014-06-29 18:38:40 +0100173 qemu_log_mask(LOG_GUEST_ERROR,
174 "pxa2xx GPIO: read from write only register GPCR\n");
175 return 0;
balroge1dad5a2007-11-17 18:43:47 +0000176
balrogc1713132007-04-30 01:26:42 +0000177 case GRER: /* GPIO Rising-Edge Detect Enable registers */
178 return s->rising[bank];
179
180 case GFER: /* GPIO Falling-Edge Detect Enable registers */
181 return s->falling[bank];
182
183 case GAFR_L: /* GPIO Alternate Function registers */
184 return s->gafr[bank * 2];
185
186 case GAFR_U: /* GPIO Alternate Function registers */
187 return s->gafr[bank * 2 + 1];
188
189 case GPLR: /* GPIO Pin-Level registers */
190 ret = (s->olevel[bank] & s->dir[bank]) |
191 (s->ilevel[bank] & ~s->dir[bank]);
balrog38641a52007-11-17 14:07:13 +0000192 qemu_irq_raise(s->read_notify);
balrogc1713132007-04-30 01:26:42 +0000193 return ret;
194
195 case GEDR: /* GPIO Edge Detect Status registers */
196 return s->status[bank];
197
198 default:
Alistair Francisa89f3642017-11-08 14:56:31 -0800199 hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
balrogc1713132007-04-30 01:26:42 +0000200 }
201
202 return 0;
203}
204
Avi Kivitya8170e52012-10-23 12:30:10 +0200205static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100206 uint64_t value, unsigned size)
balrogc1713132007-04-30 01:26:42 +0000207{
Paul Brookbc24a222009-05-10 01:44:56 +0100208 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000209 int bank;
balrogc1713132007-04-30 01:26:42 +0000210 if (offset >= 0x200)
211 return;
212
213 bank = pxa2xx_gpio_regs[offset].bank;
214 switch (pxa2xx_gpio_regs[offset].reg) {
215 case GPDR: /* GPIO Pin-Direction registers */
216 s->dir[bank] = value;
217 pxa2xx_gpio_handler_update(s);
218 break;
219
220 case GPSR: /* GPIO Pin-Output Set registers */
221 s->olevel[bank] |= value;
222 pxa2xx_gpio_handler_update(s);
223 break;
224
225 case GPCR: /* GPIO Pin-Output Clear registers */
226 s->olevel[bank] &= ~value;
227 pxa2xx_gpio_handler_update(s);
228 break;
229
230 case GRER: /* GPIO Rising-Edge Detect Enable registers */
231 s->rising[bank] = value;
232 break;
233
234 case GFER: /* GPIO Falling-Edge Detect Enable registers */
235 s->falling[bank] = value;
236 break;
237
238 case GAFR_L: /* GPIO Alternate Function registers */
239 s->gafr[bank * 2] = value;
240 break;
241
242 case GAFR_U: /* GPIO Alternate Function registers */
243 s->gafr[bank * 2 + 1] = value;
244 break;
245
246 case GEDR: /* GPIO Edge Detect Status registers */
247 s->status[bank] &= ~value;
248 pxa2xx_gpio_irq_update(s);
249 break;
250
251 default:
Alistair Francisa89f3642017-11-08 14:56:31 -0800252 hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
balrogc1713132007-04-30 01:26:42 +0000253 }
254}
255
Benoît Canet55a8b802011-10-30 14:50:11 +0100256static const MemoryRegionOps pxa_gpio_ops = {
257 .read = pxa2xx_gpio_read,
258 .write = pxa2xx_gpio_write,
259 .endianness = DEVICE_NATIVE_ENDIAN,
balrogc1713132007-04-30 01:26:42 +0000260};
261
Avi Kivitya8170e52012-10-23 12:30:10 +0200262DeviceState *pxa2xx_gpio_init(hwaddr base,
Andreas Färber55e5c282012-12-17 06:18:02 +0100263 ARMCPU *cpu, DeviceState *pic, int lines)
balrogc1713132007-04-30 01:26:42 +0000264{
Andreas Färber55e5c282012-12-17 06:18:02 +0100265 CPUState *cs = CPU(cpu);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300266 DeviceState *dev;
267
Andreas Färber922bb312013-07-24 02:03:39 +0200268 dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300269 qdev_prop_set_int32(dev, "lines", lines);
Andreas Färber55e5c282012-12-17 06:18:02 +0100270 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300271 qdev_init_nofail(dev);
272
Andreas Färber1356b982013-01-20 02:47:33 +0100273 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
274 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100275 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
Andreas Färber1356b982013-01-20 02:47:33 +0100276 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100277 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
Andreas Färber1356b982013-01-20 02:47:33 +0100278 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100279 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300280
281 return dev;
282}
283
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100284static void pxa2xx_gpio_initfn(Object *obj)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300285{
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100286 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
Andreas Färber922bb312013-07-24 02:03:39 +0200287 DeviceState *dev = DEVICE(sbd);
288 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300289
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100290 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
291 s, "pxa2xx-gpio", 0x1000);
292 sysbus_init_mmio(sbd, &s->iomem);
293 sysbus_init_irq(sbd, &s->irq0);
294 sysbus_init_irq(sbd, &s->irq1);
295 sysbus_init_irq(sbd, &s->irqX);
296}
297
298static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
299{
300 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
301
Andreas Färber38d8f5c2012-12-17 19:47:15 +0100302 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300303
Andreas Färber922bb312013-07-24 02:03:39 +0200304 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
305 qdev_init_gpio_out(dev, s->handler, s->lines);
balrogc1713132007-04-30 01:26:42 +0000306}
307
308/*
309 * Registers a callback to notify on GPLR reads. This normally
310 * shouldn't be needed but it is used for the hack on Spitz machines.
311 */
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300312void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
balrog38641a52007-11-17 14:07:13 +0000313{
Andreas Färber922bb312013-07-24 02:03:39 +0200314 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
315
balrogc1713132007-04-30 01:26:42 +0000316 s->read_notify = handler;
balrogc1713132007-04-30 01:26:42 +0000317}
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300318
319static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
320 .name = "pxa2xx-gpio",
321 .version_id = 1,
322 .minimum_version_id = 1,
Juan Quintela8f1e8842014-05-13 16:09:35 +0100323 .fields = (VMStateField[]) {
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300324 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
325 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
326 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
327 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
328 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
329 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
330 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
Peter Maydell166fa992014-06-29 18:38:40 +0100331 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300332 VMSTATE_END_OF_LIST(),
333 },
334};
335
Anthony Liguori999e12b2012-01-24 13:12:29 -0600336static Property pxa2xx_gpio_properties[] = {
337 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
338 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
339 DEFINE_PROP_END_OF_LIST(),
340};
341
342static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
343{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600344 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600345
Anthony Liguori39bffca2011-12-07 21:34:16 -0600346 dc->desc = "PXA2xx GPIO controller";
347 dc->props = pxa2xx_gpio_properties;
Peter Maydell166fa992014-06-29 18:38:40 +0100348 dc->vmsd = &vmstate_pxa2xx_gpio_regs;
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100349 dc->realize = pxa2xx_gpio_realize;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600350}
351
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100352static const TypeInfo pxa2xx_gpio_info = {
Andreas Färber922bb312013-07-24 02:03:39 +0200353 .name = TYPE_PXA2XX_GPIO,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600354 .parent = TYPE_SYS_BUS_DEVICE,
355 .instance_size = sizeof(PXA2xxGPIOInfo),
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100356 .instance_init = pxa2xx_gpio_initfn,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600357 .class_init = pxa2xx_gpio_class_init,
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300358};
359
Andreas Färber83f7d432012-02-09 15:20:55 +0100360static void pxa2xx_gpio_register_types(void)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300361{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600362 type_register_static(&pxa2xx_gpio_info);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300363}
Andreas Färber83f7d432012-02-09 15:20:55 +0100364
365type_init(pxa2xx_gpio_register_types)