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ths5856de82007-01-15 23:58:11 +00001/*
2 * QEMU Malta board support
3 *
4 * Copyright (c) 2006 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
pbrook87ecb682007-11-17 17:14:51 +000025#include "hw.h"
26#include "pc.h"
thsded7ba92007-11-26 14:52:02 +000027#include "fdc.h"
pbrook87ecb682007-11-17 17:14:51 +000028#include "net.h"
29#include "boards.h"
30#include "smbus.h"
thsc8b153d2008-01-04 19:11:32 +000031#include "block.h"
32#include "flash.h"
pbrook87ecb682007-11-17 17:14:51 +000033#include "mips.h"
Blue Swirlb970ea82010-03-27 07:26:16 +000034#include "mips_cpudevs.h"
pbrook87ecb682007-11-17 17:14:51 +000035#include "pci.h"
Michael S. Tsirkin18e08a52009-11-11 14:59:56 +020036#include "vmware_vga.h"
pbrook87ecb682007-11-17 17:14:51 +000037#include "qemu-char.h"
38#include "sysemu.h"
Isaku Yamahata0dfa5ef2011-01-21 19:53:45 +090039#include "arch_init.h"
pbrook87ecb682007-11-17 17:14:51 +000040#include "boards.h"
blueswir13b3fb322008-10-04 07:20:07 +000041#include "qemu-log.h"
Paul Brookbba831e2009-05-19 14:52:42 +010042#include "mips-bios.h"
Gerd Hoffmann977e1242009-08-20 15:22:20 +020043#include "ide.h"
Blue Swirlca20cf32009-09-20 14:58:02 +000044#include "loader.h"
45#include "elf.h"
Isaku Yamahata1d914fa2010-05-14 16:29:17 +090046#include "mc146818rtc.h"
Jan Kiszkab1277b02012-02-01 20:31:39 +010047#include "i8254.h"
Blue Swirl24463332010-08-24 15:22:24 +000048#include "blockdev.h"
Avi Kivitycfe5f012011-08-04 15:55:30 +030049#include "exec-memory.h"
Stefan Weile9b40fd2011-11-29 06:34:48 +010050#include "sysbus.h" /* SysBusDevice */
ths5856de82007-01-15 23:58:11 +000051
thsc8b153d2008-01-04 19:11:32 +000052//#define DEBUG_BOARD_INIT
53
Aurelien Jarno409dbce2010-03-14 21:20:59 +010054#define ENVP_ADDR 0x80002000l
ths5856de82007-01-15 23:58:11 +000055#define ENVP_NB_ENTRIES 16
56#define ENVP_ENTRY_SIZE 256
57
Stefan Weil03a1a8e2012-01-28 05:18:18 +000058/* Hardware addresses */
59#define FLASH_ADDRESS 0x1e000000ULL
60#define FPGA_ADDRESS 0x1f000000ULL
61#define RESET_ADDRESS 0x1fc00000ULL
62
63#define FLASH_SIZE 0x400000
64
thse4bcb142007-12-02 04:51:10 +000065#define MAX_IDE_BUS 2
66
ths5856de82007-01-15 23:58:11 +000067typedef struct {
Avi Kivityea85df72011-08-08 22:14:25 +030068 MemoryRegion iomem;
69 MemoryRegion iomem_lo; /* 0 - 0x900 */
70 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
ths5856de82007-01-15 23:58:11 +000071 uint32_t leds;
72 uint32_t brk;
73 uint32_t gpout;
ths130751e2007-02-28 20:04:26 +000074 uint32_t i2cin;
ths5856de82007-01-15 23:58:11 +000075 uint32_t i2coe;
76 uint32_t i2cout;
77 uint32_t i2csel;
78 CharDriverState *display;
79 char display_text[9];
thsa4bc3af2007-03-31 16:54:14 +000080 SerialState *uart;
ths5856de82007-01-15 23:58:11 +000081} MaltaFPGAState;
82
Stefan Weile9b40fd2011-11-29 06:34:48 +010083typedef struct {
84 SysBusDevice busdev;
85 qemu_irq *i8259;
86} MaltaState;
87
Blue Swirl64d7e9a2011-02-13 19:54:40 +000088static ISADevice *pit;
ths5856de82007-01-15 23:58:11 +000089
ths7df526e2007-11-09 17:52:11 +000090static struct _loaderparams {
91 int ram_size;
92 const char *kernel_filename;
93 const char *kernel_cmdline;
94 const char *initrd_filename;
95} loaderparams;
96
ths5856de82007-01-15 23:58:11 +000097/* Malta FPGA */
98static void malta_fpga_update_display(void *opaque)
99{
100 char leds_text[9];
101 int i;
102 MaltaFPGAState *s = opaque;
103
ths07cf0ba2007-06-21 23:38:12 +0000104 for (i = 7 ; i >= 0 ; i--) {
105 if (s->leds & (1 << i))
106 leds_text[i] = '#';
107 else
108 leds_text[i] = ' ';
ths87ee1662007-06-09 15:44:26 +0000109 }
ths07cf0ba2007-06-21 23:38:12 +0000110 leds_text[8] = '\0';
111
Anthony Liguorie7e71b02011-08-15 11:17:29 -0500112 qemu_chr_fe_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
113 qemu_chr_fe_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
ths5856de82007-01-15 23:58:11 +0000114}
115
ths130751e2007-02-28 20:04:26 +0000116/*
117 * EEPROM 24C01 / 24C02 emulation.
118 *
119 * Emulation for serial EEPROMs:
120 * 24C01 - 1024 bit (128 x 8)
121 * 24C02 - 2048 bit (256 x 8)
122 *
123 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
124 */
125
126//~ #define DEBUG
127
128#if defined(DEBUG)
Blue Swirl001faf32009-05-13 17:53:17 +0000129# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
ths130751e2007-02-28 20:04:26 +0000130#else
Blue Swirl001faf32009-05-13 17:53:17 +0000131# define logout(fmt, ...) ((void)0)
ths130751e2007-02-28 20:04:26 +0000132#endif
133
Anthony Liguoric227f092009-10-01 16:12:16 -0500134struct _eeprom24c0x_t {
ths130751e2007-02-28 20:04:26 +0000135 uint8_t tick;
136 uint8_t address;
137 uint8_t command;
138 uint8_t ack;
139 uint8_t scl;
140 uint8_t sda;
141 uint8_t data;
142 //~ uint16_t size;
143 uint8_t contents[256];
144};
145
Anthony Liguoric227f092009-10-01 16:12:16 -0500146typedef struct _eeprom24c0x_t eeprom24c0x_t;
ths130751e2007-02-28 20:04:26 +0000147
Anthony Liguoric227f092009-10-01 16:12:16 -0500148static eeprom24c0x_t eeprom = {
Blue Swirl284b08f2009-09-21 19:50:05 +0000149 .contents = {
ths130751e2007-02-28 20:04:26 +0000150 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
151 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
152 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
153 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
154 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
155 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
156 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
157 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
158 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
159 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
160 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
161 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
162 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
163 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
164 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
165 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
166 },
167};
168
blueswir1a5f1b962008-08-17 20:21:51 +0000169static uint8_t eeprom24c0x_read(void)
ths130751e2007-02-28 20:04:26 +0000170{
171 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
172 eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
173 return eeprom.sda;
174}
175
176static void eeprom24c0x_write(int scl, int sda)
177{
178 if (eeprom.scl && scl && (eeprom.sda != sda)) {
179 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
180 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
181 if (!sda) {
182 eeprom.tick = 1;
183 eeprom.command = 0;
184 }
185 } else if (eeprom.tick == 0 && !eeprom.ack) {
186 /* Waiting for start. */
187 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
188 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
189 } else if (!eeprom.scl && scl) {
190 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
191 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
192 if (eeprom.ack) {
193 logout("\ti2c ack bit = 0\n");
194 sda = 0;
195 eeprom.ack = 0;
196 } else if (eeprom.sda == sda) {
197 uint8_t bit = (sda != 0);
198 logout("\ti2c bit = %d\n", bit);
199 if (eeprom.tick < 9) {
200 eeprom.command <<= 1;
201 eeprom.command += bit;
202 eeprom.tick++;
203 if (eeprom.tick == 9) {
204 logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
205 eeprom.ack = 1;
206 }
207 } else if (eeprom.tick < 17) {
208 if (eeprom.command & 1) {
209 sda = ((eeprom.data & 0x80) != 0);
210 }
211 eeprom.address <<= 1;
212 eeprom.address += bit;
213 eeprom.tick++;
214 eeprom.data <<= 1;
215 if (eeprom.tick == 17) {
216 eeprom.data = eeprom.contents[eeprom.address];
217 logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
218 eeprom.ack = 1;
219 eeprom.tick = 0;
220 }
221 } else if (eeprom.tick >= 17) {
222 sda = 0;
223 }
224 } else {
225 logout("\tsda changed with raising scl\n");
226 }
227 } else {
228 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
229 }
230 eeprom.scl = scl;
231 eeprom.sda = sda;
232}
233
Avi Kivityea85df72011-08-08 22:14:25 +0300234static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
235 unsigned size)
ths5856de82007-01-15 23:58:11 +0000236{
237 MaltaFPGAState *s = opaque;
238 uint32_t val = 0;
239 uint32_t saddr;
240
241 saddr = (addr & 0xfffff);
242
243 switch (saddr) {
244
245 /* SWITCH Register */
246 case 0x00200:
247 val = 0x00000000; /* All switches closed */
Aurelien Jarno593c0d12009-11-14 13:10:43 +0100248 break;
ths5856de82007-01-15 23:58:11 +0000249
250 /* STATUS Register */
251 case 0x00208:
252#ifdef TARGET_WORDS_BIGENDIAN
253 val = 0x00000012;
254#else
255 val = 0x00000010;
256#endif
257 break;
258
259 /* JMPRS Register */
260 case 0x00210:
261 val = 0x00;
262 break;
263
264 /* LEDBAR Register */
265 case 0x00408:
266 val = s->leds;
267 break;
268
269 /* BRKRES Register */
270 case 0x00508:
271 val = s->brk;
272 break;
273
thsb6dc7eb2007-06-04 18:29:37 +0000274 /* UART Registers are handled directly by the serial device */
thsa4bc3af2007-03-31 16:54:14 +0000275
ths5856de82007-01-15 23:58:11 +0000276 /* GPOUT Register */
277 case 0x00a00:
278 val = s->gpout;
279 break;
280
281 /* XXX: implement a real I2C controller */
282
283 /* GPINP Register */
284 case 0x00a08:
285 /* IN = OUT until a real I2C control is implemented */
286 if (s->i2csel)
287 val = s->i2cout;
288 else
289 val = 0x00;
290 break;
291
292 /* I2CINP Register */
293 case 0x00b00:
ths130751e2007-02-28 20:04:26 +0000294 val = ((s->i2cin & ~1) | eeprom24c0x_read());
ths5856de82007-01-15 23:58:11 +0000295 break;
296
297 /* I2COE Register */
298 case 0x00b08:
299 val = s->i2coe;
300 break;
301
302 /* I2COUT Register */
303 case 0x00b10:
304 val = s->i2cout;
305 break;
306
307 /* I2CSEL Register */
308 case 0x00b18:
ths130751e2007-02-28 20:04:26 +0000309 val = s->i2csel;
ths5856de82007-01-15 23:58:11 +0000310 break;
311
312 default:
313#if 0
ths3594c772007-02-20 23:37:21 +0000314 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
Aurelien Jarno593c0d12009-11-14 13:10:43 +0100315 addr);
ths5856de82007-01-15 23:58:11 +0000316#endif
317 break;
318 }
319 return val;
320}
321
Avi Kivityea85df72011-08-08 22:14:25 +0300322static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
323 uint64_t val, unsigned size)
ths5856de82007-01-15 23:58:11 +0000324{
325 MaltaFPGAState *s = opaque;
326 uint32_t saddr;
327
328 saddr = (addr & 0xfffff);
329
330 switch (saddr) {
331
332 /* SWITCH Register */
333 case 0x00200:
334 break;
335
336 /* JMPRS Register */
337 case 0x00210:
338 break;
339
340 /* LEDBAR Register */
ths5856de82007-01-15 23:58:11 +0000341 case 0x00408:
342 s->leds = val & 0xff;
Stefan Weil1d7a1192012-01-28 05:18:19 +0000343 malta_fpga_update_display(s);
ths5856de82007-01-15 23:58:11 +0000344 break;
345
346 /* ASCIIWORD Register */
347 case 0x00410:
Avi Kivityea85df72011-08-08 22:14:25 +0300348 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
ths5856de82007-01-15 23:58:11 +0000349 malta_fpga_update_display(s);
350 break;
351
352 /* ASCIIPOS0 to ASCIIPOS7 Registers */
353 case 0x00418:
354 case 0x00420:
355 case 0x00428:
356 case 0x00430:
357 case 0x00438:
358 case 0x00440:
359 case 0x00448:
360 case 0x00450:
361 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
362 malta_fpga_update_display(s);
363 break;
364
365 /* SOFTRES Register */
366 case 0x00500:
367 if (val == 0x42)
368 qemu_system_reset_request ();
369 break;
370
371 /* BRKRES Register */
372 case 0x00508:
373 s->brk = val & 0xff;
374 break;
375
thsb6dc7eb2007-06-04 18:29:37 +0000376 /* UART Registers are handled directly by the serial device */
thsa4bc3af2007-03-31 16:54:14 +0000377
ths5856de82007-01-15 23:58:11 +0000378 /* GPOUT Register */
379 case 0x00a00:
380 s->gpout = val & 0xff;
381 break;
382
383 /* I2COE Register */
384 case 0x00b08:
385 s->i2coe = val & 0x03;
386 break;
387
388 /* I2COUT Register */
389 case 0x00b10:
ths130751e2007-02-28 20:04:26 +0000390 eeprom24c0x_write(val & 0x02, val & 0x01);
391 s->i2cout = val;
ths5856de82007-01-15 23:58:11 +0000392 break;
393
394 /* I2CSEL Register */
395 case 0x00b18:
ths130751e2007-02-28 20:04:26 +0000396 s->i2csel = val & 0x01;
ths5856de82007-01-15 23:58:11 +0000397 break;
398
399 default:
400#if 0
ths3594c772007-02-20 23:37:21 +0000401 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
Aurelien Jarno593c0d12009-11-14 13:10:43 +0100402 addr);
ths5856de82007-01-15 23:58:11 +0000403#endif
404 break;
405 }
406}
407
Avi Kivityea85df72011-08-08 22:14:25 +0300408static const MemoryRegionOps malta_fpga_ops = {
409 .read = malta_fpga_read,
410 .write = malta_fpga_write,
411 .endianness = DEVICE_NATIVE_ENDIAN,
ths5856de82007-01-15 23:58:11 +0000412};
413
pbrook9596ebb2007-11-18 01:44:38 +0000414static void malta_fpga_reset(void *opaque)
ths5856de82007-01-15 23:58:11 +0000415{
416 MaltaFPGAState *s = opaque;
417
418 s->leds = 0x00;
419 s->brk = 0x0a;
420 s->gpout = 0x00;
ths130751e2007-02-28 20:04:26 +0000421 s->i2cin = 0x3;
ths5856de82007-01-15 23:58:11 +0000422 s->i2coe = 0x0;
423 s->i2cout = 0x3;
424 s->i2csel = 0x1;
425
426 s->display_text[8] = '\0';
427 snprintf(s->display_text, 9, " ");
aurel32ceecf1d2009-01-18 14:08:04 +0000428}
429
aurel32ceecf1d2009-01-18 14:08:04 +0000430static void malta_fpga_led_init(CharDriverState *chr)
431{
Anthony Liguorie7e71b02011-08-15 11:17:29 -0500432 qemu_chr_fe_printf(chr, "\e[HMalta LEDBAR\r\n");
433 qemu_chr_fe_printf(chr, "+--------+\r\n");
434 qemu_chr_fe_printf(chr, "+ +\r\n");
435 qemu_chr_fe_printf(chr, "+--------+\r\n");
436 qemu_chr_fe_printf(chr, "\n");
437 qemu_chr_fe_printf(chr, "Malta ASCII\r\n");
438 qemu_chr_fe_printf(chr, "+--------+\r\n");
439 qemu_chr_fe_printf(chr, "+ +\r\n");
440 qemu_chr_fe_printf(chr, "+--------+\r\n");
ths5856de82007-01-15 23:58:11 +0000441}
442
Avi Kivityea85df72011-08-08 22:14:25 +0300443static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
444 target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
ths5856de82007-01-15 23:58:11 +0000445{
446 MaltaFPGAState *s;
ths5856de82007-01-15 23:58:11 +0000447
Anthony Liguori7267c092011-08-20 22:09:37 -0500448 s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
ths5856de82007-01-15 23:58:11 +0000449
Avi Kivityea85df72011-08-08 22:14:25 +0300450 memory_region_init_io(&s->iomem, &malta_fpga_ops, s,
451 "malta-fpga", 0x100000);
452 memory_region_init_alias(&s->iomem_lo, "malta-fpga",
453 &s->iomem, 0, 0x900);
454 memory_region_init_alias(&s->iomem_hi, "malta-fpga",
455 &s->iomem, 0xa00, 0x10000-0xa00);
thsa4bc3af2007-03-31 16:54:14 +0000456
Avi Kivityea85df72011-08-08 22:14:25 +0300457 memory_region_add_subregion(address_space, base, &s->iomem_lo);
458 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
ths5856de82007-01-15 23:58:11 +0000459
Anthony Liguori27143a42011-08-15 11:17:36 -0500460 s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
ths5856de82007-01-15 23:58:11 +0000461
Richard Henderson39186d82011-08-11 16:07:16 -0700462 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
463 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
thsa4bc3af2007-03-31 16:54:14 +0000464
ths5856de82007-01-15 23:58:11 +0000465 malta_fpga_reset(s);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200466 qemu_register_reset(malta_fpga_reset, s);
ths5856de82007-01-15 23:58:11 +0000467
468 return s;
469}
470
ths5856de82007-01-15 23:58:11 +0000471/* Network support */
Markus Armbruster5607c382009-06-18 15:14:08 +0200472static void network_init(void)
ths5856de82007-01-15 23:58:11 +0000473{
474 int i;
ths5856de82007-01-15 23:58:11 +0000475
476 for(i = 0; i < nb_nics; i++) {
aliguoricb457d72009-01-13 19:47:10 +0000477 NICInfo *nd = &nd_table[i];
Markus Armbruster5607c382009-06-18 15:14:08 +0200478 const char *default_devaddr = NULL;
aliguoricb457d72009-01-13 19:47:10 +0000479
480 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
ths5856de82007-01-15 23:58:11 +0000481 /* The malta board has a PCNet card using PCI SLOT 11 */
Markus Armbruster5607c382009-06-18 15:14:08 +0200482 default_devaddr = "0b";
aliguoricb457d72009-01-13 19:47:10 +0000483
Markus Armbruster07caea32009-09-25 03:53:51 +0200484 pci_nic_init_nofail(nd, "pcnet", default_devaddr);
ths5856de82007-01-15 23:58:11 +0000485 }
486}
487
488/* ROM and pseudo bootloader
489
490 The following code implements a very very simple bootloader. It first
491 loads the registers a0 to a3 to the values expected by the OS, and
492 then jump at the kernel address.
493
494 The bootloader should pass the locations of the kernel arguments and
495 environment variables tables. Those tables contain the 32-bit address
496 of NULL terminated strings. The environment variables table should be
497 terminated by a NULL address.
498
499 For a simpler implementation, the number of kernel arguments is fixed
500 to two (the name of the kernel and the command line), and the two
501 tables are actually the same one.
502
503 The registers a0 to a3 should contain the following values:
504 a0 - number of kernel arguments
505 a1 - 32-bit address of the kernel arguments table
506 a2 - 32-bit address of the environment variables table
507 a3 - RAM size in bytes
508*/
509
Andreas Färber61c56c82012-03-14 01:38:23 +0100510static void write_bootloader (CPUMIPSState *env, uint8_t *base,
pbrookd7585252009-04-10 03:36:49 +0000511 int64_t kernel_entry)
ths5856de82007-01-15 23:58:11 +0000512{
513 uint32_t *p;
514
515 /* Small bootloader */
pbrookd7585252009-04-10 03:36:49 +0000516 p = (uint32_t *)base;
ths26ea0912007-05-04 14:34:34 +0000517 stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
ths3ddd0062007-01-31 11:48:27 +0000518 stl_raw(p++, 0x00000000); /* nop */
ths5856de82007-01-15 23:58:11 +0000519
ths26ea0912007-05-04 14:34:34 +0000520 /* YAMON service vector */
pbrookd7585252009-04-10 03:36:49 +0000521 stl_raw(base + 0x500, 0xbfc00580); /* start: */
522 stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
523 stl_raw(base + 0x520, 0xbfc00580); /* start: */
524 stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
525 stl_raw(base + 0x534, 0xbfc00808); /* print: */
526 stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
527 stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
528 stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
529 stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
530 stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
531 stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
532 stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
533 stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
ths26ea0912007-05-04 14:34:34 +0000534
535
ths5856de82007-01-15 23:58:11 +0000536 /* Second part of the bootloader */
pbrookd7585252009-04-10 03:36:49 +0000537 p = (uint32_t *) (base + 0x580);
thsd52fff72007-04-24 22:57:37 +0000538 stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
539 stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
ths471ea272007-05-30 21:30:06 +0000540 stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
ths3ddd0062007-01-31 11:48:27 +0000541 stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
ths471ea272007-05-30 21:30:06 +0000542 stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
ths3ddd0062007-01-31 11:48:27 +0000543 stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
544 stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
ths7df526e2007-11-09 17:52:11 +0000545 stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
546 stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
ths2802bfe2007-04-19 15:38:26 +0000547
548 /* Load BAR registers as done by YAMON */
thsa0a87932007-07-11 16:44:32 +0000549 stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
550
551#ifdef TARGET_WORDS_BIGENDIAN
552 stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
553#else
554 stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
555#endif
556 stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
557
ths2802bfe2007-04-19 15:38:26 +0000558 stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
559
560#ifdef TARGET_WORDS_BIGENDIAN
561 stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
562#else
563 stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
564#endif
565 stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
566#ifdef TARGET_WORDS_BIGENDIAN
567 stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
568#else
569 stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
570#endif
571 stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
572
573#ifdef TARGET_WORDS_BIGENDIAN
574 stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
575#else
576 stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
577#endif
578 stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
579#ifdef TARGET_WORDS_BIGENDIAN
580 stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
581#else
582 stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
583#endif
584 stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
585
586#ifdef TARGET_WORDS_BIGENDIAN
587 stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
588#else
589 stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
590#endif
591 stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
592#ifdef TARGET_WORDS_BIGENDIAN
593 stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
594#else
595 stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
596#endif
597 stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
598
599 /* Jump to kernel code */
ths74287112007-04-01 17:56:37 +0000600 stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
601 stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
ths3ddd0062007-01-31 11:48:27 +0000602 stl_raw(p++, 0x03e00008); /* jr ra */
603 stl_raw(p++, 0x00000000); /* nop */
ths26ea0912007-05-04 14:34:34 +0000604
605 /* YAMON subroutines */
pbrookd7585252009-04-10 03:36:49 +0000606 p = (uint32_t *) (base + 0x800);
ths26ea0912007-05-04 14:34:34 +0000607 stl_raw(p++, 0x03e00008); /* jr ra */
608 stl_raw(p++, 0x24020000); /* li v0,0 */
609 /* 808 YAMON print */
610 stl_raw(p++, 0x03e06821); /* move t5,ra */
611 stl_raw(p++, 0x00805821); /* move t3,a0 */
612 stl_raw(p++, 0x00a05021); /* move t2,a1 */
613 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
614 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
615 stl_raw(p++, 0x10800005); /* beqz a0,834 */
616 stl_raw(p++, 0x00000000); /* nop */
617 stl_raw(p++, 0x0ff0021c); /* jal 870 */
618 stl_raw(p++, 0x00000000); /* nop */
619 stl_raw(p++, 0x08000205); /* j 814 */
620 stl_raw(p++, 0x00000000); /* nop */
621 stl_raw(p++, 0x01a00008); /* jr t5 */
622 stl_raw(p++, 0x01602021); /* move a0,t3 */
623 /* 0x83c YAMON print_count */
624 stl_raw(p++, 0x03e06821); /* move t5,ra */
625 stl_raw(p++, 0x00805821); /* move t3,a0 */
626 stl_raw(p++, 0x00a05021); /* move t2,a1 */
627 stl_raw(p++, 0x00c06021); /* move t4,a2 */
628 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
629 stl_raw(p++, 0x0ff0021c); /* jal 870 */
630 stl_raw(p++, 0x00000000); /* nop */
631 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
632 stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
633 stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
634 stl_raw(p++, 0x00000000); /* nop */
635 stl_raw(p++, 0x01a00008); /* jr t5 */
636 stl_raw(p++, 0x01602021); /* move a0,t3 */
637 /* 0x870 */
638 stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
639 stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
640 stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
641 stl_raw(p++, 0x00000000); /* nop */
642 stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
643 stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
644 stl_raw(p++, 0x00000000); /* nop */
645 stl_raw(p++, 0x03e00008); /* jr ra */
646 stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
647
ths5856de82007-01-15 23:58:11 +0000648}
649
Stefan Weil8b7968f2010-09-23 21:28:05 +0200650static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
651 const char *string, ...)
ths5856de82007-01-15 23:58:11 +0000652{
653 va_list ap;
ths3ddd0062007-01-31 11:48:27 +0000654 int32_t table_addr;
ths5856de82007-01-15 23:58:11 +0000655
656 if (index >= ENVP_NB_ENTRIES)
657 return;
658
ths5856de82007-01-15 23:58:11 +0000659 if (string == NULL) {
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100660 prom_buf[index] = 0;
ths5856de82007-01-15 23:58:11 +0000661 return;
662 }
663
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100664 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
665 prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
ths5856de82007-01-15 23:58:11 +0000666
667 va_start(ap, string);
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100668 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
ths5856de82007-01-15 23:58:11 +0000669 va_end(ap);
670}
671
672/* Kernel */
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100673static int64_t load_kernel (void)
ths5856de82007-01-15 23:58:11 +0000674{
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100675 int64_t kernel_entry, kernel_high;
ths5856de82007-01-15 23:58:11 +0000676 long initrd_size;
Anthony Liguoric227f092009-10-01 16:12:16 -0500677 ram_addr_t initrd_offset;
Blue Swirlca20cf32009-09-20 14:58:02 +0000678 int big_endian;
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100679 uint32_t *prom_buf;
680 long prom_size;
681 int prom_index = 0;
Blue Swirlca20cf32009-09-20 14:58:02 +0000682
683#ifdef TARGET_WORDS_BIGENDIAN
684 big_endian = 1;
685#else
686 big_endian = 0;
687#endif
ths5856de82007-01-15 23:58:11 +0000688
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100689 if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
690 (uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high,
691 big_endian, ELF_MACHINE, 1) < 0) {
ths5856de82007-01-15 23:58:11 +0000692 fprintf(stderr, "qemu: could not load kernel '%s'\n",
ths7df526e2007-11-09 17:52:11 +0000693 loaderparams.kernel_filename);
thsacdf72b2007-06-06 16:54:26 +0000694 exit(1);
ths5856de82007-01-15 23:58:11 +0000695 }
696
697 /* load initrd */
698 initrd_size = 0;
ths74287112007-04-01 17:56:37 +0000699 initrd_offset = 0;
ths7df526e2007-11-09 17:52:11 +0000700 if (loaderparams.initrd_filename) {
701 initrd_size = get_image_size (loaderparams.initrd_filename);
ths74287112007-04-01 17:56:37 +0000702 if (initrd_size > 0) {
703 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
ths7df526e2007-11-09 17:52:11 +0000704 if (initrd_offset + initrd_size > ram_size) {
ths74287112007-04-01 17:56:37 +0000705 fprintf(stderr,
706 "qemu: memory too small for initial ram disk '%s'\n",
ths7df526e2007-11-09 17:52:11 +0000707 loaderparams.initrd_filename);
ths74287112007-04-01 17:56:37 +0000708 exit(1);
709 }
pbrookdcac9672009-04-09 20:05:49 +0000710 initrd_size = load_image_targphys(loaderparams.initrd_filename,
711 initrd_offset,
712 ram_size - initrd_offset);
ths74287112007-04-01 17:56:37 +0000713 }
ths5856de82007-01-15 23:58:11 +0000714 if (initrd_size == (target_ulong) -1) {
715 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
ths7df526e2007-11-09 17:52:11 +0000716 loaderparams.initrd_filename);
ths5856de82007-01-15 23:58:11 +0000717 exit(1);
718 }
719 }
720
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100721 /* Setup prom parameters. */
722 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
Anthony Liguori7267c092011-08-20 22:09:37 -0500723 prom_buf = g_malloc(prom_size);
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100724
Stefan Weilf36d53e2010-09-20 22:18:01 +0200725 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100726 if (initrd_size > 0) {
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100727 prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
728 cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
ths7df526e2007-11-09 17:52:11 +0000729 loaderparams.kernel_cmdline);
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100730 } else {
Stefan Weilf36d53e2010-09-20 22:18:01 +0200731 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100732 }
ths5856de82007-01-15 23:58:11 +0000733
Aurelien Jarnoc938ada2009-11-14 13:04:29 +0100734 prom_set(prom_buf, prom_index++, "memsize");
735 prom_set(prom_buf, prom_index++, "%i", loaderparams.ram_size);
736 prom_set(prom_buf, prom_index++, "modetty0");
737 prom_set(prom_buf, prom_index++, "38400n8r");
738 prom_set(prom_buf, prom_index++, NULL);
739
740 rom_add_blob_fixed("prom", prom_buf, prom_size,
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100741 cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
ths5856de82007-01-15 23:58:11 +0000742
ths74287112007-04-01 17:56:37 +0000743 return kernel_entry;
ths5856de82007-01-15 23:58:11 +0000744}
745
Andreas Färber61c56c82012-03-14 01:38:23 +0100746static void malta_mips_config(CPUMIPSState *env)
Edgar E. Iglesiasc4cb2572011-08-29 23:07:41 +0200747{
748 env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
749 ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
750}
751
ths5856de82007-01-15 23:58:11 +0000752static void main_cpu_reset(void *opaque)
753{
Andreas Färber61c56c82012-03-14 01:38:23 +0100754 CPUMIPSState *env = opaque;
Andreas Färber1bba0dc2012-02-08 03:03:33 +0100755 cpu_state_reset(env);
ths5856de82007-01-15 23:58:11 +0000756
Aurelien Jarno5c434852010-01-30 21:27:54 +0100757 /* The bootloader does not need to be rewritten as it is located in a
ths5856de82007-01-15 23:58:11 +0000758 read only location. The kernel location and the arguments table
759 location does not change. */
ths7df526e2007-11-09 17:52:11 +0000760 if (loaderparams.kernel_filename) {
thsfb82fea2007-04-05 23:12:54 +0000761 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
thsfb82fea2007-04-05 23:12:54 +0000762 }
Edgar E. Iglesiasc4cb2572011-08-29 23:07:41 +0200763
764 malta_mips_config(env);
ths5856de82007-01-15 23:58:11 +0000765}
766
Blue Swirl4556bd82010-05-22 08:00:52 +0000767static void cpu_request_exit(void *opaque, int irq, int level)
768{
Andreas Färber61c56c82012-03-14 01:38:23 +0100769 CPUMIPSState *env = cpu_single_env;
Blue Swirl4556bd82010-05-22 08:00:52 +0000770
771 if (env && level) {
772 cpu_exit(env);
773 }
774}
775
ths70705262007-02-18 00:10:59 +0000776static
Anthony Liguoric227f092009-10-01 16:12:16 -0500777void mips_malta_init (ram_addr_t ram_size,
aliguori3023f332009-01-16 19:04:14 +0000778 const char *boot_device,
ths5856de82007-01-15 23:58:11 +0000779 const char *kernel_filename, const char *kernel_cmdline,
j_mayer94fc95c2007-03-05 19:44:02 +0000780 const char *initrd_filename, const char *cpu_model)
ths5856de82007-01-15 23:58:11 +0000781{
Paul Brook5cea8592009-05-30 00:52:44 +0100782 char *filename;
Avi Kivitycfe5f012011-08-04 15:55:30 +0300783 pflash_t *fl;
Avi Kivitycfe5f012011-08-04 15:55:30 +0300784 MemoryRegion *system_memory = get_system_memory();
Avi Kivityea85df72011-08-08 22:14:25 +0300785 MemoryRegion *ram = g_new(MemoryRegion, 1);
Avi Kivitycfe5f012011-08-04 15:55:30 +0300786 MemoryRegion *bios, *bios_alias = g_new(MemoryRegion, 1);
Stefan Weil03a1a8e2012-01-28 05:18:18 +0000787 target_long bios_size = FLASH_SIZE;
ths74287112007-04-01 17:56:37 +0000788 int64_t kernel_entry;
ths5856de82007-01-15 23:58:11 +0000789 PCIBus *pci_bus;
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100790 ISABus *isa_bus;
Andreas Färber61c56c82012-03-14 01:38:23 +0100791 CPUMIPSState *env;
Stefan Weile9b40fd2011-11-29 06:34:48 +0100792 qemu_irq *isa_irq;
Blue Swirl4556bd82010-05-22 08:00:52 +0000793 qemu_irq *cpu_exit_irq;
ths7b717332007-05-28 21:01:02 +0000794 int piix4_devfn;
ths7b717332007-05-28 21:01:02 +0000795 i2c_bus *smbus;
796 int i;
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200797 DriveInfo *dinfo;
Gerd Hoffmannf455e982009-08-28 15:47:03 +0200798 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200799 DriveInfo *fd[MAX_FD];
thsc8b153d2008-01-04 19:11:32 +0000800 int fl_idx = 0;
Stefan Weilbb4b3352012-01-28 05:18:17 +0000801 int fl_sectors = bios_size >> 16;
Anthony Liguori01e04512011-08-25 14:39:18 -0500802 int be;
ths5856de82007-01-15 23:58:11 +0000803
Stefan Weile9b40fd2011-11-29 06:34:48 +0100804 DeviceState *dev = qdev_create(NULL, "mips-malta");
805 MaltaState *s = DO_UPCAST(MaltaState, busdev.qdev, dev);
806
807 qdev_init_nofail(dev);
808
Aurelien Jarnoffabf032009-09-15 01:17:57 +0200809 /* Make sure the first 3 serial ports are associated with a device. */
810 for(i = 0; i < 3; i++) {
811 if (!serial_hds[i]) {
812 char label[32];
813 snprintf(label, sizeof(label), "serial%d", i);
Anthony Liguori27143a42011-08-15 11:17:36 -0500814 serial_hds[i] = qemu_chr_new(label, "null", NULL);
Aurelien Jarnoffabf032009-09-15 01:17:57 +0200815 }
816 }
817
ths33d68b52007-03-18 00:30:29 +0000818 /* init CPUs */
819 if (cpu_model == NULL) {
ths60aa19a2007-04-01 12:36:18 +0000820#ifdef TARGET_MIPS64
thsc9c1a062007-06-01 14:58:56 +0000821 cpu_model = "20Kc";
ths33d68b52007-03-18 00:30:29 +0000822#else
ths1c32f432007-04-28 21:07:41 +0000823 cpu_model = "24Kf";
ths33d68b52007-03-18 00:30:29 +0000824#endif
825 }
Edgar E. Iglesiasc4cb2572011-08-29 23:07:41 +0200826
827 for (i = 0; i < smp_cpus; i++) {
828 env = cpu_init(cpu_model);
829 if (!env) {
830 fprintf(stderr, "Unable to find CPU definition\n");
831 exit(1);
832 }
833 /* Init internal devices */
834 cpu_mips_irq_init_cpu(env);
835 cpu_mips_clock_init(env);
836 qemu_register_reset(main_cpu_reset, env);
bellardaaed9092007-11-10 15:15:54 +0000837 }
Edgar E. Iglesiasc4cb2572011-08-29 23:07:41 +0200838 env = first_cpu;
ths5856de82007-01-15 23:58:11 +0000839
840 /* allocate RAM */
aurel320ccff152009-01-24 15:07:25 +0000841 if (ram_size > (256 << 20)) {
842 fprintf(stderr,
843 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
844 ((unsigned int)ram_size / (1 << 20)));
845 exit(1);
846 }
Avi Kivityc5705a72011-12-20 15:59:12 +0200847 memory_region_init_ram(ram, "mips_malta.ram", ram_size);
848 vmstate_register_ram_global(ram);
Avi Kivityea85df72011-08-08 22:14:25 +0300849 memory_region_add_subregion(system_memory, 0, ram);
ths5856de82007-01-15 23:58:11 +0000850
Anthony Liguori01e04512011-08-25 14:39:18 -0500851#ifdef TARGET_WORDS_BIGENDIAN
852 be = 1;
853#else
854 be = 0;
855#endif
ths070ce5e2007-06-06 17:19:24 +0000856 /* FPGA */
Stefan Weil03a1a8e2012-01-28 05:18:18 +0000857 malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]);
ths070ce5e2007-06-06 17:19:24 +0000858
Stefan Weilbb4b3352012-01-28 05:18:17 +0000859 /* Load firmware in flash / BIOS. */
860 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
861#ifdef DEBUG_BOARD_INIT
862 if (dinfo) {
863 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
864 "addr %08llx '%s' %x\n",
Stefan Weil03a1a8e2012-01-28 05:18:18 +0000865 fl_idx, bios_size, FLASH_ADDRESS,
Stefan Weilbb4b3352012-01-28 05:18:17 +0000866 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
867 }
868#endif
Stefan Weil03a1a8e2012-01-28 05:18:18 +0000869 fl = pflash_cfi01_register(FLASH_ADDRESS, NULL, "mips_malta.bios",
Stefan Weilbb4b3352012-01-28 05:18:17 +0000870 BIOS_SIZE, dinfo ? dinfo->bdrv : NULL,
871 65536, fl_sectors,
872 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
873 bios = pflash_cfi01_get_memory(fl);
874 fl_idx++;
ths5856de82007-01-15 23:58:11 +0000875 if (kernel_filename) {
thsc8b153d2008-01-04 19:11:32 +0000876 /* Write a small bootloader to the flash location. */
ths7df526e2007-11-09 17:52:11 +0000877 loaderparams.ram_size = ram_size;
878 loaderparams.kernel_filename = kernel_filename;
879 loaderparams.kernel_cmdline = kernel_cmdline;
880 loaderparams.initrd_filename = initrd_filename;
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100881 kernel_entry = load_kernel();
Avi Kivitycfe5f012011-08-04 15:55:30 +0300882 write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
thsc8b153d2008-01-04 19:11:32 +0000883 } else {
Stefan Weilbb4b3352012-01-28 05:18:17 +0000884 /* Load firmware from flash. */
885 if (!dinfo) {
thsc8b153d2008-01-04 19:11:32 +0000886 /* Load a BIOS image. */
Stefan Weilbb4b3352012-01-28 05:18:17 +0000887 if (bios_name == NULL) {
thsc8b153d2008-01-04 19:11:32 +0000888 bios_name = BIOS_FILENAME;
Stefan Weilbb4b3352012-01-28 05:18:17 +0000889 }
Paul Brook5cea8592009-05-30 00:52:44 +0100890 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
891 if (filename) {
Stefan Weil03a1a8e2012-01-28 05:18:18 +0000892 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
Paul Brook5cea8592009-05-30 00:52:44 +0100893 BIOS_SIZE);
Anthony Liguori7267c092011-08-20 22:09:37 -0500894 g_free(filename);
Paul Brook5cea8592009-05-30 00:52:44 +0100895 } else {
896 bios_size = -1;
897 }
thsc8b153d2008-01-04 19:11:32 +0000898 if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
899 fprintf(stderr,
900 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
Paul Brook5cea8592009-05-30 00:52:44 +0100901 bios_name);
thsc8b153d2008-01-04 19:11:32 +0000902 exit(1);
903 }
904 }
905 /* In little endian mode the 32bit words in the bios are swapped,
906 a neat trick which allows bi-endian firmware. */
907#ifndef TARGET_WORDS_BIGENDIAN
908 {
Avi Kivitycfe5f012011-08-04 15:55:30 +0300909 uint32_t *addr = memory_region_get_ram_ptr(bios);
pbrookd7585252009-04-10 03:36:49 +0000910 uint32_t *end = addr + bios_size;
911 while (addr < end) {
912 bswap32s(addr);
Chen Ruia30cfee2011-11-13 19:42:42 +0800913 addr++;
thsc8b153d2008-01-04 19:11:32 +0000914 }
915 }
916#endif
ths5856de82007-01-15 23:58:11 +0000917 }
918
Stefan Weil82a98072012-01-28 05:18:16 +0000919 /* Map the BIOS at a 2nd physical location, as on the real board. */
920 memory_region_init_alias(bios_alias, "bios.1fc", bios, 0, BIOS_SIZE);
Stefan Weil03a1a8e2012-01-28 05:18:18 +0000921 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_alias);
Stefan Weil82a98072012-01-28 05:18:16 +0000922
ths5856de82007-01-15 23:58:11 +0000923 /* Board ID = 0x420 (Malta Board with CoreLV)
924 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
925 map to the board ID. */
Avi Kivitycfe5f012011-08-04 15:55:30 +0300926 stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420);
ths5856de82007-01-15 23:58:11 +0000927
928 /* Init internal devices */
pbrookd537cf62007-04-07 18:14:41 +0000929 cpu_mips_irq_init_cpu(env);
ths5856de82007-01-15 23:58:11 +0000930 cpu_mips_clock_init(env);
ths5856de82007-01-15 23:58:11 +0000931
Avi Kivity5632ae42011-09-12 13:00:05 +0300932 /*
933 * We have a circular dependency problem: pci_bus depends on isa_irq,
934 * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
935 * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
936 * qemu_irq_proxy() adds an extra bit of indirection, allowing us
937 * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
938 */
Stefan Weile9b40fd2011-11-29 06:34:48 +0100939 isa_irq = qemu_irq_proxy(&s->i8259, 16);
ths5856de82007-01-15 23:58:11 +0000940
941 /* Northbridge */
Avi Kivity5632ae42011-09-12 13:00:05 +0300942 pci_bus = gt64120_register(isa_irq);
ths5856de82007-01-15 23:58:11 +0000943
944 /* Southbridge */
Isaku Yamahata75717902011-04-03 20:32:46 +0900945 ide_drive_get(hd, MAX_IDE_BUS);
thse4bcb142007-12-02 04:51:10 +0000946
Hervé Poussineau142e9782011-12-15 22:09:58 +0100947 piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
Avi Kivity5632ae42011-09-12 13:00:05 +0300948
949 /* Interrupt controller */
950 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
Stefan Weile9b40fd2011-11-29 06:34:48 +0100951 s->i8259 = i8259_init(isa_bus, env->irq[2]);
Avi Kivity5632ae42011-09-12 13:00:05 +0300952
Stefan Weile9b40fd2011-11-29 06:34:48 +0100953 isa_bus_irqs(isa_bus, s->i8259);
Stefan Weilae027ad2009-08-28 19:37:00 +0200954 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
Gerd Hoffmannafb9a602012-03-07 15:06:32 +0100955 pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100956 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
Gerd Hoffmannda98c8e2012-02-23 13:45:20 +0100957 isa_get_irq(NULL, 9), NULL, 0);
Isaku Yamahataa88df0b2011-04-05 11:07:06 +0900958 /* TODO: Populate SPD eeprom data. */
959 smbus_eeprom_init(smbus, 8, NULL, 0);
Jan Kiszka319ba9f2012-02-01 20:31:40 +0100960 pit = pit_init(isa_bus, 0x40, 0, NULL);
Blue Swirl4556bd82010-05-22 08:00:52 +0000961 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
962 DMA_init(0, cpu_exit_irq);
ths5856de82007-01-15 23:58:11 +0000963
964 /* Super I/O */
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100965 isa_create_simple(isa_bus, "i8042");
Blue Swirl49a29422010-10-13 18:41:29 +0000966
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100967 rtc_init(isa_bus, 2000, NULL);
968 serial_isa_init(isa_bus, 0, serial_hds[0]);
969 serial_isa_init(isa_bus, 1, serial_hds[1]);
ths7bcc17d2007-02-21 22:43:42 +0000970 if (parallel_hds[0])
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100971 parallel_init(isa_bus, 0, parallel_hds[0]);
thse4bcb142007-12-02 04:51:10 +0000972 for(i = 0; i < MAX_FD; i++) {
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200973 fd[i] = drive_get(IF_FLOPPY, 0, i);
thse4bcb142007-12-02 04:51:10 +0000974 }
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100975 fdctrl_init_isa(isa_bus, fd);
ths5856de82007-01-15 23:58:11 +0000976
977 /* Sound card */
Hervé Poussineau4a0f0312011-12-15 22:10:01 +0100978 audio_init(isa_bus, pci_bus);
ths5856de82007-01-15 23:58:11 +0000979
980 /* Network card */
Markus Armbruster5607c382009-06-18 15:14:08 +0200981 network_init();
ths11f29512007-03-18 22:18:43 +0000982
983 /* Optional PCI video card */
aurel321f605a72009-02-08 14:51:19 +0000984 if (cirrus_vga_enabled) {
Paul Brookfbe1b592009-05-13 17:56:25 +0100985 pci_cirrus_vga_init(pci_bus);
aurel321f605a72009-02-08 14:51:19 +0000986 } else if (vmsvga_enabled) {
Blue Swirla369da52011-09-27 19:15:42 +0000987 pci_vmsvga_init(pci_bus);
aurel321f605a72009-02-08 14:51:19 +0000988 } else if (std_vga_enabled) {
Gerd Hoffmann78895422010-10-15 11:45:13 +0200989 pci_vga_init(pci_bus);
aurel321f605a72009-02-08 14:51:19 +0000990 }
ths5856de82007-01-15 23:58:11 +0000991}
992
Stefan Weile9b40fd2011-11-29 06:34:48 +0100993static int mips_malta_sysbus_device_init(SysBusDevice *sysbusdev)
994{
995 return 0;
996}
997
Anthony Liguori999e12b2012-01-24 13:12:29 -0600998static void mips_malta_class_init(ObjectClass *klass, void *data)
999{
1000 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1001
1002 k->init = mips_malta_sysbus_device_init;
1003}
1004
Anthony Liguori39bffca2011-12-07 21:34:16 -06001005static TypeInfo mips_malta_device = {
1006 .name = "mips-malta",
1007 .parent = TYPE_SYS_BUS_DEVICE,
1008 .instance_size = sizeof(MaltaState),
1009 .class_init = mips_malta_class_init,
Stefan Weile9b40fd2011-11-29 06:34:48 +01001010};
1011
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001012static QEMUMachine mips_malta_machine = {
thseec27432008-08-13 13:01:28 +00001013 .name = "malta",
1014 .desc = "MIPS Malta Core LV",
1015 .init = mips_malta_init,
Edgar E. Iglesiasc4cb2572011-08-29 23:07:41 +02001016 .max_cpus = 16,
Anthony Liguori0c257432009-05-21 20:41:01 -05001017 .is_default = 1,
ths5856de82007-01-15 23:58:11 +00001018};
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001019
Andreas Färber83f7d432012-02-09 15:20:55 +01001020static void mips_malta_register_types(void)
Stefan Weile9b40fd2011-11-29 06:34:48 +01001021{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001022 type_register_static(&mips_malta_device);
Stefan Weile9b40fd2011-11-29 06:34:48 +01001023}
1024
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001025static void mips_malta_machine_init(void)
1026{
1027 qemu_register_machine(&mips_malta_machine);
1028}
1029
Andreas Färber83f7d432012-02-09 15:20:55 +01001030type_init(mips_malta_register_types)
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001031machine_init(mips_malta_machine_init);