commit 7b717336e2873fd6d9f178a12549eaa2367d14d0
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Mon May 28 21:01:02 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Mon May 28 21:01:02 2007 +0000
tree e06da771738863c969473e57efb0130c28ff8a86
parent 6e473128b61901441fa2889dfa2079881895a9f9

SMBus support for MIPS Malta.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2893 c046a42c-6fe2-441c-8c8c-71466251a162

hw/mips_malta.c

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 82ba809..6339cc9 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -775,6 +775,10 @@
     int ret;
     mips_def_t *def;
     qemu_irq *i8259;
+    int piix4_devfn;
+    uint8_t *eeprom_buf;
+    i2c_bus *smbus;
+    int i;
 
     /* init CPUs */
     if (cpu_model == NULL) {
@@ -843,10 +847,15 @@
     pci_bus = pci_gt64120_init(i8259);
 
     /* Southbridge */
-    piix4_init(pci_bus, 80);
-    pci_piix3_ide_init(pci_bus, bs_table, 81, i8259);
-    usb_uhci_init(pci_bus, 82);
-    piix4_pm_init(pci_bus, 83);
+    piix4_devfn = piix4_init(pci_bus, 80);
+    pci_piix3_ide_init(pci_bus, bs_table, piix4_devfn + 1, i8259);
+    usb_uhci_init(pci_bus, piix4_devfn + 2);
+    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100);
+    eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
+    for (i = 0; i < 8; i++) {
+        /* TODO: Populate SPD eeprom data.  */
+        smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
+    }
     pit = pit_init(0x40, i8259[0]);
     DMA_init(0);