bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Sparc SLAVIO interrupt controller emulation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 24 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 25 | #include "sun4m.h" |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 26 | #include "monitor.h" |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 27 | #include "sysbus.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 28 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 29 | //#define DEBUG_IRQ_COUNT |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 30 | //#define DEBUG_IRQ |
| 31 | |
| 32 | #ifdef DEBUG_IRQ |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 33 | #define DPRINTF(fmt, ...) \ |
| 34 | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 35 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 36 | #define DPRINTF(fmt, ...) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 37 | #endif |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 38 | |
| 39 | /* |
| 40 | * Registers of interrupt controller in sun4m. |
| 41 | * |
| 42 | * This is the interrupt controller part of chip STP2001 (Slave I/O), also |
| 43 | * produced as NCR89C105. See |
| 44 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt |
| 45 | * |
| 46 | * There is a system master controller and one for each cpu. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 47 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 48 | */ |
| 49 | |
| 50 | #define MAX_CPUS 16 |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 51 | #define MAX_PILS 16 |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 52 | |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 53 | struct SLAVIO_INTCTLState; |
| 54 | |
| 55 | typedef struct SLAVIO_CPUINTCTLState { |
| 56 | uint32_t intreg_pending; |
| 57 | struct SLAVIO_INTCTLState *master; |
| 58 | uint32_t cpu; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 59 | uint32_t irl_out; |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 60 | } SLAVIO_CPUINTCTLState; |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 61 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 62 | typedef struct SLAVIO_INTCTLState { |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 63 | SysBusDevice busdev; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 64 | uint32_t intregm_pending; |
| 65 | uint32_t intregm_disabled; |
| 66 | uint32_t target_cpu; |
| 67 | #ifdef DEBUG_IRQ_COUNT |
| 68 | uint64_t irq_count[32]; |
| 69 | #endif |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 70 | qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 71 | SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 72 | } SLAVIO_INTCTLState; |
| 73 | |
| 74 | #define INTCTL_MAXADDR 0xf |
blueswir1 | 5aca8c3 | 2007-05-26 17:39:43 +0000 | [diff] [blame] | 75 | #define INTCTL_SIZE (INTCTL_MAXADDR + 1) |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 76 | #define INTCTLM_SIZE 0x14 |
blueswir1 | 80be36b | 2007-12-28 18:48:39 +0000 | [diff] [blame] | 77 | #define MASTER_IRQ_MASK ~0x0fa2007f |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 78 | #define MASTER_DISABLE 0x80000000 |
blueswir1 | 6341fdc | 2007-12-29 20:09:57 +0000 | [diff] [blame] | 79 | #define CPU_SOFTIRQ_MASK 0xfffe0000 |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 80 | #define CPU_IRQ_INT15_IN (1 << 15) |
| 81 | #define CPU_IRQ_TIMER_IN (1 << 14) |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 82 | |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 83 | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 84 | |
| 85 | // per-cpu interrupt controller |
| 86 | static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) |
| 87 | { |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 88 | SLAVIO_CPUINTCTLState *s = opaque; |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 89 | uint32_t saddr, ret; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 90 | |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 91 | saddr = addr >> 2; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 92 | switch (saddr) { |
| 93 | case 0: |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 94 | ret = s->intreg_pending; |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 95 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 96 | default: |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 97 | ret = 0; |
| 98 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 99 | } |
blueswir1 | 3c4cf53 | 2009-03-03 20:11:43 +0000 | [diff] [blame] | 100 | DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret); |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 101 | |
| 102 | return ret; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 103 | } |
| 104 | |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 105 | static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, |
| 106 | uint32_t val) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 107 | { |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 108 | SLAVIO_CPUINTCTLState *s = opaque; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 109 | uint32_t saddr; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 110 | |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 111 | saddr = addr >> 2; |
blueswir1 | 3c4cf53 | 2009-03-03 20:11:43 +0000 | [diff] [blame] | 112 | DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 113 | switch (saddr) { |
| 114 | case 1: // clear pending softints |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 115 | val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 116 | s->intreg_pending &= ~val; |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 117 | slavio_check_interrupts(s->master, 1); |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 118 | DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val, |
| 119 | s->intreg_pending); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 120 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 121 | case 2: // set softint |
blueswir1 | 6341fdc | 2007-12-29 20:09:57 +0000 | [diff] [blame] | 122 | val &= CPU_SOFTIRQ_MASK; |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 123 | s->intreg_pending |= val; |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 124 | slavio_check_interrupts(s->master, 1); |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 125 | DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val, |
| 126 | s->intreg_pending); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 127 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 128 | default: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 129 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 130 | } |
| 131 | } |
| 132 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 133 | static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 134 | NULL, |
| 135 | NULL, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 136 | slavio_intctl_mem_readl, |
| 137 | }; |
| 138 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 139 | static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 140 | NULL, |
| 141 | NULL, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 142 | slavio_intctl_mem_writel, |
| 143 | }; |
| 144 | |
| 145 | // master system interrupt controller |
| 146 | static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) |
| 147 | { |
| 148 | SLAVIO_INTCTLState *s = opaque; |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 149 | uint32_t saddr, ret; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 150 | |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 151 | saddr = addr >> 2; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 152 | switch (saddr) { |
| 153 | case 0: |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 154 | ret = s->intregm_pending & ~MASTER_DISABLE; |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 155 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 156 | case 1: |
blueswir1 | 80be36b | 2007-12-28 18:48:39 +0000 | [diff] [blame] | 157 | ret = s->intregm_disabled & MASTER_IRQ_MASK; |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 158 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 159 | case 4: |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 160 | ret = s->target_cpu; |
| 161 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 162 | default: |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 163 | ret = 0; |
| 164 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 165 | } |
blueswir1 | 1569fc2 | 2007-08-05 17:47:16 +0000 | [diff] [blame] | 166 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
blueswir1 | dd4131b | 2007-05-27 19:42:35 +0000 | [diff] [blame] | 167 | |
| 168 | return ret; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 169 | } |
| 170 | |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 171 | static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, |
| 172 | uint32_t val) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 173 | { |
| 174 | SLAVIO_INTCTLState *s = opaque; |
| 175 | uint32_t saddr; |
| 176 | |
blueswir1 | a8f48dc | 2008-12-02 17:51:19 +0000 | [diff] [blame] | 177 | saddr = addr >> 2; |
blueswir1 | 1569fc2 | 2007-08-05 17:47:16 +0000 | [diff] [blame] | 178 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 179 | switch (saddr) { |
| 180 | case 2: // clear (enable) |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 181 | // Force clear unused bits |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 182 | val &= MASTER_IRQ_MASK; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 183 | s->intregm_disabled &= ~val; |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 184 | DPRINTF("Enabled master irq mask %x, curmask %x\n", val, |
| 185 | s->intregm_disabled); |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 186 | slavio_check_interrupts(s, 1); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 187 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 188 | case 3: // set (disable, clear pending) |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 189 | // Force clear unused bits |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 190 | val &= MASTER_IRQ_MASK; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 191 | s->intregm_disabled |= val; |
| 192 | s->intregm_pending &= ~val; |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 193 | slavio_check_interrupts(s, 1); |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 194 | DPRINTF("Disabled master irq mask %x, curmask %x\n", val, |
| 195 | s->intregm_disabled); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 196 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 197 | case 4: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 198 | s->target_cpu = val & (MAX_CPUS - 1); |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 199 | slavio_check_interrupts(s, 1); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 200 | DPRINTF("Set master irq cpu %d\n", s->target_cpu); |
| 201 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 202 | default: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 203 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 204 | } |
| 205 | } |
| 206 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 207 | static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 208 | NULL, |
| 209 | NULL, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 210 | slavio_intctlm_mem_readl, |
| 211 | }; |
| 212 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 213 | static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 214 | NULL, |
| 215 | NULL, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 216 | slavio_intctlm_mem_writel, |
| 217 | }; |
| 218 | |
Blue Swirl | d453c2c | 2009-08-23 12:23:30 +0000 | [diff] [blame] | 219 | void slavio_pic_info(Monitor *mon, DeviceState *dev) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 220 | { |
Blue Swirl | d453c2c | 2009-08-23 12:23:30 +0000 | [diff] [blame] | 221 | SysBusDevice *sd; |
| 222 | SLAVIO_INTCTLState *s; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 223 | int i; |
| 224 | |
Blue Swirl | d453c2c | 2009-08-23 12:23:30 +0000 | [diff] [blame] | 225 | sd = sysbus_from_qdev(dev); |
| 226 | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 227 | for (i = 0; i < MAX_CPUS; i++) { |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 228 | monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i, |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 229 | s->slaves[i].intreg_pending); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 230 | } |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 231 | monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n", |
| 232 | s->intregm_pending, s->intregm_disabled); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 233 | } |
| 234 | |
Blue Swirl | d453c2c | 2009-08-23 12:23:30 +0000 | [diff] [blame] | 235 | void slavio_irq_info(Monitor *mon, DeviceState *dev) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 236 | { |
| 237 | #ifndef DEBUG_IRQ_COUNT |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 238 | monitor_printf(mon, "irq statistic code not compiled.\n"); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 239 | #else |
Blue Swirl | d453c2c | 2009-08-23 12:23:30 +0000 | [diff] [blame] | 240 | SysBusDevice *sd; |
| 241 | SLAVIO_INTCTLState *s; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 242 | int i; |
| 243 | int64_t count; |
| 244 | |
Blue Swirl | d453c2c | 2009-08-23 12:23:30 +0000 | [diff] [blame] | 245 | sd = sysbus_from_qdev(dev); |
| 246 | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 247 | monitor_printf(mon, "IRQ statistics:\n"); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 248 | for (i = 0; i < 32; i++) { |
| 249 | count = s->irq_count[i]; |
| 250 | if (count > 0) |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 251 | monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 252 | } |
| 253 | #endif |
| 254 | } |
| 255 | |
Blue Swirl | 68556e2 | 2009-08-08 20:36:08 +0000 | [diff] [blame] | 256 | static const uint32_t intbit_to_level[] = { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 257 | 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12, |
| 258 | 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0, |
Blue Swirl | 68556e2 | 2009-08-08 20:36:08 +0000 | [diff] [blame] | 259 | }; |
| 260 | |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 261 | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 262 | { |
blueswir1 | 327ac2e | 2007-08-04 10:50:30 +0000 | [diff] [blame] | 263 | uint32_t pending = s->intregm_pending, pil_pending; |
| 264 | unsigned int i, j; |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 265 | |
| 266 | pending &= ~s->intregm_disabled; |
| 267 | |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 268 | DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled); |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 269 | for (i = 0; i < MAX_CPUS; i++) { |
blueswir1 | 327ac2e | 2007-08-04 10:50:30 +0000 | [diff] [blame] | 270 | pil_pending = 0; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 271 | |
| 272 | /* If we are the current interrupt target, get hard interrupts */ |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 273 | if (pending && !(s->intregm_disabled & MASTER_DISABLE) && |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 274 | (i == s->target_cpu)) { |
| 275 | for (j = 0; j < 32; j++) { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 276 | if ((pending & (1 << j)) && intbit_to_level[j]) { |
Blue Swirl | 68556e2 | 2009-08-08 20:36:08 +0000 | [diff] [blame] | 277 | pil_pending |= 1 << intbit_to_level[j]; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 278 | } |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 279 | } |
| 280 | } |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 281 | |
| 282 | /* Calculate current pending hard interrupts for display */ |
| 283 | s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN | |
| 284 | CPU_IRQ_TIMER_IN; |
| 285 | if (i == s->target_cpu) { |
| 286 | for (j = 0; j < 32; j++) { |
| 287 | if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) { |
| 288 | s->slaves[i].intreg_pending |= 1 << intbit_to_level[j]; |
| 289 | } |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | /* Level 15 and CPU timer interrupts are not maskable */ |
| 294 | pil_pending |= s->slaves[i].intreg_pending & |
| 295 | (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); |
| 296 | |
| 297 | /* Add soft interrupts */ |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 298 | pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; |
blueswir1 | 327ac2e | 2007-08-04 10:50:30 +0000 | [diff] [blame] | 299 | |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 300 | if (set_irqs) { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 301 | for (j = MAX_PILS; j > 0; j--) { |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 302 | if (pil_pending & (1 << j)) { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 303 | if (!(s->slaves[i].irl_out & (1 << j))) { |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 304 | qemu_irq_raise(s->cpu_irqs[i][j]); |
| 305 | } |
| 306 | } else { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 307 | if (s->slaves[i].irl_out & (1 << j)) { |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 308 | qemu_irq_lower(s->cpu_irqs[i][j]); |
| 309 | } |
| 310 | } |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 311 | } |
| 312 | } |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 313 | s->slaves[i].irl_out = pil_pending; |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 314 | } |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 315 | } |
| 316 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 317 | /* |
| 318 | * "irq" here is the bit number in the system interrupt register to |
| 319 | * separate serial and keyboard interrupts sharing a level. |
| 320 | */ |
blueswir1 | d7edfd2 | 2007-05-27 16:37:49 +0000 | [diff] [blame] | 321 | static void slavio_set_irq(void *opaque, int irq, int level) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 322 | { |
| 323 | SLAVIO_INTCTLState *s = opaque; |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 324 | uint32_t mask = 1 << irq; |
Blue Swirl | 68556e2 | 2009-08-08 20:36:08 +0000 | [diff] [blame] | 325 | uint32_t pil = intbit_to_level[irq]; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 326 | unsigned int i; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 327 | |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 328 | DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil, |
| 329 | level); |
| 330 | if (pil > 0) { |
| 331 | if (level) { |
blueswir1 | 327ac2e | 2007-08-04 10:50:30 +0000 | [diff] [blame] | 332 | #ifdef DEBUG_IRQ_COUNT |
| 333 | s->irq_count[pil]++; |
| 334 | #endif |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 335 | s->intregm_pending |= mask; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 336 | if (pil == 15) { |
| 337 | for (i = 0; i < MAX_CPUS; i++) { |
| 338 | s->slaves[i].intreg_pending |= 1 << pil; |
| 339 | } |
| 340 | } |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 341 | } else { |
| 342 | s->intregm_pending &= ~mask; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 343 | if (pil == 15) { |
| 344 | for (i = 0; i < MAX_CPUS; i++) { |
| 345 | s->slaves[i].intreg_pending &= ~(1 << pil); |
| 346 | } |
| 347 | } |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 348 | } |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 349 | slavio_check_interrupts(s, 1); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 350 | } |
| 351 | } |
| 352 | |
blueswir1 | d7edfd2 | 2007-05-27 16:37:49 +0000 | [diff] [blame] | 353 | static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 354 | { |
| 355 | SLAVIO_INTCTLState *s = opaque; |
| 356 | |
blueswir1 | b3a2319 | 2007-05-27 16:42:29 +0000 | [diff] [blame] | 357 | DPRINTF("Set cpu %d local timer level %d\n", cpu, level); |
blueswir1 | d7edfd2 | 2007-05-27 16:37:49 +0000 | [diff] [blame] | 358 | |
blueswir1 | e3a79bc | 2008-01-01 20:57:25 +0000 | [diff] [blame] | 359 | if (level) { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 360 | s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; |
blueswir1 | e3a79bc | 2008-01-01 20:57:25 +0000 | [diff] [blame] | 361 | } else { |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 362 | s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN; |
blueswir1 | e3a79bc | 2008-01-01 20:57:25 +0000 | [diff] [blame] | 363 | } |
blueswir1 | d7edfd2 | 2007-05-27 16:37:49 +0000 | [diff] [blame] | 364 | |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 365 | slavio_check_interrupts(s, 1); |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 366 | } |
| 367 | |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 368 | static void slavio_set_irq_all(void *opaque, int irq, int level) |
| 369 | { |
| 370 | if (irq < 32) { |
| 371 | slavio_set_irq(opaque, irq, level); |
| 372 | } else { |
| 373 | slavio_set_timer_irq_cpu(opaque, irq - 32, level); |
| 374 | } |
| 375 | } |
| 376 | |
Blue Swirl | c9e9502 | 2009-08-28 20:22:52 +0000 | [diff] [blame] | 377 | static int vmstate_intctl_after_load(void *opaque) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 378 | { |
| 379 | SLAVIO_INTCTLState *s = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 380 | |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 381 | slavio_check_interrupts(s, 0); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 382 | return 0; |
| 383 | } |
| 384 | |
Blue Swirl | c9e9502 | 2009-08-28 20:22:52 +0000 | [diff] [blame] | 385 | static const VMStateDescription vmstate_intctl_cpu = { |
| 386 | .name ="slavio_intctl_cpu", |
| 387 | .version_id = 1, |
| 388 | .minimum_version_id = 1, |
| 389 | .minimum_version_id_old = 1, |
| 390 | .fields = (VMStateField []) { |
| 391 | VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState), |
| 392 | VMSTATE_END_OF_LIST() |
| 393 | } |
| 394 | }; |
| 395 | |
| 396 | static const VMStateDescription vmstate_intctl = { |
| 397 | .name ="slavio_intctl", |
| 398 | .version_id = 1, |
| 399 | .minimum_version_id = 1, |
| 400 | .minimum_version_id_old = 1, |
| 401 | .run_after_load = vmstate_intctl_after_load, |
| 402 | .fields = (VMStateField []) { |
| 403 | VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1, |
| 404 | vmstate_intctl_cpu, SLAVIO_CPUINTCTLState), |
| 405 | VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState), |
| 406 | VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState), |
| 407 | VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState), |
| 408 | VMSTATE_END_OF_LIST() |
| 409 | } |
| 410 | }; |
| 411 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 412 | static void slavio_intctl_reset(void *opaque) |
| 413 | { |
| 414 | SLAVIO_INTCTLState *s = opaque; |
| 415 | int i; |
| 416 | |
| 417 | for (i = 0; i < MAX_CPUS; i++) { |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 418 | s->slaves[i].intreg_pending = 0; |
Blue Swirl | 462eda2 | 2009-08-25 18:29:36 +0000 | [diff] [blame] | 419 | s->slaves[i].irl_out = 0; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 420 | } |
blueswir1 | 9a87ce9 | 2007-11-17 21:01:04 +0000 | [diff] [blame] | 421 | s->intregm_disabled = ~MASTER_IRQ_MASK; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 422 | s->intregm_pending = 0; |
| 423 | s->target_cpu = 0; |
Blue Swirl | 0d0a7e6 | 2009-06-17 17:20:01 +0000 | [diff] [blame] | 424 | slavio_check_interrupts(s, 0); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 425 | } |
| 426 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 427 | static int slavio_intctl_init1(SysBusDevice *dev) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 428 | { |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 429 | SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev); |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 430 | int io_memory; |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 431 | unsigned int i, j; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 432 | |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 433 | qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS); |
| 434 | io_memory = cpu_register_io_memory(slavio_intctlm_mem_read, |
| 435 | slavio_intctlm_mem_write, s); |
| 436 | sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 437 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 438 | for (i = 0; i < MAX_CPUS; i++) { |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 439 | for (j = 0; j < MAX_PILS; j++) { |
| 440 | sysbus_init_irq(dev, &s->cpu_irqs[i][j]); |
| 441 | } |
| 442 | io_memory = cpu_register_io_memory(slavio_intctl_mem_read, |
| 443 | slavio_intctl_mem_write, |
| 444 | &s->slaves[i]); |
| 445 | sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); |
| 446 | s->slaves[i].cpu = i; |
| 447 | s->slaves[i].master = s; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 448 | } |
Blue Swirl | c9e9502 | 2009-08-28 20:22:52 +0000 | [diff] [blame] | 449 | vmstate_register(-1, &vmstate_intctl, s); |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 450 | qemu_register_reset(slavio_intctl_reset, s); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 451 | slavio_intctl_reset(s); |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 452 | return 0; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 453 | } |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 454 | |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 455 | static SysBusDeviceInfo slavio_intctl_info = { |
| 456 | .init = slavio_intctl_init1, |
| 457 | .qdev.name = "slavio_intctl", |
| 458 | .qdev.size = sizeof(SLAVIO_INTCTLState), |
Blue Swirl | a1961a4 | 2009-07-16 14:15:34 +0000 | [diff] [blame] | 459 | }; |
| 460 | |
| 461 | static void slavio_intctl_register_devices(void) |
| 462 | { |
| 463 | sysbus_register_withprop(&slavio_intctl_info); |
| 464 | } |
| 465 | |
| 466 | device_init(slavio_intctl_register_devices) |