Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * MIPS gdb server stub |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * Copyright (c) 2013 SUSE LINUX Products GmbH |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
Andreas Färber | 5b50e79 | 2013-06-29 04:18:45 +0200 | [diff] [blame] | 20 | #include "config.h" |
| 21 | #include "qemu-common.h" |
| 22 | #include "exec/gdbstub.h" |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 23 | |
Andreas Färber | 5b50e79 | 2013-06-29 04:18:45 +0200 | [diff] [blame] | 24 | int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 25 | { |
Andreas Färber | 5b50e79 | 2013-06-29 04:18:45 +0200 | [diff] [blame] | 26 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 27 | CPUMIPSState *env = &cpu->env; |
| 28 | |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 29 | if (n < 32) { |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 30 | return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 31 | } |
Maciej W. Rozycki | cbb26c9 | 2014-12-05 18:46:04 +0000 | [diff] [blame] | 32 | if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { |
| 33 | switch (n) { |
| 34 | case 70: |
| 35 | return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31); |
| 36 | case 71: |
| 37 | return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); |
| 38 | default: |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 39 | if (env->CP0_Status & (1 << CP0St_FR)) { |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 40 | return gdb_get_regl(mem_buf, |
| 41 | env->active_fpu.fpr[n - 38].d); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 42 | } else { |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 43 | return gdb_get_regl(mem_buf, |
| 44 | env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 45 | } |
| 46 | } |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 47 | } |
| 48 | switch (n) { |
| 49 | case 32: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 50 | return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 51 | case 33: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 52 | return gdb_get_regl(mem_buf, env->active_tc.LO[0]); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 53 | case 34: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 54 | return gdb_get_regl(mem_buf, env->active_tc.HI[0]); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 55 | case 35: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 56 | return gdb_get_regl(mem_buf, env->CP0_BadVAddr); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 57 | case 36: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 58 | return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 59 | case 37: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 60 | return gdb_get_regl(mem_buf, env->active_tc.PC | |
| 61 | !!(env->hflags & MIPS_HFLAG_M16)); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 62 | case 72: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 63 | return gdb_get_regl(mem_buf, 0); /* fp */ |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 64 | case 89: |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 65 | return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid); |
Maciej W. Rozycki | cbb26c9 | 2014-12-05 18:46:04 +0000 | [diff] [blame] | 66 | default: |
| 67 | if (n > 89) { |
| 68 | return 0; |
| 69 | } |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 70 | /* 16 embedded regs. */ |
Andreas Färber | 986a299 | 2013-07-07 13:05:05 +0200 | [diff] [blame] | 71 | return gdb_get_regl(mem_buf, 0); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
Andreas Färber | 5b50e79 | 2013-06-29 04:18:45 +0200 | [diff] [blame] | 77 | int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 78 | { |
Andreas Färber | 5b50e79 | 2013-06-29 04:18:45 +0200 | [diff] [blame] | 79 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 80 | CPUMIPSState *env = &cpu->env; |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 81 | target_ulong tmp; |
| 82 | |
| 83 | tmp = ldtul_p(mem_buf); |
| 84 | |
| 85 | if (n < 32) { |
| 86 | env->active_tc.gpr[n] = tmp; |
| 87 | return sizeof(target_ulong); |
| 88 | } |
Maciej W. Rozycki | cbb26c9 | 2014-12-05 18:46:04 +0000 | [diff] [blame] | 89 | if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 90 | switch (n) { |
| 91 | case 70: |
| 92 | env->active_fpu.fcr31 = tmp & 0xFF83FFFF; |
| 93 | /* set rounding mode */ |
Maciej W. Rozycki | bb96238 | 2014-12-02 17:02:38 +0000 | [diff] [blame] | 94 | restore_rounding_mode(env); |
| 95 | /* set flush-to-zero mode */ |
| 96 | restore_flush_mode(env); |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 97 | break; |
| 98 | case 71: |
Maciej W. Rozycki | c7d4d98 | 2014-11-03 18:51:38 +0000 | [diff] [blame] | 99 | /* FIR is read-only. Ignore writes. */ |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 100 | break; |
Maciej W. Rozycki | cbb26c9 | 2014-12-05 18:46:04 +0000 | [diff] [blame] | 101 | default: |
| 102 | if (env->CP0_Status & (1 << CP0St_FR)) { |
| 103 | env->active_fpu.fpr[n - 38].d = tmp; |
| 104 | } else { |
| 105 | env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; |
| 106 | } |
| 107 | break; |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 108 | } |
| 109 | return sizeof(target_ulong); |
| 110 | } |
| 111 | switch (n) { |
| 112 | case 32: |
Maciej W. Rozycki | 81a423e | 2014-11-10 13:46:35 +0000 | [diff] [blame] | 113 | #ifndef CONFIG_USER_ONLY |
| 114 | cpu_mips_store_status(env, tmp); |
| 115 | #endif |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 116 | break; |
| 117 | case 33: |
| 118 | env->active_tc.LO[0] = tmp; |
| 119 | break; |
| 120 | case 34: |
| 121 | env->active_tc.HI[0] = tmp; |
| 122 | break; |
| 123 | case 35: |
| 124 | env->CP0_BadVAddr = tmp; |
| 125 | break; |
| 126 | case 36: |
Maciej W. Rozycki | 81a423e | 2014-11-10 13:46:35 +0000 | [diff] [blame] | 127 | #ifndef CONFIG_USER_ONLY |
| 128 | cpu_mips_store_cause(env, tmp); |
| 129 | #endif |
Andreas Färber | 814ac26 | 2013-07-07 12:38:42 +0200 | [diff] [blame] | 130 | break; |
| 131 | case 37: |
| 132 | env->active_tc.PC = tmp & ~(target_ulong)1; |
| 133 | if (tmp & 1) { |
| 134 | env->hflags |= MIPS_HFLAG_M16; |
| 135 | } else { |
| 136 | env->hflags &= ~(MIPS_HFLAG_M16); |
| 137 | } |
| 138 | break; |
| 139 | case 72: /* fp, ignored */ |
| 140 | break; |
| 141 | default: |
| 142 | if (n > 89) { |
| 143 | return 0; |
| 144 | } |
| 145 | /* Other registers are readonly. Ignore writes. */ |
| 146 | break; |
| 147 | } |
| 148 | |
| 149 | return sizeof(target_ulong); |
| 150 | } |