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Andreas Färber814ac262013-07-07 12:38:42 +02001/*
2 * MIPS gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
Andreas Färber5b50e792013-06-29 04:18:45 +020020#include "config.h"
21#include "qemu-common.h"
22#include "exec/gdbstub.h"
Andreas Färber814ac262013-07-07 12:38:42 +020023
Andreas Färber5b50e792013-06-29 04:18:45 +020024int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
Andreas Färber814ac262013-07-07 12:38:42 +020025{
Andreas Färber5b50e792013-06-29 04:18:45 +020026 MIPSCPU *cpu = MIPS_CPU(cs);
27 CPUMIPSState *env = &cpu->env;
28
Andreas Färber814ac262013-07-07 12:38:42 +020029 if (n < 32) {
Andreas Färber986a2992013-07-07 13:05:05 +020030 return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
Andreas Färber814ac262013-07-07 12:38:42 +020031 }
Maciej W. Rozyckicbb26c92014-12-05 18:46:04 +000032 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
33 switch (n) {
34 case 70:
35 return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
36 case 71:
37 return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
38 default:
Andreas Färber814ac262013-07-07 12:38:42 +020039 if (env->CP0_Status & (1 << CP0St_FR)) {
Andreas Färber986a2992013-07-07 13:05:05 +020040 return gdb_get_regl(mem_buf,
41 env->active_fpu.fpr[n - 38].d);
Andreas Färber814ac262013-07-07 12:38:42 +020042 } else {
Andreas Färber986a2992013-07-07 13:05:05 +020043 return gdb_get_regl(mem_buf,
44 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
Andreas Färber814ac262013-07-07 12:38:42 +020045 }
46 }
Andreas Färber814ac262013-07-07 12:38:42 +020047 }
48 switch (n) {
49 case 32:
Andreas Färber986a2992013-07-07 13:05:05 +020050 return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
Andreas Färber814ac262013-07-07 12:38:42 +020051 case 33:
Andreas Färber986a2992013-07-07 13:05:05 +020052 return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
Andreas Färber814ac262013-07-07 12:38:42 +020053 case 34:
Andreas Färber986a2992013-07-07 13:05:05 +020054 return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
Andreas Färber814ac262013-07-07 12:38:42 +020055 case 35:
Andreas Färber986a2992013-07-07 13:05:05 +020056 return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
Andreas Färber814ac262013-07-07 12:38:42 +020057 case 36:
Andreas Färber986a2992013-07-07 13:05:05 +020058 return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
Andreas Färber814ac262013-07-07 12:38:42 +020059 case 37:
Andreas Färber986a2992013-07-07 13:05:05 +020060 return gdb_get_regl(mem_buf, env->active_tc.PC |
61 !!(env->hflags & MIPS_HFLAG_M16));
Andreas Färber814ac262013-07-07 12:38:42 +020062 case 72:
Andreas Färber986a2992013-07-07 13:05:05 +020063 return gdb_get_regl(mem_buf, 0); /* fp */
Andreas Färber814ac262013-07-07 12:38:42 +020064 case 89:
Andreas Färber986a2992013-07-07 13:05:05 +020065 return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
Maciej W. Rozyckicbb26c92014-12-05 18:46:04 +000066 default:
67 if (n > 89) {
68 return 0;
69 }
Andreas Färber814ac262013-07-07 12:38:42 +020070 /* 16 embedded regs. */
Andreas Färber986a2992013-07-07 13:05:05 +020071 return gdb_get_regl(mem_buf, 0);
Andreas Färber814ac262013-07-07 12:38:42 +020072 }
73
74 return 0;
75}
76
Andreas Färber5b50e792013-06-29 04:18:45 +020077int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
Andreas Färber814ac262013-07-07 12:38:42 +020078{
Andreas Färber5b50e792013-06-29 04:18:45 +020079 MIPSCPU *cpu = MIPS_CPU(cs);
80 CPUMIPSState *env = &cpu->env;
Andreas Färber814ac262013-07-07 12:38:42 +020081 target_ulong tmp;
82
83 tmp = ldtul_p(mem_buf);
84
85 if (n < 32) {
86 env->active_tc.gpr[n] = tmp;
87 return sizeof(target_ulong);
88 }
Maciej W. Rozyckicbb26c92014-12-05 18:46:04 +000089 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
Andreas Färber814ac262013-07-07 12:38:42 +020090 switch (n) {
91 case 70:
92 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
93 /* set rounding mode */
Maciej W. Rozyckibb962382014-12-02 17:02:38 +000094 restore_rounding_mode(env);
95 /* set flush-to-zero mode */
96 restore_flush_mode(env);
Andreas Färber814ac262013-07-07 12:38:42 +020097 break;
98 case 71:
Maciej W. Rozyckic7d4d982014-11-03 18:51:38 +000099 /* FIR is read-only. Ignore writes. */
Andreas Färber814ac262013-07-07 12:38:42 +0200100 break;
Maciej W. Rozyckicbb26c92014-12-05 18:46:04 +0000101 default:
102 if (env->CP0_Status & (1 << CP0St_FR)) {
103 env->active_fpu.fpr[n - 38].d = tmp;
104 } else {
105 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
106 }
107 break;
Andreas Färber814ac262013-07-07 12:38:42 +0200108 }
109 return sizeof(target_ulong);
110 }
111 switch (n) {
112 case 32:
Maciej W. Rozycki81a423e2014-11-10 13:46:35 +0000113#ifndef CONFIG_USER_ONLY
114 cpu_mips_store_status(env, tmp);
115#endif
Andreas Färber814ac262013-07-07 12:38:42 +0200116 break;
117 case 33:
118 env->active_tc.LO[0] = tmp;
119 break;
120 case 34:
121 env->active_tc.HI[0] = tmp;
122 break;
123 case 35:
124 env->CP0_BadVAddr = tmp;
125 break;
126 case 36:
Maciej W. Rozycki81a423e2014-11-10 13:46:35 +0000127#ifndef CONFIG_USER_ONLY
128 cpu_mips_store_cause(env, tmp);
129#endif
Andreas Färber814ac262013-07-07 12:38:42 +0200130 break;
131 case 37:
132 env->active_tc.PC = tmp & ~(target_ulong)1;
133 if (tmp & 1) {
134 env->hflags |= MIPS_HFLAG_M16;
135 } else {
136 env->hflags &= ~(MIPS_HFLAG_M16);
137 }
138 break;
139 case 72: /* fp, ignored */
140 break;
141 default:
142 if (n > 89) {
143 return 0;
144 }
145 /* Other registers are readonly. Ignore writes. */
146 break;
147 }
148
149 return sizeof(target_ulong);
150}