commit 81a423e6c6d3ccaa79de4e58024369c660c1eeb4
author Maciej W. Rozycki <macro@codesourcery.com> Mon Nov 10 13:46:35 2014 +0000
committer Leon Alrae <leon.alrae@imgtec.com> Tue Dec 16 12:45:19 2014 +0000
tree ccc5e90b146ffa3e0d8a6c40888b063cae188961
parent f88f79ec9df06d26d84e1d2e0c02d2634b4d8583

target-mips: Correct the writes to Status and Cause registers via gdbstub

Make writes to CP0.Status and CP0.Cause have the same effect as
executing corresponding MTC0 instructions would in Kernel Mode.  Also
ignore writes in the user emulation mode.

Currently for requests from the GDB stub we write all the bits across
both registers, ignoring any read-only locations, and do not synchronise
the environment to evaluate side effects.  We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

target-mips/gdbstub.c

diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index e86df0e..964e6a7 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -112,7 +112,9 @@
     }
     switch (n) {
     case 32:
-        env->CP0_Status = tmp;
+#ifndef CONFIG_USER_ONLY
+        cpu_mips_store_status(env, tmp);
+#endif
         break;
     case 33:
         env->active_tc.LO[0] = tmp;
@@ -124,7 +126,9 @@
         env->CP0_BadVAddr = tmp;
         break;
     case 36:
-        env->CP0_Cause = tmp;
+#ifndef CONFIG_USER_ONLY
+        cpu_mips_store_cause(env, tmp);
+#endif
         break;
     case 37:
         env->active_tc.PC = tmp & ~(target_ulong)1;